MLK-12486-2 imx6: Add i.mx6sx/ul arm2 boards
Add i.MX6SX/UL arm2 boards support. Most code are from imx_v2015.04, but adapted to 2016.03 release. Tested on mx6ul_14x14_ddr3_arm2 and mx6sx_19x19_ddr3_arm2. Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
@ -117,6 +117,30 @@ config TARGET_MX6UL_14X14_EVK
|
||||
select DM_THERMAL
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_MX6UL_14X14_DDR3_ARM2
|
||||
bool "mx6ul_14x14_ddr3_arm2"
|
||||
select MX6UL
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
|
||||
config TARGET_MX6UL_14X14_LPDDR2_ARM2
|
||||
bool "mx6ul_14x14_lpddr2_arm2"
|
||||
select MX6UL
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
|
||||
config TARGET_MX6SX_17X17_ARM2
|
||||
bool "mx6sx_17x17_arm2"
|
||||
select MX6SX
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
|
||||
config TARGET_MX6SX_19X19_ARM2
|
||||
bool "mx6sx_19x19_arm2"
|
||||
select MX6SX
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
|
||||
config TARGET_NITROGEN6X
|
||||
bool "nitrogen6x"
|
||||
|
||||
@ -175,6 +199,10 @@ source "board/freescale/mx6slevk/Kconfig"
|
||||
source "board/freescale/mx6sxsabresd/Kconfig"
|
||||
source "board/freescale/mx6sxsabreauto/Kconfig"
|
||||
source "board/freescale/mx6ul_14x14_evk/Kconfig"
|
||||
source "board/freescale/mx6sx_17x17_arm2/Kconfig"
|
||||
source "board/freescale/mx6sx_19x19_arm2/Kconfig"
|
||||
source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig"
|
||||
source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig"
|
||||
source "board/gateworks/gw_ventana/Kconfig"
|
||||
source "board/kosagi/novena/Kconfig"
|
||||
source "board/seco/Kconfig"
|
||||
|
||||
12
board/freescale/mx6sx_17x17_arm2/Kconfig
Normal file
12
board/freescale/mx6sx_17x17_arm2/Kconfig
Normal file
@ -0,0 +1,12 @@
|
||||
if TARGET_MX6SX_17X17_ARM2
|
||||
|
||||
config SYS_BOARD
|
||||
default "mx6sx_17x17_arm2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "mx6sx_17x17_arm2"
|
||||
|
||||
endif
|
||||
10
board/freescale/mx6sx_17x17_arm2/Makefile
Normal file
10
board/freescale/mx6sx_17x17_arm2/Makefile
Normal file
@ -0,0 +1,10 @@
|
||||
# (C) Copyright 2014 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := mx6sx_17x17_arm2.o
|
||||
|
||||
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
|
||||
$(obj)/plugin.bin: $(obj)/plugin.o
|
||||
$(OBJCOPY) -O binary --gap-fill 0xff $< $@
|
||||
122
board/freescale/mx6sx_17x17_arm2/imximage.cfg
Normal file
122
board/freescale/mx6sx_17x17_arm2/imximage.cfg
Normal file
@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
BOOT_FROM qspi
|
||||
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
|
||||
BOOT_FROM nor
|
||||
#else
|
||||
BOOT_FROM sd
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USE_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx6sx_17x17_arm2/plugin.bin 0x00907000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x020c4068 0xffffffff
|
||||
DATA 4 0x020c406c 0xffffffff
|
||||
DATA 4 0x020c4070 0xffffffff
|
||||
DATA 4 0x020c4074 0xffffffff
|
||||
DATA 4 0x020c4078 0xffffffff
|
||||
DATA 4 0x020c407c 0xffffffff
|
||||
DATA 4 0x020c4080 0xffffffff
|
||||
DATA 4 0x020c4084 0xffffffff
|
||||
|
||||
DATA 4 0x020e0618 0x000c0000
|
||||
DATA 4 0x020e05fc 0x00000000
|
||||
DATA 4 0x020e032c 0x00000030
|
||||
|
||||
DATA 4 0x020e0300 0x00000030
|
||||
DATA 4 0x020e02fc 0x00000030
|
||||
DATA 4 0x020e05f4 0x00000030
|
||||
DATA 4 0x020e0340 0x00000030
|
||||
|
||||
DATA 4 0x020e0320 0x00000000
|
||||
DATA 4 0x020e0310 0x00000030
|
||||
DATA 4 0x020e0314 0x00000030
|
||||
DATA 4 0x020e0614 0x00000030
|
||||
|
||||
DATA 4 0x020e05f8 0x00020000
|
||||
DATA 4 0x020e0330 0x00000030
|
||||
DATA 4 0x020e0334 0x00000030
|
||||
DATA 4 0x020e0338 0x00000030
|
||||
DATA 4 0x020e033c 0x00000030
|
||||
DATA 4 0x020e0608 0x00020000
|
||||
DATA 4 0x020e060c 0x00000030
|
||||
DATA 4 0x020e0610 0x00000030
|
||||
DATA 4 0x020e061c 0x00000030
|
||||
DATA 4 0x020e0620 0x00000030
|
||||
DATA 4 0x020e02ec 0x00000030
|
||||
DATA 4 0x020e02f0 0x00000030
|
||||
DATA 4 0x020e02f4 0x00000030
|
||||
DATA 4 0x020e02f8 0x00000030
|
||||
DATA 4 0x021b0800 0xa1390003
|
||||
DATA 4 0x021b080c 0x00270025
|
||||
DATA 4 0x021b0810 0x001B001E
|
||||
DATA 4 0x021b083c 0x4144013C
|
||||
DATA 4 0x021b0840 0x01300128
|
||||
DATA 4 0x021b0848 0x4044464A
|
||||
DATA 4 0x021b0850 0x3A383C34
|
||||
DATA 4 0x021b081c 0x33333333
|
||||
DATA 4 0x021b0820 0x33333333
|
||||
DATA 4 0x021b0824 0x33333333
|
||||
DATA 4 0x021b0828 0x33333333
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
DATA 4 0x021b0004 0x0002002d
|
||||
DATA 4 0x021b0008 0x00333030
|
||||
DATA 4 0x021b000c 0x676b52f3
|
||||
DATA 4 0x021b0010 0xb66d8b63
|
||||
DATA 4 0x021b0014 0x01ff00db
|
||||
DATA 4 0x021b0018 0x00011740
|
||||
DATA 4 0x021b001c 0x00008000
|
||||
DATA 4 0x021b002c 0x000026d2
|
||||
DATA 4 0x021b0030 0x006b1023
|
||||
DATA 4 0x021b0040 0x0000005f
|
||||
DATA 4 0x021b0000 0x84190000
|
||||
DATA 4 0x021b001c 0x04008032
|
||||
DATA 4 0x021b001c 0x00008033
|
||||
DATA 4 0x021b001c 0x00068031
|
||||
DATA 4 0x021b001c 0x05208030
|
||||
DATA 4 0x021b001c 0x04008040
|
||||
DATA 4 0x021b0020 0x00000800
|
||||
DATA 4 0x021b0818 0x00011117
|
||||
DATA 4 0x021b001c 0x00000000
|
||||
|
||||
#endif
|
||||
118
board/freescale/mx6sx_17x17_arm2/imximage_wp.cfg
Normal file
118
board/freescale/mx6sx_17x17_arm2/imximage_wp.cfg
Normal file
@ -0,0 +1,118 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
BOOT_FROM qspi
|
||||
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
|
||||
BOOT_FROM nor
|
||||
#else
|
||||
BOOT_FROM sd
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x020c4068 0xffffffff
|
||||
DATA 4 0x020c406c 0xffffffff
|
||||
DATA 4 0x020c4070 0xffffffff
|
||||
DATA 4 0x020c4074 0xffffffff
|
||||
DATA 4 0x020c4078 0xffffffff
|
||||
DATA 4 0x020c407c 0xffffffff
|
||||
DATA 4 0x020c4080 0xffffffff
|
||||
DATA 4 0x020c4084 0xffffffff
|
||||
|
||||
DATA 4 0x020e0618 0x000c0000
|
||||
DATA 4 0x020e05fc 0x00000000
|
||||
DATA 4 0x020e032c 0x00000030
|
||||
|
||||
DATA 4 0x020e0300 0x00000030
|
||||
DATA 4 0x020e02fc 0x00000030
|
||||
DATA 4 0x020e05f4 0x00000030
|
||||
DATA 4 0x020e0340 0x00000030
|
||||
|
||||
DATA 4 0x020e0320 0x00000000
|
||||
DATA 4 0x020e0310 0x00000030
|
||||
DATA 4 0x020e0314 0x00000030
|
||||
DATA 4 0x020e0614 0x00000030
|
||||
|
||||
DATA 4 0x020e05f8 0x00020000
|
||||
DATA 4 0x020e0330 0x00000030
|
||||
DATA 4 0x020e0334 0x00000030
|
||||
DATA 4 0x020e0338 0x00000030
|
||||
DATA 4 0x020e033c 0x00000030
|
||||
DATA 4 0x020e0608 0x00020000
|
||||
DATA 4 0x020e060c 0x00000030
|
||||
DATA 4 0x020e0610 0x00000030
|
||||
DATA 4 0x020e061c 0x00000030
|
||||
DATA 4 0x020e0620 0x00000030
|
||||
DATA 4 0x020e02ec 0x00000030
|
||||
DATA 4 0x020e02f0 0x00000030
|
||||
DATA 4 0x020e02f4 0x00000030
|
||||
DATA 4 0x020e02f8 0x00000030
|
||||
DATA 4 0x021b0800 0xa1390003
|
||||
DATA 4 0x021b080c 0x002E003C
|
||||
DATA 4 0x021b0810 0x001A003F
|
||||
DATA 4 0x021b083c 0x41480150
|
||||
DATA 4 0x021b0840 0x012C0150
|
||||
DATA 4 0x021b0848 0x40404646
|
||||
DATA 4 0x021b0850 0x38363C32
|
||||
DATA 4 0x021b08c0 0x2492244A
|
||||
DATA 4 0x021b081c 0x33333333
|
||||
DATA 4 0x021b0820 0x33333333
|
||||
DATA 4 0x021b0824 0x33333333
|
||||
DATA 4 0x021b0828 0x33333333
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
DATA 4 0x021b0004 0x0002002d
|
||||
DATA 4 0x021b0008 0x00333030
|
||||
DATA 4 0x021b000c 0x676b52f3
|
||||
DATA 4 0x021b0010 0xb66d8b63
|
||||
DATA 4 0x021b0014 0x01ff00db
|
||||
DATA 4 0x021b0018 0x00011740
|
||||
DATA 4 0x021b001c 0x00008000
|
||||
DATA 4 0x021b002c 0x000026d2
|
||||
DATA 4 0x021b0030 0x006b1023
|
||||
DATA 4 0x021b0040 0x0000005f
|
||||
DATA 4 0x021b0000 0x84190000
|
||||
DATA 4 0x021b001c 0x04008032
|
||||
DATA 4 0x021b001c 0x00008033
|
||||
DATA 4 0x021b001c 0x00068031
|
||||
DATA 4 0x021b001c 0x05208030
|
||||
DATA 4 0x021b001c 0x04008040
|
||||
DATA 4 0x021b0020 0x00000800
|
||||
DATA 4 0x021b0818 0x00022227
|
||||
DATA 4 0x021b0004 0x0002556d
|
||||
DATA 4 0x021b0404 0x00011006
|
||||
DATA 4 0x021b001c 0x00000000
|
||||
153
board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg
Normal file
153
board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg
Normal file
@ -0,0 +1,153 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
BOOT_FROM qspi
|
||||
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
|
||||
BOOT_FROM nor
|
||||
#else
|
||||
BOOT_FROM sd
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USE_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx6sx_17x17_arm2/plugin.bin 0x00907000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x020c4068 0xffffffff
|
||||
DATA 4 0x020c406c 0xffffffff
|
||||
DATA 4 0x020c4070 0xffffffff
|
||||
DATA 4 0x020c4074 0xffffffff
|
||||
DATA 4 0x020c4078 0xffffffff
|
||||
DATA 4 0x020c407c 0xffffffff
|
||||
DATA 4 0x020c4080 0xffffffff
|
||||
DATA 4 0x020c4084 0xffffffff
|
||||
|
||||
DATA 4 0x020c4018 0x00260324
|
||||
|
||||
DATA 4 0x020e0618 0x00080000
|
||||
DATA 4 0x020e05fc 0x00000000
|
||||
DATA 4 0x020e032c 0x00000030
|
||||
|
||||
DATA 4 0x020e0300 0x00000028
|
||||
DATA 4 0x020e02fc 0x00000028
|
||||
DATA 4 0x020e05f4 0x00000028
|
||||
DATA 4 0x020e0340 0x00000028
|
||||
|
||||
DATA 4 0x020e0320 0x00000000
|
||||
DATA 4 0x020e0310 0x00000000
|
||||
DATA 4 0x020e0314 0x00000000
|
||||
DATA 4 0x020e0614 0x00000028
|
||||
|
||||
DATA 4 0x020e05f8 0x00020000
|
||||
DATA 4 0x020e0330 0x00003028
|
||||
DATA 4 0x020e0334 0x00003028
|
||||
DATA 4 0x020e0338 0x00003028
|
||||
DATA 4 0x020e033c 0x00003028
|
||||
|
||||
DATA 4 0x020e0608 0x00020000
|
||||
DATA 4 0x020e060c 0x00000028
|
||||
DATA 4 0x020e0610 0x00000028
|
||||
DATA 4 0x020e061c 0x00000028
|
||||
DATA 4 0x020e0620 0x00000028
|
||||
|
||||
DATA 4 0x020e02ec 0x00000028
|
||||
DATA 4 0x020e02f0 0x00000028
|
||||
DATA 4 0x020e02f4 0x00000028
|
||||
DATA 4 0x020e02f8 0x00000028
|
||||
|
||||
DATA 4 0x021b001c 0x00008000
|
||||
DATA 4 0x021b085c 0x1b4700c7
|
||||
|
||||
DATA 4 0x021b0800 0xa1390003
|
||||
DATA 4 0x021b0890 0x00380000
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
|
||||
DATA 4 0x021b081c 0x33333333
|
||||
DATA 4 0x021b0820 0x33333333
|
||||
DATA 4 0x021b0824 0x33333333
|
||||
DATA 4 0x021b0828 0x33333333
|
||||
|
||||
DATA 4 0x021b082c 0x51111111
|
||||
DATA 4 0x021b0830 0x51111111
|
||||
DATA 4 0x021b0834 0x51111111
|
||||
DATA 4 0x021b0838 0x51111111
|
||||
|
||||
DATA 4 0x021b0848 0x42424244
|
||||
|
||||
DATA 4 0x021b0850 0x2E30322E
|
||||
DATA 4 0x021b08c0 0x2492244A
|
||||
DATA 4 0x021b083c 0x20000000
|
||||
DATA 4 0x021b0840 0x0
|
||||
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
|
||||
DATA 4 0x021b000c 0x33374133
|
||||
DATA 4 0x021b0004 0x00020024
|
||||
DATA 4 0x021b0010 0x00100A42
|
||||
DATA 4 0x021b0014 0x00000093
|
||||
DATA 4 0x021b0018 0x00001748
|
||||
DATA 4 0x021b002c 0x0f9f26d2
|
||||
DATA 4 0x021b0030 0x0000020e
|
||||
DATA 4 0x021b0038 0x00190778
|
||||
DATA 4 0x021b0008 0x00000000
|
||||
DATA 4 0x021b0040 0x0000004f
|
||||
DATA 4 0x021b0000 0xc3110000
|
||||
|
||||
DATA 4 0x021b001c 0x003f8030
|
||||
DATA 4 0x021b001c 0xff0a8030
|
||||
DATA 4 0x021b001c 0x82018030
|
||||
DATA 4 0x021b001c 0x04028030
|
||||
DATA 4 0x021b001c 0x01038030
|
||||
|
||||
DATA 4 0x021b001c 0x003f8038
|
||||
DATA 4 0x021b001c 0xff0a8038
|
||||
DATA 4 0x021b001c 0x82018038
|
||||
DATA 4 0x021b001c 0x04028038
|
||||
DATA 4 0x021b001c 0x01038038
|
||||
|
||||
DATA 4 0x021b0020 0x00001800
|
||||
DATA 4 0x021b0818 0x00000000
|
||||
|
||||
DATA 4 0x021b0800 0xa1310003
|
||||
DATA 4 0x021b0004 0x00025576
|
||||
DATA 4 0x021b0404 0x00011006
|
||||
DATA 4 0x021b001c 0x00000000
|
||||
|
||||
#endif
|
||||
759
board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
Normal file
759
board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
Normal file
@ -0,0 +1,759 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <common.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <mmc.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
#include <i2c.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
#endif
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pfuze100_pmic.h>
|
||||
#include "../common/pfuze.h"
|
||||
#include <usb.h>
|
||||
#include <usb/ehci-fsl.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE)
|
||||
|
||||
#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
||||
|
||||
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
||||
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_SRE_FAST)
|
||||
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
|
||||
|
||||
#define SPI_PAD_CTRL (PAD_CTL_HYS | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm)
|
||||
|
||||
#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define I2C_PMIC 0
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
/* I2C1 for PMIC */
|
||||
struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 0),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 1),
|
||||
},
|
||||
};
|
||||
|
||||
/* I2C2 */
|
||||
struct i2c_pads_info i2c_pad_info2 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 2),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 3),
|
||||
},
|
||||
};
|
||||
|
||||
static struct pmic *pfuze;
|
||||
int power_init_board(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
int ret;
|
||||
|
||||
pfuze = pfuze_common_init(I2C_PMIC);
|
||||
if (!pfuze)
|
||||
return -ENODEV;
|
||||
|
||||
ret = pfuze_mode_init(pfuze, APS_PFM);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* set SW1AB staby volatage 0.975V */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®);
|
||||
reg &= ~0x3f;
|
||||
reg |= PFUZE100_SW1ABC_SETP(9750);
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
|
||||
|
||||
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®);
|
||||
reg &= ~0xc0;
|
||||
reg |= 0x40;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
|
||||
|
||||
/* set SW1C staby volatage 0.975V */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®);
|
||||
reg &= ~0x3f;
|
||||
reg |= PFUZE100_SW1ABC_SETP(9750);
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
|
||||
|
||||
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®);
|
||||
reg &= ~0xc0;
|
||||
reg |= 0x40;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LDO_BYPASS_CHECK
|
||||
void ldo_mode_set(int ldo_bypass)
|
||||
{
|
||||
unsigned int value;
|
||||
int is_400M;
|
||||
u32 vddarm;
|
||||
struct pmic *p = pfuze;
|
||||
|
||||
if (!p) {
|
||||
printf("No PMIC found!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* switch to ldo_bypass mode */
|
||||
if (ldo_bypass) {
|
||||
prep_anatop_bypass();
|
||||
/* decrease VDDARM to 1.275V */
|
||||
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(12750);
|
||||
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
|
||||
|
||||
/* decrease VDDSOC to 1.3V */
|
||||
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(13000);
|
||||
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
|
||||
|
||||
is_400M = set_anatop_bypass(1);
|
||||
if (is_400M)
|
||||
vddarm = PFUZE100_SW1ABC_SETP(10750);
|
||||
else
|
||||
vddarm = PFUZE100_SW1ABC_SETP(11750);
|
||||
|
||||
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= vddarm;
|
||||
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
|
||||
|
||||
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(11750);
|
||||
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
|
||||
|
||||
finish_anatop_bypass();
|
||||
printf("switch to ldo_bypass mode!\n");
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = PHYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
/*CD pin*/
|
||||
MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
||||
/* AR8031 PHY Reset. For arm2 board, silder the resistance */
|
||||
MX6_PAD_QSPI1A_SS0_B__GPIO4_IO_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec1(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
|
||||
|
||||
/* Reset AR8031 PHY */
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 22) , 0);
|
||||
udelay(500);
|
||||
gpio_set_value(IMX_GPIO_NR(4, 22), 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
|
||||
#define QSPI_PAD_CTRL1 \
|
||||
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
|
||||
|
||||
#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm)
|
||||
|
||||
static iomux_v3_cfg_t const quadspi_pads[] = {
|
||||
MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
|
||||
};
|
||||
|
||||
int board_qspi_init(void)
|
||||
{
|
||||
/* Set the iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
|
||||
|
||||
/* Set the clock */
|
||||
enable_qspi_clk(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
{USDHC3_BASE_ADDR},
|
||||
{USDHC4_BASE_ADDR},
|
||||
};
|
||||
|
||||
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
|
||||
|
||||
int board_mmc_get_env_dev(int dev_no)
|
||||
{
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
dev_no -= 2;
|
||||
#else
|
||||
dev_no--;
|
||||
#endif
|
||||
|
||||
return dev_no;
|
||||
}
|
||||
|
||||
int mmc_map_to_kernel_blk(int dev_no)
|
||||
{
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
return dev_no + 2;
|
||||
#else
|
||||
return dev_no + 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = 1; /*always present */
|
||||
break;
|
||||
case USDHC3_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
||||
break;
|
||||
case USDHC4_BASE_ADDR:
|
||||
ret = 1; /*always present */
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 SD3 (SDB)
|
||||
* mmc1 eMMC
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
gpio_direction_input(USDHC3_CD_GPIO);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) than supported by the board\n", i + 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 SD2 (SDA)
|
||||
* mmc1 SD3 (SDB)
|
||||
* mmc2 eMMC
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
gpio_direction_input(USDHC3_CD_GPIO);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
break;
|
||||
case 2:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) than supported by the board\n", i + 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
iomux_v3_cfg_t const ecspi4_pads[] = {
|
||||
MX6_PAD_SD2_CLK__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA3__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_SD2_CMD__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA2__GPIO6_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void setup_spinor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(ecspi4_pads,
|
||||
ARRAY_SIZE(ecspi4_pads));
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 10), 0);
|
||||
}
|
||||
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||
{
|
||||
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(6, 10)) : -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
iomux_v3_cfg_t eimnor_pads[] = {
|
||||
MX6_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
|
||||
MX6_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
|
||||
MX6_PAD_NAND_CE0_B__WEIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
|
||||
MX6_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
};
|
||||
static void eimnor_cs_setup(void)
|
||||
{
|
||||
writel(0x00000120, WEIM_BASE_ADDR + 0x090);
|
||||
writel(0x00610089, WEIM_BASE_ADDR + 0x000);
|
||||
writel(0x00000001, WEIM_BASE_ADDR + 0x004);
|
||||
writel(0x1c022000, WEIM_BASE_ADDR + 0x008);
|
||||
writel(0x00000000, WEIM_BASE_ADDR + 0x00c);
|
||||
writel(0x1404a38e, WEIM_BASE_ADDR + 0x010);
|
||||
}
|
||||
|
||||
static void setup_eimnor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(eimnor_pads,
|
||||
ARRAY_SIZE(eimnor_pads));
|
||||
|
||||
eimnor_cs_setup();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
iomux_v3_cfg_t gpmi_pads[] = {
|
||||
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
|
||||
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
};
|
||||
|
||||
static void setup_gpmi_nand(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
/* config gpmi nand iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
|
||||
|
||||
setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
|
||||
MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
|
||||
MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
|
||||
|
||||
/* enable apbh clock gating */
|
||||
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_fec1();
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
if (ret)
|
||||
printf("FEC1 MXC: %s:failed\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
|
||||
int ret;
|
||||
unsigned char value = 1;
|
||||
|
||||
/* clear gpr1[13], gpr1[17] to select anatop clock */
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
|
||||
|
||||
ret = enable_fec_anatop_clock(0, ENET_125MHZ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
#ifdef CONFIG_FEC_ENABLE_MAX7322
|
||||
/* release max7322 from reset */
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 22) , 1);
|
||||
|
||||
/* This is needed to drive the pads to 1.8V instead of 1.5V */
|
||||
i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS);
|
||||
|
||||
if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) {
|
||||
/* Write 0x1 to enable O0 output, this device has no addr */
|
||||
/* hence addr length is 0 */
|
||||
value = 0x1;
|
||||
if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1))
|
||||
printf("MAX7322 write failed\n");
|
||||
} else {
|
||||
printf("MAX7322 Not found\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
#ifdef CONFIG_FEC_ENABLE_MAX7322
|
||||
/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
|
||||
Phy control debug reg 0 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
#endif
|
||||
|
||||
/* rgmii tx clock delay enable */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
#define USB_OTHERREGS_OFFSET 0x800
|
||||
#define UCTRL_PWR_POL (1 << 9)
|
||||
|
||||
iomux_v3_cfg_t const usb_otg_pads[] = {
|
||||
/*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/
|
||||
MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_usb(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
|
||||
ARRAY_SIZE(usb_otg_pads));
|
||||
}
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
return USB_INIT_HOST;
|
||||
}
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
u32 *usbnc_usb_ctrl;
|
||||
|
||||
if (port >= 1)
|
||||
return -EINVAL;
|
||||
|
||||
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
||||
port * 4);
|
||||
|
||||
/* Set Power polarity */
|
||||
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
setup_spinor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
setup_eimnor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
setup_gpmi_nand();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
board_qspi_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
setup_usb();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
||||
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
||||
{"emmc", MAKE_CFGVAL(0x60, 0x38, 0x00, 0x00)},
|
||||
{"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
|
||||
{"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)},
|
||||
{"nand", MAKE_CFGVAL(0x80, 0x00, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
#ifdef CONFIG_MX6SX_14x14
|
||||
puts("Board: MX6SX 14x14 ARM2\n");
|
||||
#else
|
||||
puts("Board: MX6SX 17x17 ARM2\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
277
board/freescale/mx6sx_17x17_arm2/plugin.S
Normal file
277
board/freescale/mx6sx_17x17_arm2/plugin.S
Normal file
@ -0,0 +1,277 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx6sx_17x17_ddr3_evk_ddr_setting
|
||||
ldr r0, =IOMUXC_BASE_ADDR
|
||||
ldr r1, =0x000c0000
|
||||
str r1, [r0, #0x618]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x5fc]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x32c]
|
||||
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x300]
|
||||
str r1, [r0, #0x2fc]
|
||||
str r1, [r0, #0x5f4]
|
||||
str r1, [r0, #0x340]
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x320]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x310]
|
||||
str r1, [r0, #0x314]
|
||||
str r1, [r0, #0x614]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x5f8]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x330]
|
||||
str r1, [r0, #0x334]
|
||||
str r1, [r0, #0x338]
|
||||
str r1, [r0, #0x33c]
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x608]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x60c]
|
||||
str r1, [r0, #0x610]
|
||||
str r1, [r0, #0x61c]
|
||||
str r1, [r0, #0x620]
|
||||
str r1, [r0, #0x2ec]
|
||||
str r1, [r0, #0x2f0]
|
||||
str r1, [r0, #0x2f4]
|
||||
str r1, [r0, #0x2f8]
|
||||
|
||||
ldr r0, =MMDC_P0_BASE_ADDR
|
||||
ldr r2, =0xa1390003
|
||||
str r2, [r0, #0x800]
|
||||
ldr r2, =0x00270025
|
||||
str r2, [r0, #0x80c]
|
||||
ldr r2, =0x001B001E
|
||||
str r2, [r0, #0x810]
|
||||
ldr r2, =0x4144013C
|
||||
str r2, [r0, #0x83c]
|
||||
ldr r2, =0x01300128
|
||||
str r2, [r0, #0x840]
|
||||
ldr r2, =0x4044464A
|
||||
str r2, [r0, #0x848]
|
||||
ldr r2, =0x3A383C34
|
||||
str r2, [r0, #0x850]
|
||||
|
||||
ldr r2, =0x33333333
|
||||
str r2, [r0, #0x81c]
|
||||
str r2, [r0, #0x820]
|
||||
str r2, [r0, #0x824]
|
||||
str r2, [r0, #0x828]
|
||||
|
||||
ldr r2, =0x00000800
|
||||
str r2, [r0, #0x8b8]
|
||||
ldr r2, =0x0002002d
|
||||
str r2, [r0, #0x004]
|
||||
ldr r2, =0x00333030
|
||||
str r2, [r0, #0x008]
|
||||
ldr r2, =0x676b52f3
|
||||
str r2, [r0, #0x00c]
|
||||
ldr r2, =0xb66d8b63
|
||||
str r2, [r0, #0x010]
|
||||
ldr r2, =0x01ff00db
|
||||
str r2, [r0, #0x014]
|
||||
ldr r2, =0x00011740
|
||||
str r2, [r0, #0x018]
|
||||
ldr r2, =0x00008000
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x000026d2
|
||||
str r2, [r0, #0x02c]
|
||||
ldr r2, =0x006b1023
|
||||
str r2, [r0, #0x030]
|
||||
ldr r2, =0x0000005f
|
||||
str r2, [r0, #0x040]
|
||||
ldr r2, =0x84190000
|
||||
str r2, [r0, #0x000]
|
||||
ldr r2, =0x04008032
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x00008033
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x00068031
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x05208030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x04008040
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x00000800
|
||||
str r2, [r0, #0x020]
|
||||
ldr r2, =0x00011117
|
||||
str r2, [r0, #0x818]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x01c]
|
||||
|
||||
.endm
|
||||
.macro imx6_clock_gating
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0xffffffff
|
||||
str r1, [r0, #0x068]
|
||||
str r1, [r0, #0x06c]
|
||||
str r1, [r0, #0x070]
|
||||
str r1, [r0, #0x074]
|
||||
str r1, [r0, #0x078]
|
||||
str r1, [r0, #0x07c]
|
||||
str r1, [r0, #0x080]
|
||||
str r1, [r0, #0x084]
|
||||
.endm
|
||||
|
||||
.macro imx6_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx6sx_14x14_lpddr2_arm2_ddr_setting
|
||||
ldr r0, =IOMUXC_BASE_ADDR
|
||||
ldr r1, =0x00080000
|
||||
str r1, [r0, #0x618]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x5fc]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x32c]
|
||||
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x300]
|
||||
str r1, [r0, #0x2fc]
|
||||
str r1, [r0, #0x5f4]
|
||||
str r1, [r0, #0x340]
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x320]
|
||||
str r1, [r0, #0x310]
|
||||
str r1, [r0, #0x314]
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x614]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x5f8]
|
||||
ldr r1, =0x00003028
|
||||
str r1, [r0, #0x330]
|
||||
str r1, [r0, #0x334]
|
||||
str r1, [r0, #0x338]
|
||||
str r1, [r0, #0x33c]
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x608]
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x60c]
|
||||
str r1, [r0, #0x610]
|
||||
str r1, [r0, #0x61c]
|
||||
str r1, [r0, #0x620]
|
||||
str r1, [r0, #0x2ec]
|
||||
str r1, [r0, #0x2f0]
|
||||
str r1, [r0, #0x2f4]
|
||||
str r1, [r0, #0x2f8]
|
||||
|
||||
ldr r0, =MMDC_P0_BASE_ADDR
|
||||
ldr r2, =0x00008000
|
||||
str r2, [r0, #0x1c]
|
||||
ldr r2, =0x1b4700c7
|
||||
str r2, [r0, #0x85c]
|
||||
ldr r2, =0xa1390003
|
||||
str r2, [r0, #0x800]
|
||||
ldr r2, =0x00380000
|
||||
str r2, [r0, #0x890]
|
||||
ldr r2, =0x00000800
|
||||
str r2, [r0, #0x8b8]
|
||||
|
||||
ldr r2, =0x33333333
|
||||
str r2, [r0, #0x81c]
|
||||
str r2, [r0, #0x820]
|
||||
str r2, [r0, #0x824]
|
||||
str r2, [r0, #0x828]
|
||||
|
||||
ldr r2, =0x51111111
|
||||
str r2, [r0, #0x82c]
|
||||
str r2, [r0, #0x830]
|
||||
str r2, [r0, #0x834]
|
||||
str r2, [r0, #0x838]
|
||||
|
||||
ldr r2, =0x42424244
|
||||
str r2, [r0, #0x848]
|
||||
ldr r2, =0x2E30322E
|
||||
str r2, [r0, #0x850]
|
||||
ldr r2, =0x2492244A
|
||||
str r2, [r0, #0x8c0]
|
||||
ldr r2, =0x20000000
|
||||
str r2, [r0, #0x83c]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x840]
|
||||
ldr r2, =0x00000800
|
||||
str r2, [r0, #0x8b8]
|
||||
|
||||
ldr r2, =0x33374133
|
||||
str r2, [r0, #0x00c]
|
||||
ldr r2, =0x00020024
|
||||
str r2, [r0, #0x004]
|
||||
ldr r2, =0x00100A42
|
||||
str r2, [r0, #0x010]
|
||||
ldr r2, =0x00000093
|
||||
str r2, [r0, #0x014]
|
||||
ldr r2, =0x00001748
|
||||
str r2, [r0, #0x018]
|
||||
ldr r2, =0x0f9f26d2
|
||||
str r2, [r0, #0x02c]
|
||||
ldr r2, =0x0000020e
|
||||
str r2, [r0, #0x030]
|
||||
ldr r2, =0x00190778
|
||||
str r2, [r0, #0x038]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x008]
|
||||
ldr r2, =0x0000004f
|
||||
str r2, [r0, #0x040]
|
||||
ldr r2, =0xc3110000
|
||||
str r2, [r0, #0x000]
|
||||
|
||||
ldr r2, =0x003f8030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0xff0a8030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x82018030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x04028030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x01038030
|
||||
str r2, [r0, #0x01c]
|
||||
|
||||
ldr r2, =0x003f8038
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0xff0a8038
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x82018038
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x04028038
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x01038038
|
||||
str r2, [r0, #0x01c]
|
||||
|
||||
ldr r2, =0x00001800
|
||||
str r2, [r0, #0x020]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x818]
|
||||
ldr r2, =0xa1310003
|
||||
str r2, [r0, #0x800]
|
||||
ldr r2, =0x00025576
|
||||
str r2, [r0, #0x004]
|
||||
ldr r2, =0x00011006
|
||||
str r2, [r0, #0x404]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x01c]
|
||||
.endm
|
||||
|
||||
.macro imx6_ddr_setting
|
||||
#if defined(CONFIG_MX6SX_14x14) && defined (CONFIG_LPDDR)
|
||||
imx6sx_14x14_lpddr2_arm2_ddr_setting
|
||||
#else
|
||||
imx6sx_17x17_ddr3_evk_ddr_setting
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx6_plugin.S>
|
||||
12
board/freescale/mx6sx_19x19_arm2/Kconfig
Normal file
12
board/freescale/mx6sx_19x19_arm2/Kconfig
Normal file
@ -0,0 +1,12 @@
|
||||
if TARGET_MX6SX_19X19_ARM2
|
||||
|
||||
config SYS_BOARD
|
||||
default "mx6sx_19x19_arm2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "mx6sx_19x19_arm2"
|
||||
|
||||
endif
|
||||
10
board/freescale/mx6sx_19x19_arm2/Makefile
Normal file
10
board/freescale/mx6sx_19x19_arm2/Makefile
Normal file
@ -0,0 +1,10 @@
|
||||
# (C) Copyright 2014 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := mx6sx_19x19_arm2.o
|
||||
|
||||
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
|
||||
$(obj)/plugin.bin: $(obj)/plugin.o
|
||||
$(OBJCOPY) -O binary --gap-fill 0xff $< $@
|
||||
161
board/freescale/mx6sx_19x19_arm2/imximage.cfg
Normal file
161
board/freescale/mx6sx_19x19_arm2/imximage.cfg
Normal file
@ -0,0 +1,161 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
BOOT_FROM qspi
|
||||
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
|
||||
BOOT_FROM nor
|
||||
#else
|
||||
BOOT_FROM sd
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USE_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx6sx_19x19_arm2/plugin.bin 0x00907000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
/* Enable all clocks */
|
||||
DATA 4 0x020c4068 0xffffffff
|
||||
DATA 4 0x020c406c 0xffffffff
|
||||
DATA 4 0x020c4070 0xffffffff
|
||||
DATA 4 0x020c4074 0xffffffff
|
||||
DATA 4 0x020c4078 0xffffffff
|
||||
DATA 4 0x020c407c 0xffffffff
|
||||
DATA 4 0x020c4080 0xffffffff
|
||||
DATA 4 0x020c4084 0xffffffff
|
||||
|
||||
/* IOMUX */
|
||||
/* DDR IO TYPE */
|
||||
DATA 4 0x020e0618 0x000c0000
|
||||
DATA 4 0x020e05fc 0x00000000
|
||||
|
||||
/* CLOCK */
|
||||
DATA 4 0x020e032c 0x00000030
|
||||
|
||||
/* ADDRESS */
|
||||
DATA 4 0x020e0300 0x00000030
|
||||
DATA 4 0x020e02fc 0x00000030
|
||||
DATA 4 0x020e05f4 0x00000030
|
||||
|
||||
/* CONTROL */
|
||||
DATA 4 0x020e0340 0x00000030
|
||||
|
||||
DATA 4 0x020e0320 0x00000000
|
||||
DATA 4 0x020e0310 0x00000030
|
||||
DATA 4 0x020e0314 0x00000030
|
||||
DATA 4 0x020e0614 0x00000030
|
||||
|
||||
/* DATA STROBE */
|
||||
DATA 4 0x020e05f8 0x00020000
|
||||
DATA 4 0x020e0330 0x00000030
|
||||
DATA 4 0x020e0334 0x00000030
|
||||
DATA 4 0x020e0338 0x00000030
|
||||
DATA 4 0x020e033c 0x00000030
|
||||
|
||||
/* DATA */
|
||||
DATA 4 0x020e0608 0x00020000
|
||||
DATA 4 0x020e060c 0x00000030
|
||||
DATA 4 0x020e0610 0x00000030
|
||||
DATA 4 0x020e061c 0x00000030
|
||||
DATA 4 0x020e0620 0x00000030
|
||||
DATA 4 0x020e02ec 0x00000030
|
||||
DATA 4 0x020e02f0 0x00000030
|
||||
DATA 4 0x020e02f4 0x00000030
|
||||
DATA 4 0x020e02f8 0x00000030
|
||||
|
||||
/* Calibrations */
|
||||
/* ZQ */
|
||||
DATA 4 0x021b0800 0xa1390003
|
||||
/* write leveling */
|
||||
DATA 4 0x021b080c 0x002C003D
|
||||
DATA 4 0x021b0810 0x00110046
|
||||
|
||||
/* DQS Read Gate */
|
||||
DATA 4 0x021b083c 0x4160016C
|
||||
DATA 4 0x021b0840 0x013C016C
|
||||
|
||||
/* Read/Write Delay */
|
||||
DATA 4 0x021b0848 0x46424446
|
||||
DATA 4 0x021b0850 0x3A3C3C3A
|
||||
|
||||
DATA 4 0x021b08c0 0x2492244A
|
||||
|
||||
/* read data bit delay */
|
||||
DATA 4 0x021b081c 0x33333333
|
||||
DATA 4 0x021b0820 0x33333333
|
||||
DATA 4 0x021b0824 0x33333333
|
||||
DATA 4 0x021b0828 0x33333333
|
||||
|
||||
/* Complete calibration by forced measurment */
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
|
||||
/* MMDC init */
|
||||
/* in DDR3, 64-bit mode, only MMDC0 is initiated */
|
||||
DATA 4 0x021b0004 0x0002002d
|
||||
DATA 4 0x021b0008 0x00333030
|
||||
DATA 4 0x021b000c 0x676b52f3
|
||||
DATA 4 0x021b0010 0xb66d8b63
|
||||
DATA 4 0x021b0014 0x01ff00db
|
||||
DATA 4 0x021b0018 0x00011740
|
||||
DATA 4 0x021b001c 0x00008000
|
||||
DATA 4 0x021b002c 0x000026d2
|
||||
DATA 4 0x021b0030 0x006b1023
|
||||
DATA 4 0x021b0040 0x0000007f
|
||||
DATA 4 0x021b0000 0x85190000
|
||||
|
||||
/* Initialize CS0: MT41K256M16HA-125 */
|
||||
/* MR2 */
|
||||
DATA 4 0x021b001c 0x04008032
|
||||
/* MR3 */
|
||||
DATA 4 0x021b001c 0x00008033
|
||||
/* MR1 */
|
||||
DATA 4 0x021b001c 0x00068031
|
||||
/* MR0 */
|
||||
DATA 4 0x021b001c 0x05208030
|
||||
/* DDR device ZQ calibration */
|
||||
DATA 4 0x021b001c 0x04008040
|
||||
|
||||
/* final DDR setup, before operation start */
|
||||
DATA 4 0x021b0020 0x00000800
|
||||
DATA 4 0x021b0818 0x00022227
|
||||
DATA 4 0x021b0004 0x0002556d
|
||||
DATA 4 0x021b0404 0x00011006
|
||||
DATA 4 0x021b001c 0x00000000
|
||||
|
||||
#endif
|
||||
141
board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg
Normal file
141
board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg
Normal file
@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
BOOT_FROM qspi
|
||||
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
|
||||
BOOT_FROM nor
|
||||
#else
|
||||
BOOT_FROM sd
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USE_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx6sx_19x19_arm2/plugin.bin 0x00907000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x020c4068 0xffffffff
|
||||
DATA 4 0x020c406c 0xffffffff
|
||||
DATA 4 0x020c4070 0xffffffff
|
||||
DATA 4 0x020c4074 0xffffffff
|
||||
DATA 4 0x020c4078 0xffffffff
|
||||
DATA 4 0x020c407c 0xffffffff
|
||||
DATA 4 0x020c4080 0xffffffff
|
||||
DATA 4 0x020c4084 0xffffffff
|
||||
|
||||
DATA 4 0x020e0618 0x00080000
|
||||
DATA 4 0x020e05fc 0x00000000
|
||||
DATA 4 0x020e032c 0x00000030
|
||||
|
||||
DATA 4 0x020e0300 0x00000028
|
||||
DATA 4 0x020e02fc 0x00000028
|
||||
DATA 4 0x020e05f4 0x00000028
|
||||
DATA 4 0x020e0340 0x00000028
|
||||
DATA 4 0x020e0320 0x00000000
|
||||
DATA 4 0x020e0310 0x00000000
|
||||
DATA 4 0x020e0314 0x00000000
|
||||
DATA 4 0x020e0614 0x00000028
|
||||
|
||||
DATA 4 0x020e05f8 0x00020000
|
||||
DATA 4 0x020e0330 0x00003028
|
||||
DATA 4 0x020e0334 0x00003028
|
||||
DATA 4 0x020e0338 0x00003028
|
||||
DATA 4 0x020e033c 0x00003028
|
||||
DATA 4 0x020e0608 0x00020000
|
||||
DATA 4 0x020e060c 0x00000028
|
||||
DATA 4 0x020e0610 0x00000028
|
||||
DATA 4 0x020e061c 0x00000028
|
||||
DATA 4 0x020e0620 0x00000028
|
||||
DATA 4 0x020e02ec 0x00000028
|
||||
DATA 4 0x020e02f0 0x00000028
|
||||
DATA 4 0x020e02f4 0x00000028
|
||||
DATA 4 0x020e02f8 0x00000028
|
||||
|
||||
DATA 4 0x021b001c 0x00008000
|
||||
DATA 4 0x021b085c 0x1b4700c7
|
||||
DATA 4 0x021b0800 0xa1390003
|
||||
DATA 4 0x021b0890 0x00380000
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
DATA 4 0x021b081c 0x33333333
|
||||
DATA 4 0x021b0820 0x33333333
|
||||
DATA 4 0x021b0824 0x33333333
|
||||
DATA 4 0x021b0828 0x33333333
|
||||
DATA 4 0x021b082c 0x51111111
|
||||
DATA 4 0x021b0830 0x51111111
|
||||
DATA 4 0x021b0834 0x51111111
|
||||
DATA 4 0x021b0838 0x51111111
|
||||
DATA 4 0x021b0848 0x42424244
|
||||
DATA 4 0x021b0850 0x2E30322E
|
||||
DATA 4 0x021b08c0 0x2492244A
|
||||
DATA 4 0x021b083c 0x20000000
|
||||
DATA 4 0x021b0840 0x00000000
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
|
||||
DATA 4 0x021b000c 0x33374133
|
||||
DATA 4 0x021b0004 0x00020024
|
||||
DATA 4 0x021b0010 0x00100A42
|
||||
DATA 4 0x021b0014 0x00000093
|
||||
DATA 4 0x021b0018 0x00001748
|
||||
DATA 4 0x021b002c 0x0f9f26d2
|
||||
DATA 4 0x021b0030 0x0000020e
|
||||
DATA 4 0x021b0038 0x00190778
|
||||
DATA 4 0x021b0008 0x00000000
|
||||
DATA 4 0x021b0040 0x0000004f
|
||||
DATA 4 0x021b0000 0xc3110000
|
||||
|
||||
DATA 4 0x021b001c 0x003f8030
|
||||
DATA 4 0x021b001c 0xff0a8030
|
||||
DATA 4 0x021b001c 0x82018030
|
||||
DATA 4 0x021b001c 0x04028030
|
||||
DATA 4 0x021b001c 0x01038030
|
||||
|
||||
DATA 4 0x021b001c 0x003f8038
|
||||
DATA 4 0x021b001c 0xff0a8038
|
||||
DATA 4 0x021b001c 0x82018038
|
||||
DATA 4 0x021b001c 0x04028038
|
||||
DATA 4 0x021b001c 0x01038038
|
||||
|
||||
DATA 4 0x021b0020 0x00001800
|
||||
DATA 4 0x021b0818 0x00000000
|
||||
DATA 4 0x021b0800 0xa1310003
|
||||
DATA 4 0x021b0004 0x00025576
|
||||
DATA 4 0x021b0404 0x00011006
|
||||
DATA 4 0x021b001c 0x00000000
|
||||
|
||||
#endif
|
||||
756
board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c
Normal file
756
board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c
Normal file
@ -0,0 +1,756 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <common.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <mmc.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
#include <i2c.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
#endif
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pfuze100_pmic.h>
|
||||
#include "../common/pfuze.h"
|
||||
#include <usb.h>
|
||||
#include <usb/ehci-fsl.h>
|
||||
#include <asm/imx-common/video.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE)
|
||||
|
||||
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
|
||||
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
|
||||
|
||||
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
||||
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_SRE_FAST)
|
||||
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
|
||||
|
||||
#define SPI_PAD_CTRL (PAD_CTL_HYS | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm)
|
||||
|
||||
#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define I2C_PMIC 0
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
/* I2C1 for PMIC */
|
||||
struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 0),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 1),
|
||||
},
|
||||
};
|
||||
|
||||
/* I2C2 */
|
||||
struct i2c_pads_info i2c_pad_info2 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 2),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 3),
|
||||
},
|
||||
};
|
||||
|
||||
static struct pmic *pfuze;
|
||||
int power_init_board(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
int ret;
|
||||
|
||||
pfuze = pfuze_common_init(I2C_PMIC);
|
||||
if (!pfuze)
|
||||
return -ENODEV;
|
||||
|
||||
ret = pfuze_mode_init(pfuze, APS_PFM);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* set SW1AB staby volatage 0.975V */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®);
|
||||
reg &= ~0x3f;
|
||||
reg |= PFUZE100_SW1ABC_SETP(9750);
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
|
||||
|
||||
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®);
|
||||
reg &= ~0xc0;
|
||||
reg |= 0x40;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
|
||||
|
||||
/* set SW1C staby volatage 0.975V */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®);
|
||||
reg &= ~0x3f;
|
||||
reg |= PFUZE100_SW1ABC_SETP(9750);
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
|
||||
|
||||
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®);
|
||||
reg &= ~0xc0;
|
||||
reg |= 0x40;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LDO_BYPASS_CHECK
|
||||
void ldo_mode_set(int ldo_bypass)
|
||||
{
|
||||
unsigned int value;
|
||||
int is_400M;
|
||||
u32 vddarm;
|
||||
struct pmic *p = pfuze;
|
||||
|
||||
if (!p) {
|
||||
printf("No PMIC found!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* switch to ldo_bypass mode */
|
||||
if (ldo_bypass) {
|
||||
prep_anatop_bypass();
|
||||
/* decrease VDDARM to 1.275V */
|
||||
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(12750);
|
||||
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
|
||||
|
||||
/* decrease VDDSOC to 1.3V */
|
||||
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(13000);
|
||||
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
|
||||
|
||||
is_400M = set_anatop_bypass(1);
|
||||
if (is_400M)
|
||||
vddarm = PFUZE100_SW1ABC_SETP(10750);
|
||||
else
|
||||
vddarm = PFUZE100_SW1ABC_SETP(11750);
|
||||
|
||||
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= vddarm;
|
||||
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
|
||||
|
||||
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(11750);
|
||||
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
|
||||
|
||||
finish_anatop_bypass();
|
||||
printf("switch to ldo_bypass mode!\n");
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = PHYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
||||
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
static iomux_v3_cfg_t const lvds_ctrl_pads[] = {
|
||||
/* CABC enable */
|
||||
MX6_PAD_KEY_ROW1__GPIO2_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
|
||||
/* Use GPIO for Brightness adjustment, duty cycle = period */
|
||||
MX6_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const lcd_pads[] = {
|
||||
MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
|
||||
/* Use GPIO for Brightness adjustment, duty cycle = period */
|
||||
MX6_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
|
||||
struct lcd_panel_info_t {
|
||||
unsigned int lcdif_base_addr;
|
||||
int depth;
|
||||
void (*enable)(struct lcd_panel_info_t const *dev);
|
||||
struct fb_videomode mode;
|
||||
};
|
||||
|
||||
void do_enable_lvds(struct display_info_t const *dev)
|
||||
{
|
||||
enable_lcdif_clock(dev->bus);
|
||||
enable_lvds_bridge(dev->bus);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
|
||||
ARRAY_SIZE(lvds_ctrl_pads));
|
||||
|
||||
/* Enable CABC */
|
||||
gpio_direction_output(IMX_GPIO_NR(2, 16) , 1);
|
||||
|
||||
/* Set Brightness to high */
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
|
||||
}
|
||||
|
||||
void do_enable_parallel_lcd(struct display_info_t const *dev)
|
||||
{
|
||||
enable_lcdif_clock(dev->bus);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
|
||||
/* Power up the LCD */
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
|
||||
|
||||
/* Set Brightness to high */
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
|
||||
}
|
||||
|
||||
struct display_info_t const displays[] = {{
|
||||
.bus = LCDIF2_BASE_ADDR,
|
||||
.addr = 0,
|
||||
.pixfmt = 18,
|
||||
.enable = do_enable_lvds,
|
||||
.detect = NULL,
|
||||
.mode = {
|
||||
.name = "Hannstar-XGA",
|
||||
.xres = 1024,
|
||||
.yres = 768,
|
||||
.pixclock = 15385,
|
||||
.left_margin = 220,
|
||||
.right_margin = 40,
|
||||
.upper_margin = 21,
|
||||
.lower_margin = 7,
|
||||
.hsync_len = 60,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} }, {
|
||||
.bus = MX6SX_LCDIF1_BASE_ADDR,
|
||||
.pixfmt = 24,
|
||||
.addr = 0,
|
||||
.detect = NULL,
|
||||
.enable = do_enable_parallel_lcd,
|
||||
.mode = {
|
||||
.name = "MCIMX28LCD",
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 29850,
|
||||
.left_margin = 89,
|
||||
.right_margin = 164,
|
||||
.upper_margin = 23,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
||||
/* AR8031 PHY Reset. For arm2 board, silder the resistance */
|
||||
MX6_PAD_SD4_DATA4__GPIO6_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec1(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
|
||||
#define QSPI_PAD_CTRL1 \
|
||||
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
|
||||
|
||||
#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm)
|
||||
|
||||
static iomux_v3_cfg_t const quadspi_pads[] = {
|
||||
MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
|
||||
};
|
||||
|
||||
int board_qspi_init(void)
|
||||
{
|
||||
/* Set the iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
|
||||
|
||||
/* Set the clock */
|
||||
enable_qspi_clk(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
||||
{USDHC1_BASE_ADDR, 0, 4},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
return 1; /* Assume boot SD always present */
|
||||
}
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 USDHC1 (SDA)
|
||||
*/
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
||||
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
iomux_v3_cfg_t const ecspi4_pads[] = {
|
||||
MX6_PAD_SD2_CLK__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA3__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_SD2_CMD__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA2__GPIO6_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void setup_spinor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(ecspi4_pads,
|
||||
ARRAY_SIZE(ecspi4_pads));
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 10), 0);
|
||||
}
|
||||
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||
{
|
||||
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(6, 10)) : -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
iomux_v3_cfg_t eimnor_pads[] = {
|
||||
MX6_PAD_QSPI1A_SCLK__WEIM_DATA_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1A_SS0_B__WEIM_DATA_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1A_SS1_B__WEIM_DATA_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1A_DATA3__WEIM_DATA_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1A_DATA2__WEIM_DATA_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1A_DATA1__WEIM_DATA_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1A_DATA0__WEIM_DATA_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1A_DQS__WEIM_DATA_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1B_SCLK__WEIM_DATA_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1B_SS0_B__WEIM_DATA_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1B_SS1_B__WEIM_DATA_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1B_DATA3__WEIM_DATA_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1B_DATA2__WEIM_DATA_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1B_DATA1__WEIM_DATA_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1B_DATA0__WEIM_DATA_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
MX6_PAD_QSPI1B_DQS__WEIM_DATA_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
|
||||
|
||||
MX6_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
|
||||
MX6_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD1_DATA05__WEIM_ADDR_26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
|
||||
MX6_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
|
||||
MX6_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
};
|
||||
static void eimnor_cs_setup(void)
|
||||
{
|
||||
writel(0x00000120, WEIM_BASE_ADDR + 0x090);
|
||||
writel(0x00010181, WEIM_BASE_ADDR + 0x000);
|
||||
writel(0x00000001, WEIM_BASE_ADDR + 0x004);
|
||||
writel(0x0a020000, WEIM_BASE_ADDR + 0x008);
|
||||
writel(0x0000c000, WEIM_BASE_ADDR + 0x00c);
|
||||
writel(0x0804a240, WEIM_BASE_ADDR + 0x010);
|
||||
}
|
||||
|
||||
static void setup_eimnor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(eimnor_pads,
|
||||
ARRAY_SIZE(eimnor_pads));
|
||||
|
||||
eimnor_cs_setup();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
iomux_v3_cfg_t gpmi_pads[] = {
|
||||
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
|
||||
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
};
|
||||
|
||||
static void setup_gpmi_nand(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
/* config gpmi nand iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
|
||||
|
||||
setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
|
||||
MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
|
||||
MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
|
||||
|
||||
/* enable apbh clock gating */
|
||||
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
|
||||
int ret;
|
||||
unsigned char value = 1;
|
||||
|
||||
/* clear gpr1[13], gpr1[17] to select anatop clock */
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
|
||||
|
||||
ret = enable_fec_anatop_clock(0, ENET_125MHZ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Reset AR8031 PHY */
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 18) , 0);
|
||||
udelay(500);
|
||||
gpio_set_value(IMX_GPIO_NR(6, 18), 1);
|
||||
|
||||
#ifdef CONFIG_FEC_ENABLE_MAX7322
|
||||
/* This is needed to drive the pads to 1.8V instead of 1.5V */
|
||||
i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS);
|
||||
|
||||
if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) {
|
||||
/* Write 0x1 to enable O0 output, this device has no addr */
|
||||
/* hence addr length is 0 */
|
||||
value = 0x1;
|
||||
if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1))
|
||||
printf("MAX7322 write failed\n");
|
||||
} else {
|
||||
printf("MAX7322 Not found\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_fec1();
|
||||
setup_fec();
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
if (ret)
|
||||
printf("FEC1 MXC: %s:failed\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
#ifdef CONFIG_FEC_ENABLE_MAX7322
|
||||
/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
|
||||
Phy control debug reg 0 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
#endif
|
||||
|
||||
/* rgmii tx clock delay enable */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
#define USB_OTHERREGS_OFFSET 0x800
|
||||
#define UCTRL_PWR_POL (1 << 9)
|
||||
|
||||
iomux_v3_cfg_t const usb_otg_pads[] = {
|
||||
MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_usb(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
|
||||
ARRAY_SIZE(usb_otg_pads));
|
||||
}
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
if (port == 1)
|
||||
return USB_INIT_HOST;
|
||||
else
|
||||
return usb_phy_mode(port);
|
||||
}
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
u32 *usbnc_usb_ctrl;
|
||||
|
||||
if (port >= 1)
|
||||
return -EINVAL;
|
||||
|
||||
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
||||
port * 4);
|
||||
|
||||
/* Set Power polarity */
|
||||
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
setup_spinor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
setup_eimnor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
setup_gpmi_nand();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
setup_usb();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
board_qspi_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
|
||||
{"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
|
||||
{"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)},
|
||||
{"eimnor", MAKE_CFGVAL(0x00, 0x80, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX6SX 19x19 ARM2\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
285
board/freescale/mx6sx_19x19_arm2/plugin.S
Normal file
285
board/freescale/mx6sx_19x19_arm2/plugin.S
Normal file
@ -0,0 +1,285 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx6sx_19x19_ddr3_arm2_ddr_setting
|
||||
ldr r0, =IOMUXC_BASE_ADDR
|
||||
ldr r1, =0x000c0000
|
||||
str r1, [r0, #0x618]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x5fc]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x32c]
|
||||
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x300]
|
||||
str r1, [r0, #0x2fc]
|
||||
str r1, [r0, #0x5f4]
|
||||
str r1, [r0, #0x340]
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x320]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x310]
|
||||
str r1, [r0, #0x314]
|
||||
str r1, [r0, #0x614]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x5f8]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x330]
|
||||
str r1, [r0, #0x334]
|
||||
str r1, [r0, #0x338]
|
||||
str r1, [r0, #0x33c]
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x608]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x60c]
|
||||
str r1, [r0, #0x610]
|
||||
str r1, [r0, #0x61c]
|
||||
str r1, [r0, #0x620]
|
||||
str r1, [r0, #0x2ec]
|
||||
str r1, [r0, #0x2f0]
|
||||
str r1, [r0, #0x2f4]
|
||||
str r1, [r0, #0x2f8]
|
||||
|
||||
ldr r0, =MMDC_P0_BASE_ADDR
|
||||
ldr r2, =0xa1390003
|
||||
str r2, [r0, #0x800]
|
||||
ldr r2, =0x002C003D
|
||||
str r2, [r0, #0x80c]
|
||||
ldr r2, =0x00110046
|
||||
str r2, [r0, #0x810]
|
||||
ldr r2, =0x4160016C
|
||||
str r2, [r0, #0x83c]
|
||||
ldr r2, =0x013C016C
|
||||
str r2, [r0, #0x840]
|
||||
ldr r2, =0x46424446
|
||||
str r2, [r0, #0x848]
|
||||
ldr r2, =0x3A3C3C3A
|
||||
str r2, [r0, #0x850]
|
||||
ldr r2, =0x2492244A
|
||||
str r2, [r0, #0x8c0]
|
||||
|
||||
ldr r2, =0x33333333
|
||||
str r2, [r0, #0x81c]
|
||||
str r2, [r0, #0x820]
|
||||
str r2, [r0, #0x824]
|
||||
str r2, [r0, #0x828]
|
||||
|
||||
ldr r2, =0x00000800
|
||||
str r2, [r0, #0x8b8]
|
||||
ldr r2, =0x0002002d
|
||||
str r2, [r0, #0x004]
|
||||
ldr r2, =0x00333030
|
||||
str r2, [r0, #0x008]
|
||||
ldr r2, =0x676b52f3
|
||||
str r2, [r0, #0x00c]
|
||||
ldr r2, =0xb66d8b63
|
||||
str r2, [r0, #0x010]
|
||||
ldr r2, =0x01ff00db
|
||||
str r2, [r0, #0x014]
|
||||
ldr r2, =0x00011740
|
||||
str r2, [r0, #0x018]
|
||||
ldr r2, =0x00008000
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x000026d2
|
||||
str r2, [r0, #0x02c]
|
||||
ldr r2, =0x006b1023
|
||||
str r2, [r0, #0x030]
|
||||
ldr r2, =0x0000007f
|
||||
str r2, [r0, #0x040]
|
||||
ldr r2, =0x85190000
|
||||
str r2, [r0, #0x000]
|
||||
ldr r2, =0x04008032
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x00008033
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x00068031
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x05208030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x04008040
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x00000800
|
||||
str r2, [r0, #0x020]
|
||||
ldr r2, =0x00022227
|
||||
str r2, [r0, #0x818]
|
||||
ldr r2, =0x0002556d
|
||||
str r2, [r0, #0x004]
|
||||
ldr r2, =0x00011006
|
||||
str r2, [r0, #0x404]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x01c]
|
||||
|
||||
.endm
|
||||
|
||||
.macro imx6sx_19x19_lpddr2_arm2_ddr_setting
|
||||
ldr r0, =IOMUXC_BASE_ADDR
|
||||
ldr r1, =0x00080000
|
||||
str r1, [r0, #0x618]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x5fc]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x32c]
|
||||
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x300]
|
||||
str r1, [r0, #0x2fc]
|
||||
str r1, [r0, #0x5f4]
|
||||
str r1, [r0, #0x340]
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x320]
|
||||
str r1, [r0, #0x310]
|
||||
str r1, [r0, #0x314]
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x614]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x5f8]
|
||||
ldr r1, =0x00003028
|
||||
str r1, [r0, #0x330]
|
||||
str r1, [r0, #0x334]
|
||||
str r1, [r0, #0x338]
|
||||
str r1, [r0, #0x33c]
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x608]
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x60c]
|
||||
str r1, [r0, #0x610]
|
||||
str r1, [r0, #0x61c]
|
||||
str r1, [r0, #0x620]
|
||||
str r1, [r0, #0x2ec]
|
||||
str r1, [r0, #0x2f0]
|
||||
str r1, [r0, #0x2f4]
|
||||
str r1, [r0, #0x2f8]
|
||||
|
||||
ldr r0, =MMDC_P0_BASE_ADDR
|
||||
ldr r2, =0x00008000
|
||||
str r2, [r0, #0x1c]
|
||||
ldr r2, =0x1b4700c7
|
||||
str r2, [r0, #0x85c]
|
||||
ldr r2, =0xa1390003
|
||||
str r2, [r0, #0x800]
|
||||
ldr r2, =0x00380000
|
||||
str r2, [r0, #0x890]
|
||||
ldr r2, =0x00000800
|
||||
str r2, [r0, #0x8b8]
|
||||
|
||||
ldr r2, =0x33333333
|
||||
str r2, [r0, #0x81c]
|
||||
str r2, [r0, #0x820]
|
||||
str r2, [r0, #0x824]
|
||||
str r2, [r0, #0x828]
|
||||
|
||||
ldr r2, =0x51111111
|
||||
str r2, [r0, #0x82c]
|
||||
str r2, [r0, #0x830]
|
||||
str r2, [r0, #0x834]
|
||||
str r2, [r0, #0x838]
|
||||
|
||||
ldr r2, =0x42424244
|
||||
str r2, [r0, #0x848]
|
||||
ldr r2, =0x2E30322E
|
||||
str r2, [r0, #0x850]
|
||||
ldr r2, =0x2492244A
|
||||
str r2, [r0, #0x8c0]
|
||||
ldr r2, =0x20000000
|
||||
str r2, [r0, #0x83c]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x840]
|
||||
ldr r2, =0x00000800
|
||||
str r2, [r0, #0x8b8]
|
||||
|
||||
ldr r2, =0x33374133
|
||||
str r2, [r0, #0x00c]
|
||||
ldr r2, =0x00020024
|
||||
str r2, [r0, #0x004]
|
||||
ldr r2, =0x00100A42
|
||||
str r2, [r0, #0x010]
|
||||
ldr r2, =0x00000093
|
||||
str r2, [r0, #0x014]
|
||||
ldr r2, =0x00001748
|
||||
str r2, [r0, #0x018]
|
||||
ldr r2, =0x0f9f26d2
|
||||
str r2, [r0, #0x02c]
|
||||
ldr r2, =0x0000020e
|
||||
str r2, [r0, #0x030]
|
||||
ldr r2, =0x00190778
|
||||
str r2, [r0, #0x038]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x008]
|
||||
ldr r2, =0x0000004f
|
||||
str r2, [r0, #0x040]
|
||||
ldr r2, =0xc3110000
|
||||
str r2, [r0, #0x000]
|
||||
|
||||
ldr r2, =0x003f8030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0xff0a8030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x82018030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x04028030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x01038030
|
||||
str r2, [r0, #0x01c]
|
||||
|
||||
ldr r2, =0x003f8038
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0xff0a8038
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x82018038
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x04028038
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x01038038
|
||||
str r2, [r0, #0x01c]
|
||||
|
||||
ldr r2, =0x00001800
|
||||
str r2, [r0, #0x020]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x818]
|
||||
ldr r2, =0xa1310003
|
||||
str r2, [r0, #0x800]
|
||||
ldr r2, =0x00025576
|
||||
str r2, [r0, #0x004]
|
||||
ldr r2, =0x00011006
|
||||
str r2, [r0, #0x404]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x01c]
|
||||
|
||||
.endm
|
||||
.macro imx6_clock_gating
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0xffffffff
|
||||
str r1, [r0, #0x068]
|
||||
str r1, [r0, #0x06c]
|
||||
str r1, [r0, #0x070]
|
||||
str r1, [r0, #0x074]
|
||||
str r1, [r0, #0x078]
|
||||
str r1, [r0, #0x07c]
|
||||
str r1, [r0, #0x080]
|
||||
str r1, [r0, #0x084]
|
||||
.endm
|
||||
|
||||
.macro imx6_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx6_ddr_setting
|
||||
#if defined (CONFIG_LPDDR2)
|
||||
imx6sx_19x19_lpddr2_arm2_ddr_setting
|
||||
#else
|
||||
imx6sx_19x19_ddr3_arm2_ddr_setting
|
||||
#endif
|
||||
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx6_plugin.S>
|
||||
12
board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig
Normal file
12
board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig
Normal file
@ -0,0 +1,12 @@
|
||||
if TARGET_MX6UL_14X14_DDR3_ARM2
|
||||
|
||||
config SYS_BOARD
|
||||
default "mx6ul_14x14_ddr3_arm2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "mx6ul_14x14_ddr3_arm2"
|
||||
|
||||
endif
|
||||
10
board/freescale/mx6ul_14x14_ddr3_arm2/Makefile
Normal file
10
board/freescale/mx6ul_14x14_ddr3_arm2/Makefile
Normal file
@ -0,0 +1,10 @@
|
||||
# (C) Copyright 2015 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := mx6ul_14x14_ddr3_arm2.o
|
||||
|
||||
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
|
||||
$(obj)/plugin.bin: $(obj)/plugin.o
|
||||
$(OBJCOPY) -O binary --gap-fill 0xff $< $@
|
||||
115
board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg
Normal file
115
board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg
Normal file
@ -0,0 +1,115 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
BOOT_FROM qspi
|
||||
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
|
||||
BOOT_FROM nor
|
||||
#else
|
||||
BOOT_FROM sd
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USE_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin 0x00907000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x020c4068 0xffffffff
|
||||
DATA 4 0x020c406c 0xffffffff
|
||||
DATA 4 0x020c4070 0xffffffff
|
||||
DATA 4 0x020c4074 0xffffffff
|
||||
DATA 4 0x020c4078 0xffffffff
|
||||
DATA 4 0x020c407c 0xffffffff
|
||||
DATA 4 0x020c4080 0xffffffff
|
||||
DATA 4 0x020c4084 0xffffffff
|
||||
|
||||
DATA 4 0x020E04B4 0x000C0000
|
||||
DATA 4 0x020E04AC 0x00000000
|
||||
DATA 4 0x020E027C 0x00000030
|
||||
DATA 4 0x020E0250 0x00000030
|
||||
DATA 4 0x020E024C 0x00000030
|
||||
DATA 4 0x020E0490 0x00000030
|
||||
DATA 4 0x020E0288 0x00000030
|
||||
DATA 4 0x020E0270 0x00000000
|
||||
DATA 4 0x020E0260 0x00000030
|
||||
DATA 4 0x020E0264 0x00000030
|
||||
DATA 4 0x020E04A0 0x00000030
|
||||
DATA 4 0x020E0494 0x00020000
|
||||
DATA 4 0x020E0280 0x00000030
|
||||
DATA 4 0x020E0284 0x00000030
|
||||
DATA 4 0x020E04B0 0x00020000
|
||||
DATA 4 0x020E0498 0x00000030
|
||||
DATA 4 0x020E04A4 0x00000030
|
||||
DATA 4 0x020E0244 0x00000030
|
||||
DATA 4 0x020E0248 0x00000030
|
||||
|
||||
DATA 4 0x021B001C 0x00008000
|
||||
DATA 4 0x021B0800 0xA1390003
|
||||
DATA 4 0x021B080C 0x0013000F
|
||||
DATA 4 0x021B083C 0x415D0159
|
||||
DATA 4 0x021B0848 0x4040484F
|
||||
DATA 4 0x021B0850 0x40405247
|
||||
DATA 4 0x021B081C 0x33333333
|
||||
DATA 4 0x021B0820 0x33333333
|
||||
DATA 4 0x021B082C 0xf3333333
|
||||
DATA 4 0x021B0830 0xf3333333
|
||||
DATA 4 0x021B08C0 0x00922012
|
||||
DATA 4 0x021B08b8 0x00000800
|
||||
DATA 4 0x021B0004 0x0002002D
|
||||
DATA 4 0x021B0008 0x1B333000
|
||||
DATA 4 0x021B000C 0x676B54B3
|
||||
DATA 4 0x021B0010 0xB68E0A83
|
||||
DATA 4 0x021B0014 0x01FF00DB
|
||||
DATA 4 0x021B0018 0x00211740
|
||||
DATA 4 0x021B001C 0x00008000
|
||||
DATA 4 0x021B002C 0x000026D2
|
||||
DATA 4 0x021B0030 0x006B1023
|
||||
DATA 4 0x021B0040 0x0000005F
|
||||
DATA 4 0x021B0000 0x85180000
|
||||
DATA 4 0x021B001C 0x02008032
|
||||
DATA 4 0x021B001C 0x00008033
|
||||
DATA 4 0x021B001C 0x00048031
|
||||
DATA 4 0x021B001C 0x15208030
|
||||
DATA 4 0x021B001C 0x04008040
|
||||
DATA 4 0x021B0020 0x00000800
|
||||
DATA 4 0x021B0818 0x00000227
|
||||
DATA 4 0x021B0004 0x0002552D
|
||||
DATA 4 0x021B0404 0x00011006
|
||||
DATA 4 0x021B001C 0x00000000
|
||||
#endif
|
||||
918
board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c
Normal file
918
board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c
Normal file
@ -0,0 +1,918 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <i2c.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/fb.h>
|
||||
#include <miiphy.h>
|
||||
#include <mmc.h>
|
||||
#include <mxsfb.h>
|
||||
#include <netdev.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pfuze100_pmic.h>
|
||||
#include "../common/pfuze.h"
|
||||
#include <usb.h>
|
||||
#include <usb/ehci-fsl.h>
|
||||
#include <asm/imx-common/video.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
|
||||
PAD_CTL_SPEED_HIGH | \
|
||||
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE)
|
||||
|
||||
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
|
||||
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
|
||||
|
||||
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
||||
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_SRE_FAST)
|
||||
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
|
||||
|
||||
#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define SPI_PAD_CTRL (PAD_CTL_HYS | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
/* I2C1 for PMIC and EEPROM */
|
||||
struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
/* conflict with usb_otg2_pwr */
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 2),
|
||||
},
|
||||
.sda = {
|
||||
/* conflict with usb_otg2_oc */
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 3),
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = PHYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK
|
||||
static iomux_v3_cfg_t const usdhc1_emmc_pads[] = {
|
||||
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
/*
|
||||
* The following 4 pins conflicts with qspi.
|
||||
* You can comment out the following 4 pins and change
|
||||
* {USDHC1_BASE_ADDR, 0, 8} -> {USDHC1_BASE_ADDR, 0, 4}
|
||||
* to make emmc and qspi coexists.
|
||||
*/
|
||||
MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
/* Default NO WP for emmc, since we use pull down */
|
||||
MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP),
|
||||
/* RST_B */
|
||||
MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
#else
|
||||
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
||||
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
/* VSELECT */
|
||||
MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
/* CD */
|
||||
MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* RST_B */
|
||||
MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SYS_USE_NAND)
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||
MX6_PAD_CSI_VSYNC__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_CSI_HSYNC__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
#ifdef CONFIG_MX6UL_DDR3_ARM2_USDHC2_REWORK
|
||||
#if defined(CONFIG_SYS_USE_EIMNOR) || defined(CONFIG_SYS_USE_SPINOR)
|
||||
#error "Pin conflicts!"
|
||||
#endif
|
||||
/* conflict with eimnor/spinor */
|
||||
MX6_PAD_CSI_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
#endif
|
||||
/* VSELECT */
|
||||
MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
/* CD */
|
||||
MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/*
|
||||
* Pin conflicts with NAND ALE, if want to test nand,
|
||||
* Connect R169(B), disconnect R169(A).
|
||||
*
|
||||
* RST_B
|
||||
*/
|
||||
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
static iomux_v3_cfg_t const nand_pads[] = {
|
||||
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
};
|
||||
|
||||
static void setup_gpmi_nand(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
/* config gpmi nand iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
|
||||
|
||||
setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
|
||||
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
|
||||
|
||||
/* enable apbh clock gating */
|
||||
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
/* pin conflicts with eim nor */
|
||||
static iomux_v3_cfg_t const ecspi1_pads[] = {
|
||||
MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA04__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA07__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
|
||||
/* CS Pin */
|
||||
MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_spinor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
|
||||
}
|
||||
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||
{
|
||||
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 26)) : -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
/* pin conflicts with nand usdhc2 lcd enet */
|
||||
static iomux_v3_cfg_t const eimnor_pads[] = {
|
||||
MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA01__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA02__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA03__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA04__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA05__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA06__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA07__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA00__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA01__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA02__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA03__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA04__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA05__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA06__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA07__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_ALE__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_CE1_B__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_CMD__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_CLK__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA0__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA1__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA2__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA3__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_ENET2_RX_ER__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_ENET2_RX_EN__EIM_ADDR26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
|
||||
MX6_PAD_CSI_PIXCLK__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_VSYNC__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
|
||||
MX6_PAD_LCD_DATA08__EIM_DATA00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA09__EIM_DATA01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA10__EIM_DATA02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA11__EIM_DATA03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA12__EIM_DATA04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA13__EIM_DATA05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA14__EIM_DATA06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA15__EIM_DATA07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA16__EIM_DATA08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA17__EIM_DATA09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA18__EIM_DATA10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA19__EIM_DATA11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA20__EIM_DATA12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA21__EIM_DATA13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA22__EIM_DATA14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA23__EIM_DATA15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
|
||||
MX6_PAD_CSI_MCLK__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DQS__EIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void eimnor_cs_setup(void)
|
||||
{
|
||||
writel(0x00000120, WEIM_BASE_ADDR + 0x090);
|
||||
writel(0x00010181, WEIM_BASE_ADDR + 0x000);
|
||||
writel(0x00000001, WEIM_BASE_ADDR + 0x004);
|
||||
writel(0x0a020000, WEIM_BASE_ADDR + 0x008);
|
||||
writel(0x0000c000, WEIM_BASE_ADDR + 0x00c);
|
||||
writel(0x0804a240, WEIM_BASE_ADDR + 0x010);
|
||||
}
|
||||
|
||||
static void setup_eimnor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
|
||||
|
||||
eimnor_cs_setup();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
/*
|
||||
* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
|
||||
* be used for ENET1 or ENET2, cannot be used for both.
|
||||
*/
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
|
||||
/* Pin conflicts with LCD PWM1 */
|
||||
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
/*
|
||||
* ALT5 mode is only valid when TAMPER pin is used for GPIO.
|
||||
* This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
|
||||
*
|
||||
* ENET1_RST
|
||||
*/
|
||||
MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const fec2_pads[] = {
|
||||
MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
||||
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
|
||||
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
||||
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
||||
MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec(int fec_id)
|
||||
{
|
||||
if (fec_id == 0) {
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_pads,
|
||||
ARRAY_SIZE(fec1_pads));
|
||||
gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
|
||||
udelay(50);
|
||||
gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
|
||||
} else {
|
||||
imx_iomux_v3_setup_multiple_pads(fec2_pads,
|
||||
ARRAY_SIZE(fec2_pads));
|
||||
gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
|
||||
udelay(50);
|
||||
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_USE_QSPI
|
||||
|
||||
#define QSPI_PAD_CTRL1 \
|
||||
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
|
||||
|
||||
static iomux_v3_cfg_t const quadspi_pads[] = {
|
||||
MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
|
||||
MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
};
|
||||
|
||||
int board_qspi_init(void)
|
||||
{
|
||||
/* Set the iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(quadspi_pads,
|
||||
ARRAY_SIZE(quadspi_pads));
|
||||
|
||||
/* Set the clock */
|
||||
enable_qspi_clk(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||
#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK
|
||||
/* If want to use qspi, should change to 4 bit width */
|
||||
{USDHC1_BASE_ADDR, 0, 8},
|
||||
#else
|
||||
{USDHC1_BASE_ADDR, 0, 4},
|
||||
#endif
|
||||
#if !defined(CONFIG_SYS_USE_NAND)
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
#endif
|
||||
};
|
||||
|
||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
|
||||
#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
|
||||
#define USDHC1_VSELECT IMX_GPIO_NR(1, 5)
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 17)
|
||||
#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK
|
||||
ret = 1;
|
||||
#else
|
||||
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
||||
#endif
|
||||
break;
|
||||
#if !defined(CONFIG_SYS_USE_NAND)
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
* mmc1 USDHC2
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads));
|
||||
#else
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
||||
gpio_direction_input(USDHC1_CD_GPIO);
|
||||
#endif
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
/* 3.3V */
|
||||
gpio_direction_output(USDHC1_VSELECT, 0);
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 1);
|
||||
break;
|
||||
#if !defined(CONFIG_SYS_USE_NAND)
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
static iomux_v3_cfg_t const lcd_pads[] = {
|
||||
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
|
||||
/*
|
||||
* PWM1, pin conflicts with ENET1_RX_DATA0
|
||||
* Use GPIO for Brightness adjustment, duty cycle = period.
|
||||
*/
|
||||
/* MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),*/
|
||||
};
|
||||
|
||||
struct lcd_panel_info_t {
|
||||
unsigned int lcdif_base_addr;
|
||||
int depth;
|
||||
void (*enable)(struct lcd_panel_info_t const *dev);
|
||||
struct fb_videomode mode;
|
||||
};
|
||||
|
||||
void do_enable_parallel_lcd(struct display_info_t const *dev)
|
||||
{
|
||||
enable_lcdif_clock(dev->bus);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
|
||||
/* Power up the LCD */
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
|
||||
|
||||
/* Set Brightness to high */
|
||||
/* gpio_direction_output(IMX_GPIO_NR(2, 0) , 1); */
|
||||
}
|
||||
|
||||
struct display_info_t const displays[] = {{
|
||||
.bus = MX6UL_LCDIF1_BASE_ADDR,
|
||||
.addr = 0,
|
||||
.pixfmt = 24,
|
||||
.detect = NULL,
|
||||
.enable = do_enable_parallel_lcd,
|
||||
.mode = {
|
||||
.name = "MCIMX28LCD",
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 29850,
|
||||
.left_margin = 89,
|
||||
.right_margin = 164,
|
||||
.upper_margin = 23,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_fec(CONFIG_FEC_ENET_DEV);
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
if (ret)
|
||||
printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_fec(int fec_id)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
int ret;
|
||||
|
||||
if (0 == fec_id) {
|
||||
/*
|
||||
* Use 50M anatop loopback REF_CLK1 for ENET1,
|
||||
* clear gpr1[13], set gpr1[17]
|
||||
*/
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
|
||||
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
|
||||
ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
} else {
|
||||
/* clk from phy, set gpr1[14], clear gpr1[18]*/
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
|
||||
IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
|
||||
}
|
||||
|
||||
enable_enet_clk(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (CONFIG_FEC_ENET_DEV == 0) {
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
|
||||
} else if (CONFIG_FEC_ENET_DEV == 1) {
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110);
|
||||
}
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_POWER
|
||||
#define I2C_PMIC 0
|
||||
static struct pmic *pfuze;
|
||||
int power_init_board(void)
|
||||
{
|
||||
int ret;
|
||||
u32 rev_id, value;
|
||||
|
||||
ret = power_pfuze100_init(I2C_PMIC);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pfuze = pmic_get("PFUZE100");
|
||||
if (!pfuze)
|
||||
return -ENODEV;
|
||||
|
||||
ret = pmic_probe(pfuze);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pfuze_mode_init(pfuze, APS_PFM);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
|
||||
pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
|
||||
printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
|
||||
|
||||
/*
|
||||
* Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
|
||||
* Configuration is F0.
|
||||
* Default VOLT:
|
||||
* VSNVS_VOLT | 3.0V
|
||||
* SW1AB | 1.375V
|
||||
* SW2 | 3.3V
|
||||
* SW3A | 1.5V
|
||||
* SW3B | 1.5V
|
||||
* VGEN1 | 1.5V
|
||||
* VGEN2 | 1.5V
|
||||
* VGEN3 | 2.5V
|
||||
* VGEN4 | 1.8V
|
||||
* VGEN5 | 2.8V
|
||||
* VGEN6 | 3.3V
|
||||
*
|
||||
* According to schematic, we need SW3A 1.35V, SW3B 3.3V,
|
||||
* VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
|
||||
* VGEN5 3.3V, VGEN6 3.0V.
|
||||
*
|
||||
* Here we just use the default VOLT, but not configure
|
||||
* them, when needed, configure them to our requested voltage.
|
||||
*/
|
||||
|
||||
/* set SW1AB standby volatage 0.975V */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(9750);
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
|
||||
|
||||
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
|
||||
value &= ~0xc0;
|
||||
value |= 0x40;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
|
||||
|
||||
/* Enable power of VGEN5 3V3 */
|
||||
pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value);
|
||||
value &= ~0x1F;
|
||||
value |= 0x1F;
|
||||
pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LDO_BYPASS_CHECK
|
||||
void ldo_mode_set(int ldo_bypass)
|
||||
{
|
||||
unsigned int value;
|
||||
int is_400M;
|
||||
u32 vddarm;
|
||||
|
||||
struct pmic *p = pfuze;
|
||||
|
||||
if (!p) {
|
||||
printf("No PMIC found!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* switch to ldo_bypass mode */
|
||||
if (ldo_bypass) {
|
||||
prep_anatop_bypass();
|
||||
/* decrease VDDARM to 1.275V */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(12750);
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
|
||||
|
||||
is_400M = set_anatop_bypass(1);
|
||||
if (is_400M)
|
||||
vddarm = PFUZE100_SW1ABC_SETP(10750);
|
||||
else
|
||||
vddarm = PFUZE100_SW1ABC_SETP(11750);
|
||||
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= vddarm;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
|
||||
|
||||
finish_anatop_bypass();
|
||||
|
||||
printf("switch to ldo_bypass mode!\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
/*
|
||||
* Because kernel set WDOG_B mux before pad with the commone pinctrl
|
||||
* framwork now and wdog reset will be triggered once set WDOG_B mux
|
||||
* with default pad setting, we set pad setting here to workaround this.
|
||||
* Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
|
||||
* as GPIO mux firstly here to workaround it.
|
||||
*
|
||||
* Here we can not set this, since SD1_RST_B conflicts with GWDOG.
|
||||
* We use SD1, so will not set WDOG pads, also GWDOG default is
|
||||
* DNP.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec(CONFIG_FEC_ENET_DEV);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
setup_spinor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
setup_gpmi_nand();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
setup_eimnor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_QSPI
|
||||
board_qspi_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
|
||||
{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX6UL 14X14 DDR3 ARM2\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
#define USB_OTHERREGS_OFFSET 0x800
|
||||
#define UCTRL_PWR_POL (1 << 9)
|
||||
iomux_v3_cfg_t const usb_otg1_pads[] = {
|
||||
MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
};
|
||||
|
||||
/*
|
||||
* Leave it here, but default configuration only supports 1 port now,
|
||||
* because we need sd1 and i2c1
|
||||
*/
|
||||
iomux_v3_cfg_t const usb_otg2_pads[] = {
|
||||
/* conflict with i2c1_scl */
|
||||
MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* conflict with sd1_vselect */
|
||||
MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
return usb_phy_mode(port);
|
||||
}
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
u32 *usbnc_usb_ctrl;
|
||||
|
||||
if (port > 1)
|
||||
return -EINVAL;
|
||||
|
||||
switch (port) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
|
||||
ARRAY_SIZE(usb_otg1_pads));
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
|
||||
ARRAY_SIZE(usb_otg2_pads));
|
||||
break;
|
||||
default:
|
||||
printf("MXC USB port %d not yet supported\n", port);
|
||||
return 1;
|
||||
}
|
||||
|
||||
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
||||
port * 4);
|
||||
|
||||
/* Set Power polarity */
|
||||
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
135
board/freescale/mx6ul_14x14_ddr3_arm2/plugin.S
Normal file
135
board/freescale/mx6ul_14x14_ddr3_arm2/plugin.S
Normal file
@ -0,0 +1,135 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx6ul_ddr3_arm2_setting
|
||||
ldr r0, =IOMUXC_BASE_ADDR
|
||||
ldr r1, =0x000C0000
|
||||
str r1, [r0, #0x4B4]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x4AC]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x27C]
|
||||
str r1, [r0, #0x250]
|
||||
str r1, [r0, #0x24C]
|
||||
str r1, [r0, #0x490]
|
||||
str r1, [r0, #0x288]
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x270]
|
||||
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x260]
|
||||
str r1, [r0, #0x264]
|
||||
str r1, [r0, #0x4A0]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x494]
|
||||
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x280]
|
||||
str r1, [r0, #0x284]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x4B0]
|
||||
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x498]
|
||||
str r1, [r0, #0x4A4]
|
||||
str r1, [r0, #0x244]
|
||||
str r1, [r0, #0x248]
|
||||
|
||||
ldr r0, =MMDC_P0_BASE_ADDR
|
||||
ldr r1, =0x00008000
|
||||
str r1, [r0, #0x1C]
|
||||
ldr r1, =0xA1390003
|
||||
str r1, [r0, #0x800]
|
||||
ldr r1, =0x0013000F
|
||||
str r1, [r0, #0x80C]
|
||||
ldr r1, =0x415D0159
|
||||
str r1, [r0, #0x83C]
|
||||
ldr r1, =0x4040484F
|
||||
str r1, [r0, #0x848]
|
||||
ldr r1, =0x40405247
|
||||
str r1, [r0, #0x850]
|
||||
ldr r1, =0x33333333
|
||||
str r1, [r0, #0x81C]
|
||||
str r1, [r0, #0x820]
|
||||
ldr r1, =0xF3333333
|
||||
str r1, [r0, #0x82C]
|
||||
str r1, [r0, #0x830]
|
||||
ldr r1, =0x00922012
|
||||
str r1, [r0, #0x8C0]
|
||||
ldr r1, =0x00000800
|
||||
str r1, [r0, #0x8B8]
|
||||
ldr r1, =0x0002002D
|
||||
str r1, [r0, #0x004]
|
||||
ldr r1, =0x1B333000
|
||||
str r1, [r0, #0x008]
|
||||
ldr r1, =0x676B54B3
|
||||
str r1, [r0, #0x00C]
|
||||
ldr r1, =0xB68E0A83
|
||||
str r1, [r0, #0x010]
|
||||
ldr r1, =0x01FF00DB
|
||||
str r1, [r0, #0x014]
|
||||
ldr r1, =0x00211740
|
||||
str r1, [r0, #0x018]
|
||||
ldr r1, =0x00008000
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x000026D2
|
||||
str r1, [r0, #0x02C]
|
||||
ldr r1, =0x006B1023
|
||||
str r1, [r0, #0x030]
|
||||
ldr r1, =0x0000005F
|
||||
str r1, [r0, #0x040]
|
||||
ldr r1, =0x85180000
|
||||
str r1, [r0, #0x000]
|
||||
ldr r1, =0x02008032
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x00008033
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x00048031
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x15208030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x04008040
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x00000800
|
||||
str r1, [r0, #0x020]
|
||||
ldr r1, =0x00000227
|
||||
str r1, [r0, #0x818]
|
||||
ldr r1, =0x0002552D
|
||||
str r1, [r0, #0x004]
|
||||
ldr r1, =0x00011006
|
||||
str r1, [r0, #0x404]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x01C]
|
||||
.endm
|
||||
|
||||
.macro imx6_clock_gating
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0xFFFFFFFF
|
||||
str r1, [r0, #0x68]
|
||||
str r1, [r0, #0x6C]
|
||||
str r1, [r0, #0x70]
|
||||
str r1, [r0, #0x74]
|
||||
str r1, [r0, #0x78]
|
||||
str r1, [r0, #0x7C]
|
||||
str r1, [r0, #0x80]
|
||||
str r1, [r0, #0x84]
|
||||
.endm
|
||||
|
||||
.macro imx6_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx6_ddr_setting
|
||||
imx6ul_ddr3_arm2_setting
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx6_plugin.S>
|
||||
12
board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig
Normal file
12
board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig
Normal file
@ -0,0 +1,12 @@
|
||||
if TARGET_MX6UL_14X14_LPDDR2_ARM2
|
||||
|
||||
config SYS_BOARD
|
||||
default "mx6ul_14x14_lpddr2_arm2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "mx6ul_14x14_lpddr2_arm2"
|
||||
|
||||
endif
|
||||
10
board/freescale/mx6ul_14x14_lpddr2_arm2/Makefile
Normal file
10
board/freescale/mx6ul_14x14_lpddr2_arm2/Makefile
Normal file
@ -0,0 +1,10 @@
|
||||
# (C) Copyright 2015 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := mx6ul_14x14_lpddr2_arm2.o
|
||||
|
||||
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
|
||||
$(obj)/plugin.bin: $(obj)/plugin.o
|
||||
$(OBJCOPY) -O binary --gap-fill 0xff $< $@
|
||||
121
board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg
Normal file
121
board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg
Normal file
@ -0,0 +1,121 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
BOOT_FROM qspi
|
||||
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
|
||||
BOOT_FROM nor
|
||||
#else
|
||||
BOOT_FROM sd
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USE_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx6ul_14x14_lpddr2_arm2/plugin.bin 0x00907000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x020c4068 0xffffffff
|
||||
DATA 4 0x020c406c 0xffffffff
|
||||
DATA 4 0x020c4070 0xffffffff
|
||||
DATA 4 0x020c4074 0xffffffff
|
||||
DATA 4 0x020c4078 0xffffffff
|
||||
DATA 4 0x020c407c 0xffffffff
|
||||
DATA 4 0x020c4080 0xffffffff
|
||||
DATA 4 0x020c4084 0xffffffff
|
||||
|
||||
DATA 4 0x020E04B4 0x00080000
|
||||
DATA 4 0x020E04AC 0x00000000
|
||||
DATA 4 0x020E027C 0x00000028
|
||||
DATA 4 0x020E0250 0x00000028
|
||||
DATA 4 0x020E024C 0x00000028
|
||||
DATA 4 0x020E0490 0x00000028
|
||||
DATA 4 0x020E0288 0x00000028
|
||||
DATA 4 0x020E0270 0x00000000
|
||||
DATA 4 0x020E0260 0x00000000
|
||||
DATA 4 0x020E0264 0x00000000
|
||||
DATA 4 0x020E04A0 0x00000028
|
||||
DATA 4 0x020E0494 0x00020000
|
||||
DATA 4 0x020E0280 0x00003028
|
||||
DATA 4 0x020E0284 0x00003028
|
||||
DATA 4 0x020E04B0 0x00020000
|
||||
DATA 4 0x020E0498 0x00000028
|
||||
DATA 4 0x020E04A4 0x00000028
|
||||
DATA 4 0x020E0244 0x00000028
|
||||
DATA 4 0x020E0248 0x00000028
|
||||
|
||||
DATA 4 0x021B001C 0x00008000
|
||||
DATA 4 0x021B085C 0x1b4700c7
|
||||
DATA 4 0x021B0800 0xA1390003
|
||||
DATA 4 0x021B0890 0x00470000
|
||||
DATA 4 0x021B08b8 0x00000800
|
||||
|
||||
DATA 4 0x021B081C 0x33333333
|
||||
DATA 4 0x021B0820 0x33333333
|
||||
DATA 4 0x021B082C 0xf3333333
|
||||
DATA 4 0x021B0830 0xf3333333
|
||||
DATA 4 0x021B083C 0x20000000
|
||||
DATA 4 0x021B0848 0x4040484F
|
||||
DATA 4 0x021B0850 0x40405247
|
||||
DATA 4 0x021B08C0 0x00922012
|
||||
DATA 4 0x021B08b8 0x00000800
|
||||
|
||||
DATA 4 0x021B0004 0x00020012
|
||||
DATA 4 0x021B0008 0x00000000
|
||||
DATA 4 0x021B000C 0x33374133
|
||||
DATA 4 0x021B0010 0x00100A82
|
||||
DATA 4 0x021B0038 0x00170557
|
||||
DATA 4 0x021B0014 0x00000093
|
||||
DATA 4 0x021B0018 0x00001748
|
||||
DATA 4 0x021B001C 0x00008000
|
||||
DATA 4 0x021B002C 0x0F9F0682
|
||||
DATA 4 0x021B0030 0x009F0010
|
||||
DATA 4 0x021B0040 0x00000047
|
||||
DATA 4 0x021B0000 0x83100000
|
||||
DATA 4 0x021B001C 0x003F8030
|
||||
DATA 4 0x021B001C 0xFF0A8030
|
||||
DATA 4 0x021B001C 0x82018030
|
||||
DATA 4 0x021B001C 0x04028030
|
||||
DATA 4 0x021B001C 0x01038030
|
||||
DATA 4 0x021B0020 0x00001800
|
||||
DATA 4 0x021B0818 0x00000000
|
||||
DATA 4 0x021B0800 0xA1310003
|
||||
DATA 4 0x021B0004 0x00025576
|
||||
DATA 4 0x021B0404 0x00011006
|
||||
DATA 4 0x021B001C 0x00000000
|
||||
#endif
|
||||
@ -0,0 +1,890 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <i2c.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/fb.h>
|
||||
#include <miiphy.h>
|
||||
#include <mmc.h>
|
||||
#include <mxsfb.h>
|
||||
#include <netdev.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pfuze100_pmic.h>
|
||||
#include "../common/pfuze.h"
|
||||
#include <usb.h>
|
||||
#include <usb/ehci-fsl.h>
|
||||
#include <asm/imx-common/video.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
|
||||
PAD_CTL_SPEED_HIGH | \
|
||||
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE)
|
||||
|
||||
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
|
||||
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
|
||||
|
||||
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
||||
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_SRE_FAST)
|
||||
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
|
||||
|
||||
#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define SPI_PAD_CTRL (PAD_CTL_HYS | \
|
||||
PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
/* I2C1 for PMIC and EEPROM */
|
||||
struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
/* conflict with usb_otg2_pwr */
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 2),
|
||||
},
|
||||
.sda = {
|
||||
/* conflict with usb_otg2_oc */
|
||||
.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 3),
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = PHYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
|
||||
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
||||
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
#if !defined(CONFIG_SYS_USE_NAND)
|
||||
MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
#endif
|
||||
|
||||
MX6_PAD_CSI_DATA04__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
/* VSELECT */
|
||||
MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
/* CD */
|
||||
MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* RST_B */
|
||||
MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#if !defined(CONFIG_SYS_USE_NAND)
|
||||
|
||||
#ifdef CONFIG_MX6UL_LPDDR2_ARM2_USDHC2_REWORK
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
MX6_PAD_UART1_CTS_B__USDHC2_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
/* VSELECT */
|
||||
MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
/* CD */
|
||||
MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* RST_B */
|
||||
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
#else
|
||||
static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
|
||||
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
/* Default NO WP for emmc, since we use pull down */
|
||||
MX6_PAD_UART1_CTS_B__USDHC2_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP),
|
||||
|
||||
/* RST_B */
|
||||
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
static iomux_v3_cfg_t const nand_pads[] = {
|
||||
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
||||
};
|
||||
|
||||
static void setup_gpmi_nand(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
/* config gpmi nand iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
|
||||
|
||||
setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
|
||||
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
|
||||
|
||||
/* enable apbh clock gating */
|
||||
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
/* pin conflicts with eim nor */
|
||||
static iomux_v3_cfg_t const ecspi2_pads[] = {
|
||||
MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
|
||||
/* CS Pin */
|
||||
MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_spinor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 22), 0);
|
||||
}
|
||||
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||
{
|
||||
return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 22)) : -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
/* pin conflicts with ECSIP2, USDHC1, USDCH2, NAND, SIM, ENET2 */
|
||||
static iomux_v3_cfg_t const eimnor_pads[] = {
|
||||
MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_ALE__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_CE1_B__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_CMD__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_CLK__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA0__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA1__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA2__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA3__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_ENET2_RX_ER__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
|
||||
MX6_PAD_CSI_PIXCLK__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_VSYNC__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_HSYNC__EIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
|
||||
MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA01__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA02__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA03__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA04__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA05__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA06__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_CSI_DATA07__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA00__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA01__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA02__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA03__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA04__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA05__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA06__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA07__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
|
||||
MX6_PAD_CSI_MCLK__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_WP_B__EIM_BCLK | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX6_PAD_NAND_DQS__EIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void eimnor_cs_setup(void)
|
||||
{
|
||||
writel(0x00000120, WEIM_BASE_ADDR + 0x090);
|
||||
writel(0x00610089, WEIM_BASE_ADDR + 0x000);
|
||||
writel(0x00000001, WEIM_BASE_ADDR + 0x004);
|
||||
writel(0x1c022000, WEIM_BASE_ADDR + 0x008);
|
||||
writel(0x00000000, WEIM_BASE_ADDR + 0x00c);
|
||||
writel(0x1404a38e, WEIM_BASE_ADDR + 0x010);
|
||||
}
|
||||
|
||||
static void setup_eimnor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
|
||||
|
||||
eimnor_cs_setup();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
/*
|
||||
* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
|
||||
* be used for ENET1 or ENET2, cannot be used for both.
|
||||
*/
|
||||
static iomux_v3_cfg_t const fec2_pads[] = {
|
||||
MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
|
||||
|
||||
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
/*
|
||||
* ALT5 mode is only valid when TAMPER pin is used for GPIO.
|
||||
* This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
|
||||
*
|
||||
* ENET2_RST
|
||||
*/
|
||||
MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
/* Conflict with UART1 */
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
||||
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
||||
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
||||
MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec(int fec_id)
|
||||
{
|
||||
if (fec_id == 0) {
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_pads,
|
||||
ARRAY_SIZE(fec1_pads));
|
||||
gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
|
||||
udelay(50);
|
||||
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
|
||||
} else {
|
||||
imx_iomux_v3_setup_multiple_pads(fec2_pads,
|
||||
ARRAY_SIZE(fec2_pads));
|
||||
gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
|
||||
udelay(50);
|
||||
gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_USE_QSPI
|
||||
|
||||
#define QSPI_PAD_CTRL1 \
|
||||
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
|
||||
|
||||
static iomux_v3_cfg_t const quadspi_pads[] = {
|
||||
MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
|
||||
MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
};
|
||||
|
||||
int board_qspi_init(void)
|
||||
{
|
||||
/* Set the iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(quadspi_pads,
|
||||
ARRAY_SIZE(quadspi_pads));
|
||||
|
||||
/* Set the clock */
|
||||
enable_qspi_clk(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
#if !defined(CONFIG_SYS_USE_NAND)
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||
{USDHC1_BASE_ADDR, 0, 1},
|
||||
{USDHC2_BASE_ADDR, 0, 8},
|
||||
};
|
||||
#else
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
||||
{USDHC1_BASE_ADDR, 0, 4},
|
||||
};
|
||||
#endif
|
||||
|
||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 26)
|
||||
#define USDHC1_PWR_GPIO IMX_GPIO_NR(4, 11)
|
||||
#define USDHC1_VSELECT IMX_GPIO_NR(1, 5)
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 19)
|
||||
#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
||||
break;
|
||||
#if !defined(CONFIG_SYS_USE_NAND)
|
||||
case USDHC2_BASE_ADDR:
|
||||
#ifdef CONFIG_MX6UL_LPDDR2_ARM2_USDHC2_REWORK
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
#else
|
||||
ret = 1;
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
* mmc1 USDHC2
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
||||
gpio_direction_input(USDHC1_CD_GPIO);
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 1);
|
||||
break;
|
||||
#if !defined(CONFIG_SYS_USE_NAND)
|
||||
case 1:
|
||||
#ifdef CONFIG_MX6UL_LPDDR2_ARM2_USDHC2_REWORK
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
#else
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers (%d)"
|
||||
" than supported by the board\n", i + 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
static iomux_v3_cfg_t const lcd_pads[] = {
|
||||
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
|
||||
/*
|
||||
* PWM1, pin conflicts with ENET1_RX_DATA0
|
||||
* Use GPIO for Brightness adjustment, duty cycle = period.
|
||||
*/
|
||||
MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
struct lcd_panel_info_t {
|
||||
unsigned int lcdif_base_addr;
|
||||
int depth;
|
||||
void (*enable)(struct lcd_panel_info_t const *dev);
|
||||
struct fb_videomode mode;
|
||||
};
|
||||
|
||||
void do_enable_parallel_lcd(struct display_info_t const *dev)
|
||||
{
|
||||
enable_lcdif_clock(dev->bus);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
|
||||
/* Power up the LCD */
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
|
||||
|
||||
/* Set Brightness to high */
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
|
||||
}
|
||||
|
||||
struct display_info_t const displays[] = {{
|
||||
.bus = MX6UL_LCDIF1_BASE_ADDR,
|
||||
.addr = 0,
|
||||
.pixfmt = 24,
|
||||
.detect = NULL,
|
||||
.enable = do_enable_parallel_lcd,
|
||||
.mode = {
|
||||
.name = "MCIMX28LCD",
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 29850,
|
||||
.left_margin = 89,
|
||||
.right_margin = 164,
|
||||
.upper_margin = 23,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_fec(CONFIG_FEC_ENET_DEV);
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
if (ret)
|
||||
printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_fec(int fec_id)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
int ret;
|
||||
|
||||
if (1 == fec_id) {
|
||||
/*
|
||||
* Use 50M anatop loopback REF_CLK2 for ENET2,
|
||||
* clear gpr1[14], set gpr1[18]
|
||||
*/
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
|
||||
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
|
||||
ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
} else {
|
||||
/* clk from phy, set gpr1[13], clear gpr1[17]*/
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
|
||||
IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK);
|
||||
}
|
||||
|
||||
enable_enet_clk(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (CONFIG_FEC_ENET_DEV == 1) {
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
|
||||
} else if (CONFIG_FEC_ENET_DEV == 0) {
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110);
|
||||
}
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_POWER
|
||||
#define I2C_PMIC 0
|
||||
static struct pmic *pfuze;
|
||||
int power_init_board(void)
|
||||
{
|
||||
int ret;
|
||||
u32 rev_id, value;
|
||||
|
||||
ret = power_pfuze100_init(I2C_PMIC);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pfuze = pmic_get("PFUZE100");
|
||||
if (!pfuze)
|
||||
return -ENODEV;
|
||||
|
||||
ret = pmic_probe(pfuze);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pfuze_mode_init(pfuze, APS_PFM);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
|
||||
pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
|
||||
printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
|
||||
|
||||
/*
|
||||
* Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
|
||||
* Configuration is F0.
|
||||
* Default VOLT:
|
||||
* VSNVS_VOLT | 3.0V
|
||||
* SW1AB | 1.375V
|
||||
* SW2 | 3.3V
|
||||
* SW3A | 1.5V
|
||||
* SW3B | 1.5V
|
||||
* VGEN1 | 1.5V
|
||||
* VGEN2 | 1.5V
|
||||
* VGEN3 | 2.5V
|
||||
* VGEN4 | 1.8V
|
||||
* VGEN5 | 2.8V
|
||||
* VGEN6 | 3.3V
|
||||
*
|
||||
* According to schematic, we need SW3A 1.35V, SW3B 3.3V,
|
||||
* VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
|
||||
* VGEN5 3.3V, VGEN6 3.0V.
|
||||
*
|
||||
* Here we just use the default VOLT, but not configure
|
||||
* them, when needed, configure them to our requested voltage.
|
||||
*/
|
||||
|
||||
/* set SW1AB standby volatage 1.3V */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(13000);
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
|
||||
|
||||
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
|
||||
value &= ~0xc0;
|
||||
value |= 0x40;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
|
||||
|
||||
/* Enable power of VGEN5 3V3 */
|
||||
pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value);
|
||||
value &= ~0x1F;
|
||||
value |= 0x1F;
|
||||
pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LDO_BYPASS_CHECK
|
||||
void ldo_mode_set(int ldo_bypass)
|
||||
{
|
||||
unsigned int value;
|
||||
int is_400M;
|
||||
u32 vddarm;
|
||||
|
||||
struct pmic *p = pfuze;
|
||||
|
||||
if (!p) {
|
||||
printf("No PMIC found!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* switch to ldo_bypass mode */
|
||||
if (ldo_bypass) {
|
||||
prep_anatop_bypass();
|
||||
/* decrease VDDARM to 1.275V */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(12750);
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
|
||||
|
||||
is_400M = set_anatop_bypass(1);
|
||||
if (is_400M)
|
||||
vddarm = PFUZE100_SW1ABC_SETP(10750);
|
||||
else
|
||||
vddarm = PFUZE100_SW1ABC_SETP(11750);
|
||||
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= vddarm;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
|
||||
|
||||
finish_anatop_bypass();
|
||||
|
||||
printf("switch to ldo_bypass mode!\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec(CONFIG_FEC_ENET_DEV);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
setup_spinor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
setup_gpmi_nand();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
/*
|
||||
* This function should be invoked after setup_fec,
|
||||
* because ENET2_RX_ER conflicts. However, we rarely need
|
||||
* ENET2_RX_ER for enet, and when use eimnor, we do not
|
||||
* have sd1/sd2, enet is a must to boot kernel and nfsrootfs.
|
||||
*/
|
||||
setup_eimnor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_QSPI
|
||||
board_qspi_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX6UL 14X14 LPDDR2 ARM2\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
#define USB_OTHERREGS_OFFSET 0x800
|
||||
#define UCTRL_PWR_POL (1 << 9)
|
||||
iomux_v3_cfg_t const usb_otg1_pads[] = {
|
||||
MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
};
|
||||
|
||||
/*
|
||||
* Leave it here, but default configuration only supports 1 port now,
|
||||
* because we need sd1 and i2c1
|
||||
*/
|
||||
iomux_v3_cfg_t const usb_otg2_pads[] = {
|
||||
/* conflict with i2c1_scl */
|
||||
MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* conflict with sd1_vselect */
|
||||
MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
return usb_phy_mode(port);
|
||||
}
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
u32 *usbnc_usb_ctrl;
|
||||
|
||||
if (port > 1)
|
||||
return -EINVAL;
|
||||
|
||||
switch (port) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
|
||||
ARRAY_SIZE(usb_otg1_pads));
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
|
||||
ARRAY_SIZE(usb_otg2_pads));
|
||||
break;
|
||||
default:
|
||||
printf("MXC USB port %d not yet supported\n", port);
|
||||
return 1;
|
||||
}
|
||||
|
||||
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
||||
port * 4);
|
||||
|
||||
/* Set Power polarity */
|
||||
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
145
board/freescale/mx6ul_14x14_lpddr2_arm2/plugin.S
Normal file
145
board/freescale/mx6ul_14x14_lpddr2_arm2/plugin.S
Normal file
@ -0,0 +1,145 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx6ul_lpddr2_arm2_setting
|
||||
ldr r0, =IOMUXC_BASE_ADDR
|
||||
ldr r1, =0x00080000
|
||||
str r1, [r0, #0x4B4]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x4AC]
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x27C]
|
||||
str r1, [r0, #0x250]
|
||||
str r1, [r0, #0x24C]
|
||||
str r1, [r0, #0x490]
|
||||
str r1, [r0, #0x288]
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x270]
|
||||
str r1, [r0, #0x260]
|
||||
str r1, [r0, #0x264]
|
||||
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x4A0]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x494]
|
||||
|
||||
ldr r1, =0x00003028
|
||||
str r1, [r0, #0x280]
|
||||
str r1, [r0, #0x284]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x4B0]
|
||||
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x498]
|
||||
str r1, [r0, #0x4A4]
|
||||
str r1, [r0, #0x244]
|
||||
str r1, [r0, #0x248]
|
||||
|
||||
ldr r0, =MMDC_P0_BASE_ADDR
|
||||
ldr r1, =0x00008000
|
||||
str r1, [r0, #0x1C]
|
||||
ldr r1, =0x1b4700c7
|
||||
str r1, [r0, #0x5C]
|
||||
ldr r1, =0xA1390003
|
||||
str r1, [r0, #0x800]
|
||||
ldr r1, =0x00470000
|
||||
str r1, [r0, #0x890]
|
||||
ldr r1, =0x00000800
|
||||
str r1, [r0, #0x8b8]
|
||||
|
||||
ldr r1, =0x33333333
|
||||
str r1, [r0, #0x81C]
|
||||
str r1, [r0, #0x820]
|
||||
ldr r1, =0xF3333333
|
||||
str r1, [r0, #0x82C]
|
||||
str r1, [r0, #0x830]
|
||||
ldr r1, =0x20000000
|
||||
str r1, [r0, #0x83C]
|
||||
ldr r1, =0x4040484F
|
||||
str r1, [r0, #0x848]
|
||||
ldr r1, =0x40405247
|
||||
str r1, [r0, #0x850]
|
||||
ldr r1, =0x00922012
|
||||
str r1, [r0, #0x8C0]
|
||||
ldr r1, =0x00000800
|
||||
str r1, [r0, #0x8b8]
|
||||
|
||||
ldr r1, =0x00020012
|
||||
str r1, [r0, #0x004]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x008]
|
||||
ldr r1, =0x33374133
|
||||
str r1, [r0, #0x00C]
|
||||
ldr r1, =0x00100A82
|
||||
str r1, [r0, #0x010]
|
||||
ldr r1, =0x00170557
|
||||
str r1, [r0, #0x038]
|
||||
ldr r1, =0x00000093
|
||||
str r1, [r0, #0x014]
|
||||
ldr r1, =0x00001748
|
||||
str r1, [r0, #0x018]
|
||||
ldr r1, =0x00008000
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x0F9F0682
|
||||
str r1, [r0, #0x02C]
|
||||
ldr r1, =0x009F0010
|
||||
str r1, [r0, #0x030]
|
||||
ldr r1, =0x0000004F
|
||||
str r1, [r0, #0x040]
|
||||
ldr r1, =0x83100000
|
||||
str r1, [r0, #0x000]
|
||||
ldr r1, =0x003F8030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0xFF0A8030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x82018030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x04028030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x01038030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x00001800
|
||||
str r1, [r0, #0x020]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x818]
|
||||
ldr r1, =0xA1310003
|
||||
str r1, [r0, #0x800]
|
||||
ldr r1, =0x00025576
|
||||
str r1, [r0, #0x004]
|
||||
ldr r1, =0x00010106
|
||||
str r1, [r0, #0x404]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x01C]
|
||||
.endm
|
||||
|
||||
.macro imx6_clock_gating
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0xFFFFFFFF
|
||||
str r1, [r0, #0x68]
|
||||
str r1, [r0, #0x6C]
|
||||
str r1, [r0, #0x70]
|
||||
str r1, [r0, #0x74]
|
||||
str r1, [r0, #0x78]
|
||||
str r1, [r0, #0x7C]
|
||||
str r1, [r0, #0x80]
|
||||
str r1, [r0, #0x84]
|
||||
.endm
|
||||
|
||||
.macro imx6_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx6_ddr_setting
|
||||
imx6ul_lpddr2_arm2_setting
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx6_plugin.S>
|
||||
5
configs/mx6sx_14x14_lpddr2_arm2_defconfig
Normal file
5
configs/mx6sx_14x14_lpddr2_arm2_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_17X17_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg,MX6SX_14x14,LPDDR2"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_14x14_lpddr2_arm2_nand_defconfig
Normal file
5
configs/mx6sx_14x14_lpddr2_arm2_nand_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_17X17_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg,MX6SX_14x14,LPDDR2,SYS_BOOT_NAND"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_17x17_arm2_defconfig
Normal file
5
configs/mx6sx_17x17_arm2_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_17X17_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_17x17_arm2_eimnor_defconfig
Normal file
5
configs/mx6sx_17x17_arm2_eimnor_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_17X17_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,SYS_BOOT_EIMNOR"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_17x17_arm2_nand_defconfig
Normal file
5
configs/mx6sx_17x17_arm2_nand_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_17X17_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,SYS_BOOT_NAND"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_17x17_arm2_qspi2_defconfig
Normal file
5
configs/mx6sx_17x17_arm2_qspi2_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_17X17_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,SYS_BOOT_QSPI"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_17x17_arm2_spinor_defconfig
Normal file
5
configs/mx6sx_17x17_arm2_spinor_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_17X17_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,SYS_BOOT_SPINOR"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_17x17wp_arm2_defconfig
Normal file
5
configs/mx6sx_17x17wp_arm2_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_17X17_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage_wp.cfg"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_19x19_ddr3_arm2_defconfig
Normal file
5
configs/mx6sx_19x19_ddr3_arm2_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_19X19_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_19x19_ddr3_arm2_eimnor_defconfig
Normal file
5
configs/mx6sx_19x19_ddr3_arm2_eimnor_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_19X19_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg,SYS_BOOT_EIMNOR"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_19x19_ddr3_arm2_nand_defconfig
Normal file
5
configs/mx6sx_19x19_ddr3_arm2_nand_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_19X19_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg,SYS_BOOT_NAND"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_19x19_ddr3_arm2_qspi2_defconfig
Normal file
5
configs/mx6sx_19x19_ddr3_arm2_qspi2_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_19X19_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg,SYS_BOOT_QSPI"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_19x19_ddr3_arm2_spinor_defconfig
Normal file
5
configs/mx6sx_19x19_ddr3_arm2_spinor_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_19X19_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg,SYS_BOOT_SPINOR"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_19x19_lpddr2_arm2_defconfig
Normal file
5
configs/mx6sx_19x19_lpddr2_arm2_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_19X19_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg,LPDDR2"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6sx_19x19_lpddr2_arm2_qspi2_defconfig
Normal file
5
configs/mx6sx_19x19_lpddr2_arm2_qspi2_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SX_19X19_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg,LPDDR2,SYS_BOOT_QSPI"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6ul_14x14_ddr3_arm2_defconfig
Normal file
5
configs/mx6ul_14x14_ddr3_arm2_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6ul_14x14_ddr3_arm2_eimnor_defconfig
Normal file
5
configs/mx6ul_14x14_ddr3_arm2_eimnor_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg,SYS_BOOT_EIMNOR"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6ul_14x14_ddr3_arm2_emmc_defconfig
Normal file
5
configs/mx6ul_14x14_ddr3_arm2_emmc_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg,MX6UL_DDR3_ARM2_EMMC_REWORK"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6ul_14x14_ddr3_arm2_nand_defconfig
Normal file
5
configs/mx6ul_14x14_ddr3_arm2_nand_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg,SYS_BOOT_NAND"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6ul_14x14_ddr3_arm2_qspi1_defconfig
Normal file
5
configs/mx6ul_14x14_ddr3_arm2_qspi1_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg,SYS_BOOT_QSPI"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6ul_14x14_ddr3_arm2_spinor_defconfig
Normal file
5
configs/mx6ul_14x14_ddr3_arm2_spinor_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6UL_14X14_DDR3_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg,SYS_BOOT_SPINOR"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6ul_14x14_lpddr2_arm2_defconfig
Normal file
5
configs/mx6ul_14x14_lpddr2_arm2_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6UL_14X14_LPDDR2_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg"
|
||||
CONFIG_CMD_GPIO=y
|
||||
5
configs/mx6ul_14x14_lpddr2_arm2_eimnor_defconfig
Normal file
5
configs/mx6ul_14x14_lpddr2_arm2_eimnor_defconfig
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6UL_14X14_LPDDR2_ARM2=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg,SYS_BOOT_EIMNOR"
|
||||
CONFIG_CMD_GPIO=y
|
||||
40
include/configs/mx6sx_17x17_arm2.h
Normal file
40
include/configs/mx6sx_17x17_arm2.h
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6SX 17x17 ARM2 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX6SX_17X17_ARM2_CONFIG_H
|
||||
#define __MX6SX_17X17_ARM2_CONFIG_H
|
||||
|
||||
#include "mx6sx_arm2.h"
|
||||
|
||||
#ifdef CONFIG_MX6SX_14x14
|
||||
#define CONFIG_DEFAULT_FDT_FILE "imx6sx-14x14-arm2.dtb"
|
||||
#else
|
||||
#define CONFIG_DEFAULT_FDT_FILE "imx6sx-17x17-arm2.dtb"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR /* Pin conflict between SPI-NOR and SD2 */
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC3 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC3 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
#undef CONFIG_SYS_FLASH_SECT_SIZE
|
||||
#undef CONFIG_SYS_MAX_FLASH_SECT
|
||||
#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
#endif
|
||||
|
||||
#endif
|
||||
23
include/configs/mx6sx_19x19_arm2.h
Normal file
23
include/configs/mx6sx_19x19_arm2.h
Normal file
@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6SX 19x19 ARM2 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX6SX_19X19_ARM2_CONFIG_H
|
||||
#define __MX6SX_19X19_ARM2_CONFIG_H
|
||||
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_GIS
|
||||
|
||||
#include "mx6sx_arm2.h"
|
||||
|
||||
#define CONFIG_DEFAULT_FDT_FILE "imx6sx-19x19-arm2.dtb"
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
|
||||
|
||||
#endif
|
||||
375
include/configs/mx6sx_arm2.h
Normal file
375
include/configs/mx6sx_arm2.h
Normal file
@ -0,0 +1,375 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6SX ARM2 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX6SX_ARM2_CONFIG_H
|
||||
#define __MX6SX_ARM2_CONFIG_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <linux/sizes.h>
|
||||
#include "mx6_common.h"
|
||||
#include <asm/imx-common/gpio.h>
|
||||
|
||||
#define CONFIG_DBG_MONITOR
|
||||
/* uncomment for PLUGIN mode support */
|
||||
/* #define CONFIG_USE_PLUGIN */
|
||||
|
||||
/* uncomment for SECURE mode support */
|
||||
/* #define CONFIG_SECURE_BOOT */
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#ifndef CONFIG_CSF_SIZE
|
||||
#define CONFIG_CSF_SIZE 0x4000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_IMX_THERMAL
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
#define CONFIG_FEC_ENABLE_MAX7322
|
||||
/* MAX7322 */
|
||||
#ifdef CONFIG_FEC_ENABLE_MAX7322
|
||||
#define CONFIG_MAX7322_I2C_ADDR 0x68
|
||||
#define CONFIG_MAX7322_I2C_BUS 1
|
||||
#endif
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PFUZE100
|
||||
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
||||
|
||||
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 /* Set to QSPI2 B flash at default */
|
||||
#define CONFIG_CMD_BOOTAUX /* Boot M4 */
|
||||
|
||||
#ifdef CONFIG_CMD_BOOTAUX
|
||||
#define UPDATE_M4_ENV \
|
||||
"m4image=m4_qspi.bin\0" \
|
||||
"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
|
||||
"update_m4_from_sd=" \
|
||||
"if sf probe 1:0; then " \
|
||||
"if run loadm4image; then " \
|
||||
"setexpr fw_sz ${filesize} + 0xffff; " \
|
||||
"setexpr fw_sz ${fw_sz} / 0x10000; " \
|
||||
"setexpr fw_sz ${fw_sz} * 0x10000; " \
|
||||
"sf erase 0x0 ${fw_sz}; " \
|
||||
"sf write ${loadaddr} 0x0 ${filesize}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
|
||||
#else
|
||||
#define UPDATE_M4_ENV ""
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
#ifdef CONFIG_SYS_BOOT_NAND
|
||||
#define CONFIG_MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs) "
|
||||
#else
|
||||
#define CONFIG_MFG_NAND_PARTITION ""
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MODE \
|
||||
"panel=Hannstar-XGA\0"
|
||||
#else
|
||||
#define CONFIG_VIDEO_MODE ""
|
||||
#endif
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
CONFIG_MFG_NAND_PARTITION \
|
||||
"\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
|
||||
#if defined(CONFIG_SYS_BOOT_NAND)
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
CONFIG_VIDEO_MODE \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"bootargs=console=ttymxc0,115200 ubi.mtd=3 " \
|
||||
"root=ubi0:rootfs rootfstype=ubifs " \
|
||||
"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
|
||||
"bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
|
||||
"nand read ${fdt_addr} 0x5000000 0x100000;"\
|
||||
"bootz ${loadaddr} - ${fdt_addr}\0"
|
||||
|
||||
#else
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
UPDATE_M4_ENV \
|
||||
CONFIG_VIDEO_MODE \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_STACKSIZE SZ_128K
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
#define PHYS_SDRAM_SIZE SZ_1G
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
#define CONFIG_FSL_QSPI
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#elif defined CONFIG_SYS_BOOT_NAND
|
||||
#define CONFIG_SYS_USE_NAND
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#elif defined CONFIG_SYS_BOOT_SPINOR
|
||||
#define CONFIG_SYS_USE_SPINOR
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#elif defined CONFIG_SYS_BOOT_EIMNOR
|
||||
#define CONFIG_SYS_USE_EIMNOR
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#else
|
||||
#define CONFIG_FSL_QSPI /* Enable the QSPI flash at default */
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define CONFIG_QSPI_BASE QSPI1_BASE_ADDR
|
||||
#define CONFIG_QSPI_MEMMAP_BASE QSPI1_AMBA_BASE
|
||||
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SPI_FLASH_BAR
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_MXC_SPI
|
||||
#define CONFIG_SF_DEFAULT_BUS 3
|
||||
#define CONFIG_SF_DEFAULT_SPEED 20000000
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
#undef CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
|
||||
#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NAND_TRIMFFS
|
||||
|
||||
/* NAND stuff */
|
||||
#define CONFIG_NAND_MXS
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */
|
||||
#define CONFIG_APBH_DMA
|
||||
#define CONFIG_APBH_DMA_BURST
|
||||
#define CONFIG_APBH_DMA_BURST8
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
|
||||
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
||||
#define CONFIG_ENV_OFFSET (768 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#elif defined(CONFIG_ENV_IS_IN_NAND)
|
||||
#undef CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_OFFSET (37 << 20)
|
||||
#define CONFIG_ENV_SECT_SIZE (128 << 10)
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#elif defined(CONFIG_ENV_IS_IN_FLASH)
|
||||
#undef CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE
|
||||
#define CONFIG_ENV_OFFSET (4 * CONFIG_SYS_FLASH_SECT_SIZE)
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_BMODE
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_VIDEO_MXS
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_VIDEO_SW_CURSOR
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#ifdef CONFIG_VIDEO_GIS
|
||||
#define CONFIG_VIDEO_CSI
|
||||
#define CONFIG_VIDEO_PXP
|
||||
#define CONFIG_VIDEO_VADC
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MX6
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
/*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
71
include/configs/mx6ul_14x14_ddr3_arm2.h
Normal file
71
include/configs/mx6ul_14x14_ddr3_arm2.h
Normal file
@ -0,0 +1,71 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __MX6UL_14X14_DDR3_ARM2_CONFIG_H
|
||||
#define __MX6UL_14X14_DDR3_ARM2_CONFIG_H
|
||||
|
||||
#define CONFIG_DEFAULT_FDT_FILE "imx6ul-14x14-ddr3-arm2.dtb"
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
#define CONFIG_SYS_USE_QSPI
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#elif defined CONFIG_SYS_BOOT_SPINOR
|
||||
#define CONFIG_SYS_USE_SPINOR
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#elif defined CONFIG_SYS_BOOT_EIMNOR
|
||||
#define CONFIG_SYS_USE_EIMNOR
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#elif defined CONFIG_SYS_BOOT_NAND
|
||||
#define CONFIG_SYS_USE_NAND
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#else
|
||||
#define CONFIG_SYS_USE_QSPI
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#endif
|
||||
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_BOOTARGS_CMA_SIZE ""
|
||||
|
||||
#include "mx6ul_arm2.h"
|
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_1G
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_MXC_SPI
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 20000000
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_FEC_ENET_DEV 1
|
||||
|
||||
#if (CONFIG_FEC_ENET_DEV == 0)
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#elif (CONFIG_FEC_ENET_DEV == 1)
|
||||
#define IMX_FEC_BASE ENET2_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x2
|
||||
#define CONFIG_FEC_XCV_TYPE MII100
|
||||
#endif
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#endif
|
||||
|
||||
#endif
|
||||
82
include/configs/mx6ul_14x14_lpddr2_arm2.h
Normal file
82
include/configs/mx6ul_14x14_lpddr2_arm2.h
Normal file
@ -0,0 +1,82 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6UL 14x14 LPDDR2 ARM2.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __MX6UL_14X14_LPDDR2_ARM2_CONFIG_H
|
||||
#define __MX6UL_14X14_LPDDR2_ARM2_CONFIG_H
|
||||
|
||||
#define CONFIG_DEFAULT_FDT_FILE "imx6ul-14x14-lpddr2-arm2.dtb"
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
#define CONFIG_SYS_USE_QSPI
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#elif defined CONFIG_SYS_BOOT_SPINOR
|
||||
#define CONFIG_SYS_USE_SPINOR
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#elif defined CONFIG_SYS_BOOT_EIMNOR
|
||||
#define CONFIG_SYS_USE_EIMNOR
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
#elif defined CONFIG_SYS_BOOT_NAND
|
||||
#define CONFIG_SYS_USE_NAND
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#endif
|
||||
|
||||
#define CONFIG_VIDEO
|
||||
#ifdef CONFIG_SYS_BOOT_EIMNOR
|
||||
/*
|
||||
* Conflicts with SD1/SD2/VIDEO/ENET
|
||||
* ENET is keeped, since only RXER conflicts.
|
||||
* If removed ENET, we can not boot kernel, since sd1/sd2 is disabled
|
||||
* when support weimnor.
|
||||
*/
|
||||
#undef CONFIG_FSL_USDHC
|
||||
#undef CONFIG_VIDEO
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTARGS_CMA_SIZE "cma=96M "
|
||||
|
||||
#include "mx6ul_arm2.h"
|
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_256M
|
||||
|
||||
#ifdef CONFIG_SYS_USE_SPINOR
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_MXC_SPI
|
||||
#define CONFIG_SF_DEFAULT_BUS 1
|
||||
#define CONFIG_SF_DEFAULT_SPEED 20000000
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_FEC_ENET_DEV 1 /* The ENET1 has pin conflict with UART1 */
|
||||
|
||||
#if (CONFIG_FEC_ENET_DEV == 0)
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x2
|
||||
#define CONFIG_FEC_XCV_TYPE MII100
|
||||
#elif (CONFIG_FEC_ENET_DEV == 1)
|
||||
#define IMX_FEC_BASE ENET2_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#endif
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#endif
|
||||
|
||||
#endif
|
||||
309
include/configs/mx6ul_arm2.h
Normal file
309
include/configs/mx6ul_arm2.h
Normal file
@ -0,0 +1,309 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6UL ARM2 common.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __MX6UL_ARM2_CONFIG_H
|
||||
#define __MX6UL_ARM2_CONFIG_H
|
||||
|
||||
|
||||
#include "mx6_common.h"
|
||||
|
||||
/* uncomment for PLUGIN mode support */
|
||||
/* #define CONFIG_USE_PLUGIN */
|
||||
|
||||
/* uncomment for SECURE mode support */
|
||||
/* #define CONFIG_SECURE_BOOT */
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#ifndef CONFIG_CSF_SIZE
|
||||
#define CONFIG_CSF_SIZE 0x4000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_CMD_I2C
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PFUZE100
|
||||
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
#ifdef CONFIG_SYS_BOOT_NAND
|
||||
#define CONFIG_MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs) "
|
||||
#else
|
||||
#define CONFIG_MFG_NAND_PARTITION ""
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MODE \
|
||||
"panel=MCIMX28LCD\0"
|
||||
#else
|
||||
#define CONFIG_VIDEO_MODE ""
|
||||
#endif
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
CONFIG_BOOTARGS_CMA_SIZE \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
CONFIG_MFG_NAND_PARTITION \
|
||||
"clk_ignore_unused "\
|
||||
"\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
|
||||
#if defined(CONFIG_SYS_BOOT_NAND)
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
CONFIG_VIDEO_MODE \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"bootargs=console=ttymxc0,115200 ubi.mtd=3 " \
|
||||
"root=ubi0:rootfs rootfstype=ubifs " \
|
||||
CONFIG_BOOTARGS_CMA_SIZE \
|
||||
"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
|
||||
"bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
|
||||
"nand read ${fdt_addr} 0x5000000 0x100000;"\
|
||||
"bootz ${loadaddr} - ${fdt_addr}\0"
|
||||
|
||||
#else
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
CONFIG_VIDEO_MODE \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
CONFIG_BOOTARGS_CMA_SIZE \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
CONFIG_BOOTARGS_CMA_SIZE \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_STACKSIZE SZ_128K
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NAND_TRIMFFS
|
||||
|
||||
/* NAND stuff */
|
||||
#define CONFIG_NAND_MXS
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */
|
||||
#define CONFIG_APBH_DMA
|
||||
#define CONFIG_APBH_DMA_BURST
|
||||
#define CONFIG_APBH_DMA_BURST8
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_EIMNOR
|
||||
#undef CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
|
||||
#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_QSPI
|
||||
#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */
|
||||
#define CONFIG_QSPI_BASE QSPI0_BASE_ADDR
|
||||
#define CONFIG_QSPI_MEMMAP_BASE QSPI0_AMBA_BASE
|
||||
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SPI_FLASH_BAR
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
|
||||
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
||||
#define CONFIG_ENV_OFFSET (768 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#elif defined(CONFIG_ENV_IS_IN_FLASH)
|
||||
#undef CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE
|
||||
#define CONFIG_ENV_OFFSET (4 * CONFIG_SYS_FLASH_SECT_SIZE)
|
||||
#elif defined(CONFIG_ENV_IS_IN_NAND)
|
||||
#undef CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_OFFSET (37 << 20)
|
||||
#define CONFIG_ENV_SECT_SIZE (128 << 10)
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#endif
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#endif
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
|
||||
|
||||
#define CONFIG_CMD_BMODE
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_VIDEO_MXS
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_VIDEO_SW_CURSOR
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#endif
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_CMD_USB
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MX6
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user