MLK-12425-3: mx6slevk: support epdc
Support epdc for mx6slevk board. Introduce a new configuration file mx6slevk_epdc_defconfig. Add related settings. Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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* Copyright (C) 2013 - 2016 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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@ -29,6 +29,10 @@
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#include "../common/pfuze.h"
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#include <usb.h>
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#include <usb/ehci-fsl.h>
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#if defined(CONFIG_MXC_EPDC)
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#include <lcd.h>
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#include <mxc_epdc_fb.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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@ -56,6 +60,8 @@ DECLARE_GLOBAL_DATA_PTR;
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
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PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
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PAD_CTL_SRE_FAST)
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#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define ETH_PHY_POWER IMX_GPIO_NR(4, 21)
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@ -145,6 +151,52 @@ static void setup_spi(void)
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}
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#endif
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static iomux_v3_cfg_t const epdc_enable_pads[] = {
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MX6_PAD_EPDC_D0__EPDC_SDDO_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_D1__EPDC_SDDO_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_D2__EPDC_SDDO_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_D3__EPDC_SDDO_3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_D4__EPDC_SDDO_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_D5__EPDC_SDDO_5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_D6__EPDC_SDDO_6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_D7__EPDC_SDDO_7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_BDR0__EPDC_BDR_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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};
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static iomux_v3_cfg_t const epdc_disable_pads[] = {
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MX6_PAD_EPDC_D0__GPIO_1_7,
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MX6_PAD_EPDC_D1__GPIO_1_8,
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MX6_PAD_EPDC_D2__GPIO_1_9,
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MX6_PAD_EPDC_D3__GPIO_1_10,
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MX6_PAD_EPDC_D4__GPIO_1_11,
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MX6_PAD_EPDC_D5__GPIO_1_12,
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MX6_PAD_EPDC_D6__GPIO_1_13,
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MX6_PAD_EPDC_D7__GPIO_1_14,
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MX6_PAD_EPDC_GDCLK__GPIO_1_31,
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MX6_PAD_EPDC_GDSP__GPIO_2_2,
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MX6_PAD_EPDC_GDOE__GPIO_2_0,
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MX6_PAD_EPDC_GDRL__GPIO_2_1,
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MX6_PAD_EPDC_SDCLK__GPIO_1_23,
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MX6_PAD_EPDC_SDOE__GPIO_1_25,
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MX6_PAD_EPDC_SDLE__GPIO_1_24,
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MX6_PAD_EPDC_SDSHR__GPIO_1_26,
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MX6_PAD_EPDC_BDR0__GPIO_2_5,
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MX6_PAD_EPDC_SDCE0__GPIO_1_27,
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MX6_PAD_EPDC_SDCE1__GPIO_1_28,
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MX6_PAD_EPDC_SDCE2__GPIO_1_29,
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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@ -380,6 +432,191 @@ int board_early_init_f(void)
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return 0;
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}
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#ifdef CONFIG_MXC_EPDC
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vidinfo_t panel_info = {
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.vl_refresh = 85,
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.vl_col = 800,
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.vl_row = 600,
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.vl_rot = 0,
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.vl_pixclock = 26666667,
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.vl_left_margin = 8,
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.vl_right_margin = 100,
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.vl_upper_margin = 4,
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.vl_lower_margin = 8,
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.vl_hsync = 4,
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.vl_vsync = 1,
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.vl_sync = 0,
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.vl_mode = 0,
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.vl_flag = 0,
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.vl_bpix = 3,
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.cmap = 0,
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};
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struct epdc_timing_params panel_timings = {
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.vscan_holdoff = 4,
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.sdoed_width = 10,
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.sdoed_delay = 20,
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.sdoez_width = 10,
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.sdoez_delay = 20,
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.gdclk_hp_offs = 419,
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.gdsp_offs = 20,
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.gdoe_offs = 0,
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.gdclk_offs = 5,
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.num_ce = 1,
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};
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static void setup_epdc_power(void)
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{
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/* Setup epdc voltage */
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/* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */
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imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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gpio_direction_input(IMX_GPIO_NR(2, 13));
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/* EPDC_VCOM0 - GPIO2[3] for VCOM control */
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imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* Set as output */
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gpio_direction_output(IMX_GPIO_NR(2, 3), 1);
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/* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */
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imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* Set as output */
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gpio_direction_output(IMX_GPIO_NR(2, 14), 1);
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/* EPDC_PWRCTRL0 - GPIO2[7] for EPD PWR CTL0 */
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imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* Set as output */
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gpio_direction_output(IMX_GPIO_NR(2, 7), 1);
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}
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static void epdc_enable_pins(void)
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{
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/* epdc iomux settings */
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imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
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ARRAY_SIZE(epdc_enable_pads));
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}
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static void epdc_disable_pins(void)
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{
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/* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
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imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
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ARRAY_SIZE(epdc_disable_pads));
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}
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static void setup_epdc(void)
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{
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unsigned int reg;
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struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/*** epdc Maxim PMIC settings ***/
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/* EPDC PWRSTAT - GPIO2[13] for PWR_GOOD status */
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imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* EPDC VCOM0 - GPIO2[3] for VCOM control */
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imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* UART4 TXD - GPIO2[14] for EPD PMIC WAKEUP */
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imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* EIM_A18 - GPIO2[7] for EPD PWR CTL0 */
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imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/*** Set pixel clock rates for EPDC ***/
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/* EPDC AXI clk from PFD_400M, set to 396/2 = 198MHz */
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reg = readl(&ccm_regs->chsccdr);
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reg &= ~0x3F000;
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reg |= (0x4 << 15) | (1 << 12);
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writel(reg, &ccm_regs->chsccdr);
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/* EPDC AXI clk enable */
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reg = readl(&ccm_regs->CCGR3);
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reg |= 0x0030;
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writel(reg, &ccm_regs->CCGR3);
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/* EPDC PIX clk from PFD_540M, set to 540/4/5 = 27MHz */
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reg = readl(&ccm_regs->cscdr2);
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reg &= ~0x03F000;
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reg |= (0x5 << 15) | (4 << 12);
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writel(reg, &ccm_regs->cscdr2);
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reg = readl(&ccm_regs->cbcmr);
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reg &= ~0x03800000;
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reg |= (0x3 << 23);
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writel(reg, &ccm_regs->cbcmr);
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/* EPDC PIX clk enable */
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reg = readl(&ccm_regs->CCGR3);
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reg |= 0x0C00;
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writel(reg, &ccm_regs->CCGR3);
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panel_info.epdc_data.wv_modes.mode_init = 0;
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panel_info.epdc_data.wv_modes.mode_du = 1;
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panel_info.epdc_data.wv_modes.mode_gc4 = 3;
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panel_info.epdc_data.wv_modes.mode_gc8 = 2;
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panel_info.epdc_data.wv_modes.mode_gc16 = 2;
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panel_info.epdc_data.wv_modes.mode_gc32 = 2;
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panel_info.epdc_data.epdc_timings = panel_timings;
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setup_epdc_power();
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}
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void epdc_power_on(void)
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{
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unsigned int reg;
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struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
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/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
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gpio_set_value(IMX_GPIO_NR(2, 7), 1);
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udelay(1000);
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/* Enable epdc signal pin */
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epdc_enable_pins();
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/* Set PMIC Wakeup to high - enable Display power */
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gpio_set_value(IMX_GPIO_NR(2, 14), 1);
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/* Wait for PWRGOOD == 1 */
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while (1) {
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reg = readl(&gpio_regs->gpio_psr);
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if (!(reg & (1 << 13)))
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break;
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udelay(100);
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}
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/* Enable VCOM */
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gpio_set_value(IMX_GPIO_NR(2, 3), 1);
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udelay(500);
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}
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void epdc_power_off(void)
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{
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/* Set PMIC Wakeup to low - disable Display power */
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gpio_set_value(IMX_GPIO_NR(2, 14), 0);
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/* Disable VCOM */
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gpio_set_value(IMX_GPIO_NR(2, 3), 0);
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epdc_disable_pins();
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/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
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gpio_set_value(IMX_GPIO_NR(2, 7), 0);
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}
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#endif
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int board_init(void)
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{
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/* address of boot parameters */
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@ -393,6 +630,10 @@ int board_init(void)
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setup_fec();
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#endif
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#ifdef CONFIG_MXC_EPDC
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setup_epdc();
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#endif
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#ifdef CONFIG_USB_EHCI_MX6
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setup_usb();
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#endif
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9
configs/mx6slevk_epdc_defconfig
Normal file
9
configs/mx6slevk_epdc_defconfig
Normal file
@ -0,0 +1,9 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX6=y
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SPLASH_SCREEN"
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CONFIG_TARGET_MX6SLEVK=y
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CONFIG_CMD_GPIO=y
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CONFIG_DM=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_DM_THERMAL=y
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@ -1,5 +1,5 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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* Copyright 2013-2016 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Freescale i.MX6SL EVK board.
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*
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@ -21,7 +21,7 @@
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#define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
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#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
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#define CONFIG_BOARD_EARLY_INIT_F
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@ -59,6 +59,7 @@
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#define CONFIG_PHY_SMSC
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"epdc_waveform=epdc_splash.bin\0" \
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"script=boot.scr\0" \
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"image=zImage\0" \
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"console=ttymxc0\0" \
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@ -198,4 +199,25 @@
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#define CONFIG_IMX_THERMAL
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/*#define CONFIG_SPLASH_SCREEN*/
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/*
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* SPLASH SCREEN Configs
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*/
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#ifdef CONFIG_SPLASH_SCREEN
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/*
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* Framebuffer and LCD
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*/
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#define CONFIG_CMD_BMP
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#define CONFIG_MXC_EPDC 1
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#define CONFIG_LCD
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#ifdef CONFIG_MXC_EPDC
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#undef LCD_TEST_PATTERN
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#define LCD_BPP LCD_MONOCHROME
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#define CONFIG_WAVEFORM_BUF_SIZE 0x200000
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#endif
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#endif /* CONFIG_SPLASH_SCREEN */
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#endif /* __CONFIG_H */
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