MLK-12436-3: mx6qarm2: add new board revision support
Add mx6qarm2 new board revision support using mx6q pop SoC
Enable DRAM support for imx6q PoP SoC with populated LPDDR2
MT42L128M64D2
DDR calibration script:
040ee38ba9
Test result: Stress test passed.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
This commit is contained in:
Peng Fan
294
board/freescale/mx6qarm2/mt128x64mx32.cfg
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294
board/freescale/mx6qarm2/mt128x64mx32.cfg
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/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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#ifdef CONFIG_USE_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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#ifdef CONFIG_MX6DQ_POP_LPDDR2
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/* set ddr to 400Mhz */
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DATA 4 0x020C4018 0x21324
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DATA 4 0x020C4014 0x2018900
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CHECK_BITS_CLR 4 0x020C4048 0x3F
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DATA 4 0x020C4018 0x61324
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DATA 4 0x020C4014 0x18900
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CHECK_BITS_CLR 4 0x020C4048 0x3F
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DATA 4 0x020C4018 0x60324
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020c4084 0xffffffff
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// Switch PL301_FAST2 to DDR dual channel mapping
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//DATA 4 0x00B00000 0x1
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//=============================================================================
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/// IOMUX
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//=============================================================================
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//DDR IO TYPE:
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DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
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DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
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//CLOCK:
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DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
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DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
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//Control:
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DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
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DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
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DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
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DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
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DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
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DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
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DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
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DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
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//Data Strobes:
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DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
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DATA 4 0x020e05a8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
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DATA 4 0x020e05b0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
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DATA 4 0x020e0524 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
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DATA 4 0x020e051c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
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DATA 4 0x020e0518 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
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DATA 4 0x020e050c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
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DATA 4 0x020e05b8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
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DATA 4 0x020e05c0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
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//Data:
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DATA 4 0x020e0798 0x00080000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
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DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
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DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
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DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS
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DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS
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DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS
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DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS
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DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS
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DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS
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DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
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DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
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DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
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DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
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DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
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DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
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DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
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DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
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//=============================================================================
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// DDR Controller Registers
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//=============================================================================
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// Manufacturer: Micron - POP Package
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// Device Part Number: MT42L128M64D2LL-25WT
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// Clock Freq.: 400MHz
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// Density per CS in Gb: 4
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// Chip Selects used: 1
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// Number of channels 2
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// Density per channel (Gb) 4
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// Total DRAM density (Gb) 8
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// Number of Banks: 8
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// Row address: 14
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// Column address: 10
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// Data bus width 32
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//=============================================================================
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// MMDC0_MDSCR, set the Configuration request bit during MMDC set up
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DATA 4 0x021b001c 0x00008000 // Chan 0
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DATA 4 0x021b401c 0x00008000 // Chan 1
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DATA 4 0x021b085c 0x1b5f0109 //LPDDR2 ZQ params
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DATA 4 0x021b485c 0x1b5f0109 //LPDDR2 ZQ params
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//=============================================================================
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// Calibration setup.
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//
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//=============================================================================
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DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable one time ZQ calibration
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DATA 4 0x021b4800 0xa1380003 // DDR_PHY_P1_MPZQHWCTRL
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DATA 4 0x021b0890 0x00400000 //ca bus abs delay
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DATA 4 0x021b4890 0x00400000 //ca bus abs delay
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//DATA 4 0x021b48bc0x00055555 // DDR_PHY_P1_MPWRCADL
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DATA 4 0x021b08b8 0x00000800 //frc_msr.
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DATA 4 0x021b48b8 0x00000800 //frc_msr.
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// read delays, settings recommended by design to remain constant
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DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
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DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
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DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
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DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
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DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
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DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
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DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
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DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
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// write delays, settings recommended by design to remain constant
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DATA 4 0x021b082c 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
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DATA 4 0x021b0830 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
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DATA 4 0x021b0834 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
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DATA 4 0x021b0838 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
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DATA 4 0x021b482c 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
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DATA 4 0x021b4830 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
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DATA 4 0x021b4834 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
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DATA 4 0x021b4838 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
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DATA 4 0x021b0848 0x36383644 // MPRDDLCTL PHY0
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DATA 4 0x021b4848 0x3a383846 // MPRDDLCTL PHY1
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DATA 4 0x021b0850 0x38343E34 // MPWRDLCTL PHY0
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DATA 4 0x021b4850 0x48384A44 // MPWRDLCTL PHY1
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DATA 4 0x021b083c 0x20000000 //PHY0 dqs gating dis
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DATA 4 0x021b0840 0x0
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DATA 4 0x021b483c 0x20000000 //PHY0 dqs gating dis
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DATA 4 0x021b4840 0x0
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//For i.mx6qd parts of versions C and later (v1.2, v1.3).
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DATA 4 0x021b08c0 0x24921492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
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DATA 4 0x021b48c0 0x24921492
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DATA 4 0x021b08b8 0x00000800 //frc_msr.
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DATA 4 0x021b48b8 0x00000800 //frc_msr.
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//=============================================================================
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// Calibration setup end
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//=============================================================================
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// Channel0 - starting address 0x80000000
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DATA 4 0x021b000c 0x33374133 // MMDC0_MDCFG0
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DATA 4 0x021b0004 0x00020024 // MMDC0_MDPDC
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DATA 4 0x021b0010 0x00100A82 // MMDC0_MDCFG1
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DATA 4 0x021b0014 0x00000093 // MMDC0_MDCFG2
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//MDMISC: RALAT kept to the high level of 5.
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//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
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//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
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//b. Small performence improvment
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DATA 4 0x021b0018 0x0000174C // MMDC0_MDMISC
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DATA 4 0x021b002c 0x0F9F26D2 // MMDC0_MDRWD
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DATA 4 0x021b0030 0x009F0E10 // MMDC0_MDOR
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DATA 4 0x021b0038 0x001A0889 // MMDC0_MDCFG3LP
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DATA 4 0x021b0008 0x00000000 // MMDC0_MDOTC
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DATA 4 0x021b0040 0x00000053 // Chan0 CS0_END 2 channel with 4K-interleave mode
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// DATA 4 0x021b0400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
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DATA 4 0x021b0000 0x83110000 // MMDC0_MDCTL
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// Channel1 - starting address 0x10000000
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// Note: the values for Chan1 should match those of Chan0
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DATA 4 0x021b400c 0x33374133 // MMDC1_MDCFG0
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DATA 4 0x021b4004 0x00020024 // MMDC1_MDPDC
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DATA 4 0x021b4010 0x00100A82 // MMDC1_MDCFG1
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DATA 4 0x021b4014 0x00000093 // MMDC1_MDCFG2
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DATA 4 0x021b4018 0x0000174C // MMDC1_MDMISC
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DATA 4 0x021b402c 0x0F9F26D2 // MMDC1_MDRWD
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DATA 4 0x021b4030 0x009F0E10 // MMDC1_MDOR
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DATA 4 0x021b4038 0x001A0889 // MMDC1_MDCFG3LP
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DATA 4 0x021b4008 0x00000000 // MMDC1_MDOTC
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DATA 4 0x021b4040 0x00000013 // Chan1 CS0_END
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// DATA 4 0x021b4400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
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DATA 4 0x021b4000 0x83110000 // MMDC1_MDCTL
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//=============================================================================
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// LPDDR2 Mode Register Writes
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//=============================================================================
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// Channel 0 CS0
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DATA 4 0x021b001c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset)
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DATA 4 0x021b001c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
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DATA 4 0x021b001c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration
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DATA 4 0x021b001c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration
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DATA 4 0x021b001c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration
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// Channel 0 CS1
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// Note, CS1 does not exist in this memory hence these writes are commented out
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// They are only shown here for completeness
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// If you use a memory where CS1 exists, simply uncomment these lines
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//DATA 4 0x021b001c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset)
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//DATA 4 0x021b001c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
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//DATA 4 0x021b001c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration
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//DATA 4 0x021b001c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration
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//DATA 4 0x021b001c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration
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// For Channel 1 mode register writes - these should match channel 0 settings
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// Channel 1 CS0
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DATA 4 0x021b401c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset)
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DATA 4 0x021b401c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
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DATA 4 0x021b401c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration
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DATA 4 0x021b401c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration
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DATA 4 0x021b401c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration
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// Channel 1 CS1
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// Note, CS1 does not exist in this memory hence these writes are commented out
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// They are only shown here for completeness
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// If you use a memory where CS1 exists, simply uncomment these lines
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//DATA 4 0x021b401c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset)
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//DATA 4 0x021b401c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
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//DATA 4 0x021b401c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration
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//DATA 4 0x021b401c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration
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//DATA 4 0x021b401c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration
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//////////#################################################//
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//final DDR setup, before operation start:
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DATA 4 0x021b0020 0x00001800 // MMDC0_MDREF
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DATA 4 0x021b4020 0x00001800 // MMDC1_MDREF, align with Chan 0 setting
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DATA 4 0x021b0818 0x0 // DDR_PHY_P0_MPODTCTRL
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DATA 4 0x021b4818 0x0 // DDR_PHY_P1_MPODTCTRL
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DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
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DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P1_MPMUR0, frc_msr
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DATA 4 0x021b0004 0x00025564 // MMDC0_MDPDC now SDCTL power down enabled
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DATA 4 0x021b4004 0x00025564 // MMDC1_MDPDC now SDCTL power down enabled, align with Chan 0 setting
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DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled
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DATA 4 0x021b4404 0x00011006 //MMDC1_MAPSR ADOPT power down enabled, align with Chan 0 setting
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DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register
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DATA 4 0x021b401c 0x00000000 // MMDC1_MDSCR, clear this register
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4, 0x020e0010, 0xF00000CF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4, 0x020e0018, 0x007F007F
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DATA 4, 0x020e001c, 0x007F007F
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#endif
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#endif
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5
configs/mx6qarm2_pop_lpddr2_revb_defconfig
Normal file
5
configs/mx6qarm2_pop_lpddr2_revb_defconfig
Normal file
@ -0,0 +1,5 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX6=y
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CONFIG_TARGET_MX6QARM2=y
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/mt128x64mx32.cfg,MX6Q,MX6DQ_POP_LPDDR2,DDR_MB=1024"
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CONFIG_CMD_GPIO=y
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