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MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369

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Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
This commit is contained in:
Nitin Garg
2015-03-31 20:37:36 -05:00
committed by Ye Li
parent 1c27c9ecf8
commit f20a658475
3 changed files with 8 additions and 0 deletions
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1
README
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@ -645,6 +645,7 @@ The following options need to be configured:
CONFIG_ARM_ERRATA_773022
CONFIG_ARM_ERRATA_774769
CONFIG_ARM_ERRATA_794072
CONFIG_ARM_ERRATA_845369
If set, the workarounds for these ARM errata are applied early
during U-Boot startup. Note that these options force the

6
arch/arm/cpu/armv7/start.S
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@ -9,6 +9,7 @@
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -163,6 +164,11 @@ ENTRY(cpu_init_cp15)
orr r0, r0, #1 << 21 @ set bit #21
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_845369
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 22 @ set bit #22
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
mov r5, lr @ Store my Caller
mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)

1
include/configs/mx6_common.h
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@ -13,6 +13,7 @@
#define CONFIG_ARM_ERRATA_751472
#define CONFIG_ARM_ERRATA_794072
#define CONFIG_ARM_ERRATA_761320
#define CONFIG_ARM_ERRATA_845369
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310