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12 Commits
v5.15-stm3
...
v5.15-stm3
| Author | SHA1 | Date | |
|---|---|---|---|
| c482328ed5 | |||
| 658a6b7a76 | |||
| 56021ad257 | |||
| da7d08ef4e | |||
| ced3ab1c20 | |||
| 9966461848 | |||
| cc3792e44c | |||
| 17b6044099 | |||
| 7fb4e1bb72 | |||
| 94b2e0328a | |||
| 1aafc35ee6 | |||
| a5e86672a3 |
@ -1155,6 +1155,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
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stm32h750i-art-pi.dtb \
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stm32mp135f-dk.dtb \
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stm32mp135f-dk-a7-examples.dtb \
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stm32mp135d-gateway.dtb \
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stm32mp153c-dhcom-drc02.dtb \
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stm32mp157a-avenger96.dtb \
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stm32mp157a-dhcor-avenger96.dtb \
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759
arch/arm/boot/dts/stm32mp13-gateway-pinctrl.dtsi
Executable file
759
arch/arm/boot/dts/stm32mp13-gateway-pinctrl.dtsi
Executable file
@ -0,0 +1,759 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) MYiR 2021 - All Rights Reserved
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* Author: Alex
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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&pinctrl {
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adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1 in2 */
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<STM32_PINMUX('F', 11, ANALOG)>; /* ADC1 in8 */
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};
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};
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dcmiapp_pins_mx:dcmi_pins_mx{
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pins {
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pinmux = <STM32_PINMUX('A', 9, AF13)>, /* DCMPIPP_D0 */
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<STM32_PINMUX('D', 0, AF13)>, /* DCMPIPP_D1 */
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<STM32_PINMUX('H', 14, AF13)>, /* DCMPIPP_D2*/
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<STM32_PINMUX('E', 4, AF13)>, /* DCMPIPP_D3 */
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<STM32_PINMUX('E', 13, AF13)>, /* DCMPIPP_D4 */
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<STM32_PINMUX('D', 3, AF13)>, /* DCMPIPP_D5 */
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<STM32_PINMUX('B', 8, AF13)>, /* DCMPIPP_D6 */
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<STM32_PINMUX('E', 9, AF13)>, /* DCMPIPP_D7 */
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<STM32_PINMUX('B', 7, AF14)>, /* DCMPIPP_PIXCLK */
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<STM32_PINMUX('G', 9, AF13)>, /* DCMPIPP_VSYNC */
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<STM32_PINMUX('H', 8, AF13)>; /* DCMPIPP_HSYNC */
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};
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};
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dcmiapp_sleep_pins_mx:dcmi_sleep_pins_mx{
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pins {
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pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* DCMPIPP_D0 */
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<STM32_PINMUX('D', 0, ANALOG)>, /* DCMPIPP_D1 */
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<STM32_PINMUX('H', 14, ANALOG)>, /* DCMPIPP_D2*/
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<STM32_PINMUX('E', 4, ANALOG)>, /* DCMPIPP_D3 */
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<STM32_PINMUX('E', 13, ANALOG)>, /* DCMPIPP_D4 */
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<STM32_PINMUX('D', 3, ANALOG)>, /* DCMPIPP_D5 */
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<STM32_PINMUX('B', 8, ANALOG)>, /* DCMPIPP_D6 */
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<STM32_PINMUX('E', 9, ANALOG)>, /* DCMPIPP_D7 */
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<STM32_PINMUX('B', 7, ANALOG)>, /* DCMPIPP_PIXCLK */
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<STM32_PINMUX('G', 9, ANALOG)>, /* DCMPIPP_VS */
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<STM32_PINMUX('H', 8, ANALOG)>; /* DCMPIPP_HS */
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};
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};
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eth1_rgmii_pins_a: eth1_mx-0 {
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pins1 {
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pinmux = <STM32_PINMUX('D', 7, AF10)>, /* ETH1_RX_CLK */
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<STM32_PINMUX('A', 7, AF11)>, /* ETH1_RX_CTL */
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<STM32_PINMUX('B', 0, AF11)>, /* ETH1_RXD2 */
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<STM32_PINMUX('B', 1, AF11)>, /* ETH1_RXD3 */
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<STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
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<STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
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bias-disable;
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins3 {
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pinmux = <STM32_PINMUX('B', 11, AF11)>, /* ETH1_TX_CTL */
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<STM32_PINMUX('C', 1, AF11)>, /* ETH1_GTX_CLK */
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<STM32_PINMUX('C', 2, AF11)>, /* ETH1_TXD2 */
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<STM32_PINMUX('E', 5, AF10)>, /* ETH1_TXD3 */
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<STM32_PINMUX('F', 12, AF11)>, /* ETH1_CLK125 */
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<STM32_PINMUX('G', 2, AF11)>, /* ETH1_MDC */
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<STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
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<STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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eth1_rgmii_sleep_pins_a: eth1_sleep_mx-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 7, ANALOG)>, /* ETH1_RX_CLK */
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<STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
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<STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_RX_CTL */
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<STM32_PINMUX('B', 0, ANALOG)>, /* ETH1_RXD2 */
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<STM32_PINMUX('B', 1, ANALOG)>, /* ETH1_RXD3 */
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<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_CTL */
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<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_GTX_CLK */
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<STM32_PINMUX('C', 2, ANALOG)>, /* ETH1_TXD2 */
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<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
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<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
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<STM32_PINMUX('E', 5, ANALOG)>, /* ETH1_TXD3 */
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<STM32_PINMUX('F', 12, ANALOG)>, /* ETH1_CLK125 */
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<STM32_PINMUX('G', 2, ANALOG)>, /* ETH1_MDC */
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<STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
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<STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
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};
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};
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eth2_rgmii_pins_a: eth2_mx-0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 8, AF11)>, /* ETH2_RXD3 */
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<STM32_PINMUX('A', 12, AF11)>, /* ETH2_RX_CTL */
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<STM32_PINMUX('E', 2, AF10)>, /* ETH2_RXD1 */
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<STM32_PINMUX('F', 4, AF11)>, /* ETH2_RXD0 */
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<STM32_PINMUX('H', 6, AF12)>, /* ETH2_RXD2 */
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<STM32_PINMUX('H', 11, AF11)>; /* ETH2_RX_CLK */
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bias-disable;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 6, AF11)>; /* ETH2_MDIO */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins3 {
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pinmux = <STM32_PINMUX('E', 6, AF11)>, /* ETH2_TXD3 */
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<STM32_PINMUX('F', 6, AF11)>, /* ETH2_TX_CTL */
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<STM32_PINMUX('F', 7, AF11)>, /* ETH2_TXD0 */
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<STM32_PINMUX('G', 1, AF10)>, /* ETH2_TXD2 */
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<STM32_PINMUX('G', 3, AF10)>, /* ETH2_GTX_CLK */
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<STM32_PINMUX('G', 5, AF10)>, /* ETH2_MDC */
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<STM32_PINMUX('G', 11, AF10)>, /* ETH2_TXD1 */
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<STM32_PINMUX('H', 2, AF13)>; /* ETH2_CLK125 */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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eth2_rgmii_sleep_pins_a: eth2_sleep_mx-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* ETH2_RXD3 */
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<STM32_PINMUX('A', 12, ANALOG)>, /* ETH2_RX_CTL */
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<STM32_PINMUX('B', 6, ANALOG)>, /* ETH2_MDIO */
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<STM32_PINMUX('E', 2, ANALOG)>, /* ETH2_RXD1 */
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<STM32_PINMUX('E', 6, ANALOG)>, /* ETH2_TXD3 */
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<STM32_PINMUX('F', 4, ANALOG)>, /* ETH2_RXD0 */
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<STM32_PINMUX('F', 6, ANALOG)>, /* ETH2_TX_CTL */
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<STM32_PINMUX('F', 7, ANALOG)>, /* ETH2_TXD0 */
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<STM32_PINMUX('G', 1, ANALOG)>, /* ETH2_TXD2 */
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<STM32_PINMUX('G', 3, ANALOG)>, /* ETH2_GTX_CLK */
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<STM32_PINMUX('G', 5, ANALOG)>, /* ETH2_MDC */
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<STM32_PINMUX('G', 11, ANALOG)>, /* ETH2_TXD1 */
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<STM32_PINMUX('H', 2, ANALOG)>, /* ETH2_CLK125 */
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<STM32_PINMUX('H', 6, ANALOG)>, /* ETH2_RXD2 */
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<STM32_PINMUX('H', 11, ANALOG)>; /* ETH2_RX_CLK */
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};
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};
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i2c1_pins_a: i2c1-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
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<STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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i2c1_sleep_pins_a: i2c1-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
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<STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
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};
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};
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i2c3_pins_a: i2c3-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 8, AF5)>, /* I2C3_SCL */
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<STM32_PINMUX('H', 14, AF4)>; /* I2C3_SDA */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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i2c3_sleep_pins_a: i2c3-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 8, ANALOG)>, /* I2C3_SCL */
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<STM32_PINMUX('H', 14, ANALOG)>; /* I2C3_SDA */
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};
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};
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ltdc_pins_a: ltdc-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
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<STM32_PINMUX('E', 1, AF9)>, /* LCD_HSYNC */
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<STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */
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<STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */
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<STM32_PINMUX('D', 5, AF13)>, /* LCD_B0 */
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<STM32_PINMUX('E', 0, AF11)>, /* LCD_B1 */
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<STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */
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<STM32_PINMUX('E', 7, AF13)>, /* LCD_B3 */
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<STM32_PINMUX('G', 15, AF11)>, /* LCD_B4 */
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<STM32_PINMUX('D', 15, AF14)>, /* LCD_B5 */
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<STM32_PINMUX('D', 1, AF11)>, /* LCD_B6 */
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<STM32_PINMUX('E', 15, AF14)>, /* LCD_B7 */
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<STM32_PINMUX('E', 11, AF9)>, /* LCD_R0 */
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<STM32_PINMUX('G', 7, AF11)>, /* LCD_R1 */
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<STM32_PINMUX('H', 10, AF14)>, /* LCD_R2 */
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<STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */
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<STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */
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<STM32_PINMUX('F', 5, AF14)>, /* LCD_R5 */
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<STM32_PINMUX('D', 4, AF14)>, /* LCD_R6 */
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<STM32_PINMUX('D', 11, AF11)>, /* LCD_R7 */
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<STM32_PINMUX('E', 14, AF14)>, /* LCD_G0 */
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<STM32_PINMUX('F', 1, AF14)>, /* LCD_G1 */
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<STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
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<STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */
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<STM32_PINMUX('F', 2, AF13)>, /* LCD_G4 */
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<STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */
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<STM32_PINMUX('E', 12, AF14)>, /* LCD_G6 */
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<STM32_PINMUX('A', 15, AF11)>; /* LCD_G7 */
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bias-disable;
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drive-push-pull;
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slew-rate = <1>;
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};
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};
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ltdc_sleep_pins_a: ltdc-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
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<STM32_PINMUX('E', 1, ANALOG)>, /* LCD_HSYNC */
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<STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */
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<STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */
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<STM32_PINMUX('D', 5, ANALOG)>, /* LCD_B0 */
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<STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B1 */
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<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */
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<STM32_PINMUX('E', 7, ANALOG)>, /* LCD_B3 */
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<STM32_PINMUX('G', 15, ANALOG)>, /* LCD_B4 */
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<STM32_PINMUX('D', 15, ANALOG)>, /* LCD_B5 */
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<STM32_PINMUX('D', 1, ANALOG)>, /* LCD_B6 */
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<STM32_PINMUX('E', 15, ANALOG)>, /* LCD_B7 */
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<STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R1 */
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<STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R2 */
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<STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */
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<STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */
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<STM32_PINMUX('F', 5, ANALOG)>, /* LCD_R5 */
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<STM32_PINMUX('D', 4, ANALOG)>, /* LCD_R6 */
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<STM32_PINMUX('D', 11, ANALOG)>, /* LCD_R7 */
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<STM32_PINMUX('E', 14, ANALOG)>, /* LCD_G0 */
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<STM32_PINMUX('F', 1, ANALOG)>, /* LCD_G1 */
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<STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
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<STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */
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<STM32_PINMUX('F', 2, ANALOG)>, /* LCD_G4 */
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<STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */
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<STM32_PINMUX('E', 12, ANALOG)>, /* LCD_G6 */
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<STM32_PINMUX('A', 15, ANALOG)>; /* LCD_G7 */
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bias-disable;
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drive-push-pull;
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slew-rate = <1>;
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};
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};
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m_can2_pins_a: m-can2-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
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slew-rate = <1>;
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drive-push-pull;
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bias-disable;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
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bias-disable;
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};
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};
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m_can2_sleep_pins_a: m_can2-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
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<STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
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};
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};
|
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// rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
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// pins {
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// pinmux = <STM32_PINMUX('I', 1, ANALOG)>; /* RTC_OUT2_RMP */
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// };
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// };
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sai1_pins_a: sai1-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
|
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<STM32_PINMUX('A', 0, AF6)>, /* SAI1_SD_B */
|
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<STM32_PINMUX('A', 5, AF6)>, /* SAI1_SD_A */
|
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<STM32_PINMUX('F', 11, AF6)>; /* SAI1_FS_A */
|
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slew-rate = <0>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
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sai1_sleep_pins_a: sai1-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
|
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<STM32_PINMUX('A', 0, ANALOG)>, /* SAI1_SD_B */
|
||||
<STM32_PINMUX('A', 5, ANALOG)>, /* SAI1_SD_A */
|
||||
<STM32_PINMUX('F', 11, ANALOG)>; /* SAI1_FS_A */
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
||||
slew-rate = <1>;
|
||||
drive-open-drain;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
|
||||
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
|
||||
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
|
||||
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
|
||||
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
|
||||
<STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
|
||||
<STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
|
||||
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
|
||||
<STM32_PINMUX('C', 7, AF10)>, /* SDMMC2_D7 */
|
||||
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
|
||||
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
|
||||
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
|
||||
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
|
||||
<STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
|
||||
<STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
|
||||
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
|
||||
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
||||
slew-rate = <1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
|
||||
<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
|
||||
<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
|
||||
<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
|
||||
<STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
|
||||
<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
|
||||
<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
|
||||
<STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC2_D7 */
|
||||
<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
|
||||
<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
stm32g0_intn_pins_a: stm32g0-intn-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('I', 2, GPIO)>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart7_pins_a: uart7-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart7_idle_pins_a: uart7-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart7_sleep_pins_a: uart7-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */
|
||||
<STM32_PINMUX('E', 10, ANALOG)>; /* UART7_RX */
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins_a: uart4-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_idle_pins_a: uart4-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_sleep_pins_a: uart4-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
|
||||
<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
|
||||
};
|
||||
};
|
||||
|
||||
uart5_pins_b: uart5-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 7, AF8)>; /* UART5_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 5, AF11)>; /* UART5_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart5_sleep_pins_b: uart5-sleep-1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 7, ANALOG)>, /* UART5_TX */
|
||||
<STM32_PINMUX('B', 5, ANALOG)>; /* UART5_RX */
|
||||
};
|
||||
};
|
||||
|
||||
uart5_idle_pins_b: uart5-idle-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 7, ANALOG)>; /* UART4_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 5, AF11)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
uart8_pins_a: uart8-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart8_idle_pins_a: uart8-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart8_sleep_pins_a: uart8-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
|
||||
<STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
|
||||
};
|
||||
};
|
||||
|
||||
i2s1_pins_a: i2s1_mx-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 3, AF5)>, /* I2S1_SDO */
|
||||
<STM32_PINMUX('A', 4, AF5)>, /* I2S1_WS */
|
||||
<STM32_PINMUX('A', 6, AF5)>, /* I2S1_SDI */
|
||||
<STM32_PINMUX('C', 0, AF5)>, /* I2S1_MCK */
|
||||
<STM32_PINMUX('C', 3, AF6)>; /* I2S1_CK */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s1_pins_sleep_a: i2s1_sleep_mx-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 3, ANALOG)>, /* I2S1_SDO */
|
||||
<STM32_PINMUX('A', 4, ANALOG)>, /* I2S1_WS */
|
||||
<STM32_PINMUX('A', 6, ANALOG)>, /* I2S1_SDI */
|
||||
<STM32_PINMUX('C', 0, ANALOG)>, /* I2S1_MCK */
|
||||
<STM32_PINMUX('C', 3, ANALOG)>; /* I2S1_CK */
|
||||
};
|
||||
};
|
||||
|
||||
quadspi_pins_mx: quadspi_mx-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* QUADSPI_BK1_NCS */
|
||||
<STM32_PINMUX('D', 7, AF11)>, /* QUADSPI_BK1_IO2 */
|
||||
<STM32_PINMUX('D', 13, AF9)>, /* QUADSPI_BK1_IO3 */
|
||||
<STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
|
||||
<STM32_PINMUX('F', 9, AF10)>; /* QUADSPI_BK1_IO1 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
quadspi_sleep_pins_mx: quadspi_sleep_mx-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 2, ANALOG)>, /* QUADSPI_BK1_NCS */
|
||||
<STM32_PINMUX('D', 7, ANALOG)>, /* QUADSPI_BK1_IO2 */
|
||||
<STM32_PINMUX('D', 13, ANALOG)>, /* QUADSPI_BK1_IO3 */
|
||||
<STM32_PINMUX('F', 8, ANALOG)>, /* QUADSPI_BK1_IO0 */
|
||||
<STM32_PINMUX('F', 9, ANALOG)>, /* QUADSPI_BK1_IO1 */
|
||||
<STM32_PINMUX('F', 10, ANALOG)>; /* QUADSPI_CLK */
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_a: usart1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
|
||||
<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
|
||||
<STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_idle_pins_a: usart1-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
|
||||
<STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins3 {
|
||||
pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_sleep_pins_a: usart1-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
|
||||
<STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
|
||||
<STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
|
||||
<STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_b: usart1-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_idle_pins_b: usart1-idle-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* USART1_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_sleep_pins_b: usart1-sleep-1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* USART1_TX */
|
||||
<STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
usart2_pins_a: usart2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
|
||||
<STM32_PINMUX('D', 4, AF3)>;
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_idle_pins_a: usart2-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
|
||||
<STM32_PINMUX('D', 4, ANALOG)>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_sleep_pins_a: usart2-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
|
||||
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
|
||||
<STM32_PINMUX('D', 4, ANALOG)>;
|
||||
};
|
||||
};
|
||||
|
||||
usart3_pins_a: usart3-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
||||
<STM32_PINMUX('G', 8, AF8)>;
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart3_idle_pins_a: usart3-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
||||
<STM32_PINMUX('G', 8, ANALOG)>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart3_sleep_pins_a: usart3-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
||||
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_DE */
|
||||
<STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
|
||||
};
|
||||
};
|
||||
|
||||
spi3_pins_a: spi3-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */
|
||||
<STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('G', 7, AF5)>; /* SPI3_MISO */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi3_sleep_pins_a: spi3-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */
|
||||
<STM32_PINMUX('F', 1, ANALOG)>, /* SPI3_MISO */
|
||||
<STM32_PINMUX('G', 7, ANALOG)>; /* SPI3_MOSI */
|
||||
};
|
||||
};
|
||||
};
|
||||
540
arch/arm/boot/dts/stm32mp135d-gateway.dts
Executable file
540
arch/arm/boot/dts/stm32mp135d-gateway.dts
Executable file
@ -0,0 +1,540 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) MYiR 2022 - All Rights Reserved
|
||||
* Author: Alexhu <fan.hu@myirtech.com> for MYiR.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/rtc/rtc-stm32.h>
|
||||
#include "stm32mp135.dtsi"
|
||||
#include "stm32mp13xf.dtsi"
|
||||
#include "stm32mp13-gateway-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP135F-DK Discovery Board";
|
||||
compatible = "st,stm32mp135f-dk", "st,stm32mp135";
|
||||
|
||||
aliases {
|
||||
ethernet0 = ð1;
|
||||
ethernet1 = ð2;
|
||||
serial0 = &uart4;
|
||||
serial3 = &usart1;
|
||||
serial1 = &usart2;
|
||||
serial2 = &usart3;
|
||||
serial5 = &uart5;
|
||||
};
|
||||
|
||||
chosen {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x20000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
optee_framebuffer@dd000000 {
|
||||
reg = <0xdd000000 0x1000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
optee@de000000 {
|
||||
reg = <0xde000000 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_ext_audio: clk-ext-audio {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
clk_ext_camera: clk-ext-camera {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
clk_mco1: clk-mco1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
sys_mclk: clock-mclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#size-cells = <0>;
|
||||
|
||||
user {
|
||||
label = "user";
|
||||
linux,code = <BTN_1>;
|
||||
gpios = <&gpioi 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
run {
|
||||
label = "run";
|
||||
gpios = <&gpioe 14 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
data {
|
||||
label = "data";
|
||||
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
srv {
|
||||
label = "srv";
|
||||
gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
watchdog: watchdog {
|
||||
compatible = "linux,wdt-gpio";
|
||||
pinctrl-names = "default";
|
||||
gpios = <&gpiod 1 GPIO_ACTIVE_LOW>;
|
||||
hw_algo = "toggle";
|
||||
hw_margin_ms = <1000>;
|
||||
/*always-running;*/
|
||||
};
|
||||
|
||||
v3v3_hdmi: regulator-v3v3-hdmi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v3v3_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v1v2_hdmi: regulator-v1v2-hdmi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v1v2_hdmi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_usb: reg-vdd_usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v3v3_ao: v3v3_ao {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v3v3_ao";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v3v3_panle: v3v3_panle {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v3v3_panle";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddmmc: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vddadcvref: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddadcvref";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vddadc: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddadc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd1v8: vdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd1v8";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
v2v8: v2v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v2v8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
};
|
||||
|
||||
&crc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dma1 {
|
||||
sram = <&dma_pool>;
|
||||
};
|
||||
|
||||
&dma2 {
|
||||
sram = <&dma_pool>;
|
||||
};
|
||||
|
||||
&dts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ð1_rgmii_pins_a>;
|
||||
pinctrl-1 = <ð1_rgmii_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
phy-mode = "rgmii-id";
|
||||
max-speed = <1000>;
|
||||
phy-handle = <&phy0_eth1>;
|
||||
//st,phy-reset-gpios = <&gpiog 10 GPIO_ACTIVE_HIGH>;
|
||||
//snps,phy-reset-gpios = <&gpiog 10 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
mdio1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0_eth1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
reset-gpios = <&gpiog 10 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
ð2 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ð2_rgmii_pins_a>;
|
||||
pinctrl-1 = <ð2_rgmii_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
phy-mode = "rgmii-id";
|
||||
max-speed = <1000>;
|
||||
phy-handle = <&phy0_eth2>;
|
||||
phy-supply = <&v3v3_ao>;
|
||||
//st,phy-reset-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
|
||||
//snps,phy-reset-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
|
||||
// reset-deassert-us = <1000>;
|
||||
// reset-assert-us = <1000>;
|
||||
|
||||
|
||||
mdio1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0_eth2: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
pinctrl-1 = <&i2c1_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <96>;
|
||||
i2c-scl-falling-time-ns = <3>;
|
||||
clock-frequency = <1000000>;
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
rx8010: rx8010@32 {
|
||||
compatible = "epson,rx8010";
|
||||
reg = <0x32>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c3_pins_a>;
|
||||
pinctrl-1 = <&i2c3_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <300>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
disable-wp;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vddmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sdmmc2 {
|
||||
arm,primecell-periphid = <0x10153180>;
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>;
|
||||
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>;
|
||||
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
st,neg-edge;
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&vddmmc>;
|
||||
vqmmc-supply = <&vdd1v8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sram {
|
||||
dma_pool: dma-sram@0 {
|
||||
reg = <0x0 0x4000>;
|
||||
pool;
|
||||
};
|
||||
};
|
||||
|
||||
&timers3 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timers4 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timers8 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timers14 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart8 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart8_pins_a>;
|
||||
pinctrl-1 = <&uart8_sleep_pins_a>;
|
||||
pinctrl-2 = <&uart8_idle_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&usart1_pins_b>;
|
||||
pinctrl-1 = <&usart1_sleep_pins_b>;
|
||||
//pinctrl-2 = <&usart1_idle_pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&usart2_pins_a>;
|
||||
pinctrl-1 = <&usart2_sleep_pins_a>;
|
||||
pinctrl-2 = <&usart2_idle_pins_a>;
|
||||
//rts-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usart3 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&usart3_pins_a>;
|
||||
pinctrl-1 = <&usart3_sleep_pins_a>;
|
||||
pinctrl-2 = <&usart3_idle_pins_a>;
|
||||
//rts-gpios = <&gpiog 8 GPIO_ACTIVE_HIGH>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*console*/
|
||||
&uart4 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
pinctrl-1 = <&uart4_sleep_pins_a>;
|
||||
pinctrl-2 = <&uart4_idle_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*RS232*/
|
||||
&uart5 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart5_pins_b>;
|
||||
pinctrl-1 = <&uart5_sleep_pins_b>;
|
||||
pinctrl-2 = <&uart5_idle_pins_b>;
|
||||
// /delete-property/dmas;
|
||||
// /delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi3 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&spi3_pins_a>;
|
||||
pinctrl-1 = <&spi3_sleep_pins_a>;
|
||||
cs-gpios = <&gpiof 3 0>;
|
||||
status = "okay";
|
||||
|
||||
spidev@0 {
|
||||
compatible = "semtech,sx1301";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&usbh_ehci {
|
||||
phys = <&usbphyc_port0>, <&usbphyc_port1 1>;
|
||||
phy-names = "usb", "usb";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh_ohci {
|
||||
phys = <&usbphyc_port0>, <&usbphyc_port1 1>;
|
||||
phy-names = "usb", "usb";
|
||||
status = "okay";
|
||||
};
|
||||
/*
|
||||
&usbotg_hs {
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
usb-role-switch;
|
||||
//dr_mode = "otg";
|
||||
dr_mode = "host";
|
||||
// hnp-disable;
|
||||
// srp-disable;
|
||||
// adp-disable;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
usbotg_hs_ep: endpoint {
|
||||
remote-endpoint = <&con_usb_c_ep>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
*/
|
||||
|
||||
&usbphyc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
st,current-boost-microamp = <1000>;
|
||||
st,decrease-hs-slew-rate;
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <11>;
|
||||
st,trim-hs-impedance = <2>;
|
||||
st,tune-squelch-level = <1>;
|
||||
st,enable-hs-rx-gain-eq;
|
||||
st,no-hs-ftime-ctrl;
|
||||
st,no-lsfs-sc;
|
||||
|
||||
/*
|
||||
* Hack to keep hub active if wakeup source is enabled
|
||||
* otherwise the hub will wakeup the port0 as soon as the v3v3_sw is disabled
|
||||
*/
|
||||
// connector {
|
||||
// compatible = "usb-a-connector";
|
||||
// vbus-supply = <&scmi_v3v3_sw>;
|
||||
// };
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
st,current-boost-microamp = <1000>;
|
||||
st,decrease-hs-slew-rate;
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <11>;
|
||||
st,trim-hs-impedance = <2>;
|
||||
st,tune-squelch-level = <1>;
|
||||
st,enable-hs-rx-gain-eq;
|
||||
st,no-hs-ftime-ctrl;
|
||||
st,no-lsfs-sc;
|
||||
};
|
||||
818
arch/arm/configs/mp13gw_defconfig
Normal file
818
arch/arm/configs/mp13gw_defconfig
Normal file
@ -0,0 +1,818 @@
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_USELIB=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BPF_SYSCALL=y
|
||||
CONFIG_BPF_JIT=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_TASKSTATS=y
|
||||
CONFIG_TASK_DELAY_ACCT=y
|
||||
CONFIG_TASK_XACCT=y
|
||||
CONFIG_TASK_IO_ACCOUNTING=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_MEMCG=y
|
||||
CONFIG_BLK_CGROUP=y
|
||||
CONFIG_CGROUP_PIDS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_CGROUP_BPF=y
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_CHECKPOINT_RESTORE=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_ARCH_MILBEAUT=y
|
||||
CONFIG_ARCH_MILBEAUT_M10V=y
|
||||
CONFIG_ARCH_STM32=y
|
||||
CONFIG_ARM_THUMBEE=y
|
||||
CONFIG_SWP_EMULATE=y
|
||||
# CONFIG_CACHE_L2X0 is not set
|
||||
CONFIG_ARM_ERRATA_430973=y
|
||||
CONFIG_ARM_ERRATA_720789=y
|
||||
CONFIG_ARM_ERRATA_754322=y
|
||||
CONFIG_ARM_ERRATA_775420=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=12
|
||||
# CONFIG_ATAGS is not set
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=m
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_ARM_SCMI_CPUFREQ=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_ARM_STM32_CPUIDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_KERNEL_MODE_NEON=y
|
||||
CONFIG_ARM_CRYPTO=y
|
||||
CONFIG_CRYPTO_SHA1_ARM_NEON=m
|
||||
CONFIG_CRYPTO_SHA1_ARM_CE=m
|
||||
CONFIG_CRYPTO_SHA2_ARM_CE=m
|
||||
CONFIG_CRYPTO_SHA512_ARM=m
|
||||
CONFIG_CRYPTO_AES_ARM=m
|
||||
CONFIG_CRYPTO_AES_ARM_BS=m
|
||||
CONFIG_CRYPTO_AES_ARM_CE=m
|
||||
CONFIG_CRYPTO_GHASH_ARM_CE=m
|
||||
CONFIG_CRYPTO_CRC32_ARM_CE=m
|
||||
CONFIG_CRYPTO_CHACHA20_NEON=m
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_FORCE_LOAD=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_CMDLINE_PARTITION=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_UNIX_DIAG=y
|
||||
CONFIG_TLS=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_XFRM_INTERFACE=m
|
||||
CONFIG_XFRM_SUB_POLICY=y
|
||||
CONFIG_XFRM_MIGRATE=y
|
||||
CONFIG_XFRM_STATISTICS=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_FIB_TRIE_STATS=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=m
|
||||
CONFIG_NET_IPGRE_DEMUX=m
|
||||
CONFIG_NET_IPGRE=m
|
||||
CONFIG_NET_IPGRE_BROADCAST=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_NET_IPVTI=m
|
||||
CONFIG_NET_FOU_IP_TUNNELS=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_ESP_OFFLOAD=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
CONFIG_INET_DIAG=m
|
||||
CONFIG_INET_UDP_DIAG=m
|
||||
CONFIG_INET_RAW_DIAG=m
|
||||
CONFIG_INET_DIAG_DESTROY=y
|
||||
CONFIG_TCP_CONG_ADVANCED=y
|
||||
CONFIG_TCP_MD5SIG=y
|
||||
CONFIG_IPV6=m
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_ESP_OFFLOAD=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_IPV6_MIP6=m
|
||||
CONFIG_IPV6_VTI=m
|
||||
CONFIG_IPV6_SIT_6RD=y
|
||||
CONFIG_IPV6_GRE=m
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_IPV6_MROUTE=y
|
||||
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
|
||||
CONFIG_IPV6_PIMSM_V2=y
|
||||
CONFIG_IPV6_SEG6_LWTUNNEL=y
|
||||
CONFIG_IPV6_SEG6_HMAC=y
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
CONFIG_NETWORK_PHY_TIMESTAMPING=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NF_CONNTRACK=m
|
||||
CONFIG_NF_CONNTRACK_SECMARK=y
|
||||
CONFIG_NF_CONNTRACK_PROCFS=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CONNTRACK_TIMEOUT=y
|
||||
CONFIG_NF_CONNTRACK_TIMESTAMP=y
|
||||
CONFIG_NF_CONNTRACK_AMANDA=m
|
||||
CONFIG_NF_CONNTRACK_FTP=m
|
||||
CONFIG_NF_CONNTRACK_H323=m
|
||||
CONFIG_NF_CONNTRACK_IRC=m
|
||||
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
|
||||
CONFIG_NF_CONNTRACK_SNMP=m
|
||||
CONFIG_NF_CONNTRACK_PPTP=m
|
||||
CONFIG_NF_CONNTRACK_SIP=m
|
||||
CONFIG_NF_CONNTRACK_TFTP=m
|
||||
CONFIG_NF_CT_NETLINK=m
|
||||
CONFIG_NF_CT_NETLINK_TIMEOUT=m
|
||||
CONFIG_NF_CT_NETLINK_HELPER=m
|
||||
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
|
||||
CONFIG_NF_TABLES=m
|
||||
CONFIG_NF_TABLES_INET=y
|
||||
CONFIG_NF_TABLES_NETDEV=y
|
||||
CONFIG_NFT_NUMGEN=m
|
||||
CONFIG_NFT_CT=m
|
||||
CONFIG_NFT_COUNTER=m
|
||||
CONFIG_NFT_CONNLIMIT=m
|
||||
CONFIG_NFT_LOG=m
|
||||
CONFIG_NFT_LIMIT=m
|
||||
CONFIG_NFT_MASQ=m
|
||||
CONFIG_NFT_REDIR=m
|
||||
CONFIG_NFT_NAT=m
|
||||
CONFIG_NFT_TUNNEL=m
|
||||
CONFIG_NFT_OBJREF=m
|
||||
CONFIG_NFT_QUEUE=m
|
||||
CONFIG_NFT_QUOTA=m
|
||||
CONFIG_NFT_REJECT=m
|
||||
CONFIG_NFT_HASH=m
|
||||
CONFIG_NFT_XFRM=m
|
||||
CONFIG_NFT_SOCKET=m
|
||||
CONFIG_NFT_TPROXY=m
|
||||
CONFIG_NFT_SYNPROXY=m
|
||||
CONFIG_NFT_DUP_NETDEV=m
|
||||
CONFIG_NFT_FWD_NETDEV=m
|
||||
CONFIG_NFT_REJECT_NETDEV=m
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
|
||||
CONFIG_NETFILTER_XT_TARGET_HMARK=m
|
||||
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
|
||||
CONFIG_NETFILTER_XT_TARGET_LED=m
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=m
|
||||
CONFIG_NETFILTER_XT_TARGET_MARK=m
|
||||
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
|
||||
CONFIG_NETFILTER_XT_TARGET_TEE=m
|
||||
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
|
||||
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
|
||||
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
|
||||
CONFIG_NETFILTER_XT_MATCH_BPF=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CPU=m
|
||||
CONFIG_NETFILTER_XT_MATCH_DCCP=m
|
||||
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
|
||||
CONFIG_NETFILTER_XT_MATCH_DSCP=m
|
||||
CONFIG_NETFILTER_XT_MATCH_ESP=m
|
||||
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_HELPER=m
|
||||
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
|
||||
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MARK=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_OSF=m
|
||||
CONFIG_NETFILTER_XT_MATCH_OWNER=m
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=m
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
|
||||
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
|
||||
CONFIG_NETFILTER_XT_MATCH_REALM=m
|
||||
CONFIG_NETFILTER_XT_MATCH_RECENT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_SCTP=m
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=m
|
||||
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
|
||||
CONFIG_NETFILTER_XT_MATCH_STRING=m
|
||||
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
|
||||
CONFIG_NETFILTER_XT_MATCH_TIME=m
|
||||
CONFIG_NETFILTER_XT_MATCH_U32=m
|
||||
CONFIG_IP_SET=m
|
||||
CONFIG_IP_VS=m
|
||||
CONFIG_NF_LOG_ARP=m
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
CONFIG_IP_NF_MATCH_AH=m
|
||||
CONFIG_IP_NF_MATCH_ECN=m
|
||||
CONFIG_IP_NF_MATCH_RPFILTER=m
|
||||
CONFIG_IP_NF_MATCH_TTL=m
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
CONFIG_IP_NF_TARGET_REJECT=m
|
||||
CONFIG_IP_NF_TARGET_SYNPROXY=m
|
||||
CONFIG_IP_NF_NAT=m
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=m
|
||||
CONFIG_IP_NF_TARGET_NETMAP=m
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=m
|
||||
CONFIG_IP_NF_MANGLE=m
|
||||
CONFIG_IP_NF_TARGET_CLUSTERIP=m
|
||||
CONFIG_IP_NF_TARGET_ECN=m
|
||||
CONFIG_IP_NF_TARGET_TTL=m
|
||||
CONFIG_IP_NF_RAW=m
|
||||
CONFIG_IP_NF_ARPTABLES=m
|
||||
CONFIG_IP_NF_ARPFILTER=m
|
||||
CONFIG_IP_NF_ARP_MANGLE=m
|
||||
CONFIG_IP6_NF_IPTABLES=m
|
||||
CONFIG_IP6_NF_MATCH_AH=m
|
||||
CONFIG_IP6_NF_MATCH_EUI64=m
|
||||
CONFIG_IP6_NF_MATCH_FRAG=m
|
||||
CONFIG_IP6_NF_MATCH_OPTS=m
|
||||
CONFIG_IP6_NF_MATCH_HL=m
|
||||
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
|
||||
CONFIG_IP6_NF_MATCH_MH=m
|
||||
CONFIG_IP6_NF_MATCH_RPFILTER=m
|
||||
CONFIG_IP6_NF_MATCH_RT=m
|
||||
CONFIG_IP6_NF_TARGET_HL=m
|
||||
CONFIG_IP6_NF_FILTER=m
|
||||
CONFIG_IP6_NF_TARGET_REJECT=m
|
||||
CONFIG_IP6_NF_TARGET_SYNPROXY=m
|
||||
CONFIG_IP6_NF_MANGLE=m
|
||||
CONFIG_IP6_NF_RAW=m
|
||||
CONFIG_IP6_NF_NAT=m
|
||||
CONFIG_IP6_NF_TARGET_MASQUERADE=m
|
||||
CONFIG_IP6_NF_TARGET_NPT=m
|
||||
CONFIG_NF_TABLES_BRIDGE=m
|
||||
CONFIG_NFT_BRIDGE_META=m
|
||||
CONFIG_NFT_BRIDGE_REJECT=m
|
||||
CONFIG_BRIDGE_NF_EBTABLES=m
|
||||
CONFIG_BRIDGE_EBT_BROUTE=m
|
||||
CONFIG_BRIDGE_EBT_T_FILTER=m
|
||||
CONFIG_BRIDGE_EBT_T_NAT=m
|
||||
CONFIG_BRIDGE_EBT_802_3=m
|
||||
CONFIG_BRIDGE_EBT_AMONG=m
|
||||
CONFIG_BRIDGE_EBT_ARP=m
|
||||
CONFIG_BRIDGE_EBT_IP=m
|
||||
CONFIG_BRIDGE_EBT_IP6=m
|
||||
CONFIG_BRIDGE_EBT_LIMIT=m
|
||||
CONFIG_BRIDGE_EBT_MARK=m
|
||||
CONFIG_BRIDGE_EBT_PKTTYPE=m
|
||||
CONFIG_BRIDGE_EBT_STP=m
|
||||
CONFIG_BRIDGE_EBT_VLAN=m
|
||||
CONFIG_BRIDGE_EBT_ARPREPLY=m
|
||||
CONFIG_BRIDGE_EBT_DNAT=m
|
||||
CONFIG_BRIDGE_EBT_MARK_T=m
|
||||
CONFIG_BRIDGE_EBT_REDIRECT=m
|
||||
CONFIG_BRIDGE_EBT_SNAT=m
|
||||
CONFIG_BRIDGE_EBT_LOG=m
|
||||
CONFIG_BRIDGE_EBT_NFLOG=m
|
||||
CONFIG_L2TP=m
|
||||
CONFIG_BRIDGE=m
|
||||
CONFIG_VLAN_8021Q=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q_MVRP=y
|
||||
CONFIG_LLC2=m
|
||||
CONFIG_6LOWPAN=m
|
||||
CONFIG_6LOWPAN_DEBUGFS=y
|
||||
CONFIG_IEEE802154=m
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_CBQ=m
|
||||
CONFIG_NET_SCH_HTB=m
|
||||
CONFIG_NET_SCH_HFSC=m
|
||||
CONFIG_NET_SCH_PRIO=m
|
||||
CONFIG_NET_SCH_MULTIQ=m
|
||||
CONFIG_NET_SCH_RED=m
|
||||
CONFIG_NET_SCH_SFB=m
|
||||
CONFIG_NET_SCH_SFQ=m
|
||||
CONFIG_NET_SCH_TEQL=m
|
||||
CONFIG_NET_SCH_TBF=m
|
||||
CONFIG_NET_SCH_GRED=m
|
||||
CONFIG_NET_SCH_DSMARK=m
|
||||
CONFIG_NET_SCH_NETEM=m
|
||||
CONFIG_NET_SCH_DRR=m
|
||||
CONFIG_NET_SCH_MQPRIO=m
|
||||
CONFIG_NET_SCH_CHOKE=m
|
||||
CONFIG_NET_SCH_QFQ=m
|
||||
CONFIG_NET_SCH_CODEL=m
|
||||
CONFIG_NET_SCH_FQ_CODEL=m
|
||||
CONFIG_NET_SCH_FQ=m
|
||||
CONFIG_NET_SCH_HHF=m
|
||||
CONFIG_NET_SCH_PIE=m
|
||||
CONFIG_NET_SCH_PLUG=m
|
||||
CONFIG_NET_SCH_DEFAULT=y
|
||||
CONFIG_NET_CLS_BASIC=m
|
||||
CONFIG_NET_CLS_TCINDEX=m
|
||||
CONFIG_NET_CLS_ROUTE4=m
|
||||
CONFIG_NET_CLS_FW=m
|
||||
CONFIG_NET_CLS_U32=m
|
||||
CONFIG_CLS_U32_PERF=y
|
||||
CONFIG_CLS_U32_MARK=y
|
||||
CONFIG_NET_CLS_RSVP=m
|
||||
CONFIG_NET_CLS_RSVP6=m
|
||||
CONFIG_NET_CLS_FLOW=m
|
||||
CONFIG_NET_CLS_CGROUP=m
|
||||
CONFIG_NET_CLS_BPF=m
|
||||
CONFIG_NET_CLS_FLOWER=m
|
||||
CONFIG_NET_CLS_MATCHALL=m
|
||||
CONFIG_NET_EMATCH=y
|
||||
CONFIG_NET_EMATCH_CMP=m
|
||||
CONFIG_NET_EMATCH_NBYTE=m
|
||||
CONFIG_NET_EMATCH_U32=m
|
||||
CONFIG_NET_EMATCH_META=m
|
||||
CONFIG_NET_EMATCH_TEXT=m
|
||||
CONFIG_NET_EMATCH_CANID=m
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_NET_ACT_POLICE=m
|
||||
CONFIG_NET_ACT_GACT=m
|
||||
CONFIG_GACT_PROB=y
|
||||
CONFIG_NET_ACT_MIRRED=m
|
||||
CONFIG_NET_ACT_SAMPLE=m
|
||||
CONFIG_NET_ACT_NAT=m
|
||||
CONFIG_NET_ACT_PEDIT=m
|
||||
CONFIG_NET_ACT_CSUM=m
|
||||
CONFIG_NET_ACT_VLAN=m
|
||||
CONFIG_NET_ACT_BPF=m
|
||||
CONFIG_NET_ACT_SKBMOD=m
|
||||
CONFIG_NET_ACT_IFE=m
|
||||
CONFIG_NET_ACT_TUNNEL_KEY=m
|
||||
CONFIG_NET_IFE_SKBMARK=m
|
||||
CONFIG_NET_IFE_SKBPRIO=m
|
||||
CONFIG_NET_IFE_SKBTCINDEX=m
|
||||
CONFIG_DCB=y
|
||||
CONFIG_BATMAN_ADV=m
|
||||
CONFIG_BATMAN_ADV_NC=y
|
||||
CONFIG_BATMAN_ADV_DEBUG=y
|
||||
CONFIG_OPENVSWITCH=m
|
||||
CONFIG_VSOCKETS=m
|
||||
CONFIG_VIRTIO_VSOCKETS=m
|
||||
CONFIG_NETLINK_DIAG=m
|
||||
CONFIG_HSR=m
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_CGROUP_NET_PRIO=y
|
||||
CONFIG_CAN=y
|
||||
CONFIG_CAN_M_CAN=y
|
||||
CONFIG_CAN_M_CAN_PLATFORM=y
|
||||
CONFIG_BT=m
|
||||
CONFIG_BT_6LOWPAN=m
|
||||
CONFIG_BT_HCIUART=m
|
||||
CONFIG_BT_HCIUART_BCM=y
|
||||
CONFIG_BT_MRVL=m
|
||||
CONFIG_BT_MRVL_SDIO=m
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_RFKILL_INPUT=y
|
||||
CONFIG_RFKILL_GPIO=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_VEXPRESS_CONFIG=y
|
||||
CONFIG_TRUSTED_FOUNDATIONS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_MCHP23K256=m
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_MTD_NAND_DENALI_DT=y
|
||||
CONFIG_MTD_NAND_BRCMNAND=y
|
||||
CONFIG_MTD_NAND_STM32_FMC2=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
||||
CONFIG_VIRTIO_BLK=y
|
||||
CONFIG_AD525X_DPOT=y
|
||||
CONFIG_AD525X_DPOT_I2C=y
|
||||
CONFIG_ICS932S401=y
|
||||
CONFIG_APDS9802ALS=y
|
||||
CONFIG_ISL29003=y
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_EEPROM_93CX6=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_AHCI_PLATFORM=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_MACVLAN=m
|
||||
CONFIG_MACVTAP=m
|
||||
CONFIG_TUN=m
|
||||
CONFIG_TUN_VNET_CROSS_LE=y
|
||||
CONFIG_VETH=m
|
||||
CONFIG_VIRTIO_NET=y
|
||||
# CONFIG_NET_VENDOR_ALACRITECH is not set
|
||||
# CONFIG_NET_VENDOR_AMAZON is not set
|
||||
# CONFIG_NET_VENDOR_AQUANTIA is not set
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CADENCE is not set
|
||||
# CONFIG_NET_VENDOR_CAVIUM is not set
|
||||
# CONFIG_NET_VENDOR_CIRRUS is not set
|
||||
# CONFIG_NET_VENDOR_CORTINA is not set
|
||||
# CONFIG_NET_VENDOR_EZCHIP is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_GOOGLE is not set
|
||||
# CONFIG_NET_VENDOR_HISILICON is not set
|
||||
# CONFIG_NET_VENDOR_HUAWEI is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_LITEX is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MELLANOX is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
||||
# CONFIG_NET_VENDOR_MICROSEMI is not set
|
||||
# CONFIG_NET_VENDOR_MICROSOFT is not set
|
||||
# CONFIG_NET_VENDOR_NI is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NETRONOME is not set
|
||||
# CONFIG_NET_VENDOR_QUALCOMM is not set
|
||||
# CONFIG_NET_VENDOR_RENESAS is not set
|
||||
# CONFIG_NET_VENDOR_ROCKER is not set
|
||||
# CONFIG_NET_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SOLARFLARE is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
# CONFIG_NET_VENDOR_SOCIONEXT is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_DWMAC_DWC_QOS_ETH=y
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
# CONFIG_NET_VENDOR_XILINX is not set
|
||||
CONFIG_MOTORCOMM_PHY=y
|
||||
CONFIG_MDIO_BITBANG=y
|
||||
CONFIG_PPP=y
|
||||
CONFIG_PPP_BSDCOMP=y
|
||||
CONFIG_PPP_DEFLATE=y
|
||||
CONFIG_PPP_FILTER=y
|
||||
CONFIG_PPP_MPPE=y
|
||||
CONFIG_PPP_MULTILINK=y
|
||||
CONFIG_PPPOE=y
|
||||
CONFIG_PPTP=m
|
||||
CONFIG_PPPOL2TP=m
|
||||
CONFIG_PPP_ASYNC=y
|
||||
CONFIG_PPP_SYNC_TTY=y
|
||||
CONFIG_USB_PEGASUS=m
|
||||
CONFIG_USB_RTL8152=m
|
||||
CONFIG_USB_USBNET=y
|
||||
CONFIG_USB_NET_CDC_MBIM=y
|
||||
CONFIG_USB_NET_SMSC75XX=y
|
||||
CONFIG_USB_NET_SMSC95XX=y
|
||||
CONFIG_USB_NET_RNDIS_HOST=y
|
||||
CONFIG_USB_NET_QMI_WWAN=y
|
||||
# CONFIG_WLAN_VENDOR_ADMTEK is not set
|
||||
# CONFIG_WLAN_VENDOR_ATMEL is not set
|
||||
CONFIG_BRCMFMAC=m
|
||||
CONFIG_MWIFIEX=m
|
||||
CONFIG_MWIFIEX_SDIO=m
|
||||
CONFIG_RT2X00=m
|
||||
CONFIG_RT2800USB=m
|
||||
# CONFIG_WLAN_VENDOR_TI is not set
|
||||
# CONFIG_WLAN_VENDOR_ZYDAS is not set
|
||||
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
# CONFIG_MOUSE_PS2 is not set
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=m
|
||||
CONFIG_INPUT_STPMIC1_ONKEY=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_LEGACY_PTY_COUNT=8
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_STM32=y
|
||||
CONFIG_SERIAL_STM32_CONSOLE=y
|
||||
CONFIG_SERIAL_NONSTANDARD=y
|
||||
CONFIG_RPMSG_TTY=m
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_TCG_TPM=m
|
||||
CONFIG_TCG_TIS_I2C_INFINEON=m
|
||||
# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_I2C_MUX_PINCTRL=y
|
||||
CONFIG_I2C_DEMUX_PINCTRL=y
|
||||
CONFIG_I2C_STM32F7=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_CADENCE=y
|
||||
CONFIG_SPI_GPIO=m
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_SPI_STM32=y
|
||||
CONFIG_SPI_STM32_QSPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
CONFIG_SPMI=y
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_PINCTRL_STMFX=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_PL061=y
|
||||
CONFIG_GPIO_SYSCON=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_BRCMKONA=y
|
||||
CONFIG_POWER_RESET_BRCMSTB=y
|
||||
CONFIG_POWER_RESET_GPIO=y
|
||||
CONFIG_POWER_RESET_GPIO_RESTART=y
|
||||
CONFIG_POWER_RESET_VEXPRESS=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
|
||||
CONFIG_SYSCON_REBOOT_MODE=y
|
||||
CONFIG_CHARGER_GPIO=m
|
||||
CONFIG_SENSORS_ARM_SCMI=y
|
||||
CONFIG_SENSORS_IIO_HWMON=y
|
||||
CONFIG_SENSORS_LM90=y
|
||||
CONFIG_SENSORS_LM95245=y
|
||||
CONFIG_SENSORS_NTC_THERMISTOR=m
|
||||
CONFIG_SENSORS_PWM_FAN=m
|
||||
CONFIG_SENSORS_INA2XX=m
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_DEVFREQ_THERMAL=y
|
||||
CONFIG_ST_THERMAL_MEMMAP=y
|
||||
CONFIG_GENERIC_ADC_THERMAL=m
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_WATCHDOG_NOWAYOUT=y
|
||||
CONFIG_WATCHDOG_SYSFS=y
|
||||
CONFIG_GPIO_WATCHDOG=y
|
||||
CONFIG_ARM_SP805_WATCHDOG=y
|
||||
CONFIG_DW_WATCHDOG=y
|
||||
CONFIG_STPMIC1_WATCHDOG=y
|
||||
CONFIG_MFD_STMPE=y
|
||||
CONFIG_MFD_STM32_LPTIMER=m
|
||||
CONFIG_MFD_STPMIC1=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_ARM_SCMI=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_STM32_BOOSTER=m
|
||||
CONFIG_REGULATOR_STM32_VREFBUF=y
|
||||
CONFIG_REGULATOR_STM32_PWR=y
|
||||
CONFIG_REGULATOR_STPMIC1=y
|
||||
CONFIG_REGULATOR_VEXPRESS=y
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_STM=y
|
||||
CONFIG_DRM_STM_DSI=y
|
||||
CONFIG_DRM_PANEL_SIMPLE=y
|
||||
CONFIG_DRM_SII902X=m
|
||||
CONFIG_DRM_SII9234=m
|
||||
CONFIG_DRM_SIMPLE_BRIDGE=m
|
||||
CONFIG_DRM_STI=m
|
||||
CONFIG_DRM_ETNAVIV=m
|
||||
CONFIG_DRM_SIMPLEDRM=y
|
||||
CONFIG_DRM_PL111=m
|
||||
CONFIG_DRM_LIMA=m
|
||||
CONFIG_DRM_PANFROST=m
|
||||
CONFIG_DRM_LEGACY=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_BACKLIGHT_GPIO=y
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_CONN_GPIO=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_OTG=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_UAS=y
|
||||
CONFIG_USBIP_CORE=y
|
||||
CONFIG_USBIP_HOST=y
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_SERIAL=y
|
||||
CONFIG_USB_SERIAL_SIMPLE=m
|
||||
CONFIG_USB_SERIAL_CP210X=m
|
||||
CONFIG_USB_SERIAL_FTDI_SIO=m
|
||||
CONFIG_USB_SERIAL_OPTION=y
|
||||
CONFIG_USB_HSIC_USB3503=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_USB_GPIO_VBUS=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_SNP_UDC_PLAT=y
|
||||
CONFIG_USB_BDC_UDC=y
|
||||
CONFIG_USB_CONFIGFS=m
|
||||
CONFIG_USB_CONFIGFS_SERIAL=y
|
||||
CONFIG_USB_CONFIGFS_ACM=y
|
||||
CONFIG_USB_CONFIGFS_OBEX=y
|
||||
CONFIG_USB_CONFIGFS_NCM=y
|
||||
CONFIG_USB_CONFIGFS_ECM=y
|
||||
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
|
||||
CONFIG_USB_CONFIGFS_RNDIS=y
|
||||
CONFIG_USB_CONFIGFS_EEM=y
|
||||
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
|
||||
CONFIG_USB_CONFIGFS_F_LB_SS=y
|
||||
CONFIG_USB_CONFIGFS_F_FS=y
|
||||
CONFIG_USB_CONFIGFS_F_HID=y
|
||||
CONFIG_USB_CONFIGFS_F_PRINTER=y
|
||||
CONFIG_USB_ETH=m
|
||||
CONFIG_USB_MASS_STORAGE=m
|
||||
CONFIG_TYPEC=y
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
CONFIG_TYPEC_TCPCI=y
|
||||
CONFIG_TYPEC_UCSI=y
|
||||
CONFIG_UCSI_STM32G0=m
|
||||
CONFIG_TYPEC_STUSB160X=y
|
||||
CONFIG_TYPEC_MUX_PI3USB30532=y
|
||||
CONFIG_TYPEC_DP_ALTMODE=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK_MINORS=16
|
||||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_AT91=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_EXYNOS=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_CLASS_FLASH=m
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PWM=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_ONESHOT=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_LEDS_TRIGGER_ACTIVITY=y
|
||||
CONFIG_LEDS_TRIGGER_GPIO=y
|
||||
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
||||
CONFIG_LEDS_TRIGGER_TRANSIENT=y
|
||||
CONFIG_LEDS_TRIGGER_CAMERA=y
|
||||
CONFIG_LEDS_TRIGGER_PANIC=y
|
||||
CONFIG_LEDS_TRIGGER_AUDIO=m
|
||||
CONFIG_EDAC=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_RX8010=y
|
||||
CONFIG_RTC_DRV_PL031=y
|
||||
CONFIG_RTC_DRV_STM32=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_STM32_DMA=y
|
||||
CONFIG_STM32_DMAMUX=y
|
||||
CONFIG_STM32_MDMA=y
|
||||
CONFIG_DW_DMAC=y
|
||||
CONFIG_VIRTIO_MMIO=y
|
||||
CONFIG_ICST=y
|
||||
CONFIG_CLK_SP810=y
|
||||
CONFIG_CLK_VEXPRESS_OSC=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HWSPINLOCK_STM32=y
|
||||
CONFIG_CLKSRC_STM32_LP=y
|
||||
CONFIG_MICROCHIP_PIT64B=y
|
||||
CONFIG_PL320_MBOX=y
|
||||
CONFIG_STM32_IPCC=y
|
||||
CONFIG_REMOTEPROC=y
|
||||
CONFIG_REMOTEPROC_SRM_CORE=y
|
||||
CONFIG_REMOTEPROC_SRM_DEV=y
|
||||
CONFIG_STM32_RPROC=y
|
||||
CONFIG_RPMSG_VIRTIO=y
|
||||
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
|
||||
CONFIG_DEVFREQ_GOV_PASSIVE=m
|
||||
CONFIG_PM_DEVFREQ_EVENT=y
|
||||
CONFIG_EXTCON_GPIO=y
|
||||
CONFIG_EXTCON_PTN5150=y
|
||||
CONFIG_MEMORY=y
|
||||
CONFIG_STM32_FMC2_EBI=y
|
||||
CONFIG_IIO=y
|
||||
CONFIG_IIO_BUFFER_CB=m
|
||||
CONFIG_IIO_SW_TRIGGER=y
|
||||
CONFIG_SD_ADC_MODULATOR=y
|
||||
CONFIG_STM32_ADC_CORE=m
|
||||
CONFIG_STM32_ADC=m
|
||||
CONFIG_STM32_DFSDM_ADC=m
|
||||
CONFIG_STMPE_ADC=m
|
||||
CONFIG_STM32_DAC=m
|
||||
CONFIG_HTS221=y
|
||||
CONFIG_IIO_HRTIMER_TRIGGER=y
|
||||
CONFIG_IIO_STM32_LPTIMER_TRIGGER=m
|
||||
CONFIG_IIO_ST_PRESS=m
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_STM32=m
|
||||
CONFIG_PWM_STM32_LP=m
|
||||
CONFIG_PHY_CPCAP_USB=m
|
||||
CONFIG_PHY_STM32_USBPHYC=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_NVMEM_STM32_ROMEM=y
|
||||
CONFIG_NVMEM_RMEM=m
|
||||
CONFIG_FSI=m
|
||||
CONFIG_FSI_MASTER_GPIO=m
|
||||
CONFIG_FSI_MASTER_HUB=m
|
||||
CONFIG_FSI_MASTER_ASPEED=m
|
||||
CONFIG_FSI_SCOM=m
|
||||
CONFIG_FSI_SBEFIFO=m
|
||||
CONFIG_FSI_OCC=m
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_INTERCONNECT=y
|
||||
CONFIG_COUNTER=m
|
||||
CONFIG_STM32_TIMER_CNT=m
|
||||
CONFIG_STM32_LPTIMER_CNT=m
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_AUTOFS4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_OVERLAY_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_SQUASHFS=y
|
||||
CONFIG_SQUASHFS_LZO=y
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_PSTORE=y
|
||||
CONFIG_PSTORE_CONSOLE=y
|
||||
CONFIG_PSTORE_PMSG=y
|
||||
CONFIG_PSTORE_RAM=y
|
||||
CONFIG_SYSV_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_NFS_V4_1=y
|
||||
CONFIG_NFS_V4_2=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_UTF8=y
|
||||
CONFIG_CRYPTO_USER=m
|
||||
CONFIG_CRYPTO_XTS=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_USER_API_HASH=y
|
||||
CONFIG_CRYPTO_USER_API_SKCIPHER=m
|
||||
CONFIG_CRYPTO_USER_API_RNG=m
|
||||
CONFIG_CRYPTO_USER_API_AEAD=m
|
||||
CONFIG_CRYPTO_DEV_STM32_CRC=m
|
||||
CONFIG_CRYPTO_DEV_STM32_HASH=m
|
||||
CONFIG_CRYPTO_DEV_STM32_CRYP=m
|
||||
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
|
||||
CONFIG_CRC_ITU_T=m
|
||||
CONFIG_CMA_SIZE_MBYTES=64
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_GDB_SCRIPTS=y
|
||||
CONFIG_DEBUG_SECTION_MISMATCH=y
|
||||
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_SAMPLES=y
|
||||
CONFIG_SAMPLE_RPMSG_CLIENT=m
|
||||
File diff suppressed because it is too large
Load Diff
@ -259,6 +259,8 @@ static void option_instat_callback(struct urb *urb);
|
||||
#define QUECTEL_PRODUCT_EC200S_CN 0x6002
|
||||
#define QUECTEL_PRODUCT_EC200T 0x6026
|
||||
#define QUECTEL_PRODUCT_RM500K 0x7001
|
||||
#define QUECTEL_PRODUCT_RG200U 0x0900
|
||||
#define QUECTEL_PRODUCT_EC200A 0x6005
|
||||
|
||||
#define CMOTECH_VENDOR_ID 0x16d8
|
||||
#define CMOTECH_PRODUCT_6001 0x6001
|
||||
@ -580,6 +582,9 @@ static void option_instat_callback(struct urb *urb);
|
||||
#define OPPO_VENDOR_ID 0x22d9
|
||||
#define OPPO_PRODUCT_R11 0x276c
|
||||
|
||||
/* Lierda products */
|
||||
#define LIERDA_VENDOR_ID 0x3505
|
||||
#define LIERDA_PRODUCT_NR90 0x1101
|
||||
|
||||
/* Device flags */
|
||||
|
||||
@ -1162,6 +1167,9 @@ static const struct usb_device_id option_ids[] = {
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200S_CN, 0xff, 0, 0) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200T, 0xff, 0, 0) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500K, 0xff, 0x00, 0x00) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RG200U, 0xff, 0x00, 0x00) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200A, 0xff, 0x00, 0x00),
|
||||
.driver_info = RSVD(0) | RSVD(1) },
|
||||
|
||||
{ USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6001) },
|
||||
{ USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_CMU_300) },
|
||||
@ -2170,6 +2178,11 @@ static const struct usb_device_id option_ids[] = {
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1405, 0xff) }, /* GosunCn GM500 MBIM */
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1406, 0xff) }, /* GosunCn GM500 ECM/NCM */
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(OPPO_VENDOR_ID, OPPO_PRODUCT_R11, 0xff, 0xff, 0x30) },
|
||||
{ USB_VENDOR_AND_INTERFACE_INFO(LIERDA_VENDOR_ID, 0xff, 0x03, 0x01) }, // Lierda NR90 Modem
|
||||
{ USB_VENDOR_AND_INTERFACE_INFO(LIERDA_VENDOR_ID, 0xff, 0x03, 0x03) }, // Lierda NR90 Cali
|
||||
{ USB_VENDOR_AND_INTERFACE_INFO(LIERDA_VENDOR_ID, 0xff, 0x03, 0x12) }, // Lierda NR90 AT
|
||||
{ USB_VENDOR_AND_INTERFACE_INFO(LIERDA_VENDOR_ID, 0xff, 0x03, 0x13) }, // Lierda NR90 Diag Data
|
||||
{ USB_VENDOR_AND_INTERFACE_INFO(LIERDA_VENDOR_ID, 0xff, 0x03, 0x14) }, // Lierda NR90 Diag Command
|
||||
{ } /* Terminating entry */
|
||||
};
|
||||
MODULE_DEVICE_TABLE(usb, option_ids);
|
||||
@ -2204,6 +2217,7 @@ static struct usb_serial_driver option_1port_device = {
|
||||
.suspend = usb_wwan_suspend,
|
||||
.resume = usb_wwan_resume,
|
||||
#endif
|
||||
.reset_resume = usb_wwan_resume,
|
||||
};
|
||||
|
||||
static struct usb_serial_driver * const serial_drivers[] = {
|
||||
|
||||
@ -432,6 +432,14 @@ static struct urb *usb_wwan_setup_urb(struct usb_serial_port *port,
|
||||
usb_sndbulkpipe(serial->dev, endpoint) | dir,
|
||||
buf, len, callback, ctx);
|
||||
|
||||
// Quectel for zero packet
|
||||
if (dir == USB_DIR_OUT) {
|
||||
struct usb_device_descriptor *desc = &serial->dev->descriptor;
|
||||
|
||||
if (desc->idVendor == cpu_to_le16(0x2C7C))
|
||||
urb->transfer_flags |= URB_ZERO_PACKET;
|
||||
}
|
||||
|
||||
if (intfdata->use_zlp && dir == USB_DIR_OUT)
|
||||
urb->transfer_flags |= URB_ZERO_PACKET;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user