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dts: add stm32mp135 gateway board

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This commit is contained in:
Steve Chen
2023-07-06 15:18:15 +08:00
parent 3984366f69
commit f2edc5c545
5 changed files with 1181 additions and 1 deletions
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3
arch/arm/dts/Makefile
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@ -1075,7 +1075,8 @@ dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13x) += \
stm32mp135f-dk.dtb
stm32mp135f-dk.dtb \
stm32mp135d-gateway.dtb
dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \

662
arch/arm/dts/stm32mp13-gateway-pinctrl.dtsi Executable file
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@ -0,0 +1,662 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) i2SOM 2023 - All Rights Reserved
* Author: Steve Chen <steve.chen@i2som.com>
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1 in12 */
<STM32_PINMUX('A', 5, ANALOG)>; /* ADC1 in6 */
};
};
eth1_rgmii_pins_a: eth1_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 7, AF10)>, /* ETH1_RX_CLK */
<STM32_PINMUX('A', 7, AF11)>, /* ETH1_RX_CTL */
<STM32_PINMUX('B', 0, AF11)>, /* ETH1_RXD2 */
<STM32_PINMUX('B', 1, AF11)>, /* ETH1_RXD3 */
<STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('B', 11, AF11)>, /* ETH1_TX_CTL */
<STM32_PINMUX('C', 1, AF11)>, /* ETH1_GTX_CLK */
<STM32_PINMUX('C', 2, AF11)>, /* ETH1_TXD2 */
<STM32_PINMUX('E', 5, AF10)>, /* ETH1_TXD3 */
<STM32_PINMUX('F', 12, AF11)>, /* ETH1_CLK125 */
<STM32_PINMUX('G', 2, AF11)>, /* ETH1_MDC */
<STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
<STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
eth1_rgmii_sleep_pins_a: eth1_sleep_mx-0 {
pins {
pinmux = <STM32_PINMUX('D', 7, ANALOG)>, /* ETH1_RX_CLK */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
<STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_RX_CTL */
<STM32_PINMUX('B', 0, ANALOG)>, /* ETH1_RXD2 */
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH1_RXD3 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_CTL */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_GTX_CLK */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH1_TXD2 */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
<STM32_PINMUX('E', 5, ANALOG)>, /* ETH1_TXD3 */
<STM32_PINMUX('F', 12, ANALOG)>, /* ETH1_CLK125 */
<STM32_PINMUX('G', 2, ANALOG)>, /* ETH1_MDC */
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
};
};
eth2_rgmii_pins_a: eth2_mx-0 {
pins1 {
pinmux =
<STM32_PINMUX('F', 7, AF11)>, /* ETH2_TXD0 */
<STM32_PINMUX('G', 11, AF10)>, /* ETH2_TXD1 */
<STM32_PINMUX('G', 1, AF10)>, /* ETH2_TXD2 */
<STM32_PINMUX('E', 6, AF11)>, /* ETH2_TXD3 */
<STM32_PINMUX('F', 6, AF11)>, /* ETH2_TX_CTL */
<STM32_PINMUX('G', 3, AF10)>, /* ETH2_GTX_CLK */
<STM32_PINMUX('G', 5, AF10)>, /* ETH2_MDC */
<STM32_PINMUX('B', 6, AF11)>, /* ETH2_MDIO */
<STM32_PINMUX('H', 2, AF13)>; /* ETH2_CLK125 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux =
<STM32_PINMUX('A', 12, AF11)>, /* ETH2_RX_CTL */
<STM32_PINMUX('F', 4, AF11)>, /* ETH2_RXD0 */
<STM32_PINMUX('E', 2, AF10)>, /* ETH2_RXD1 */
<STM32_PINMUX('H', 6, AF12)>, /* ETH2_RXD2 */
<STM32_PINMUX('A', 8, AF11)>, /* ETH2_RXD3 */
<STM32_PINMUX('H', 11, AF11)>; /* ETH2_RX_CLK */
bias-disable;
};
};
eth2_rgmii_sleep_pins_a: eth2_sleep_mx-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* ETH2_RXD3 */
<STM32_PINMUX('A', 12, ANALOG)>, /* ETH2_RX_CTL */
<STM32_PINMUX('B', 6, ANALOG)>, /* ETH2_MDIO */
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH2_RXD1 */
<STM32_PINMUX('E', 6, ANALOG)>, /* ETH2_TXD3 */
<STM32_PINMUX('F', 4, ANALOG)>, /* ETH2_RXD0 */
<STM32_PINMUX('F', 6, ANALOG)>, /* ETH2_TX_CTL */
<STM32_PINMUX('F', 7, ANALOG)>, /* ETH2_TXD0 */
<STM32_PINMUX('G', 1, ANALOG)>, /* ETH2_TXD2 */
<STM32_PINMUX('G', 3, ANALOG)>, /* ETH2_GTX_CLK */
<STM32_PINMUX('G', 5, ANALOG)>, /* ETH2_MDC */
<STM32_PINMUX('G', 11, ANALOG)>, /* ETH2_TXD1 */
<STM32_PINMUX('H', 2, ANALOG)>, /* ETH2_CLK125 */
<STM32_PINMUX('H', 6, ANALOG)>, /* ETH2_RXD2 */
<STM32_PINMUX('H', 11, ANALOG)>; /* ETH2_RX_CLK */
};
};
goodix_pins_a: goodix-0 {
pins {
pinmux = <STM32_PINMUX('F', 5, GPIO)>;
bias-pull-down;
};
};
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
<STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c1_sleep_pins_a: i2c1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
<STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
};
};
i2c3_pins_test_b: i2c3-test-1 {
pins {
pinmux = <STM32_PINMUX('H', 3, AF4)>, /* i2c3_SCL */
<STM32_PINMUX('H', 7, AF5)>; /* i2c3_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c3_sleep_pins_test_b: i2c3-test-sleep-1 {
pins {
pinmux = <STM32_PINMUX('H', 3, ANALOG)>, /* i2c3_SCL */
<STM32_PINMUX('H', 7, ANALOG)>; /* i2c3_SDA */
};
};
i2c5_pins_a: i2c5-0 {
pins {
pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
<STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c5_sleep_pins_a: i2c5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
<STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
};
};
ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
<STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */
<STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */
<STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */
<STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */
<STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */
<STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */
<STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */
<STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */
<STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
<STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */
<STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */
<STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */
<STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */
<STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */
<STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */
<STM32_PINMUX('F', 2, AF14)>, /* LCD_B3 */
<STM32_PINMUX('H', 14, AF11)>, /* LCD_B4 */
<STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */
<STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */
<STM32_PINMUX('F', 1, AF13)>; /* LCD_B7 */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
ltdc_sleep_pins_a: ltdc-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
<STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */
<STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */
<STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */
<STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */
<STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */
<STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */
<STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */
<STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */
<STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */
<STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
<STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */
<STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */
<STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */
<STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */
<STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */
<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */
<STM32_PINMUX('F', 2, ANALOG)>, /* LCD_B3 */
<STM32_PINMUX('H', 14, ANALOG)>, /* LCD_B4 */
<STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */
<STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */
<STM32_PINMUX('F', 1, ANALOG)>; /* LCD_B7 */
};
};
m_can2_pins_a: m-can2-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 1, AF9)>; /* CAN2_TX */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('G', 3, AF9)>; /* CAN2_RX */
bias-disable;
};
};
m_can2_sleep_pins_a: m_can2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('G', 1, ANALOG)>, /* CAN2_TX */
<STM32_PINMUX('G', 3, ANALOG)>; /* CAN2_RX */
};
};
pwm3_pins_a: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm3_sleep_pins_a: pwm3-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
};
};
pwm4_pins_a: pwm4-0 {
pins {
pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm4_sleep_pins_a: pwm4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
};
};
pwm8_pins_a: pwm8-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm8_sleep_pins_a: pwm8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
};
};
pwm14_pins_a: pwm12-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm14_sleep_pins_a: pwm12-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
};
};
rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
pins {
pinmux = <STM32_PINMUX('I', 1, ANALOG)>; /* RTC_OUT2_RMP */
};
};
sai1_pins_a: sai1-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
<STM32_PINMUX('A', 0, AF6)>, /* SAI1_SD_B */
<STM32_PINMUX('A', 5, AF6)>, /* SAI1_SD_A */
<STM32_PINMUX('F', 11, AF6)>; /* SAI1_FS_A */
slew-rate = <0>;
drive-push-pull;
bias-disable;
};
};
sai1_sleep_pins_a: sai1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
<STM32_PINMUX('A', 0, ANALOG)>, /* SAI1_SD_B */
<STM32_PINMUX('A', 5, ANALOG)>, /* SAI1_SD_A */
<STM32_PINMUX('F', 11, ANALOG)>; /* SAI1_FS_A */
};
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-open-drain;
bias-disable;
};
};
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
};
};
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
pins {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
<STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
<STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>, /* SDMMC2_D7 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
<STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
<STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
pins2 {
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-open-drain;
bias-pull-up;
};
};
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
<STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC2_D7 */
<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
pins {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
spi5_pins_a: spi5-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
<STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
bias-disable;
};
};
spi5_sleep_pins_a: spi5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
<STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
<STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
};
};
stm32g0_intn_pins_a: stm32g0-intn-0 {
pins {
pinmux = <STM32_PINMUX('I', 2, GPIO)>;
bias-pull-up;
};
};
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_idle_pins_a: uart4-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_sleep_pins_a: uart4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
};
};
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
uart8_idle_pins_a: uart8-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
uart8_sleep_pins_a: uart8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
<STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
};
};
usart1_idle_pins_a: usart1-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
bias-pull-up;
};
};
usart1_sleep_pins_a: usart1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
<STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
<STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
<STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
bias-disable;
};
};
usart2_idle_pins_a: usart2-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
bias-disable;
};
};
usart2_sleep_pins_a: usart2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
};
m_can2_pins_a: m-can2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
bias-disable;
};
};
m_can2_sleep_pins_a: m_can2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
<STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
};
};
quadspi_pins_mx: quadspi_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* QUADSPI_BK1_NCS */
<STM32_PINMUX('D', 7, AF11)>, /* QUADSPI_BK1_IO2 */
<STM32_PINMUX('D', 13, AF9)>, /* QUADSPI_BK1_IO3 */
<STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>; /* QUADSPI_BK1_IO1 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
quadspi_sleep_pins_mx: quadspi_sleep_mx-0 {
pins {
pinmux = <STM32_PINMUX('B', 2, ANALOG)>, /* QUADSPI_BK1_NCS */
<STM32_PINMUX('D', 7, ANALOG)>, /* QUADSPI_BK1_IO2 */
<STM32_PINMUX('D', 13, ANALOG)>, /* QUADSPI_BK1_IO3 */
<STM32_PINMUX('F', 8, ANALOG)>, /* QUADSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, ANALOG)>, /* QUADSPI_BK1_IO1 */
<STM32_PINMUX('F', 10, ANALOG)>; /* QUADSPI_CLK */
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/rtc/rtc-stm32.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
#include "stm32mp13-gateway-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32MP135F-DK Discovery Board";
compatible = "st,stm32mp135f-dk", "st,stm32mp135";
aliases {
ethernet0 = &eth1;
ethernet1 = &eth2;
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
serial3 = &usart2;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_mco1: clk-mco1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
/*
leds {
compatible = "gpio-leds";
led-blue {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
*/
v3v3_ao: v3v3_ao {
compatible = "regulator-fixed";
regulator-name = "v3v3_ao";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_usb: vdd_usb {
compatible = "regulator-fixed";
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&crc1 {
status = "okay";
};
&cryp {
status = "okay";
};
&dcmipp {
status = "disabled";
};
&dma1 {
sram = <&dma_pool>;
};
&dma2 {
sram = <&dma_pool>;
};
&dts {
status = "okay";
};
&i2c3 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c3_pins_test_b>;
pinctrl-1 = <&i2c3_sleep_pins_test_b>;
i2c-scl-rising-time-ns = <285>;
i2c-scl-falling-time-ns = <9>;
clock-frequency = <400000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&eth1 {
status = "okay";
pinctrl-0 = <&eth1_rgmii_pins_a>;
pinctrl-1 = <&eth1_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0_eth1>;
// st,ext-phyclk;
// st,eth-clk-sel;
st,phy-reset-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>;
mdio1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0_eth1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&eth2 {
status = "okay";
pinctrl-0 = <&eth2_rgmii_pins_a>;
pinctrl-1 = <&eth2_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0_eth2>;
// st,ext-phyclk;
// st,eth-clk-sel;
phy-supply = <&v3v3_ao>;
st,phy-reset-gpios = <&gpioh 5 GPIO_ACTIVE_HIGH>;
// reset-deassert-us = <1000>;
// reset-assert-us = <1000>;
mdio1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0_eth2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
};
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-1 = <&i2c1_sleep_pins_a>;
i2c-scl-rising-time-ns = <96>;
i2c-scl-falling-time-ns = <3>;
clock-frequency = <1000000>;
status = "disabled";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_pins_a>;
pinctrl-1 = <&i2c5_sleep_pins_a>;
i2c-scl-rising-time-ns = <170>;
i2c-scl-falling-time-ns = <5>;
clock-frequency = <400000>;
status = "disabled";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&ltdc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_a>;
pinctrl-1 = <&ltdc_sleep_pins_a>;
status = "disabled";
};
&rtc {
st,lsco = <RTC_OUT2_RMP>;
pinctrl-0 = <&rtc_out2_rmp_pins_a>;
pinctrl-names = "default";
status = "okay";
};
/* TF */
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3_ao>;
status = "okay";
};
/* eMMC */
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
non-removable;
no-sd;
no-sdio;
// st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3_ao>;
vqmmc-supply = <&v3v3_ao>;
// mmc-pwrseq = <&wifi_pwrseq>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
&spi5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi5_pins_a>;
pinctrl-1 = <&spi5_sleep_pins_a>;
status = "disabled";
};
&sram {
dma_pool: dma-sram@0 {
reg = <0x0 0x4000>;
pool;
};
};
&timers3 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm3_pins_a>;
pinctrl-1 = <&pwm3_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@2 {
status = "okay";
};
};
&timers4 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm4_pins_a>;
pinctrl-1 = <&pwm4_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@3 {
status = "okay";
};
};
&timers8 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm8_pins_a>;
pinctrl-1 = <&pwm8_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@7 {
status = "okay";
};
};
&timers14 {
status = "disabled";
pwm {
pinctrl-0 = <&pwm14_pins_a>;
pinctrl-1 = <&pwm14_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@13 {
status = "okay";
};
};
&uart4 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&uart8 {
pinctrl-names = "default", "sleep", "idle";
// pinctrl-0 = <&uart8_pins_a>;
// pinctrl-1 = <&uart8_sleep_pins_a>;
// pinctrl-2 = <&uart8_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
};
&usart1 {
pinctrl-names = "default", "sleep", "idle";
// pinctrl-0 = <&usart1_pins_a>;
// pinctrl-1 = <&usart1_sleep_pins_a>;
// pinctrl-2 = <&usart1_idle_pins_a>;
// uart-has-rtscts;
status = "disabled";
};
&usart2 {
pinctrl-names = "default", "sleep", "idle";
// pinctrl-0 = <&usart2_pins_a>;
// pinctrl-1 = <&usart2_sleep_pins_a>;
// pinctrl-2 = <&usart2_idle_pins_a>;
// uart-has-rtscts;
status = "disabled";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
u-boot,force-b-session-valid;
u-boot,force-vbus-detection;
dr_mode = "peripheral";
usb-role-switch;
role-switch-default-mode = "peripheral";
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};
&vdd_usb {
u-boot,dm-pre-reloc;
};
/*
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&quadspi_pins_mx>;
pinctrl-1 = <&quadspi_sleep_pins_mx>;
reg = <0x58003000 0x1000>,
<0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
flash0: MT29F2G01AB@0 {
compatible = "spi-nand";
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <64000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
*/

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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
*/
#include "stm32mp13-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdmmc1;
usb0 = &usbotg_hs;
};
config {
//u-boot,boot-led = "led-blue";
//u-boot,error-led = "led-red";
u-boot,mmc-env-partition = "u-boot-env";
st,adc_usb_pd = <&adc1 6>, <&adc1 12>;
//st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
//st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
watchdog-gpios = <&gpiod 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
watchdog-wdi-gpios = <&gpiod 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
};
//leds {
// led-red {
// color = <LED_COLOR_ID_RED>;
// gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
// default-state = "off";
// };
//};
};
&adc_1 {
status = "okay";
};
&uart4 {
u-boot,dm-pre-reloc;
};
&uart4_pins_a {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp135-gwbase.dts"
/ {
model = "i2SOM STM32MP135 GW103 Board";
compatible = "stm32mp135-gw103", "st,stm32mp135";
aliases {
ethernet0 = &eth1;
ethernet1 = &eth2;
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
serial3 = &usart2;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
optee_framebuffer@dd000000 {
reg = <0xdd000000 0x1000000>;
no-map;
};
optee@de000000 {
reg = <0xde000000 0x2000000>;
no-map;
};
};
};