Prepare for release 1.2.0

This patch fixes a problem with an incorrect setup for the refresh
timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c

Signed-off-by: Stefan Roese <sr@denx.de>

COPYING

@@ -1,3 +1,21 @@
+  NOTE! This copyright does *not* cover the so-called "standalone"
+applications that use U-Boot services by means of the jump table
+provided by U-Boot exactly for this purpose - this is merely
+considered normal use of U-Boot, and does *not* fall under the
+heading of "derived work".
+
+  The header files "include/image.h" and "include/asm-*/u-boot.h"
+define interfaces to U-Boot. Including these (unmodified) header
+files in another file is considered normal use of U-Boot, and does
+*not* fall under the heading of "derived work".
+
+  Also note that the GPL below is copyrighted by the Free Software
+Foundation, but the instance of code that it refers to (the U-Boot
+source code) is copyrighted by me and others who actually wrote it.
+-- Wolfgang Denk
+
+=======================================================================
+
 		    GNU GENERAL PUBLIC LICENSE
 		       Version 2, June 1991
 

CREDITS

@@ -18,26 +18,41 @@ N: Dr. Bruno Achauer
 E: bruno@exet-ag.de
 D: Support for NetBSD (both as host and target system)
 
-N: Swen Anderson
-E: sand@peppercon.de
-D: ERIC Support
-
 N: Guillaume Alexandre
 E: guillaume.alexandre@gespac.ch
 D: Add PCIPPC6 configuration
 
+N: Swen Anderson
+E: sand@peppercon.de
+D: ERIC Support
+
 N: Pantelis Antoniou
 E: panto@intracom.gr
-D: NETVIA board support, ARTOS support.
+D: NETVIA & NETPHONE board support, ARTOS support.
+D: Support for Silicon Turnkey eXpress XTc
 
 N: Pierre Aubert
 E: <p.aubert@staubli.com>
 D: Support for RPXClassic board
 
+N: Yuli Barcohen
+E: yuli@arabellasw.com
+D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
+D: Support for Zephyr Engineering ZPC.1900 board.
+D: Support for Interphase iSPAN boards.
+D: Support for Analogue&Micro Adder boards.
+D: Support for Analogue&Micro Rattler boards.
+W: http://www.arabellasw.com
+
 N: Jerry van Baren
 E: <vanbaren@cideas.com>
 D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test.
 
+N: Pavel Bartusek
+E: <pba@sysgo.com>
+D: Reiserfs support
+W: http://www.elinos.com
+
 N: Andre Beaudin
 E: <andre.beaudin@colubris.com>
 D: PCMCIA, Ethernet, TFTP
@@ -50,6 +65,12 @@ N: Raphael Bossek
 E: raphael.bossek@solutions4linux.de
 D: 8xxrom-0.3.0
 
+N: Cliff Brake
+E: cliff.brake@gmail.com
+D: Port to Vibren PXA255 IDP platform
+W: http://www.vibren.com
+W: http://bec-systems.com
+
 N: Rick Bronson
 E: rick@efn.org
 D: Atmel AT91RM9200DK and NAND support
@@ -62,18 +83,36 @@ N: Oliver Brown
 E: obrown@adventnetworks.com
 D: Port to the gw8260 board
 
+N: Curt Brune
+E: curt@cucy.com
+D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
+D: Added support for ESPD-Inc. EVB4510 Board
+W: http://www.cucy.com
+
 N: Jonathan De Bruyne
 E: jonathan.debruyne@siemens.atea.be
 D: Port to Siemens IAD210 board
 
+N: Ken Chou
+E: kchou@ieee.org
+D: Support for A3000 SBC board
+
 N: Conn Clark
 E: clark@esteem.com
 D: ESTEEM192E support
 
 N: Magnus Damm
-E: eramdam@kieray1.p.y.ki.era.ericsson.se
+E: damm@opensource.se
 D: 8xxrom
 
+N: Richard Danter
+E: richard.danter@windriver.com
+D: Support for Wind River PPMC 7xx/74xx boards
+
+N: George G. Davis
+E: gdavis@mvista.com
+D: Board ports for ADS GraphicsClient+ and Intel Assabet
+
 N: Arun Dharankar
 E: ADharankar@ATTBI.Com
 D: threads / scheduler example code
@@ -99,6 +138,11 @@ N: Dave Ellis
 E: DGE@sixnetio.com
 D: EEPROM Speedup, SXNI855T port
 
+N: Thomas Elste
+E: info@elste.org
+D: Port for the ModNET50 Board, NET+50 CPU Port
+W: http://www.imms.de
+
 N: Daniel Engstr<74>m
 E: daniel@omicron.se
 D: x86 port, Support for sc520_cdp board
@@ -142,6 +186,10 @@ N: Andreas Heppel
 E: aheppel@sysgo.de
 D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!]
 
+N: August Hoeraendl
+E: august.hoerandl@gmx.at
+D: Support for the logodl board (PXA2xx)
+
 N: Josh Huber
 E: huber@alum.wpi.edu
 D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series.
@@ -161,39 +209,90 @@ D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB"
 W: www.denx.de
 
 N: Murray Jensen
-E: Murray.Jensen@cmst.csiro.au
+E: Murray.Jensen@csiro.au
 D: Initial 8260 support; GDB support
 D: Port to Cogent+Hymod boards; Hymod Board Database
-W: http://www.msa.cmst.csiro.au/ourstaff/MurrayJensen/mjj.html
 
 N: Yoo. Jonghoon
 E: yooth@ipone.co.kr
 D: Added port to the RPXlite board
 
+N: Mark Jonas
+E: mark.jonas@freescale.com
+D: Support for Freescale Total5200 platform
+W: http://www.mobilegt.com/
+
+N: Sam Song
+E: samsongshu@yahoo.com.cn
+D: Port to the RPXlite_DW board
+
 N: Brad Kemp
 E: Brad.Kemp@seranoa.com
 D: Port to Windriver ppmc8260 board
 
+N: Sangmoon Kim
+E: dogoil@etinsys.com
+D: Support for debris board
+D: Support for KVME080 board
+
+N: Frederick W. Klatt
+E: fred.klatt@windriver.com
+D: Support for Wind River SBC8540/SBC8560 boards
+
 N: Thomas Koeller
 E: tkoeller@gmx.net
 D: Port to Motorola Sandpoint 3 (MPC8240)
 
+N: Raghu Krishnaprasad
+E: Raghu.Krishnaprasad@fci.com
+D: Support for Adder-II MPC852T evaluation board
+W: http://www.forcecomputers.com
+
+N: Bernhard Kuhn
+E: bkuhn@metrowerks.com
+D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards
+
+N: Prakash Kumar
+E: prakash@embedx.com
+D  Support for Intrinsyc CERF PXA250 board.
+
 N: Thomas Lange
-E: thomas@corelatus.com
-D: Support for GTH board; lots of PCMCIA fixes
+E: thomas@corelatus.se
+D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes
+
+N: Marc Leeman
+E: marc.leeman@barco.com
+D: Support for Barco Streaming Video Card (SVC) and Sample Compress Network (SCN)
+W: www.barco.com
 
 N: The LEOX team
 E: team@leox.org
 D: Support for LEOX boards, DS164x RTC
 W: http://www.leox.org
 
+N: Leif Lindholm
+E: leif.lindholm@i3micro.com
+D: Support for AMD dbau1550 board.
+
+N: Stephan Linz
+E: linz@li-pro.net
+D: Support for Nios Stratix Development Kit (DK-1S10)
+D: Support for SSV ADNP/ESC1 (Nios Cyclone)
+W: http://www.li-pro.net
+
 N: Raymond Lo
 E: lo@routefree.com
 D: Support for DOS partitions
 
 N: Dan Malek
-E: dan@netx4.com
+E: dan@embeddedalley.com
 D: FADSROM, the grandfather of all of this
+D: Support for Silicon Turnkey eXpress XTc
+
+N: Andrea "llandre" Marson
+E: andrea.marson@dave-tech.it
+D: Port to PPChameleonEVB board
+W: www.dave-tech.it
 
 N: Reinhard Meyer
 E: r.meyer@emk-elektronik.de
@@ -211,11 +310,26 @@ N: David M
 E: d.mueller@elsoft.ch
 D: Support for Samsung ARM920T SMDK2410 eval board
 
+N: Scott McNutt
+E: smcnutt@psyent.com
+D: Support for Altera Nios-32 CPU
+D: Support for Altera Nios-II CPU
+D: Support for Nios Cyclone Development Kit (DK-1C20)
+W: http://www.psyent.com
+
 N: Rolf Offermanns
 E: rof@sysgo.de
 D: Initial support for SSV-DNP1110, SMC91111 driver
 W: www.elinos.com
 
+N: John Otken
+E: jotken@softadvances.com
+D: Support for AMCC Luan 440SP board
+
+N: Tolunay Orkun
+E: torkun@nextio.com
+D: Support for Cogent CSB272 & CSB472 boards
+
 N: Keith Outwater
 E: keith_outwater@mvis.com
 D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC)
@@ -230,29 +344,68 @@ D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ...
 D: Support for PIP405 board
 D: Support for MIP405 board
 
+N: Dave Peverley
+E: dpeverley@mpc-data.co.uk
+W: http://www.mpc-data.co.uk
+D: OMAP730 P2 board support
+
 N: Bill Pitts
 E: wlp@mindspring.com
 D: BedBug embedded debugger code
 
+N: Daniel Poirot
+E: dan.poirot@windriver.com
+D: Support for the Wind River sbc405, sbc8240 board
+W: http://www.windriver.com
+
 N: Stefan Roese
 E: stefan.roese@esd-electronics.com
-D: IBM PPC401/403/405GP Support; Windows environment support
+D: AMCC PPC401/403/405GP Support; Windows environment support
 
 N: Erwin Rol
 E: erwin@muffin.org
 D: boot support for RTEMS
 
+N: Paul Ruhland
+E: pruhland@rochester.rr.com
+D: Port to Logic Zoom LH7A40x SDK board(s)
+
 N: Neil Russell
 E: caret@c-side.com
 D: Author of LiMon-1.4.2, which contributed some ideas
 
+N: Travis B. Sawyer
+E: travis.sawyer@sandburst.com
+D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board.  AMCC 440gx Ref Platform (Ocotea)
+
 N: Paolo Scaffardi
 E: arsenio@tin.it
 D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
 
 N: Robert Schwebel
 E: r.schwebel@pengutronix.de
-D: Support for csb226 and innokom boards (xscale)
+D: Support for csb226, logodl and innokom boards (PXA2xx)
+
+N: Aaron Sells
+E: sellsa@embeddedplanet.com
+D: Support for EP82xxM
+
+N: Art Shipkowski
+E: art@videon-central.com
+D: Support for NetSilicon NS7520
+
+N: Yasushi Shoji
+E: yashi@atmark-techno.com
+D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
+
+N: Kurt Stremerch
+E: kurt@exys.be
+D: Support for Exys XSEngine board
+
+N: Andrea Scian
+E: andrea.scian@dave-tech.it
+D: Port to B2 board
+W: www.dave-tech.it
 
 N: Rob Taylor
 E: robt@flyingpig.com
@@ -270,17 +423,34 @@ N: Rune Torgersen
 E: <runet@innovsys.com>
 D: Support for Motorola MPC8266ADS board
 
+N: Greg Ungerer
+E: greg.ungerer@opengear.com
+D: Support for ks8695 CPU, and OpenGear cmXXXX boards
+
 N: David Updegraff
 E: dave@cray.com
 D: Port to Cray L1 board; DHCP vendor extensions
 
+N: Christian Vejlbo
+E: christian.vejlbo@tellabs.com
+D: FADS860T ethernet support
+
+N: Robert Whaley
+E: rwhaley@applieddata.net
+D: Port to ARM PXA27x adsvix SBC
+
 N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board
 
-N: Christian Vejlbo
-E: christian.vejlbo@tellabs.com
-D: FADS860T ethernet support
+N: Ming-Len Wu
+E: minglen_wu@techware.com.tw
+D: Motorola MX1ADS board support
+W: http://www.techware.com.tw/
+
+N: Xianghua Xiao
+E: x.xiao@motorola.com
+D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
 
 N: John Zhan
 E: zhanz@sinovee.com
@@ -290,3 +460,13 @@ N: Alex Zuepke
 E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com
+
+N: James MacAulay
+E: james.macaulay@amirix.com
+D: Suppport for Amirix AP1000
+W: www.amirix.com
+
+N: Timur Tabi
+E: timur@freescale.com
+D: Support for MPC8349E-mITX
+W: www.freescale.com

MAINTAINERS

@@ -3,10 +3,7 @@
 # Regular Maintainers for U-Boot board support:				#
 #									#
 # For any board without permanent maintainer, please contact		#
-#    for PowerPC systems:						#
 #	Wolfgang Denk <wd@denx.de>					#
-#    for ARM systems:							#
-#	Marius Gr<47>ger <mag@sysgo.de>					#
 # and Cc: the <U-Boot-Users@lists.sourceforge.net> mailing lists.	#
 #									#
 # Note: lists sorted by Maintainer Name					#
@@ -28,14 +25,26 @@ Pantelis Antoniou <panto@intracom.gr>
 
 	NETVIA			MPC8xx
 
+Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+	cpci5200		MPC5200
+	pf5200			MPC5200
+
+	CPCI750			PPC750FX/GX
+
+Yuli Barcohen <yuli@arabellasw.com>
+
+	Adder			MPC87x/MPC852T
+	ep8248			MPC8248
+	ISPAN			MPC8260
+	MPC8260ADS		MPC826x/MPC827x/MPC8280
+	Rattler			MPC8248
+	ZPC1900			MPC8265
+
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 
 	sacsng			MPC8260
 
-Rick Bronson <rick@efn.org>
-
-	AT91RM9200DK		at91rm9200
-
 Oliver Brown <obrown@adventnetworks.com>
 
 	gw8260			MPC8260
@@ -48,8 +57,15 @@ K
 
 	FLAGADM			MPC823
 
+Torsten Demke <torsten.demke@fci.com>
+
+	eXalion			MPC824x
+
 Wolfgang Denk <wd@denx.de>
 
+	IceCube_5100		MGT5100
+	IceCube_5200		MPC5200
+
 	AMX860			MPC860
 	ETX094			MPC850
 	FPS850L			MPC850
@@ -64,6 +80,7 @@ Wolfgang Denk <wd@denx.de>
 	IVMS8_256		MPC860
 	LANTEC			MPC850
 	LWMON			MPC823
+	NC650			MPC852
 	R360MPI			MPC823
 	RMU			MPC850
 	RRvision		MPC823
@@ -75,7 +92,6 @@ Wolfgang Denk <wd@denx.de>
 	TQM855L			MPC855
 	TQM860L			MPC860
 	TQM860L_FEC		MPC860
-	TTTech			MPC823
 	c2mon			MPC855
 	hermes			MPC860
 	lwmon			MPC823
@@ -83,6 +99,7 @@ Wolfgang Denk <wd@denx.de>
 
 	CU824			MPC8240
 	Sandpoint8240		MPC8240
+	SL8245			MPC8245
 
 	ATC			MPC8250
 	PM825			MPC8250
@@ -93,9 +110,13 @@ Wolfgang Denk <wd@denx.de>
 	PM826			MPC8260
 	TQM8260			MPC8260
 
+	P3G4			MPC7410
+
 	PCIPPC2			MPC750
 	PCIPPC6			MPC750
 
+	EXBITGEN		PPC405GP
+
 Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260			MPC8260
@@ -108,6 +129,36 @@ Thomas Frieden <ThomasF@hyperion-entertainment.com>
 
 	AmigaOneG3SE		MPC7xx
 
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+	ADCIOP			IOP480 (PPC401)
+	APC405			PPC405GP
+	AR405			PPC405GP
+	ASH405			PPC405EP
+	CANBT			PPC405CR
+	CPCI2DP			PPC405GP
+	CPCI405			PPC405GP
+	CPCI4052		PPC405GP
+	CPCI405AB		PPC405GP
+	CPCI405DT		PPC405GP
+	CPCI440			PPC440GP
+	CPCIISER4		PPC405GP
+	DASA_SIM		IOP480 (PPC401)
+	DP405			PPC405EP
+	DU405			PPC405GP
+	G2000			PPC405EP
+	HH405			PPC405EP
+	HUB405			PPC405EP
+	OCRTC			PPC405GP
+	ORSG			PPC405GP
+	PCI405			PPC405GP
+	PLU405			PPC405EP
+	PMC405			PPC405GP
+	VOH405			PPC405EP
+	VOM405			PPC405EP
+	WUH405			PPC405EP
+	CMS700                  PPC405EP
+
 Frank Gottschling <fgottschling@eltec.de>
 
 	MHPC			MPC8xx
@@ -130,8 +181,9 @@ Howard Gray <mvsensor@matrix-vision.de>
 Klaus Heydeck <heydeck@kieback-peter.de>
 
 	KUP4K			MPC855
+	KUP4X			MPC859
 
-Murray Jensen <Murray.Jensen@cmst.csiro.au>
+Murray Jensen <Murray.Jensen@csiro.au>
 
 	cogent_mpc8xx		MPC8xx
 
@@ -142,11 +194,12 @@ Brad Kemp <Brad.Kemp@seranoa.com>
 
 	ppmc8260		MPC8260
 
-Nye Liu <nyet@zumanetworks.com>
+Sangmoon Kim <dogoil@etinsys.com>
 
-	ZUMA			MPC7xx_74xx
+	debris			MPC8245
+	KVME080			MPC8245
 
-Thomas Lange <thomas@corelatus.com>
+Thomas Lange <thomas@corelatus.se>
 
 	GTH			MPC860
 
@@ -154,17 +207,45 @@ The LEOX team <team@leox.org>
 
 	ELPT860			MPC860T
 
+Nye Liu <nyet@zumanetworks.com>
+
+	ZUMA			MPC7xx_74xx
+
+Jon Loeliger <jdl@freescale.com>
+
+	MPC8540ADS		MPC8540
+	MPC8560ADS		MPC8560
+	MPC8541CDS		MPC8541
+	MPC8555CDS		MPC8555
+
+	MPC8641HPCN		MPC8641D
+
+Dan Malek <dan@embeddededge.com>
+
+	STxGP3			MPC85xx
+	STxXTc			MPC8xx
+
 Eran Man <eran@nbase.co.il>
 
 	EVB64260_750CX		MPC750CX
 
+Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+
+	PPChameleonEVB	PPC405EP
+
 Reinhard Meyer <r.meyer@emk-elektronik.de>
 
-	TOP860			MPC860
+	TOP860			MPC860T
+	TOP5200			MPC5200
 
-Scott McNutt <smcnutt@artesyncp.com>
+Tolunay Orkun <torkun@nextio.com>
 
-	EBONY			PPC440GP
+	csb272			PPC405GP
+	csb472			PPC405GP
+
+John Otken <jotken@softadvances.com>
+
+	luan			PPC440SP
 
 Keith Outwater <Keith_Outwater@mvis.com>
 
@@ -175,28 +256,57 @@ Frank Panno <fpanno@delphintech.com>
 
 	ep8260			MPC8260
 
+Peter Pearse <peter.pearse@arm.com>
+	integratorcp		All current ARM supplied &
+				supported core modules
+				- see http://www.arm.com
+				/products/DevTools
+				/Hardware_Platforms.html
+	versatile		ARM926EJ-S
+	versatile		ARM926EJ-S
+
 Denis Peter <d.peter@mpl.ch>
 
 	MIP405			PPC4xx
 	PIP405			PPC4xx
 
-Stefan Roese <stefan.roese@esd-electronics.com>
+Daniel Poirot <dan.poirot@windriver.com>
 
-	ADCIOP			IOP480 (PPC401)
-	AR405			PPC405GP
-	ASH405			PPC405EP
-	CANBT			PPC405CR
-	CPCI405			PPC405GP
-	CPCI4052		PPC405GP
-	CPCI405AB		PPC405GP
-	CPCI440			PPC440GP
-	CPCIISER4		PPC405GP
-	DASA_SIM		IOP480 (PPC401)
-	DU405			PPC405GP
-	OCRTC			PPC405GP
-	ORSG			PPC405GP
-	PCI405			PPC405GP
-	PMC405			PPC405GP
+	sbc8240			MPC8240
+	sbc405			PPC405GP
+
+Stefan Roese <sr@denx.de>
+
+	P3M7448			MPC7448
+
+	uc100			MPC857
+
+	TQM85xx			MPC8540/8541/8555/8560
+
+	alpr			PPC440GX
+	bamboo			PPC440EP
+	bunbinga		PPC405EP
+	ebony			PPC440GP
+	ocotea			PPC440GX
+	p3p440			PPC440GP
+	pcs440ep		PPC440EP
+	sequoia			PPC440EPx
+	sycamore		PPC405GPr
+	walnut			PPC405GP
+	yellowstone		PPC440GR
+	yosemite		PPC440EP
+
+	P3M750			PPC750FX/GX/GL
+
+Yusdi Santoso <yusdi_santoso@adaptec.com>
+
+	HIDDEN_DRAGON	MPC8241/MPC8245
+
+Travis Sawyer (travis.sawyer@sandburst.com>
+
+	KAREF			PPC440GX
+	METROBOX		PPC440GX
+	XPEDITE1K		PPC440GX
 
 Peter De Schrijver <p2@mind.be>
 
@@ -216,10 +326,36 @@ Rune Torgersen <runet@innovsys.com>
 
 	MPC8266ADS		MPC8266
 
+
+David Updegraff <dave@cray.com>
+
+	CRAYL1			PPC4xx
+
+Josef Wagner <Wagner@Microsys.de>
+
+	CPC45			MPC8245
+	PM520			MPC5200
+
+Stephen Williams <steve@icarus.com>
+
+	JSE			PPC405GPr
+
 John Zhan <zhanz@sinovee.com>
 
 	svm_sc8xx		MPC8xx
 
+Timur Tabi <timur@freescale.com>
+
+	MPC8349E-mITX		MPC8349
+
+Kim Phillips <kim.phillips@freescale.com>
+
+	MPC8349EMDS		MPC8349
+
+Dave Liu <daveliu@freescale.com>
+
+	MPC8360EMDS		MPC8360
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -236,13 +372,10 @@ Unknown / orphaned boards:
 	RPXClassic		MPC8xx
 	RPXlite			MPC8xx
 
-	CRAYL1			PPC4xx
 	ERIC			PPC4xx
-	WALNUT405		PPC4xx
 
 	MOUSSE			MPC824x
 
-	MPC8260ADS		MPC8260
 	RPXsuper		MPC8260
 	rsdproto		MPC8260
 
@@ -256,6 +389,31 @@ Unknown / orphaned boards:
 #	Board			CPU					#
 #########################################################################
 
+Rowel Atienza <rowel@diwalabs.com>
+
+	armadillo		ARM720T
+
+Rishi Bhattacharya <rishi@ti.com>
+
+	omap5912osk		ARM926EJS
+
+Cliff Brake <cliff.brake@gmail.com>
+
+	pxa255_idp		xscale
+
+Rick Bronson <rick@efn.org>
+
+	AT91RM9200DK		at91rm9200
+
+George G. Davis <gdavis@mvista.com>
+
+	assabet			SA1100
+	gcplus			SA1100
+
+Thomas Elste <info@elste.org>
+
+	modnet50		ARM720T (NET+50)
+
 Peter Figuli <peposh@etc.sk>
 
 	wepep250		xscale
@@ -265,16 +423,30 @@ Marius Gr
 	impa7			ARM720T (EP7211)
 	ep7312			ARM720T (EP7312)
 
+Kshitij Gupta <kshitij@ti.com>
+
+	omap1510inn		ARM925T
+	omap1610inn		ARM926EJS
+
 Kyle Harris <kharris@nexus-tech.net>
 
 	lubbock			xscale
 	cradle			xscale
+	ixdp425			xscale
 
 Gary Jennejohn <gj@denx.de>
 
 	smdk2400		ARM920T
 	trab			ARM920T
 
+Nishant Kamat <nskamat@ti.com>
+
+	omap1610h2		ARM926EJS
+
+Prakash Kumar <prakash@embedx.com>
+
+	cerf250			xscale
+
 David M<>ller <d.mueller@elsoft.ch>
 
 	smdk2410		ARM920T
@@ -284,11 +456,34 @@ Rolf Offermanns <rof@sysgo.de>
 
 	shannon			SA1100
 
+Dave Peverley <dpeverley@mpc-data.co.uk>
+
+	omap730p2		ARM926EJS
+
+Stefan Roese <sr@denx.de>
+
+	ixdpg425		xscale
+	pdnb3			xscale
+
 Robert Schwebel <r.schwebel@pengutronix.de>
 
 	csb226			xscale
 	innokom			xscale
 
+Andrea Scian <andrea.scian@dave-tech.it>
+
+	B2			ARM7TDMI (S3C44B0X)
+
+Greg Ungerer <greg.ungerer@opengear.com>
+
+	cm4008			ks8695p
+	cm4116			ks8695p
+	cm4148			ks8695p
+
+Richard Woodruff <r-woodruff2@ti.com>
+
+	omap2420h4		ARM1136EJS
+
 Alex Z<>pke <azu@sysgo.de>
 
 	lart			SA1100
@@ -317,6 +512,78 @@ Wolfgang Denk <wd@denx.de>
 	incaip			MIPS32 4Kc
 	purple			MIPS64 5Kc
 
+Thomas Lange <thomas@corelatus.se>
+	dbau1x00		MIPS32 Au1000
+	gth2			MIPS32 Au1000
+
+#########################################################################
+# Nios-32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Stephan Linz <linz@li-pro.net>
+
+	DK1S10			Nios-32
+	ADNPESC1		Nios-32
+
+Scott McNutt <smcnutt@psyent.com>
+
+	DK1C20			Nios-32
+
+#########################################################################
+# Nios-II Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Scott McNutt <smcnutt@psyent.com>
+
+	PCI5441			Nios-II
+	PK1C20			Nios-II
+	EP1C20			Nios-II
+	EP1S10			Nios-II
+	EP1S40			Nios-II
+
+#########################################################################
+# MicroBlaze Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Yasushi Shoji <yashi@atmark-techno.com>
+
+	SUZAKU			MicroBlaze
+
+#########################################################################
+# Coldfire Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+	TASREG			MCF5249
+
+Zachary P. Landau <zachary.landau@labxtechnologies.com>
+
+	r5200			mcf52x2
+
+#########################################################################
+# AVR32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+	ATSTK1000		AT32AP7000
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################

MAKEALL

@@ -1,12 +1,24 @@
 #!/bin/sh
 
+: ${JOBS:=}
+
 if [ "${CROSS_COMPILE}" ] ; then
 	MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
 else
 	MAKE=make
 fi
 
-[ -d LOG ] || mkdir LOG || exit 1
+if [ "${MAKEALL_LOGDIR}" ] ; then
+	LOG_DIR=${MAKEALL_LOGDIR}
+else
+	LOG_DIR="LOG"
+fi
+
+if [ ! "${BUILD_DIR}" ] ; then
+	BUILD_DIR="."
+fi
+
+[ -d ${LOG_DIR} ] || mkdir ${LOG_DIR} || exit 1
 
 LIST=""
 
@@ -19,24 +31,42 @@ LIST_5xx="	\
 "
 
 #########################################################################
-## MPC8xx Systems
+## MPC5xxx Systems
 #########################################################################
 
+LIST_5xxx="	\
+	BC3450		cpci5200	EVAL5200	fo300		\
+	icecube_5100	icecube_5200	lite5200b	mcc200		\
+	o2dnt		pf5200		PM520		TB5200		\
+	Total5100	Total5200	Total5200_Rev2	TQM5200		\
+	TQM5200_B	TQM5200S	v38b				\
+"
+
+#########################################################################
+## MPC8xx Systems
+#########################################################################
 LIST_8xx="	\
-	ADS860		AMX860		c2mon		CCM		\
-	cogent_mpc8xx	ESTEEM192E	ETX094		ELPT860		\
-	FADS823		FADS850SAR	FADS860T	FLAGADM		\
-	FPS850L		GEN860T		GEN860T_SC	GENIETV		\
-	GTH		hermes		IAD210		ICU862_100MHz	\
-	IP860		IVML24		IVML24_128	IVML24_256	\
-	IVMS8		IVMS8_128	IVMS8_256	KUP4K           \
-	LANTEC	        lwmon   	MBX		MBX860T		\
-	MHPC		MVS1		NETVIA		NX823		\
-	pcu_e		R360MPI		RBC823		rmu		\
-	RPXClassic	RPXlite		RRvision	SM850		\
-	SPD823TS	svm_sc8xx	SXNI855T	TOP860		\
-	TQM823L		TQM823L_LCD	TQM850L		TQM855L		\
-	TQM860L		TTTech		v37				\
+	Adder87x	GENIETV		MBX860T		R360MPI		\
+	AdderII		GTH		MHPC		RBC823		\
+	ADS860		hermes		MPC86xADS	rmu		\
+	AMX860		IAD210		MPC885ADS	RPXClassic	\
+	c2mon		ICU862_100MHz	MVS1		RPXlite		\
+	CCM		IP860		NETPHONE	RPXlite_DW	\
+	cogent_mpc8xx	IVML24		NETTA		RRvision	\
+	ELPT860		IVML24_128	NETTA2		SM850		\
+	EP88x		IVML24_256	NETTA_ISDN	spc1920		\
+	ESTEEM192E	IVMS8		NETVIA		SPD823TS	\
+	ETX094		IVMS8_128	NETVIA_V2	svm_sc8xx	\
+	FADS823		IVMS8_256	NX823		SXNI855T	\
+	FADS850SAR	KUP4K		pcu_e		TOP860		\
+	FADS860T	KUP4X		QS823		TQM823L		\
+	FLAGADM		LANTEC		QS850		TQM823L_LCD	\
+	FPS850L		lwmon		QS860T		TQM850L		\
+	GEN860T		MBX		quantum		TQM855L		\
+	GEN860T_SC					TQM860L		\
+							TQM885D		\
+							uc100		\
+							v37		\
 "
 
 #########################################################################
@@ -44,13 +74,29 @@ LIST_8xx="	\
 #########################################################################
 
 LIST_4xx="	\
-	ADCIOP		AR405		ASH405          BUBINGA405EP    \
-        CANBT		CPCI405		CPCI4052 	CPCI405AB       \
-        CPCI440         CPCIISER4	CRAYL1  	DASA_SIM	\
-        DU405    	EBONY           ERIC  		MIP405  	\
-        MIP405T		ML2		OCRTC		ORSG		\
-	PCI405		PIP405		PMC405          W7OLMC		\
-	W7OLMG          WALNUT405	\
+	ADCIOP		alpr		AP1000		AR405		\
+	ASH405		bamboo		bubinga		CANBT		\
+	CMS700		CPCI2DP		CPCI405		CPCI4052	\
+	CPCI405AB	CPCI405DT	CPCI440		CPCIISER4	\
+	CRAYL1		csb272		csb472		DASA_SIM	\
+	DP405		DU405		ebony		ERIC		\
+	EXBITGEN	G2000		HH405		HUB405		\
+	JSE		KAREF		luan		METROBOX	\
+	MIP405		MIP405T		ML2		ml300		\
+	ocotea		OCRTC		ORSG		p3p440		\
+	PCI405		pcs440ep	PIP405		PLU405		\
+	PMC405		PPChameleonEVB	sbc405		sequoia		\
+	sequoia_nand	VOH405		VOM405		W7OLMC		\
+	W7OLMG		walnut		WUH405		XPEDITE1K	\
+	yellowstone	yosemite	yucca				\
+"
+
+#########################################################################
+## MPC8220 Systems
+#########################################################################
+
+LIST_8220="	\
+	Alaska8220	Yukon8220					\
 "
 
 #########################################################################
@@ -58,9 +104,11 @@ LIST_4xx="	\
 #########################################################################
 
 LIST_824x="	\
-	BMW		CPC45		CU824		MOUSSE		\
-	MUSENKI		OXC		PN62		Sandpoint8240	\
-	Sandpoint8245	utx8245						\
+	A3000		barco		BMW		CPC45		\
+	CU824		debris		eXalion		HIDDEN_DRAGON	\
+			MOUSSE		MUSENKI		MVBLUE		\
+	OXC		PN62		Sandpoint8240	Sandpoint8245	\
+	sbc8240		SL8245		utx8245				\
 "
 
 #########################################################################
@@ -68,11 +116,33 @@ LIST_824x="	\
 #########################################################################
 
 LIST_8260="	\
-	atc		cogent_mpc8260	CPU86		ep8260		\
-	gw8260		hymod		IPHASE4539	MPC8260ADS	\
-	MPC8266ADS	PM826		ppmc8260	RPXsuper	\
-	rsdproto	sacsng		sbc8260		SCM		\
-	TQM8260								\
+	atc		cogent_mpc8260	CPU86		CPU87		\
+	ep8248		ep8260		ep82xxm		gw8260		\
+	hymod		IPHASE4539	ISPAN		MPC8260ADS	\
+	MPC8266ADS	MPC8272ADS	PM826		PM828		\
+	ppmc8260	Rattler8248	RPXsuper	rsdproto	\
+	sacsng		sbc8260		SCM		TQM8260_AC	\
+	TQM8260_AD	TQM8260_AE	ZPC1900				\
+"
+
+#########################################################################
+## MPC83xx Systems (includes 8349, etc.)
+#########################################################################
+
+LIST_83xx="	\
+	TQM834x		MPC8349EMDS	MPC8349ITX	MPC8360EMDS	\
+"
+
+
+#########################################################################
+## MPC85xx Systems (includes 8540, 8560 etc.)
+#########################################################################
+
+LIST_85xx="	\
+	MPC8540ADS	MPC8540EVAL	MPC8541CDS	MPC8548CDS	\
+	MPC8555CDS	MPC8560ADS	PM854		PM856		\
+	sbc8540		sbc8560		stxgp3		TQM8540		\
+	TQM8541		TQM8555		TQM8560				\
 "
 
 #########################################################################
@@ -80,54 +150,112 @@ LIST_8260="	\
 #########################################################################
 
 LIST_74xx="	\
-	EVB64260	PCIPPC2		PCIPPC6		ZUMA		\
+	DB64360		DB64460		EVB64260	P3G4		\
+	p3m7448		PCIPPC2		PCIPPC6		ZUMA		\
 "
 
 LIST_7xx="	\
-	BAB7xx		ELPPC						\
+	BAB7xx		CPCI750		ELPPC		p3m750		\
+	ppmc7xx								\
 "
 
-LIST_ppc="${LIST_5xx}  ${LIST_8xx}  \
-	  ${LIST_824x} ${LIST_8260} \
-	  ${LIST_4xx}		    \
+LIST_ppc="${LIST_5xx}  ${LIST_5xxx}		\
+	  ${LIST_8xx}				\
+	  ${LIST_8220} ${LIST_824x} ${LIST_8260} \
+	  ${LIST_83xx}				\
+	  ${LIST_85xx}				\
+	  ${LIST_4xx}				\
 	  ${LIST_74xx} ${LIST_7xx}"
 
 #########################################################################
 ## StrongARM Systems
 #########################################################################
 
-LIST_SA="dnp1110 lart shannon"
+LIST_SA="assabet dnp1110 gcplus lart shannon"
 
 #########################################################################
 ## ARM7 Systems
 #########################################################################
 
-LIST_ARM7="ep7312 impa7"
+LIST_ARM7="	\
+	armadillo	B2		ep7312		evb4510		\
+	impa7		integratorap	ap7		ap720t		\
+	modnet50							\
+"
 
 #########################################################################
 ## ARM9 Systems
 #########################################################################
 
-LIST_ARM9="at91rm9200dk smdk2400 smdk2410 trab VCMA9"
+LIST_ARM9="	\
+	at91rm9200dk	cmc_pu2						\
+	ap920t		ap922_XA10	ap926ejs	ap946es		\
+	ap966		cp920t		cp922_XA10	cp926ejs	\
+	cp946es		cp966		lpd7a400	mp2usb		\
+	mx1ads		mx1fs2		netstar		omap1510inn	\
+	omap1610h2	omap1610inn	omap730p2	sbc2410x	\
+	scb9328		smdk2400	smdk2410	trab		\
+	VCMA9		versatile	versatileab	versatilepb	\
+	voiceblue							\
+"
+
+#########################################################################
+## ARM10 Systems
+#########################################################################
+LIST_ARM10="	\
+	integratorcp	cp1026						\
+"
+
+#########################################################################
+## ARM11 Systems
+#########################################################################
+LIST_ARM11="	\
+	cp1136		omap2420h4					\
+"
 
 #########################################################################
 ## Xscale Systems
 #########################################################################
 
-LIST_pxa="cradle csb226 innokom lubbock wepep250"
+LIST_pxa="	\
+	adsvix		cerf250		cradle		csb226		\
+	delta		innokom		lubbock		pleb2		\
+	pxa255_idp	wepep250	xaeniax		xm250		\
+	xsengine	zylonite					\
+"
+
+LIST_ixp="ixdp425	ixdpg425	pdnb3"
 
 
-LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa}"
+LIST_arm="	\
+	${LIST_SA}							\
+	${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11}		\
+	${LIST_pxa} ${LIST_ixp}						\
+"
 
 #########################################################################
-## MIPS 4Kc Systems
+## MIPS Systems		(default = big endian)
 #########################################################################
 
 LIST_mips4kc="incaip"
 
 LIST_mips5kc="purple"
 
-LIST_mips="${LIST_mips4kc} ${LIST_mips5kc}"
+LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el gth2"
+
+LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
+
+#########################################################################
+## MIPS Systems		(little endian)
+#########################################################################
+
+LIST_mips4kc_el=""
+
+LIST_mips5kc_el=""
+
+LIST_au1xx0_el="dbau1550_el"
+
+LIST_mips_el="${LIST_mips4kc_el} ${LIST_mips5kc_el} ${LIST_au1xx0_el}"
 
 #########################################################################
 ## i386 Systems
@@ -137,6 +265,50 @@ LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel"
 
 LIST_x86="${LIST_I486}"
 
+#########################################################################
+## NIOS Systems
+#########################################################################
+
+LIST_nios="	\
+	ADNPESC1		ADNPESC1_base_32			\
+	ADNPESC1_DNPEVA2_base_32					\
+	DK1C20			DK1C20_standard_32			\
+	DK1S10			DK1S10_standard_32 DK1S10_mtx_ldk_20	\
+"
+
+#########################################################################
+## Nios-II Systems
+#########################################################################
+
+LIST_nios2="	\
+	EP1C20		EP1S10		EP1S40				\
+	PCI5441		PK1C20						\
+"
+
+#########################################################################
+## MicroBlaze Systems
+#########################################################################
+
+LIST_microblaze="	\
+	suzaku
+"
+
+#########################################################################
+## ColdFire Systems
+#########################################################################
+
+LIST_coldfire="	\
+	cobra5272	EB+MCF-EV123	EB+MCF-EV123_internal		\
+	idmr		M5271EVB	M5272C3		M5282EVB	\
+	TASREG		r5200		M5271EVB			\
+"
+
+#########################################################################
+## AVR32 Systems
+#########################################################################
+
+LIST_avr32="atstk1002"
+
 #-----------------------------------------------------------------------
 
 #----- for now, just run PPC by default -----
@@ -149,8 +321,12 @@ build_target() {
 
 	${MAKE} distclean >/dev/null
 	${MAKE} ${target}_config
-	${MAKE} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
-	${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
+
+	${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
+				| tee ${LOG_DIR}/$target.ERR
+
+	${CROSS_COMPILE:-ppc_8xx-}size ${BUILD_DIR}/u-boot \
+				| tee -a ${LOG_DIR}/$target.MAKELOG
 }
 
 #-----------------------------------------------------------------------
@@ -159,7 +335,14 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	5xx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips|I486|x86)
+	ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
+	arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp| \
+	microblaze| \
+	mips|mips_el| \
+	nios|nios2| \
+	x86|I486| \
+	coldfire| \
+	avr32)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}

avr32_config.mk

@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS	+= -ffixed-r5 -mno-pic -mrelax
+PLATFORM_LDFLAGS	+= --relax

blackfin_config.mk

@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__

board/AtmarkTechno/suzaku/Makefile

@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/AtmarkTechno/suzaku/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2004 Atmark Techno, Inc.
+#
+# Yasushi SHOJI <yashi@atmark-techno.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x80F00000
+
+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
+PLATFORM_CPPFLAGS += -mno-xl-soft-div
+PLATFORM_CPPFLAGS += -mxl-barrel-shift

board/AtmarkTechno/suzaku/flash.c

@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+unsigned long flash_init(void)
+{
+	return 0;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	return 0;
+}
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	return 0;
+}

board/AtmarkTechno/suzaku/suzaku.c

@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This is a board specific file.  It's OK to include board specific
+ * header files */
+#include <asm/suzaku.h>
+
+void do_reset(void)
+{
+	*((unsigned long *)(MICROBLAZE_SYSREG_BASE_ADDR)) = MICROBLAZE_SYSREG_RECONFIGURE;
+}

board/AtmarkTechno/suzaku/u-boot.lds

@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(microblaze)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text ALIGN(0x4):
+	{
+		__text_start = .;
+		cpu/microblaze/start.o (.text)
+		*(.text)
+		__text_end = .;
+	}
+
+	.rodata ALIGN(0x4):
+	{
+		__rodata_start = .;
+		*(.rodata)
+		__rodata_end = .;
+	}
+
+	.data ALIGN(0x4):
+	{
+		__data_start = .;
+		*(.data)
+		__data_end = .;
+	}
+
+	.u_boot_cmd ALIGN(0x4):
+	{
+		. = .;
+		__u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		__u_boot_cmd_end = .;
+	}
+
+	.bss ALIGN(0x4):
+	{
+		__bss_start = .;
+		*(.bss)
+		__bss_start = .;
+	}
+}

board/BuS/EB+MCF-EV123/EB+MCF-EV123.c

@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include "asm/m5282.h"
+#include "VCxK.h"
+
+int checkboard (void)
+{
+	puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
+#if (TEXT_BASE ==  CFG_INT_FLASH_BASE)
+	puts ("       Boot from Internal FLASH\n");
+#endif
+
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	int size,i;
+
+	size = 0;
+	MCFSDRAMC_DCR =	MCFSDRAMC_DCR_RTIM_6
+			| MCFSDRAMC_DCR_RC((15 * CFG_CLK)>>4);
+	#ifdef CFG_SDRAM_BASE0
+
+		MCFSDRAMC_DACR0 =	MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0)
+					| MCFSDRAMC_DACR_CASL(1)
+					| MCFSDRAMC_DACR_CBM(3)
+					| MCFSDRAMC_DACR_PS_16);
+
+		MCFSDRAMC_DMR0 =	MCFSDRAMC_DMR_BAM_16M
+					| MCFSDRAMC_DMR_V;
+
+		MCFSDRAMC_DACR0 |=	MCFSDRAMC_DACR_IP;
+
+		*(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5;
+		MCFSDRAMC_DACR0 |=	MCFSDRAMC_DACR_RE;
+		for (i=0; i < 2000; i++)
+			asm(" nop");
+		mbar_writeLong(MCFSDRAMC_DACR0, mbar_readLong(MCFSDRAMC_DACR0)
+								    | MCFSDRAMC_DACR_IMRS);
+		*(unsigned int *)(CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
+		size += CFG_SDRAM_SIZE * 1024 * 1024;
+	#endif
+	#ifdef CFG_SDRAM_BASE1
+		MCFSDRAMC_DACR1 =	MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1)
+					| MCFSDRAMC_DACR_CASL(1)
+					| MCFSDRAMC_DACR_CBM(3)
+					| MCFSDRAMC_DACR_PS_16;
+
+		MCFSDRAMC_DMR1 =	MCFSDRAMC_DMR_BAM_16M
+					| MCFSDRAMC_DMR_V;
+
+		MCFSDRAMC_DACR1 |=	MCFSDRAMC_DACR_IP;
+
+		*(unsigned short *)(CFG_SDRAM_BASE1) = 0xA5A5;
+		MCFSDRAMC_DACR1 |=	MCFSDRAMC_DACR_RE;
+		for (i=0; i < 2000; i++)
+			asm(" nop");
+		MCFSDRAMC_DACR1 |=	MCFSDRAMC_DACR_IMRS;
+		*(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
+		size += CFG_SDRAM_SIZE1 * 1024 * 1024;
+	#endif
+	return size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+	init_vcxk();
+	return 1;
+}
+
+/*---------------------------------------------------------------------------*/
+
+int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int rcode = 0;
+	ulong source;
+
+	switch (argc) {
+	case 2:
+		source = simple_strtoul(argv[1],NULL,16);
+		vcxk_loadimage(source);
+		rcode = 0;
+		break;
+	default:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		rcode = 1;
+		break;
+	}
+	return rcode;
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+	vcimage,	2,	0,	do_vcimage,
+	"vcimage - loads an image to Display\n",
+	"vcimage addr\n"
+);
+
+/* EOF EB+MCF-EV123c */

board/BuS/EB+MCF-EV123/Makefile

@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o cfm_flash.o flash.o VCxK.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/BuS/EB+MCF-EV123/VCxK.c

@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5282.h>
+#include "VCxK.h"
+
+vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
+#define VCXK_BWS vcxk_bws
+
+static ulong vcxk_driver;
+
+
+ulong search_vcxk_driver(void);
+void vcxk_cls(void);
+void vcxk_setbrightness(short brightness);
+int vcxk_request(void);
+int vcxk_acknowledge_wait(void);
+void vcxk_clear(void);
+
+int init_vcxk(void)
+{
+	VIDEO_Invert_CFG &= ~VIDEO_Invert_IO;
+	VIDEO_INVERT_PORT |= VIDEO_INVERT_PIN;
+	VIDEO_INVERT_DDR  |= VIDEO_INVERT_PIN;
+
+	VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
+	VIDEO_REQUEST_DDR |= VIDEO_REQUEST_PIN;
+
+	VIDEO_ACKNOWLEDGE_DDR &= ~VIDEO_ACKNOWLEDGE_PIN;
+
+	vcxk_driver = search_vcxk_driver();
+	if (vcxk_driver)
+	{
+		/* use flash resist driver */
+	}
+	else
+	{
+		vcxk_cls();
+		vcxk_cls();
+		vcxk_setbrightness(1000);
+	}
+	VIDEO_ENABLE_DDR |= VIDEO_ENABLE_PIN;
+	VIDEO_ENABLE_PORT |= VIDEO_ENABLE_PIN;
+	VIDEO_ENABLE_PORT &= ~VIDEO_ENABLE_PIN;
+	return 1;
+}
+
+void	vcxk_loadimage(ulong source)
+{
+	int cnt;
+	vcxk_acknowledge_wait();
+	for (cnt=0; cnt<16384; cnt++)
+	{
+		VCXK_BWS[cnt*2] = (*(vu_char*) source);
+		source++;
+	}
+	vcxk_request();
+}
+
+void vcxk_cls(void)
+{
+	vcxk_acknowledge_wait();
+	vcxk_clear();
+	vcxk_request();
+}
+
+void vcxk_clear(void)
+{
+	int cnt;
+	for (cnt=0; cnt<16384; cnt++)
+	{
+		VCXK_BWS[cnt*2] = 0x00;
+	}
+}
+
+void vcxk_setbrightness(short brightness)
+{
+	VCXK_BWS[0x8000]=(brightness >> 4) +2;
+	VCXK_BWS[0xC000]= (brightness + 23) >> 8;
+	VCXK_BWS[0xC001]= (brightness + 23) & 0xFF;
+}
+
+int vcxk_request(void)
+{
+	if (vcxk_driver)
+	{
+		/* use flash resist driver */
+	}
+	else
+	{
+		VIDEO_REQUEST_PORT &= ~VIDEO_REQUEST_PIN;
+		VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
+	}
+	return 1;
+}
+
+int vcxk_acknowledge_wait(void)
+{
+	if (vcxk_driver)
+	{
+		/* use flash resist driver */
+	}
+	else
+	{
+		while (!(VIDEO_ACKNOWLEDGE_PORT & VIDEO_ACKNOWLEDGE_PIN));
+	}
+	return 1;
+}
+
+ulong search_vcxk_driver(void)
+{
+	return 0;
+}
+
+/* eof */

board/BuS/EB+MCF-EV123/VCxK.h

@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __VCXK_H_
+#define __VCXK_H_
+
+extern int init_vcxk(void);
+void	vcxk_loadimage(ulong source);
+
+#define VIDEO_ACKNOWLEDGE_PORT	MCFGPTB_GPTPORT
+#define VIDEO_ACKNOWLEDGE_DDR	MCFGPTB_GPTDDR
+#define VIDEO_ACKNOWLEDGE_PIN	0x0001
+
+#define VIDEO_ENABLE_PORT	MCFGPTB_GPTPORT
+#define VIDEO_ENABLE_DDR	MCFGPTB_GPTDDR
+#define VIDEO_ENABLE_PIN	0x0002
+
+#define VIDEO_REQUEST_PORT	MCFGPTB_GPTPORT
+#define VIDEO_REQUEST_DDR	MCFGPTB_GPTDDR
+#define VIDEO_REQUEST_PIN	0x0004
+
+#define VIDEO_Invert_CFG	MCFGPIO_PEPAR
+#define VIDEO_Invert_IO		MCFGPIO_PEPAR_PEPA2
+#define VIDEO_INVERT_PORT	MCFGPIO_PORTE
+#define VIDEO_INVERT_DDR	MCFGPIO_DDRE
+#define VIDEO_INVERT_PIN	MCFGPIO_PORT2
+
+#endif

board/BuS/EB+MCF-EV123/cfm_flash.c

@@ -0,0 +1,212 @@
+/*
+ * Basic Flash Driver for Freescale MCF 5281/5282 internal FLASH
+ *
+ * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5282.h>
+#include  "cfm_flash.h"
+
+#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
+
+#if (CFG_CLK>20000000)
+	#define CFM_CLK  (((long) CFG_CLK / (400000 * 8) + 1) | 0x40)
+#else
+	#define CFM_CLK  ((long) CFG_CLK / 400000 + 1)
+#endif
+
+#define cmf_backdoor_address(addr)	(((addr) & 0x0007FFFF) | 0x04000000 | \
+					 (CFG_MBAR & 0xC0000000))
+
+void cfm_flash_print_info (flash_info_t * info)
+{
+	printf ("Freescale: ");
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FREESCALE_ID_MCF5281 & FLASH_TYPEMASK:
+		printf ("MCF5281 internal FLASH\n");
+		break;
+	case FREESCALE_ID_MCF5282 & FLASH_TYPEMASK:
+		printf ("MCF5282 internal FLASH\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+}
+
+void cfm_flash_init (flash_info_t * info)
+{
+	int sector;
+	ulong protection;
+	MCFCFM_MCR = 0;
+	MCFCFM_CLKD = CFM_CLK;
+	debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
+		CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
+		CFG_CLK);
+	MCFCFM_SACC = 0;
+	MCFCFM_DACC = 0;
+
+	if (MCFCFM_SEC & MCFCFM_SEC_KEYEN)
+		puts("CFM backdoor access is enabled\n");
+	if (MCFCFM_SEC & MCFCFM_SEC_SECSTAT)
+		puts("CFM securety is enabled\n");
+
+	#ifdef CONFIG_M5281
+		info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
+				 (FREESCALE_ID_MCF5281 & FLASH_TYPEMASK);
+		info->size = 256*1024;
+		info->sector_count = 16;
+	#else
+		info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
+				 (FREESCALE_ID_MCF5282 & FLASH_TYPEMASK);
+		info->size = 512*1024;
+		info->sector_count = 32;
+	#endif
+	protection = MCFCFM_PROT;
+	for (sector = 0; sector < info->sector_count; sector++)
+	{
+		if (sector == 0)
+		{
+			info->start[sector] = CFG_INT_FLASH_BASE;
+		}
+		else
+		{
+			info->start[sector] = info->start[sector-1] + 0x04000;
+		}
+		info->protect[sector] = protection & 1;
+		protection >>= 1;
+	}
+}
+
+int cfm_flash_readycheck(int checkblank)
+{
+	int	rc;
+	unsigned char state;
+
+	rc	= ERR_OK;
+	while (!(MCFCFM_USTAT & MCFCFM_USTAT_CCIF));
+	state = MCFCFM_USTAT;
+	if (state & MCFCFM_USTAT_ACCERR)
+	{
+		debug ("%s(): CFM access error",__FUNCTION__);
+		rc = ERR_PROG_ERROR;
+	}
+	if (state & MCFCFM_USTAT_PVIOL)
+	{
+		debug ("%s(): CFM protection violation",__FUNCTION__);
+		rc = ERR_PROTECTED;
+	}
+	if (checkblank)
+	{
+		if (!(state & MCFCFM_USTAT_BLANK))
+		{
+			debug ("%s(): CFM erras error",__FUNCTION__);
+			rc = ERR_NOT_ERASED;
+		}
+	}
+	MCFCFM_USTAT = state & 0x34; /* reset state */
+	return rc;
+}
+
+/* Erase 16KiB = 8 2KiB pages */
+
+int cfm_flash_erase_sector (flash_info_t * info, int sector)
+{
+	ulong address;
+	int page;
+	int rc;
+	rc= ERR_OK;
+	address = cmf_backdoor_address(info->start[sector]);
+	for (page=0; (page<8) && (rc==ERR_OK); page++)
+	{
+		*(volatile __u32*) address = 0;
+		MCFCFM_CMD = MCFCFM_CMD_PGERS;
+		MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
+		rc = cfm_flash_readycheck(0);
+		if (rc==ERR_OK)
+		{
+			*(volatile __u32*) address = 0;
+			MCFCFM_CMD = MCFCFM_CMD_PGERSVER;
+			MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
+			rc = cfm_flash_readycheck(1);
+		}
+		address += 0x800;
+	}
+	return rc;
+}
+
+int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+	ulong dest, data;
+
+	rc = ERR_OK;
+	if (addr & 3)
+	{
+		debug ("Byte and Word alignment not supported\n");
+		rc = ERR_ALIGN;
+	}
+	if (cnt & 3)
+	{
+		debug ("Byte and Word transfer not supported\n");
+		rc = ERR_ALIGN;
+	}
+	dest = cmf_backdoor_address(addr);
+	while ((cnt>=4) && (rc == ERR_OK))
+	{
+		data =*((volatile u32 *) src);
+		*(volatile u32*) dest = data;
+		MCFCFM_CMD = MCFCFM_CMD_PGM;
+		MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
+		rc = cfm_flash_readycheck(0);
+		if (*(volatile u32*) addr != data) rc = ERR_PROG_ERROR;
+		src +=4;
+		dest +=4;
+		addr +=4;
+		cnt -=4;
+	}
+	return rc;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+
+int cfm_flash_protect(flash_info_t * info,long sector,int prot)
+{
+	int rc;
+
+	rc= ERR_OK;
+	if (prot)
+	{
+		MCFCFM_PROT |= (1<<sector);
+		info->protect[sector]=1;
+	}
+	else
+	{
+		MCFCFM_PROT &= ~(1<<sector);
+		info->protect[sector]=0;
+	}
+	return rc;
+}
+
+#endif
+
+#endif

board/BuS/EB+MCF-EV123/cfm_flash.h

@@ -1,7 +1,7 @@
 /*
- * (C) Copyright 2001
- * Thomas Frieden, Hyperion Entertainment
- * ThomasF@hyperion-entertainment.com
+ * Basic Flash Driver for Freescale MCF 5282 internal FLASH
+ *
+ * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -21,22 +21,20 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-#ifndef _CMD_BOOTA_H
-#define _CMD_BOOTA_H
 
-#include <common.h>
-#include <command.h>
+#ifndef __CFM_FLASH_H_
+#define __CFM_FLASH_H_
 
-#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
-#define CMD_TBL_BOOTA     MK_CMD_TBL_ENTRY(                      \
-        "boota", 5,   3,      1,      do_boota,                   \
-        "boota   - boot an Amiga kernel\n",                     \
-        "address disk"                                        \
-),
+#define	FREESCALE_MANUFACT 0xFACFFACF
+#define	FREESCALE_ID_MCF5281 0x5281
+#define	FREESCALE_ID_MCF5282 0x5282
 
-int do_boota (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] );
-#else
-#define CMD_TBL_BOOTA
+extern void cfm_flash_print_info (flash_info_t * info);
+extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
+extern void cfm_flash_init (flash_info_t * info);
+extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+#ifdef CFG_FLASH_PROTECTION
+extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
 #endif
 
-#endif /* _CMD_BOOTA_H */
+#endif

board/BuS/EB+MCF-EV123/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/textbase.mk
+ifndef TEXT_BASE
+TEXT_BASE = 0xFE000000
+endif

board/BuS/EB+MCF-EV123/flash.c

@@ -0,0 +1,413 @@
+/*
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * Based On
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include  "cfm_flash.h"
+
+#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (AMD_ID_LV160B & FLASH_TYPEMASK):
+			printf ("AM29LV160B (16Bit)\n");
+			break;
+		default:
+			printf ("Unknown Chip Type\n");
+			break;
+		}
+		break;
+	case FREESCALE_MANUFACT & FLASH_VENDMASK:
+		cfm_flash_print_info (info);
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	puts ("  Size: ");
+	if ((info->size >> 20) > 0)
+	{
+		printf ("%ld MiB",info->size >> 20);
+	}
+	else
+	{
+		printf ("%ld KiB",info->size >> 10);
+	}
+	printf (" in %d Sectors\n", info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 4) == 0) {
+			printf ("\n    ");
+		}
+		printf ("%02d: %08lX%s  ", i,info->start[i],
+			info->protect[i] ? " P" : "  ");
+	}
+	printf ("\n\n");
+}
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		switch (i)
+		{
+		case 1:
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV160B & FLASH_TYPEMASK);
+			flash_info[i].size = FLASH_BANK_SIZE;
+			flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+			flashbase = PHYS_FLASH_1;
+			for (j = 0; j < flash_info[i].sector_count; j++) {
+				if (j == 0) {
+					/* 1st is 16 KiB */
+					flash_info[i].start[j] = flashbase;
+				}
+				if ((j >= 1) && (j <= 2)) {
+				/* 2nd and 3rd are 8 KiB */
+					flash_info[i].start[j] =
+						flashbase + 0x4000 + 0x2000 * (j - 1);
+				}
+				if (j == 3) {
+					/* 4th is 32 KiB */
+					flash_info[i].start[j] = flashbase + 0x8000;
+				}
+				if ((j >= 4) && (j <= 34)) {
+					/* rest is 256 KiB */
+					flash_info[i].start[j] =
+						flashbase + 0x10000 + 0x10000 * (j - 4);
+				}
+			}
+			break;
+		case 0:
+			cfm_flash_init (&flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+		}
+
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + 0xffff, &flash_info[0]);
+
+	return size;
+}
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(info->start[0] + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(info->start[0] + (0x000002AA<<1)))
+
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define ERR_READY -1
+
+int amd_flash_erase_sector(flash_info_t * info, int sector)
+{
+	int state;
+	ulong result;
+
+	volatile u16 *addr =
+				(volatile u16 *) (info->start[sector]);
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	*addr = CMD_ERASE_CONFIRM;
+
+	/* wait until flash is ready */
+	state = 0;
+	set_timer (0);
+
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+			state = ERR_TIMOUT;
+		}
+
+		if (!state && (result & 0xFFFF) & BIT_ERASE_DONE)
+			state = ERR_READY;
+	}
+	while (!state);
+	if (state == ERR_READY)
+		state = ERR_OK;
+
+	MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+	return state;
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int iflag, cflag;
+	int sector;
+	int rc;
+
+	rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+	{
+		rc = ERR_UNKNOWN_FLASH_TYPE;
+	} /* (info->flash_id == FLASH_UNKNOWN) */
+
+	if ((s_first < 0) || (s_first > s_last) || s_last >= info->sector_count)
+	{
+		rc = ERR_INVAL;
+	}
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	for (sector = s_first; (sector <= s_last) && (rc == ERR_OK); sector++) {
+
+		if (info->protect[sector])
+		{
+			putc('P'); /*  protected sector will not erase */
+		}
+		else
+		{
+			/* erase on unprotected sector */
+			puts("E\b");
+			switch (info->flash_id & FLASH_VENDMASK)
+			{
+			case (AMD_MANUFACT & FLASH_VENDMASK):
+				rc = amd_flash_erase_sector(info,sector);
+				break;
+			case (FREESCALE_MANUFACT & FLASH_VENDMASK):
+				rc = cfm_flash_erase_sector(info,sector);
+				break;
+			default:
+				return ERR_UNKNOWN_FLASH_VENDOR;
+			}
+			putc('.');
+		}
+	}
+	if (rc!=ERR_OK)
+	{
+		printf ("\n   ");
+		flash_perror (rc);
+	}
+	else
+	{
+		printf (" done\n");
+	}
+
+	udelay (10000);	/* allow flash to settle - wait 10 ms */
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
+{
+	volatile u16 *addr;
+	ulong result;
+	int cflag, iflag;
+	int state;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	addr = (volatile u16 *) dest;
+
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	state = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+				state = ERR_TIMOUT;
+		}
+		if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
+			state = ERR_READY;
+
+	} while (!state);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (state == ERR_READY)
+		state = ERR_OK;
+	if ((*addr != data) && (state != ERR_TIMOUT))
+		state = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return state;
+}
+
+int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+	ulong dest;
+	u16 data;
+
+	rc = ERR_OK;
+	if (addr & 1)
+	{
+		debug ("Byte alignment not supported\n");
+		rc = ERR_ALIGN;
+	}
+	if (cnt & 1)
+	{
+		debug ("Byte transfer not supported\n");
+		rc = ERR_ALIGN;
+	}
+
+	dest = addr;
+	while ((cnt>=2) && (rc == ERR_OK))
+	{
+		data =*((volatile u16 *) src);
+		rc=amd_write_word (info,dest,data);
+		src +=2;
+		dest +=2;
+		cnt -=2;
+	}
+	return rc;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case (AMD_MANUFACT & FLASH_VENDMASK):
+			rc = amd_flash_write_buff(info,src,addr,cnt);
+			break;
+		case (FREESCALE_MANUFACT & FLASH_VENDMASK):
+			rc = cfm_flash_write_buff(info,src,addr,cnt);
+			break;
+		default:
+			rc = ERR_UNKNOWN_FLASH_VENDOR;
+	}
+	return rc;
+
+}
+int amd_flash_protect(flash_info_t * info,long sector,int prot)
+{
+	int rc;
+	rc= ERR_OK;
+	if (prot)
+	{
+		info->protect[sector]=1;
+	}
+	else
+	{
+		info->protect[sector]=0;
+	}
+	return rc;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+
+int flash_real_protect(flash_info_t * info,long sector,int prot)
+{
+	int rc;
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case (AMD_MANUFACT & FLASH_VENDMASK):
+			rc = amd_flash_protect(info,sector,prot);
+			break;
+		case (FREESCALE_MANUFACT & FLASH_VENDMASK):
+			rc = cfm_flash_protect(info,sector,prot);
+			break;
+		default:
+			rc = ERR_UNKNOWN_FLASH_VENDOR;
+	}
+	return rc;
+}
+
+#endif

board/BuS/EB+MCF-EV123/textbase.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0xFFE00000

board/BuS/EB+MCF-EV123/u-boot.lds

@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/string.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o	(.text)
+    lib_generic/zlib.o	(.text)
+
+/*    . = env_offset; */
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+    .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/LEOX/elpt860/Makefile

@@ -1,8 +1,12 @@
+
 #######################################################################
 #
 # Copyright (C) 2000, 2001, 2002, 2003
 # The LEOX team <team@leox.org>, http://www.leox.org
 #
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
 # LEOX.org is about the development of free hardware and software resources
 #   for system on chip.
 #
@@ -30,18 +34,22 @@
 
 include $(TOPDIR)/config.mk
 
-LIB	= lib$(BOARD).a
+LIB	= $(obj)lib$(BOARD).a
 
-OBJS	= $(BOARD).o flash.o
+COBJS	= $(BOARD).o flash.o
 
-$(LIB):	.depend $(OBJS)
-	$(AR) crv $@ $^
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 #########################################################################
 
-.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
 
-sinclude .depend
+sinclude $(obj).depend
 
 #########################################################################

board/LEOX/elpt860/README.LEOX

@@ -1,20 +1,20 @@
 =============================================================================
 
-             U-Boot port on the LEOX's ELPT860 CPU board
-             -------------------------------------------
+	     U-Boot port on the LEOX's ELPT860 CPU board
+	     -------------------------------------------
 
 LEOX.org is about the development of free hardware and software resources
-         for system on chip.
+	 for system on chip.
 
 For more information, contact The LEOX team <team@leox.org>
 
 References:
 ~~~~~~~~~~
     1) Get the last stable release from denx.de:
-           o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2
+	   o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2
     2) Get the current CVS snapshot:
-           o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
-           o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
+	   o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
+	   o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
 
 =============================================================================
 
@@ -42,7 +42,7 @@ U-Boot, at the address of 0x03000000.
 
 =============================================================================
 
-                        U-Boot test results
+			U-Boot test results
 
 =============================================================================
 
@@ -54,7 +54,7 @@ U-Boot, at the address of 0x03000000.
 U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
 
 CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
-         *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
 Board: ### No HW ID - assuming ELPT860
 DRAM:  16 MB
 FLASH: 512 kB
@@ -101,7 +101,7 @@ saveenv - save environment variables to persistent storage
 setenv  - set environment variables
 sleep   - delay execution for some time
 tftpboot- boot image via network using TFTP protocol
-               and env variables ipaddr and serverip
+	       and env variables ipaddr and serverip
 version - print monitor version
 ?       - alias for 'help'
 
@@ -124,9 +124,9 @@ nfsserverip=192.168.0.1
 preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo
 gatewayip=192.168.0.1
 ramargs=setenv bootargs root=/dev/ram rw
-rootargs=setenv rootpath /tftp/$(ipaddr)
-nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(nfsserverip):$(rootpath)
-addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(nfsserverip):$(gatewayip):$(netmask):$(hostname):eth0:
+rootargs=setenv rootpath /tftp/${ipaddr}
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${nfsserverip}:${rootpath}
+addip=setenv bootargs ${bootargs} ip=${ipaddr}:${nfsserverip}:${gatewayip}:${netmask}:${hostname}:eth0:
 ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm
 nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm
 bootcmd=run ramboot
@@ -143,8 +143,8 @@ LEOX_elpt860: flinfo
 Bank # 1: AMD AM29F040   (4 Mbits)
   Size: 512 KB in 8 Sectors
   Sector Start Addresses:
-    02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000     
-    02050000      02060000      02070000     
+    02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000
+    02050000      02060000      02070000
 
 ##################################################
 # Board Information Structure
@@ -177,7 +177,7 @@ baudrate    =   9600 bps
 U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
 
 CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
-         *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
 Board: ### No HW ID - assuming ELPT860
 DRAM:  16 MB
 FLASH: 512 kB
@@ -219,7 +219,7 @@ Hit any key to exit ...
 U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
 
 CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
-         *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
 Board: ### No HW ID - assuming ELPT860
 DRAM:  16 MB
 FLASH: 512 kB
@@ -237,7 +237,7 @@ TFTP from server 192.168.0.1; our IP address is 192.168.0.30
 Filename '/home/leox/uImage'.
 Load address: 0x400000
 Loading: #################################################################
-         #############################
+	 #############################
 done
 Bytes transferred = 477294 (7486e hex)
 ## Booting image at 00400000 ...
@@ -282,8 +282,8 @@ Looking up port of RPC 100005/2 on 192.168.0.1
 VFS: Mounted root (nfs filesystem).
 Freeing unused kernel memory: 44k init
 INIT: version 2.78 booting
-                Welcome to DENX Embedded Linux Environment
-                Press 'I' to enter interactive startup.
+		Welcome to DENX Embedded Linux Environment
+		Press 'I' to enter interactive startup.
 Mounting proc filesystem:  [  OK  ]
 Configuring kernel parameters:  [  OK  ]
 Cannot access the Hardware Clock via any known method.
@@ -316,7 +316,7 @@ bash-2.04#
 U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
 
 CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
-         *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
 Board: ### No HW ID - assuming ELPT860
 DRAM:  16 MB
 FLASH: 512 kB
@@ -334,11 +334,11 @@ TFTP from server 192.168.0.1; our IP address is 192.168.0.30
 Filename '/home/leox/pMulti'.
 Load address: 0x400000
 Loading: #################################################################
-         #################################################################
-         #################################################################
-         #################################################################
-         #################################################################
-         ########################################################
+	 #################################################################
+	 #################################################################
+	 #################################################################
+	 #################################################################
+	 ########################################################
 done
 Bytes transferred = 1947816 (1db8a8 hex)
 ## Booting image at 00400000 ...
@@ -398,22 +398,22 @@ ELPT860 login: root
 Password:
 Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz)
 
-                                              a8888b.
-                                             d888888b.
-                                             8P"YP"Y88
+					      a8888b.
+					     d888888b.
+					     8P"YP"Y88
      _      _                                8|o||o|88
     | |    |_|                               8'    .88
     | |     _ ____  _   _  _  _              8`._.' Y8.
     | |    | |  _ \| | | |\ \/ /            d/      `8b.
     | |___ | | | | | |_| |/    \          .dP   .     Y8b.
     |_____||_|_| |_|\____|\_/\_/         d8:'   "   `::88b.
-                                        d8"           `Y88b
-                                       :8P     '       :888
-                                        8a.    :      _a88P
-                                      ._/"Yaa_ :    .| 88P|
-                                      \    YP"      `| 8P  `.
-                                      /     \._____.d|    .'
-                                      `--..__)888888P`._.'
+					d8"           `Y88b
+				       :8P     '       :888
+					8a.    :      _a88P
+				      ._/"Yaa_ :    .| 88P|
+				      \    YP"      `| 8P  `.
+				      /     \._____.d|    .'
+				      `--..__)888888P`._.'
 login[21]: root login  on `ttyS0'
 
 

board/LEOX/elpt860/elpt860.c

@@ -33,7 +33,7 @@
 /*
 ** Note 1: In this file, you have to provide the following functions:
 ** ------
-**              int             board_pre_init(void)
+**              int             board_early_init_f(void)
 **              int             checkboard(void)
 **              long int        initdram(int board_type)
 ** called from 'board_init_f()' into 'common/board.c'
@@ -53,89 +53,87 @@ static long int dram_size (long int, long int *, long int);
 
 #define	_NOT_USED_	0xFFFFFFFF
 
-const uint init_sdram_table[] =
-{
-  /*
-   * Single Read. (Offset 0 in UPMA RAM)
-   */
-  0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
-  0xFFFFFC04, /* last */
-  /*
-   * SDRAM Initialization (offset 5 in UPMA RAM)
-   *
-   * This is no UPM entry point. The following definition uses
-   * the remaining space to establish an initialization
-   * sequence, which is executed by a RUN command.
-   *
-   */
-  0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,  /* last */
-  /*
-   * Burst Read. (Offset 8 in UPMA RAM)
-   */
-  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-  0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
-  0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
-  /*
-   * Single Write. (Offset 18 in UPMA RAM)
-   */
-  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
-  0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
-  /*
-   * Burst Write. (Offset 20 in UPMA RAM)
-   */
-  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-  0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
-  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
-  0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
+const uint init_sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
+	0xFFFFFC04,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,	/* last */
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04,	/* last */
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
+	0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05,	/* last */
 };
 
-const uint sdram_table[] =
-{
-  /*
-   * Single Read. (Offset 0 in UPMA RAM)
-   */
-  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, 
-  0xFF0FFC00, /* last */
-  /*
-   * SDRAM Initialization (offset 5 in UPMA RAM)
-   *
-   * This is no UPM entry point. The following definition uses
-   * the remaining space to establish an initialization
-   * sequence, which is executed by a RUN command.
-   *
-   */
-  0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
-  /*
-   * Burst Read. (Offset 8 in UPMA RAM)
-   */
-  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, 
-  0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
-  0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, 
-  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
-  /*
-   * Single Write. (Offset 18 in UPMA RAM)
-   */
-  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00, 
-  0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
-  _NOT_USED_, 
-  /*
-   * Burst Write. (Offset 20 in UPMA RAM)
-   */
-  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00, 
-  0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04, 
-  0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, 
-  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
-  /*
-   * Refresh  (Offset 30 in UPMA RAM)
-   */
-  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 
-  0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_, 
-  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
-  /*
-   * Exception. (Offset 3c in UPMA RAM)
-   */
-  0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+	0xFF0FFC00,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+	0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
+	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
+	0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05,	/* last */
+	_NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
+	0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
+	0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04,	/* last */
 };
 
 /* ------------------------------------------------------------------------- */
@@ -147,19 +145,18 @@ const uint sdram_table[] =
 /*
  * Very early board init code (fpga boot, etc.)
  */
-int
-board_pre_init (void)
+int board_early_init_f (void)
 {
-  volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
-  /* 
-   * Light up the red led on ELPT860 pcb (DS1) (PCDAT) 
-   */
-  immr->im_ioport.iop_pcdat &= ~CFG_DS1;   /* PCDAT (DS1 = 0)                */
-  immr->im_ioport.iop_pcpar &= ~CFG_DS1;   /* PCPAR (0=general purpose I/O)  */
-  immr->im_ioport.iop_pcdir |=  CFG_DS1;   /* PCDIR (I/O: 0=input, 1=output) */
+	/*
+	 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
+	 */
+	immr->im_ioport.iop_pcdat &= ~CFG_DS1;	/* PCDAT (DS1 = 0)                */
+	immr->im_ioport.iop_pcpar &= ~CFG_DS1;	/* PCPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_pcdir |= CFG_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
 
-  return ( 0 );    /* success */
+	return (0);		/* success */
 }
 
 /*
@@ -170,150 +167,143 @@ board_pre_init (void)
  * Return 1 if no second DRAM bank, otherwise returns 0
  */
 
-int 
-checkboard (void)
+int checkboard (void)
 {
-    unsigned char *s = getenv("serial#");
+	char *s = getenv ("serial#");
 
-    if ( !s || strncmp(s, "ELPT860", 7) )
-      printf ("### No HW ID - assuming ELPT860\n");
-    
-    return ( 0 );    /* success */
+	if (!s || strncmp (s, "ELPT860", 7))
+		printf ("### No HW ID - assuming ELPT860\n");
+
+	return (0);		/* success */
 }
 
 /* ------------------------------------------------------------------------- */
 
-long int 
-initdram (int board_type)
+long int initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
-    long int              size8, size9;
-    long int              size_b0 = 0;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
 
-    /*
-     * This sequence initializes SDRAM chips on ELPT860 board
-     */
-    upmconfig(UPMA, (uint *)init_sdram_table, 
-	      sizeof(init_sdram_table)/sizeof(uint));
+	/*
+	 * This sequence initializes SDRAM chips on ELPT860 board
+	 */
+	upmconfig (UPMA, (uint *) init_sdram_table,
+		   sizeof (init_sdram_table) / sizeof (uint));
 
-    memctl->memc_mptpr = 0x0200;
-    memctl->memc_mamr  = 0x18002111;
+	memctl->memc_mptpr = 0x0200;
+	memctl->memc_mamr = 0x18002111;
 
-    memctl->memc_mar   = 0x00000088;
-    memctl->memc_mcr   = 0x80002000;	/* CS1: SDRAM bank 0 */
+	memctl->memc_mar = 0x00000088;
+	memctl->memc_mcr = 0x80002000;	/* CS1: SDRAM bank 0 */
 
-    upmconfig(UPMA, (uint *)sdram_table, 
-	      sizeof(sdram_table)/sizeof(uint));
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
 
-    /*
-     * Preliminary prescaler for refresh (depends on number of
-     * banks): This value is selected for four cycles every 62.4 us
-     * with two SDRAM banks or four cycles every 31.2 us with one
-     * bank. It will be adjusted after memory sizing.
-     */
-    memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
 
-    /*
-     * The following value is used as an address (i.e. opcode) for
-     * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
-     * the port size is 32bit the SDRAM does NOT "see" the lower two
-     * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
-     * MICRON SDRAMs:
-     * ->    0 00 010 0 010
-     *       |  |   | |   +- Burst Length = 4
-     *       |  |   | +----- Burst Type   = Sequential
-     *       |  |   +------- CAS Latency  = 2
-     *       |  +----------- Operating Mode = Standard
-     *       +-------------- Write Burst Mode = Programmed Burst Length
-     */
-    memctl->memc_mar   = 0x00000088;
+	/*
+	 * The following value is used as an address (i.e. opcode) for
+	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+	 * the port size is 32bit the SDRAM does NOT "see" the lower two
+	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+	 * MICRON SDRAMs:
+	 * ->    0 00 010 0 010
+	 *       |  |   | |   +- Burst Length = 4
+	 *       |  |   | +----- Burst Type   = Sequential
+	 *       |  |   +------- CAS Latency  = 2
+	 *       |  +----------- Operating Mode = Standard
+	 *       +-------------- Write Burst Mode = Programmed Burst Length
+	 */
+	memctl->memc_mar = 0x00000088;
 
-    /*
-     * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
-     * preliminary addresses - these have to be modified after the
-     * SDRAM size has been determined.
-     */
-    memctl->memc_or1   = CFG_OR1_PRELIM;
-    memctl->memc_br1   = CFG_BR1_PRELIM;
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
 
-    memctl->memc_mamr  = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
-    udelay (200);
+	udelay (200);
 
-    /* perform SDRAM initializsation sequence */
+	/* perform SDRAM initializsation sequence */
 
-    memctl->memc_mcr   = 0x80002105;	/* CS1: SDRAM bank 0 */
-    udelay (1);
-    memctl->memc_mcr   = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
-    udelay (1);
+	memctl->memc_mcr = 0x80002105;	/* CS1: SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
+	udelay (1);
 
-    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
 
-    udelay (1000);
-
-    /*
-     * Check Bank 0 Memory Size for re-configuration
-     *
-     * try 8 column mode
-     */
-    size8 = dram_size (CFG_MAMR_8COL, 
-		       (ulong *) SDRAM_BASE1_PRELIM, 
-		       SDRAM_MAX_SIZE);
-
-    udelay (1000);
-
-    /*
-     * try 9 column mode
-     */
-    size9 = dram_size (CFG_MAMR_9COL, 
-		       (ulong *) SDRAM_BASE1_PRELIM, 
-		       SDRAM_MAX_SIZE);
-
-    if ( size8 < size9 )    /* leave configuration at 9 columns	*/
-      {
-	size_b0 = size9;
-	/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
-      } 
-    else                  /* back to 8 columns			*/
-      {
-	size_b0 = size8;
-	memctl->memc_mamr = CFG_MAMR_8COL;
-	udelay (500);
-	/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
-      }
-    
-    udelay (1000);
-
-    /*
-     * Adjust refresh rate depending on SDRAM type, both banks
-     * For types > 128 MBit leave it at the current (fast) rate
-     */
-    if ( size_b0 < 0x02000000 ) 
-      {
-	/* reduce to 15.6 us (62.4 us / quad) */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
 	udelay (1000);
-      }
 
-    /*
-     * Final mapping: map bigger bank first
-     */
-    memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-    memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL,
+			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 
-    {
-      unsigned long reg;
-      
-      /* adjust refresh rate depending on SDRAM type, one bank */
-      reg = memctl->memc_mptpr;
-      reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
-      memctl->memc_mptpr = reg;
-    }
+	udelay (1000);
 
-    udelay(10000);
-    
-    return (size_b0);
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL,
+			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {	/* leave configuration at 9 columns       */
+		size_b0 = size9;
+		/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
+	} else {		/* back to 8 columns                      */
+
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if (size_b0 < 0x02000000) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	{
+		unsigned long reg;
+
+		/* adjust refresh rate depending on SDRAM type, one bank */
+		reg = memctl->memc_mptpr;
+		reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+		memctl->memc_mptpr = reg;
+	}
+
+	udelay (10000);
+
+	return (size_b0);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -326,55 +316,15 @@ initdram (int board_type)
  * - short between data lines
  */
 
-static long int 
-dram_size (long int   mamr_value, 
-	   long int  *base, 
-	   long int   maxsize)
+static long int
+dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-  volatile memctl8xx_t *memctl = &immap->im_memctl;
-  volatile long int    *addr;
-  ulong                 cnt, val;
-  ulong                 save[32];    /* to make test non-destructive */
-  unsigned char         i = 0;
-  
-  memctl->memc_mamr = mamr_value;
-  
-  for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) 
-    {
-      addr = base + cnt;    /* pointer arith! */
-      
-      save[i++] = *addr;
-      *addr     = ~cnt;
-    }
-  
-  /* write 0 to base address */
-  addr    = base;
-  save[i] = *addr;
-  *addr   = 0;
-  
-  /* check at base address */
-  if ( (val = *addr) != 0 ) 
-    {
-      *addr = save[i];
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
-      return (0);
-    }
-  
-  for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) 
-    {
-      addr = base + cnt;    /* pointer arith! */
-      
-      val   = *addr;
-      *addr = save[--i];
-      
-      if ( val != (~cnt) ) 
-	{
-	  return (cnt * sizeof(long));
-	}
-    }
+	memctl->memc_mamr = mamr_value;
 
-  return (maxsize);
+	return (get_ram_size (base, maxsize));
 }
 
 /* ------------------------------------------------------------------------- */
@@ -384,16 +334,15 @@ dram_size (long int   mamr_value,
 
 #define CFG_LBKs    (CFG_PA2 | CFG_PA1)
 
-void
-reset_phy (void)
+void reset_phy (void)
 {
-  volatile immap_t *immr = (immap_t *) CFG_IMMR;
-  
-  /*
-   * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
-   *                                          and no AUI loopback
-   */
-  immr->im_ioport.iop_padat &= ~CFG_LBKs;  /* PADAT (LBK eth 1&2 = 0)        */
-  immr->im_ioport.iop_papar &= ~CFG_LBKs;  /* PAPAR (0=general purpose I/O)  */
-  immr->im_ioport.iop_padir |=  CFG_LBKs;  /* PADIR (I/O: 0=input, 1=output) */
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/*
+	 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
+	 *                                          and no AUI loopback
+	 */
+	immr->im_ioport.iop_padat &= ~CFG_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
+	immr->im_ioport.iop_papar &= ~CFG_LBKs;	/* PAPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_padir |= CFG_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
 }

board/LEOX/elpt860/flash.c

@@ -79,41 +79,41 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data);
 /*-----------------------------------------------------------------------
  */
 
-unsigned long 
+unsigned long
 flash_init (void)
 {
   volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
   volatile memctl8xx_t *memctl = &immap->im_memctl;
   unsigned long         size_b0;
   int i;
-  
+
   /* Init: no FLASHes known */
-  for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) 
+  for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
     {
       flash_info[i].flash_id = FLASH_UNKNOWN;
     }
-  
+
   /* Static FLASH Bank configuration here - FIXME XXX */
-  
-  size_b0 = flash_get_size ((volatile unsigned char *)FLASH_BASE0_PRELIM, 
+
+  size_b0 = flash_get_size ((volatile unsigned char *)FLASH_BASE0_PRELIM,
 			    &flash_info[0]);
-  
-  if ( flash_info[0].flash_id == FLASH_UNKNOWN ) 
+
+  if ( flash_info[0].flash_id == FLASH_UNKNOWN )
     {
       printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 	      size_b0, size_b0<<20);
     }
-  
+
   /* Remap FLASH according to real size */
   memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
   memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
-  
+
   /* Re-do sizing to get full correct info */
-  size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE, 
+  size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE,
 			    &flash_info[0]);
-  
+
   flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
-  
+
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
   /* monitor protection ON by default */
   flash_protect (FLAG_PROTECT_SET,
@@ -121,7 +121,7 @@ flash_init (void)
 		 CFG_MONITOR_BASE + monitor_flash_len-1,
 		 &flash_info[0]);
 #endif
-  
+
 #ifdef	CFG_ENV_IS_IN_FLASH
   /* ENV protection ON by default */
   flash_protect(FLAG_PROTECT_SET,
@@ -131,14 +131,14 @@ flash_init (void)
 #endif
 
   flash_info[0].size = size_b0;
-  
+
   return (size_b0);
 }
 
 /*-----------------------------------------------------------------------
  */
-static void 
-flash_get_offsets (ulong          base, 
+static void
+flash_get_offsets (ulong          base,
 		   flash_info_t  *info)
 {
   int i;
@@ -146,7 +146,7 @@ flash_get_offsets (ulong          base,
 #define SECTOR_64KB    0x00010000
 
   /* set up sector start adress table */
-  for (i = 0; i < info->sector_count; i++) 
+  for (i = 0; i < info->sector_count; i++)
     {
       info->start[i] = base + (i * SECTOR_64KB);
     }
@@ -154,38 +154,38 @@ flash_get_offsets (ulong          base,
 
 /*-----------------------------------------------------------------------
  */
-void 
+void
 flash_print_info (flash_info_t *info)
 {
   int i;
-  
-  if ( info->flash_id == FLASH_UNKNOWN ) 
+
+  if ( info->flash_id == FLASH_UNKNOWN )
     {
       printf ("missing or unknown FLASH type\n");
       return;
     }
 
-  switch ( info->flash_id & FLASH_VENDMASK ) 
+  switch ( info->flash_id & FLASH_VENDMASK )
     {
     case FLASH_MAN_AMD:	printf ("AMD ");		break;
     case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
     case FLASH_MAN_STM: printf ("STM (Thomson) ");      break;
     default:		printf ("Unknown Vendor ");	break;
     }
-  
-  switch ( info->flash_id & FLASH_TYPEMASK ) 
+
+  switch ( info->flash_id & FLASH_TYPEMASK )
     {
     case FLASH_AM040:   printf ("AM29F040   (4 Mbits)\n");
       break;
     default:	        printf ("Unknown Chip Type\n");
       break;
     }
-  
-  printf ("  Size: %ld KB in %d Sectors\n", 
+
+  printf ("  Size: %ld KB in %d Sectors\n",
 	  info->size >> 10, info->sector_count);
-  
+
   printf ("  Sector Start Addresses:");
-  for (i=0; i<info->sector_count; ++i) 
+  for (i=0; i<info->sector_count; ++i)
     {
       if ((i % 5) == 0)
 	printf ("\n   ");
@@ -210,9 +210,9 @@ flash_print_info (flash_info_t *info)
  * The following code cannot be run from FLASH!
  */
 
-static ulong 
-flash_get_size (volatile unsigned char *addr, 
-                flash_info_t           *info)
+static ulong
+flash_get_size (volatile unsigned char *addr,
+		flash_info_t           *info)
 {
   short i;
   uchar value;
@@ -222,10 +222,10 @@ flash_get_size (volatile unsigned char *addr,
   addr[0x0555] = 0xAA;
   addr[0x02AA] = 0x55;
   addr[0x0555] = 0x90;
-  
+
   value = addr[0];
 
-  switch ( value ) 
+  switch ( value )
     {
       /*    case AMD_MANUFACT: */
     case 0x01:
@@ -246,10 +246,10 @@ flash_get_size (volatile unsigned char *addr,
       info->size = 0;
       return (0);			/* no or unknown flash	*/
     }
-  
+
   value = addr[1];			/* device ID		*/
-  
-  switch ( value ) 
+
+  switch ( value )
     {
     case STM_ID_F040B:
     case AMD_ID_F040B:
@@ -264,13 +264,13 @@ flash_get_size (volatile unsigned char *addr,
     }
 
   /* set up sector start adress table */
-  for (i = 0; i < info->sector_count; i++) 
+  for (i = 0; i < info->sector_count; i++)
     {
       info->start[i] = base + (i * 0x00010000);
     }
-  
+
   /* check for protected sectors */
-  for (i = 0; i < info->sector_count; i++) 
+  for (i = 0; i < info->sector_count; i++)
     {
       /* read sector protection at sector address, (A7 .. A0) = 0x02 */
       /* D0 = 1 if protected */
@@ -281,13 +281,13 @@ flash_get_size (volatile unsigned char *addr,
   /*
    * Prevent writes to uninitialized FLASH.
    */
-  if ( info->flash_id != FLASH_UNKNOWN ) 
+  if ( info->flash_id != FLASH_UNKNOWN )
     {
       addr = (volatile unsigned char *)info->start[0];
-      
+
       *addr = 0xF0;	/* reset bank */
     }
-  
+
   return (info->size);
 }
 
@@ -296,21 +296,21 @@ flash_get_size (volatile unsigned char *addr,
  */
 
 int
-flash_erase (flash_info_t  *info, 
-	     int            s_first, 
+flash_erase (flash_info_t  *info,
+	     int            s_first,
 	     int            s_last)
 {
   volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
   int flag, prot, sect, l_sect;
   ulong start, now, last;
-  
-  if ( (s_first < 0) || (s_first > s_last) ) 
+
+  if ( (s_first < 0) || (s_first > s_last) )
     {
-      if ( info->flash_id == FLASH_UNKNOWN ) 
+      if ( info->flash_id == FLASH_UNKNOWN )
 	{
 	  printf ("- missing\n");
-	} 
-      else 
+	}
+      else
 	{
 	  printf ("- no sectors to erase\n");
 	}
@@ -318,44 +318,44 @@ flash_erase (flash_info_t  *info,
     }
 
   if ( (info->flash_id == FLASH_UNKNOWN) ||
-       (info->flash_id > FLASH_AMD_COMP) ) 
+       (info->flash_id > FLASH_AMD_COMP) )
     {
       printf ("Can't erase unknown flash type %08lx - aborted\n",
 	      info->flash_id);
       return ( 1 );
     }
-  
+
   prot = 0;
-  for (sect=s_first; sect<=s_last; ++sect) 
+  for (sect=s_first; sect<=s_last; ++sect)
     {
-      if ( info->protect[sect] ) 
+      if ( info->protect[sect] )
 	{
 	  prot++;
 	}
     }
-  
-  if ( prot ) 
+
+  if ( prot )
     {
       printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-    } 
-  else 
+    }
+  else
     {
       printf ("\n");
     }
-  
+
   l_sect = -1;
-  
+
   /* Disable interrupts which might cause a timeout here */
   flag = disable_interrupts();
-  
+
   addr[0x0555] = 0xAA;
   addr[0x02AA] = 0x55;
   addr[0x0555] = 0x80;
   addr[0x0555] = 0xAA;
   addr[0x02AA] = 0x55;
-  
+
   /* Start erase on unprotected sectors */
-  for (sect = s_first; sect<=s_last; sect++) 
+  for (sect = s_first; sect<=s_last; sect++)
     {
       if (info->protect[sect] == 0)    /* not protected */
 	{
@@ -364,26 +364,26 @@ flash_erase (flash_info_t  *info,
 	  l_sect = sect;
 	}
     }
-  
+
   /* re-enable interrupts if necessary */
   if ( flag )
     enable_interrupts();
-  
+
   /* wait at least 80us - let's wait 1 ms */
   udelay (1000);
-  
+
   /*
    * We wait for the last triggered sector
    */
   if ( l_sect < 0 )
     goto DONE;
-  
+
   start = get_timer (0);
   last  = start;
   addr = (volatile unsigned char *)(info->start[l_sect]);
-  while ( (addr[0] & 0x80) != 0x80 ) 
+  while ( (addr[0] & 0x80) != 0x80 )
     {
-      if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT ) 
+      if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT )
 	{
 	  printf ("Timeout\n");
 	  return ( 1 );
@@ -395,14 +395,14 @@ flash_erase (flash_info_t  *info,
 	  last = now;
 	}
     }
-  
+
 DONE:
   /* reset to read mode */
   addr = (volatile unsigned char *)info->start[0];
   addr[0] = 0xF0;	/* reset bank */
-  
+
   printf (" done\n");
-  
+
   return ( 0 );
 }
 
@@ -413,10 +413,10 @@ DONE:
  * 2 - Flash not erased
  */
 
-int 
-write_buff (flash_info_t  *info, 
-	    uchar         *src, 
-	    ulong          addr, 
+int
+write_buff (flash_info_t  *info,
+	    uchar         *src,
+	    ulong          addr,
 	    ulong          cnt)
 {
   ulong cp, wp, data;
@@ -428,16 +428,16 @@ write_buff (flash_info_t  *info,
       /* Width of the data bus: 8 bits */
 
       wp = addr;
-      
+
       while ( cnt )
 	{
 	  bdata = *src++;
-	  
+
 	  if ( (rc = write_byte(info, wp, bdata)) != 0 )
 	    {
 	      return (rc);
 	    }
-	  
+
 	  ++wp;
 	  --cnt;
 	}
@@ -449,72 +449,72 @@ write_buff (flash_info_t  *info,
       /* Width of the data bus: 32 bits */
 
       wp = (addr & ~3);	/* get lower word aligned address */
-      
+
       /*
        * handle unaligned start bytes
        */
-      if ( (l = addr - wp) != 0 ) 
+      if ( (l = addr - wp) != 0 )
 	{
 	  data = 0;
-	  for (i=0, cp=wp; i<l; ++i, ++cp) 
+	  for (i=0, cp=wp; i<l; ++i, ++cp)
 	    {
 	      data = (data << 8) | (*(uchar *)cp);
 	    }
-	  for (; i<4 && cnt>0; ++i) 
+	  for (; i<4 && cnt>0; ++i)
 	    {
 	      data = (data << 8) | *src++;
 	      --cnt;
 	      ++cp;
 	    }
-	  for (; cnt==0 && i<4; ++i, ++cp) 
+	  for (; cnt==0 && i<4; ++i, ++cp)
 	    {
 	      data = (data << 8) | (*(uchar *)cp);
 	    }
-	  
-	  if ( (rc = write_word(info, wp, data)) != 0 ) 
+
+	  if ( (rc = write_word(info, wp, data)) != 0 )
 	    {
 	      return (rc);
 	    }
 	  wp += 4;
 	}
-      
+
       /*
        * handle word aligned part
        */
-      while ( cnt >= 4 ) 
+      while ( cnt >= 4 )
 	{
 	  data = 0;
-	  for (i=0; i<4; ++i) 
+	  for (i=0; i<4; ++i)
 	    {
 	      data = (data << 8) | *src++;
 	    }
-	  if ( (rc = write_word(info, wp, data)) != 0 ) 
+	  if ( (rc = write_word(info, wp, data)) != 0 )
 	    {
 	      return (rc);
 	    }
 	  wp  += 4;
 	  cnt -= 4;
 	}
-      
-      if ( cnt == 0 ) 
+
+      if ( cnt == 0 )
 	{
 	  return (0);
 	}
-      
+
       /*
        * handle unaligned tail bytes
        */
       data = 0;
-      for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) 
+      for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp)
 	{
 	  data = (data << 8) | *src++;
 	  --cnt;
 	}
-      for (; i<4; ++i, ++cp) 
+      for (; i<4; ++i, ++cp)
 	{
 	  data = (data << 8) | (*(uchar *)cp);
 	}
-      
+
       return (write_word(info, wp, data));
     }
 }
@@ -525,38 +525,38 @@ write_buff (flash_info_t  *info,
  * 1 - write timeout
  * 2 - Flash not erased
  */
-static int 
-write_word (flash_info_t  *info, 
-	    ulong          dest, 
+static int
+write_word (flash_info_t  *info,
+	    ulong          dest,
 	    ulong          data)
 {
   vu_long *addr = (vu_long*)(info->start[0]);
   ulong start;
   int flag;
-  
+
   /* Check if Flash is (sufficiently) erased */
-  if ( (*((vu_long *)dest) & data) != data ) 
+  if ( (*((vu_long *)dest) & data) != data )
     {
       return (2);
     }
   /* Disable interrupts which might cause a timeout here */
   flag = disable_interrupts();
-  
+
   addr[0x0555] = 0x00AA00AA;
   addr[0x02AA] = 0x00550055;
   addr[0x0555] = 0x00A000A0;
-  
+
   *((vu_long *)dest) = data;
-  
+
   /* re-enable interrupts if necessary */
   if ( flag )
     enable_interrupts();
 
   /* data polling for D7 */
   start = get_timer (0);
-  while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) ) 
+  while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
     {
-      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) 
+      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
 	{
 	  return (1);
 	}
@@ -571,38 +571,38 @@ write_word (flash_info_t  *info,
  * 1 - write timeout
  * 2 - Flash not erased
  */
-static int 
-write_byte (flash_info_t  *info, 
-	    ulong          dest, 
+static int
+write_byte (flash_info_t  *info,
+	    ulong          dest,
 	    uchar          data)
 {
   volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
   ulong  start;
   int    flag;
-  
+
   /* Check if Flash is (sufficiently) erased */
-  if ( (*((volatile unsigned char *)dest) & data) != data ) 
+  if ( (*((volatile unsigned char *)dest) & data) != data )
     {
       return (2);
     }
   /* Disable interrupts which might cause a timeout here */
   flag = disable_interrupts();
-  
+
   addr[0x0555] = 0xAA;
   addr[0x02AA] = 0x55;
   addr[0x0555] = 0xA0;
-  
+
   *((volatile unsigned char *)dest) = data;
-  
+
   /* re-enable interrupts if necessary */
   if ( flag )
     enable_interrupts();
 
   /* data polling for D7 */
   start = get_timer (0);
-  while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) ) 
+  while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
     {
-      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) 
+      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
 	{
 	  return (1);
 	}

board/LEOX/elpt860/u-boot.lds

@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
@@ -90,6 +90,8 @@ SECTIONS
   {
     *(.rodata)
     *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
   }
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
@@ -122,6 +124,12 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
   __start___ex_table = .;
   __ex_table : { *(__ex_table) }
   __stop___ex_table = .;

board/LEOX/elpt860/u-boot.lds.debug

@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
@@ -83,6 +83,8 @@ SECTIONS
   {
     *(.rodata)
     *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
   }
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
@@ -137,4 +139,3 @@ SECTIONS
   _end = . ;
   PROVIDE (end = .);
 }
-

board/MAI/AmigaOneG3SE/AmigaOneG3SE.c

@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2002
  * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
+ * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -30,47 +31,47 @@
 #include "via686.h"
 
 __asm(" .globl send_kb                                      \n
-        send_kb:                                            \n
-                lis     r9, 0xfe00                          \n
-                                                            \n
-                li      r4, 0x10        # retries           \n
-                mtctr   r4                                  \n
-                                                            \n
-        idle:                                               \n
-                lbz     r4, 0x64(r9)                        \n
-                andi.   r4, r4, 0x02                        \n
-                bne     idle                                \n
-                                                            \n
-        ready:                                              \n
-                stb     r3, 0x60(r9)                        \n
-                                                            \n
-        check:                                              \n
-                lbz     r4, 0x64(r9)                        \n
-                andi.   r4, r4, 0x01                        \n
-                beq     check                               \n
-                                                            \n
-                lbz     r4, 0x60(r9)                        \n
-                cmpwi   r4, 0xfa                            \n
-                beq     done                                \n
-                                                            \n
-                bdnz    idle                                \n
-                                                            \n
-                li      r3, 0                               \n
-                blr                                         \n
-                                                            \n
-        done:                                               \n
-                li      r3, 1                               \n
-                blr                                         \n
-                                                            \n
-        .globl test_kb                                      \n
-        test_kb:                                            \n
-                mflr    r10                                 \n
-	        li      r3, 0xed                            \n
-                bl      send_kb                             \n
-                li      r3, 0x01                            \n
-                bl      send_kb                             \n
-                mtlr    r10                                 \n
-                blr                                         \n
+	send_kb:                                            \n
+		lis     r9, 0xfe00                          \n
+							    \n
+		li      r4, 0x10        # retries           \n
+		mtctr   r4                                  \n
+							    \n
+	idle:                                               \n
+		lbz     r4, 0x64(r9)                        \n
+		andi.   r4, r4, 0x02                        \n
+		bne     idle                                \n
+							    \n
+	ready:                                              \n
+		stb     r3, 0x60(r9)                        \n
+							    \n
+	check:                                              \n
+		lbz     r4, 0x64(r9)                        \n
+		andi.   r4, r4, 0x01                        \n
+		beq     check                               \n
+							    \n
+		lbz     r4, 0x60(r9)                        \n
+		cmpwi   r4, 0xfa                            \n
+		beq     done                                \n
+							    \n
+		bdnz    idle                                \n
+							    \n
+		li      r3, 0                               \n
+		blr                                         \n
+							    \n
+	done:                                               \n
+		li      r3, 1                               \n
+		blr                                         \n
+							    \n
+	.globl test_kb                                      \n
+	test_kb:                                            \n
+		mflr    r10                                 \n
+		li      r3, 0xed                            \n
+		bl      send_kb                             \n
+		li      r3, 0x01                            \n
+		bl      send_kb                             \n
+		mtlr    r10                                 \n
+		blr                                         \n
 ");
 
 
@@ -86,11 +87,8 @@ long initdram (int board_type)
 }
 
 
-
 void after_reloc (ulong dest_addr, gd_t *gd)
 {
-/* HJF:	DECLARE_GLOBAL_DATA_PTR; */
-
 	board_init_r (gd, dest_addr);
 }
 

board/MAI/AmigaOneG3SE/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -22,35 +22,42 @@
 #
 
 include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../menu)
+$(shell mkdir -p $(obj)../bios_emulator)
+endif
 
-LIB	= lib$(BOARD).a
+LIB	= $(obj)lib$(BOARD).a
 
 COBJS	= $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \
-		via686.o i8259.o ../bios_emulator/x86interface.o 	\
+		via686.o i8259.o ../bios_emulator/x86interface.o	\
 		../bios_emulator/bios.o ../bios_emulator/glue.o		\
 		interrupts.o ps2kbd.o video.o usb_uhci.o enet.o	        \
 		../menu/cmd_menu.o cmd_boota.o nvram.o
 
-AOBJS	= board_asm_init.o memio.o
-
-OBJS	= $(COBJS) $(AOBJS) 
+SOBJS	= board_asm_init.o memio.o
 
 EMUDIR  = ../bios_emulator/scitech/src/x86emu/
 EMUOBJ  = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \
 		$(EMUDIR)ops.o $(EMUDIR)sys.o
-EMUSRC = $(EMUOBJ:.o=.c)
+EMUSRC  = $(EMUOBJ:.o=.c)
 
-$(LIB):	.depend $(OBJS) $(EMUSRC) 
-	make libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+EMUOBJ  := $(addprefix $(obj),$(EMUOBJ))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS) $(EMUSRC)
+	make $(obj)libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE)
 	-rm $(LIB)
-	$(AR) crv $@ $(OBJS) $(EMUOBJ)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(EMUOBJ)
 
 
 #########################################################################
 
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
-	$(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
 
-sinclude .depend
+sinclude $(obj).depend
 
 #########################################################################

board/MAI/AmigaOneG3SE/articiaS.c

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Hyperion Entertainment, ThomasF@hyperion-entertainment.com 
+ * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -29,6 +29,8 @@
 #include "smbus.h"
 #include "via686.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef DEBUG
 
 struct dimm_bank {
@@ -82,7 +84,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte)
 
 long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
 {
-    DECLARE_GLOBAL_DATA_PTR;
 	int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
 	uint32 busclock = gd->bus_clk;
 	uint32 memclock = busclock;
@@ -394,8 +395,6 @@ uint32 burst_to_len (uint32 support)
 
 long articiaS_ram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	register uint32 i;
 	register uint32 value1;
 	register uint32 value2;
@@ -572,7 +571,7 @@ long articiaS_ram_init (void)
 	if (banks[3].used)
 		burst_support = banks[3].burst_len;
 
-	/* 
+	/*
 	   ** Mode register:
 	   ** Bits         Use
 	   ** 0-2          Burst len
@@ -675,7 +674,7 @@ static __inline__ void set_msr (unsigned long msr)
 	asm volatile ("mtmsr %0"::"r" (msr));
 }
 
-int board_pre_init (void)
+int board_early_init_f (void)
 {
 	unsigned char c_value = 0;
 	unsigned long msr;

board/MAI/AmigaOneG3SE/articiaS.h

@@ -99,14 +99,14 @@
 #define XDBCR_HWTOXD          (1<<0)
 #define XDBCR_KBTOXD          (1<<1)
 #define XDBCR_RTCTOXD         (1<<2)
-#define XDBCR_SCALE_1_1       (0x0<<3)       
-#define XDBCR_SCALE_2_2       (0x1<<3)       
-#define XDBCR_SCALE_3_2       (0x2<<3)       
-#define XDBCR_SCALE_4_4       (0x3<<3)       
-#define XDBCR_SCALE_5_8       (0x4<<3)       
-#define XDBCR_SCALE_6_8       (0x5<<3)       
-#define XDBCR_SCALE_8_8       (0x6<<3)       
-#define XDBCR_SCALE_0_16      (0x7<<3)       
+#define XDBCR_SCALE_1_1       (0x0<<3)
+#define XDBCR_SCALE_2_2       (0x1<<3)
+#define XDBCR_SCALE_3_2       (0x2<<3)
+#define XDBCR_SCALE_4_4       (0x3<<3)
+#define XDBCR_SCALE_5_8       (0x4<<3)
+#define XDBCR_SCALE_6_8       (0x5<<3)
+#define XDBCR_SCALE_8_8       (0x6<<3)
+#define XDBCR_SCALE_0_16      (0x7<<3)
 #define XDBCR_XDPROM          (1<<7)
 
 
@@ -134,7 +134,6 @@
 #define ARTICIAS_ISAIO_PHYS    0xfe002000
 
 
-
 /* Prototypes */
 long articiaS_ram_init(void);
 void articiaS_pci_init(void);

board/MAI/AmigaOneG3SE/articiaS_pci.c

@@ -26,6 +26,8 @@
 #include "memio.h"
 #include "articiaS.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef ARTICIA_PCI_DEBUG
 
 #ifdef  ARTICIA_PCI_DEBUG
@@ -123,14 +125,14 @@ struct pci_irq_fixup_table fixuptab [] =
 {
     { 0, 0, 0, 0xff},        /* Articia S host bridge */
     { 0, 1, 0, 0xff},        /* Articia S AGP bridge */
-//    { 0, 6, 0, 0x05},        /* 3COM ethernet */
+/*    { 0, 6, 0, 0x05},        /###* 3COM ethernet */
     { 0, 7, 0, 0xff},        /* VIA southbridge */
     { 0, 7, 1, 0x0e},        /* IDE controller in legacy mode */
-//    { 0, 7, 2, 0x05},        /* First USB controller */
-//    { 0, 7, 3, 0x0c},        /* Second USB controller (shares interrupt with ethernet) */
+/*    { 0, 7, 2, 0x05},        /###* First USB controller */
+/*    { 0, 7, 3, 0x0c},        /###* Second USB controller (shares interrupt with ethernet) */
     { 0, 7, 4, 0xff},        /* ACPI Power Management */
-//    { 0, 7, 5, 0x08},        /* AC97 */
-//    { 0, 7, 6, 0x08},        /* MC97 */
+/*    { 0, 7, 5, 0x08},        /###* AC97 */
+/*    { 0, 7, 6, 0x08},        /###* MC97 */
     { 0xff, 0xff, 0xff, 0xff}
 };
 
@@ -287,7 +289,7 @@ void articiaS_pci_init (void)
 
     PRINTF("atriciaS_pci_init\n");
 
-    // Why aren't these relocated??
+    /* Why aren't these relocated?? */
     for (i=0; config_table[i].config_device; i++)
     {
 	switch((int)config_table[i].config_device)
@@ -335,7 +337,6 @@ void articiaS_pci_init (void)
 		   PCI_REGION_IO);
 
 
-
     articiaS_hose.region_count = 4;
 
     pci_setup_indirect(&articiaS_hose, ARTICIAS_PCI_CFGADDR, ARTICIAS_PCI_CFGDATA);
@@ -367,11 +368,11 @@ void articiaS_pci_init (void)
 	if (articiaS_init_vga() == -1)
 	{
 	    /* If the VGA didn't init and we have stdout set to VGA, reset to serial */
-/* 	    s = getenv("stdout"); */
-/* 	    if (s && strcmp(s, "vga") == 0) */
-/* 	    { */
-/* 		setenv("stdout", "serial"); */
-/* 	    } */
+/*	    s = getenv("stdout"); */
+/*	    if (s && strcmp(s, "vga") == 0) */
+/*	    { */
+/*		setenv("stdout", "serial"); */
+/*	    } */
 	}
     }
     pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);
@@ -410,8 +411,8 @@ pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_c
 	    pci_hose_read_config_byte(hose, dev, 0x0B, &c1);
 	    pci_hose_read_config_byte(hose, dev, 0x0A, &c2);
 	    class = c1<<8 | c2;
-	    //printf("At %02x:%02x:%02x: class %x\n",
-	    //	   PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), class);
+	    /*printf("At %02x:%02x:%02x: class %x\n", */
+	    /*	   PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), class); */
 	    if (class == find_class)
 	    {
 		if (index == 0)
@@ -441,7 +442,7 @@ pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr)
 
     if (hose == NULL) hose = &articiaS_hose;
 
-    if (busnr < hose->first_busno || busnr > hose->last_busno) return PCI_ANY_ID; // Not in range
+    if (busnr < hose->first_busno || busnr > hose->last_busno) return PCI_ANY_ID; /* Not in range */
 
     /*
      * The bridge must be on a lower bus number
@@ -467,7 +468,7 @@ pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr)
 
 		if (!PCI_FUNC(dev))
 		    found_multi = header_type & 0x80;
-		if (header_type == 1) // Bridge device header
+		if (header_type == 1) /* Bridge device header */
 		{
 		    pci_hose_read_config_byte(hose, dev, PCI_SECONDARY_BUS, &secondary_bus);
 		    if ((int)secondary_bus == busnr) return dev;
@@ -494,8 +495,6 @@ pci_dev_t video_dev;
 
 int articiaS_init_vga (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
     extern void shutdown_bios(void);
     pci_dev_t dev = ~0;
     int busnr = 0;
@@ -512,7 +511,7 @@ int articiaS_init_vga (void)
 	PRINTF("Searching for class 0x%x on bus %d\n", classes[classnr], busnr);
 	/* Find the first of this class on this bus */
 	dev = pci_hose_find_class(&articiaS_hose, busnr, classes[classnr], 0);
-	if (dev != ~0) 
+	if (dev != ~0)
 	{
 	    PRINTF("Found VGA Card at %02x:%02x:%02x\n", PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 	    break;

board/MAI/AmigaOneG3SE/board_asm_init.S

@@ -1,14 +1,13 @@
-	#include	"macros.h"
-	
-	
+#include	"macros.h"
 
-#define GLOBALINFO0	      0x50	
+
+#define GLOBALINFO0	      0x50
 #define GLOBALINFO0_BO        (1<<7)
 #define GLOBALINFO2_B1ARBITER (1<<6)
 #define HBUSACR0              0x5c
 #define HBUSACR2_BURST        (1<<0)
 #define HBUSACR2_LAT          (1<<1)
-	
+
 #define RECEIVER_HOLDING 0
 #define TRANSMITTER_HOLDING 0
 #define INTERRUPT_ENABLE 1
@@ -35,9 +34,9 @@
 
 #define SUPERIO_1               ((7 << 3) | (0))
 #define SUPERIO_2               ((7 << 3) | (1))
-	
+
 	.globl	board_asm_init
-	
+
 board_asm_init:
 	mflr	r29
 	/* Set 'Must-set' register */
@@ -77,7 +76,7 @@ board_asm_init:
 	li	r5, 0x47
 	bl	pci_write_cfg_byte*/
 
-	
+
 	/* Enable NVRAM for environment */
 	li	r3, 0
 	li	r4, 0
@@ -91,7 +90,7 @@ board_asm_init:
 	siowb	0x40, 0x08
 	siowb	0x41, 0x01
 	siowb	0x45, 0x80
-	siowb	0x46, 0x60	
+	siowb	0x46, 0x60
 	siowb	0x47, 0x20
 	siowb	0x48, 0x01
 	siowb	0x4a, 0xc4
@@ -103,7 +102,7 @@ board_asm_init:
 	siowb	0x56, 0x99
 	siowb	0x57, 0x90
 	siowb	0x85, 0x01
-		
+
 	/* Enable configuration mode for SuperIO */
 	li	r3, 0
 	li	r4, (7<<3)
@@ -128,7 +127,7 @@ board_asm_init:
 	ori	r3, r3, 0x0c
 	outb	0x3f0, 0xe2
 	outbr	0x3f1, r3
-	
+
 	/* Disable configuration mode */
 	li	r3, 0
 	li	r4, (7<<3)
@@ -145,7 +144,7 @@ board_asm_init:
 	mtlr	r29
 	blr
 
-		
+
 	.globl	new_reset
 	.globl	new_reset_end
 new_reset:
@@ -153,5 +152,5 @@ new_reset:
 	oris	r0, r0, 0xFFF0
 	mtlr	r0
 	blr
-	
-new_reset_end:	
+
+new_reset_end:

board/MAI/AmigaOneG3SE/cmd_boota.c

@@ -1,9 +1,9 @@
 #include <common.h>
 #include <command.h>
-#include <cmd_boota.h>
 #include "../disk/part_amiga.h"
 #include <asm/cache.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #undef BOOTA_DEBUG
 
@@ -109,8 +109,6 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 	s = getenv ("autostart");
 	if (s && strcmp (s, "yes") == 0) {
-		DECLARE_GLOBAL_DATA_PTR;
-
 		void (*boot) (bd_t *, char *, block_dev_desc_t *);
 		char *args;
 
@@ -121,3 +119,10 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 	return 0;
 }
+#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
+U_BOOT_CMD(
+	boota,   3,      1,      do_boota,
+	"boota   - boot an Amiga kernel\n",
+	"address disk"
+);
+#endif /* _CMD_BOOTA_H */

board/MAI/AmigaOneG3SE/config.mk

@@ -29,5 +29,4 @@ X86EMU =  -I../bios_emulator/scitech/include -I../bios_emulator/scitech/src/x86e
 
 TEXT_BASE = 0xfff00000
 
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -Wa,-mregnames -DEASTEREGG $(X86EMU) -Dprintk=printf #-DDEBUG 
-
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -Wa,-mregnames -DEASTEREGG $(X86EMU) -Dprintk=printf #-DDEBUG

board/MAI/AmigaOneG3SE/enet.c

@@ -36,62 +36,62 @@
 
 /* 3Com Ethernet PCI definitions*/
 
-// #define PCI_VENDOR_ID_3COM		0x10B7
+/* #define PCI_VENDOR_ID_3COM		0x10B7 */
 #define PCI_DEVICE_ID_3COM_3C905C	0x9200
 
 /* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */
 
-#define TotalReset 		(0<<11) 
-#define SelectWindow 		(1<<11)
-#define StartCoax 		(2<<11)
-#define RxDisable 		(3<<11) 
-#define RxEnable 		(4<<11) 
-#define RxReset 		(5<<11)
-#define UpStall 		(6<<11) 
-#define UpUnstall 		(6<<11)+1
-#define DownStall 		(6<<11)+2 
-#define DownUnstall 		(6<<11)+3
-#define RxDiscard 		(8<<11)
-#define TxEnable 		(9<<11)
-#define TxDisable 		(10<<11) 
-#define TxReset 		(11<<11)
-#define FakeIntr 		(12<<11) 
-#define AckIntr 		(13<<11) 
-#define SetIntrEnb 		(14<<11)
-#define SetStatusEnb 		(15<<11) 
-#define SetRxFilter 		(16<<11)
-#define SetRxThreshold 		(17<<11)
-#define SetTxThreshold 		(18<<11) 
-#define SetTxStart 		(19<<11)
-#define StartDMAUp 		(20<<11)
-#define StartDMADown 		(20<<11)+1
+#define TotalReset		(0<<11)
+#define SelectWindow		(1<<11)
+#define StartCoax		(2<<11)
+#define RxDisable		(3<<11)
+#define RxEnable		(4<<11)
+#define RxReset			(5<<11)
+#define UpStall			(6<<11)
+#define UpUnstall		(6<<11)+1
+#define DownStall		(6<<11)+2
+#define DownUnstall		(6<<11)+3
+#define RxDiscard		(8<<11)
+#define TxEnable		(9<<11)
+#define TxDisable		(10<<11)
+#define TxReset			(11<<11)
+#define FakeIntr		(12<<11)
+#define AckIntr			(13<<11)
+#define SetIntrEnb		(14<<11)
+#define SetStatusEnb		(15<<11)
+#define SetRxFilter		(16<<11)
+#define SetRxThreshold		(17<<11)
+#define SetTxThreshold		(18<<11)
+#define SetTxStart		(19<<11)
+#define StartDMAUp		(20<<11)
+#define StartDMADown		(20<<11)+1
 #define StatsEnable		(21<<11)
-#define StatsDisable		(22<<11) 
-#define StopCoax 		(23<<11)
-#define SetFilterBit 		(25<<11)
+#define StatsDisable		(22<<11)
+#define StopCoax		(23<<11)
+#define SetFilterBit		(25<<11)
 
 /* The SetRxFilter command accepts the following classes */
 
-#define RxStation 		1 
-#define RxMulticast		2 
-#define RxBroadcast		4 
-#define RxProm 			8
+#define RxStation		1
+#define RxMulticast		2
+#define RxBroadcast		4
+#define RxProm			8
 
 /* 3Com status word defnitions */
 
-#define IntLatch 		0x0001
-#define HostError 		0x0002
-#define TxComplete 		0x0004
-#define TxAvailable 		0x0008
-#define RxComplete 		0x0010 
-#define RxEarly 		0x0020
-#define IntReq 			0x0040
-#define StatsFull 		0x0080
-#define DMADone 		(1<<8)
-#define DownComplete 		(1<<9) 
-#define UpComplete 		(1<<10)
-#define DMAInProgress 		(1<<11)			/* DMA controller is still busy.*/
-#define CmdInProgress 		(1<<12)           	/* EL3_CMD is still busy.*/
+#define IntLatch		0x0001
+#define HostError		0x0002
+#define TxComplete		0x0004
+#define TxAvailable		0x0008
+#define RxComplete		0x0010
+#define RxEarly			0x0020
+#define IntReq			0x0040
+#define StatsFull		0x0080
+#define DMADone			(1<<8)
+#define DownComplete		(1<<9)
+#define UpComplete		(1<<10)
+#define DMAInProgress		(1<<11)			/* DMA controller is still busy.*/
+#define CmdInProgress		(1<<12)          	/* EL3_CMD is still busy.*/
 
 /* Polling Registers */
 
@@ -100,45 +100,45 @@
 
 /* Register window 0 offets */
 
-#define Wn0EepromCmd 		10	          	/* Window 0: EEPROM command register. */
-#define Wn0EepromData 		12             		/* Window 0: EEPROM results register. */
+#define Wn0EepromCmd		10	         	/* Window 0: EEPROM command register. */
+#define Wn0EepromData		12            		/* Window 0: EEPROM results register. */
 #define IntrStatus		0x0E	                /* Valid in all windows. */
 
 /* Register window 0 EEPROM bits */
 
-#define EEPROM_Read 		0x80
-#define EEPROM_WRITE 		0x40
-#define EEPROM_ERASE 		0xC0
-#define EEPROM_EWENB 		0x30            	/* Enable erasing/writing for 10 msec. */
-#define EEPROM_EWDIS 		0x00            	/* Disable EWENB before 10 msec timeout. */
+#define EEPROM_Read		0x80
+#define EEPROM_WRITE		0x40
+#define EEPROM_ERASE		0xC0
+#define EEPROM_EWENB		0x30          		/* Enable erasing/writing for 10 msec. */
+#define EEPROM_EWDIS		0x00           		/* Disable EWENB before 10 msec timeout. */
 
 /* EEPROM locations. */
 
-#define PhysAddr01		0 
+#define PhysAddr01		0
 #define PhysAddr23		1
-#define PhysAddr45		2 
+#define PhysAddr45		2
 #define ModelID			3
-#define EtherLink3ID		7 
-#define IFXcvrIO		8 
+#define EtherLink3ID		7
+#define IFXcvrIO		8
 #define IRQLine			9
-#define NodeAddr01		10 
-#define NodeAddr23		11 
+#define NodeAddr01		10
+#define NodeAddr23		11
 #define NodeAddr45		12
-#define DriverTune		13 
+#define DriverTune		13
 #define Checksum		15
 
 /* Register window 1 offsets, the window used in normal operation */
 
-#define TX_FIFO 		0x10  
-#define RX_FIFO 		0x10  
-#define RxErrors 		0x14
-#define RxStatus 		0x18  
-#define Timer			0x1A 
-#define TxStatus 		0x1B
-#define TxFree 			0x1C	 		/* Remaining free bytes in Tx buffer. */
+#define TX_FIFO			0x10
+#define RX_FIFOa		0x10
+#define RxErrors		0x14
+#define RxStatus		0x18
+#define Timer			0x1A
+#define TxStatus		0x1B
+#define TxFree			0x1C			/* Remaining free bytes in Tx buffer. */
 
 /* Register Window 2 */
-        
+
 #define Wn2_ResetOptions	12
 
 /* Register Window 3: MAC/config bits */
@@ -147,47 +147,47 @@
 #define Wn3_MAC_Ctrl		6
 #define Wn3_Options		8
 
-#define BFEXT(value, offset, bitcount)  					\
-    	((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
+#define BFEXT(value, offset, bitcount)					\
+	((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
 
 #define BFINS(lhs, rhs, offset, bitcount)                                       \
-        (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) |   		\
-        (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
+	(((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) |			\
+	(((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
 
 #define RAM_SIZE(v)             BFEXT(v, 0, 3)
-#define RAM_WIDTH(v)    	BFEXT(v, 3, 1)
-#define RAM_SPEED(v)    	BFEXT(v, 4, 2)
+#define RAM_WIDTH(v)		BFEXT(v, 3, 1)
+#define RAM_SPEED(v) 	   	BFEXT(v, 4, 2)
 #define ROM_SIZE(v)             BFEXT(v, 6, 2)
-#define RAM_SPLIT(v)    	BFEXT(v, 16, 2)
+#define RAM_SPLIT(v)		BFEXT(v, 16, 2)
 #define XCVR(v)                 BFEXT(v, 20, 4)
-#define AUTOSELECT(v)   	BFEXT(v, 24, 1)
+#define AUTOSELECT(v)		BFEXT(v, 24, 1)
 
 /* Register Window 4: Xcvr/media bits */
-        
-#define Wn4_FIFODiag 		4
-#define Wn4_NetDiag 		6
-#define Wn4_PhysicalMgmt	8
-#define Wn4_Media 		10
 
-#define Media_SQE 		0x0008     		/* Enable SQE error counting for AUI. */
-#define Media_10TP 		0x00C0			/* Enable link beat and jabber for 10baseT. */
-#define Media_Lnk 		0x0080			/* Enable just link beat for 100TX/100FX. */
-#define Media_LnkBeat 		0x0800
+#define Wn4_FIFODiag		4
+#define Wn4_NetDiag		6
+#define Wn4_PhysicalMgmt	8
+#define Wn4_Media		10
+
+#define Media_SQE		0x0008		/* Enable SQE error counting for AUI. */
+#define Media_10TP		0x00C0		/* Enable link beat and jabber for 10baseT. */
+#define Media_Lnk		0x0080		/* Enable just link beat for 100TX/100FX. */
+#define Media_LnkBeat		0x0800
 
 /* Register Window 7: Bus Master control */
 
-#define Wn7_MasterAddr 		0
-#define Wn7_MasterLen 		6
-#define Wn7_MasterStatus 	12
+#define Wn7_MasterAddr		0
+#define Wn7_MasterLen		6
+#define Wn7_MasterStatus	12
 
 /* Boomerang bus master control registers. */
 
-#define PktStatus 		0x20
+#define PktStatus		0x20
 #define DownListPtr		0x24
-#define FragAddr 		0x28
-#define FragLen 		0x2c
+#define FragAddr		0x28
+#define FragLen			0x2c
 #define TxFreeThreshold 	0x2f
-#define UpPktStatus 		0x30
+#define UpPktStatus		0x30
 #define UpListPtr 		0x38
 
 /* The Rx and Tx descriptor lists. */
@@ -196,28 +196,28 @@
 #define DN_COMPLETE     0x00010000                      /* This packet has been downloaded */
 
 struct rx_desc_3com {
-        u32 next;                                       /* Last entry points to 0	   	*/
-        u32 status;					/* FSH -> Frame Start Header 		*/
-        u32 addr;                                       /* Up to 63 addr/len pairs possible 	*/
-        u32 length;                                     /* Set LAST_FRAG to indicate last pair	*/
+	u32 next;                                       /* Last entry points to 0	   	*/
+	u32 status;					/* FSH -> Frame Start Header 		*/
+	u32 addr;                                       /* Up to 63 addr/len pairs possible 	*/
+	u32 length;                                     /* Set LAST_FRAG to indicate last pair	*/
 };
 
 /* Values for the Rx status entry. */
 
 #define RxDComplete		0x00008000
 #define RxDError		0x4000
-#define IPChksumErr		(1<<25) 
-#define TCPChksumErr		(1<<26) 
+#define IPChksumErr		(1<<25)
+#define TCPChksumErr		(1<<26)
 #define UDPChksumErr		(1<<27)
-#define IPChksumValid		(1<<29) 
+#define IPChksumValid		(1<<29)
 #define TCPChksumValid		(1<<30)
 #define UDPChksumValid		(1<<31)
 
 struct tx_desc_3com {
-        u32 next;                                       /* Last entry points to 0		*/
-        u32 status;                                     /* bits 0:12 length, others see below	*/
-        u32 addr;
-        u32 length;
+	u32 next;                                       /* Last entry points to 0		*/
+	u32 status;                                     /* bits 0:12 length, others see below	*/
+	u32 addr;
+	u32 length;
 };
 
 /* Values for the Tx status entry. */
@@ -232,9 +232,9 @@ struct tx_desc_3com {
 /* XCVR Types */
 
 #define XCVR_10baseT		0
-#define XCVR_AUI		1 
+#define XCVR_AUI		1
 #define XCVR_10baseTOnly	2
-#define XCVR_10base2		3 
+#define XCVR_10base2		3
 #define XCVR_100baseTx		4
 #define XCVR_100baseFx		5
 #define XCVR_MII		6
@@ -243,10 +243,10 @@ struct tx_desc_3com {
 #define XCVR_Default		10			/* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
 
 struct descriptor {			    		/* A generic descriptor. */
-        u32 next;                                       /* Last entry points to 0	   	*/
-        u32 status;					/* FSH -> Frame Start Header 		*/
-        u32 addr;                                       /* Up to 63 addr/len pairs possible 	*/
-        u32 length;                                     /* Set LAST_FRAG to indicate last pair	*/
+	u32 next;                                       /* Last entry points to 0	   	*/
+	u32 status;					/* FSH -> Frame Start Header 		*/
+	u32 addr;                                       /* Up to 63 addr/len pairs possible 	*/
+	u32 length;                                     /* Set LAST_FRAG to indicate last pair	*/
 };
 
 /* Misc. definitions */
@@ -338,7 +338,7 @@ static inline int ETH_STATUS(struct eth_device* dev)
 
 static inline void ETH_CMD(struct eth_device* dev, int command)
 {
-	*(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command); 
+	*(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command);
     __asm volatile ("eieio");
 }
 
@@ -348,24 +348,24 @@ static inline void ETH_CMD(struct eth_device* dev, int command)
 static int issue_and_wait(struct eth_device* dev, int command)
 {
 
-        int i, status;
+	int i, status;
 
 	ETH_CMD(dev, command);
-        for (i = 0; i < 2000; i++) {
-                status = ETH_STATUS(dev);
-		//printf ("Issue: status 0x%4x.\n", status);
+	for (i = 0; i < 2000; i++) {
+		status = ETH_STATUS(dev);
+		/*printf ("Issue: status 0x%4x.\n", status); */
 		if (!(status & CmdInProgress))
-                        return 1;
-        }
+			return 1;
+	}
 
-        /* OK, that didn't work.  Do it the slow way.  One second */
-        for (i = 0; i < 100000; i++) {
-                status = ETH_STATUS(dev);
-		//printf ("Issue: status 0x%4x.\n", status);
-                        return 1;
-                udelay(10);
-        }
-        PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) );
+	/* OK, that didn't work.  Do it the slow way.  One second */
+	for (i = 0; i < 100000; i++) {
+		status = ETH_STATUS(dev);
+		/*printf ("Issue: status 0x%4x.\n", status); */
+			return 1;
+		udelay(10);
+	}
+	PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) );
 	return 0;
 }
 
@@ -378,7 +378,7 @@ static int auto_negotiate(struct eth_device* dev)
 
     EL3WINDOW(dev, 1);
 
-    // Wait for Auto negotiation to complete
+    /* Wait for Auto negotiation to complete */
     for (i = 0; i <= 1000; i++)
     {
 	if (ETH_INW(dev, 2) & 0x04)
@@ -391,7 +391,6 @@ static int auto_negotiate(struct eth_device* dev)
 	    return 0;
 	}
     }
-    
 
 
     return 1;
@@ -430,10 +429,10 @@ void eth_interrupt(struct eth_device *dev)
 
 int eth_3com_initialize(bd_t *bis)
 {
-        u32 eth_iobase = 0, status;
-        int card_number = 0, ret;
-        struct eth_device* dev;
-        pci_dev_t devno;
+	u32 eth_iobase = 0, status;
+	int card_number = 0, ret;
+	struct eth_device* dev;
+	pci_dev_t devno;
 	char *s;
 
 	s = getenv("3com_base");
@@ -453,10 +452,10 @@ int eth_3com_initialize(bd_t *bis)
 	}
 
 	ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &eth_iobase);
-        eth_iobase &= ~0xf;
+	eth_iobase &= ~0xf;
 
 	PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
-  
+
 	pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 
 	 /* Check if I/O accesses and Bus Mastering are enabled */
@@ -481,28 +480,28 @@ int eth_3com_initialize(bd_t *bis)
 		goto Done;
 	}
 
-        dev = (struct eth_device*) malloc(sizeof(*dev)); //struct eth_device));
+	dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */
 
-        sprintf(dev->name, "3Com 3c920c#%d", card_number);
-        dev->iobase = eth_iobase;
-        dev->priv   = (void*) devno;
-        dev->init   = eth_3com_init;
-        dev->halt   = eth_3com_halt;
-        dev->send   = eth_3com_send;
-        dev->recv   = eth_3com_recv;
+	sprintf(dev->name, "3Com 3c920c#%d", card_number);
+	dev->iobase = eth_iobase;
+	dev->priv   = (void*) devno;
+	dev->init   = eth_3com_init;
+	dev->halt   = eth_3com_halt;
+	dev->send   = eth_3com_send;
+	dev->recv   = eth_3com_recv;
 
-        eth_register(dev);
+	eth_register(dev);
 
 /* 	{ */
 /* 	    char interrupt; */
 /* 	    devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
 /* 	    pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
-	    
+
 /* 	    printf("Installing eth0 interrupt handler to %d\n", interrupt); */
 /* 	    irq_install_handler(interrupt, eth_interrupt, dev); */
 /* 	} */
 
-        card_number++;
+	card_number++;
 
 	/* Set the latency timer for value */
 	s = getenv("3com_latency");
@@ -532,13 +531,13 @@ int eth_3com_initialize(bd_t *bis)
 		PRINTF ("Cannot allocate memory for RX_RING.....\n");
 		goto Done;
 	}
-	
+
 	if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
 	{
 		PRINTF ("Cannot allocate memory for TX_RING.....\n");
 		goto Done;
 	}
-	
+
 Done:
 	return status;
 }
@@ -552,7 +551,7 @@ static int eth_3com_init(struct eth_device* dev, bd_t *bis)
 	struct descriptor *ias_cmd;
 
 	/* Determine what type of network the machine is connected to	*/
-	/* presently drops the connect to 10Mbps			*/	     
+	/* presently drops the connect to 10Mbps			*/
 
 	if (!auto_negotiate(dev))
 	{
@@ -560,43 +559,43 @@ static int eth_3com_init(struct eth_device* dev, bd_t *bis)
 		goto Done;
 	}
 
-        issue_and_wait(dev, TxReset);
-        issue_and_wait(dev, RxReset|0x04);
+	issue_and_wait(dev, TxReset);
+	issue_and_wait(dev, RxReset|0x04);
 
-        /* Switch to register set 7 for normal use. */
-        EL3WINDOW(dev, 7);
+	/* Switch to register set 7 for normal use. */
+	EL3WINDOW(dev, 7);
 
 	/* Initialize Rx and Tx rings */
 
 	init_rx_ring(dev);
 	purge_tx_ring(dev);
 
- 	ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
+	ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
 
-        issue_and_wait(dev,SetTxStart|0x07ff);
+	issue_and_wait(dev,SetTxStart|0x07ff);
 
-        /* Below sets which indication bits to be seen. */
+	/* Below sets which indication bits to be seen. */
 
-        status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
-        ETH_CMD(dev, status_enable);
+	status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
+	ETH_CMD(dev, status_enable);
 
 	/* Below sets no bits are to cause an interrupt since this is just polling */
 
-        intr_enable   = SetIntrEnb;
-//	intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6);
-        ETH_CMD(dev, intr_enable);
+	intr_enable   = SetIntrEnb;
+/*	intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
+	ETH_CMD(dev, intr_enable);
 	ETH_OUTB(dev, 127, UpPoll);
 
-        /* Ack all pending events, and set active indicator mask */
+	/* Ack all pending events, and set active indicator mask */
 
-        ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
-        ETH_CMD(dev, intr_enable);
+	ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
+	ETH_CMD(dev, intr_enable);
 
 	/* Tell the adapter where the RX ring is located */
 
 	issue_and_wait(dev,UpStall);				/* Stall and set the UplistPtr 		*/
 	ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr);
-        ETH_CMD(dev, RxEnable); 				/* Enable the receiver. 		*/
+	ETH_CMD(dev, RxEnable); 				/* Enable the receiver. 		*/
 	issue_and_wait(dev,UpUnstall);
 
 	/* Send the Individual Address Setup frame */
@@ -612,7 +611,7 @@ static int eth_3com_init(struct eth_device* dev, bd_t *bis)
 
 	/* Tell the adapter where the TX ring is located */
 
-        ETH_CMD(dev, TxEnable); 				/* Enable transmitter. 			*/
+	ETH_CMD(dev, TxEnable); 				/* Enable transmitter. 			*/
 	issue_and_wait(dev, DownStall);				/* Stall and set the DownListPtr. 	*/
 	ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr);
 	issue_and_wait(dev, DownUnstall);
@@ -627,13 +626,13 @@ static int eth_3com_init(struct eth_device* dev, bd_t *bis)
 	}
 	if (ETH_STATUS(dev) & DownComplete)			/* If DownLoad Complete ACK the bit 	*/
 	{
-        	ETH_CMD(dev, AckIntr | DownComplete);		/* acknowledge the indication bit	*/
- 		issue_and_wait(dev, DownStall);			/* stall and clear DownListPtr 		*/
+		ETH_CMD(dev, AckIntr | DownComplete);		/* acknowledge the indication bit	*/
+		issue_and_wait(dev, DownStall);			/* stall and clear DownListPtr 		*/
 		ETH_OUTL(dev, 0, DownListPtr);
 		issue_and_wait(dev, DownUnstall);
 	}
 	status = 1;
-	    
+
 Done:
 	return status;
 }
@@ -673,8 +672,8 @@ int eth_3com_send(struct eth_device* dev, volatile void *packet, int length)
 	}
 	if (ETH_STATUS(dev) & DownComplete)			/* If DownLoad Complete ACK the bit 	*/
 	{
-        	ETH_CMD(dev, AckIntr | DownComplete);		/* acknowledge the indication bit	*/
- 		issue_and_wait(dev, DownStall);			/* stall and clear DownListPtr 		*/
+		ETH_CMD(dev, AckIntr | DownComplete);		/* acknowledge the indication bit	*/
+		issue_and_wait(dev, DownStall);			/* stall and clear DownListPtr 		*/
 		ETH_OUTL(dev, 0, DownListPtr);
 		issue_and_wait(dev, DownUnstall);
 	}
@@ -710,15 +709,15 @@ int eth_3com_recv(struct eth_device* dev)
 	status = le32_to_cpu(rx_ring[rx_next].status);		/* packet status		*/
 
 	while (status & (1<<15))
-	{		
+	{
 		/* A packet has been received */
 
-		if (status & (1<<15))		
+		if (status & (1<<15))
 		{
 			/* A valid frame received  */
-			
+
 			length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff;		/* length is in bits 0 - 12 	*/
-			
+
 			/* Pass the packet up to the protocol layers */
 
 			NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
@@ -748,7 +747,7 @@ Done:
 
 void eth_3com_halt(struct eth_device* dev)
 {
-	if (!(dev->iobase)) 
+	if (!(dev->iobase))
 	{
 		goto Done;
 	}
@@ -758,14 +757,14 @@ void eth_3com_halt(struct eth_device* dev)
 	issue_and_wait(dev, RxDisable);
 	issue_and_wait(dev, TxDisable);
 
-//	free(tx_ring);				/* release memory allocated to the DPD and UPD rings */
-//	free(rx_ring);
+/*	free(tx_ring);				/###* release memory allocated to the DPD and UPD rings */
+/*	free(rx_ring); */
 
 Done:
 	return;
 }
 
-static void init_rx_ring(struct eth_device* dev) 
+static void init_rx_ring(struct eth_device* dev)
 {
 	int i;
 
@@ -782,7 +781,7 @@ static void init_rx_ring(struct eth_device* dev)
 	rx_next = 0;
 }
 
-static void purge_tx_ring(struct eth_device* dev) 
+static void purge_tx_ring(struct eth_device* dev)
 {
 	int i;
 
@@ -799,39 +798,39 @@ static void purge_tx_ring(struct eth_device* dev)
 	}
 }
 
-static void read_hw_addr(struct eth_device* dev, bd_t *bis) 
+static void read_hw_addr(struct eth_device* dev, bd_t *bis)
 {
 	u8 hw_addr[ETH_ALEN];
 	unsigned int eeprom[0x40];
 	unsigned int checksum = 0;
 	int i, j, timer;
 
-        /* Read the station address from the EEPROM. */
+	/* Read the station address from the EEPROM. */
 
-        EL3WINDOW(dev, 0);
+	EL3WINDOW(dev, 0);
 	for (i = 0; i < 0x40; i++)
 	{
-        	ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
-                /* Pause for at least 162 us. for the read to take place. */
-                for (timer = 10; timer >= 0; timer--) 
+		ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
+		/* Pause for at least 162 us. for the read to take place. */
+		for (timer = 10; timer >= 0; timer--)
 		{
-                	udelay(162);
-                        if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
-                        	break;
-                }
-                eeprom[i] = ETH_INW(dev, Wn0EepromData);
-        }
+			udelay(162);
+			if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
+				break;
+		}
+		eeprom[i] = ETH_INW(dev, Wn0EepromData);
+	}
 
 	/* Checksum calculation.  I'm not sure about this part and there seems to be a bug on the 3com side of things */
 
-        for (i = 0; i < 0x21; i++)
-                checksum  ^= eeprom[i];
-        checksum = (checksum ^ (checksum >> 8)) & 0xff;
+	for (i = 0; i < 0x21; i++)
+		checksum  ^= eeprom[i];
+	checksum = (checksum ^ (checksum >> 8)) & 0xff;
 
-        if (checksum != 0xbb)
-                printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
+	if (checksum != 0xbb)
+		printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
 
-        for (i = 0, j = 0; i < 3; i++)
+	for (i = 0, j = 0; i < 3; i++)
 	{
 		hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff);
 		hw_addr[j++] = (u8)(eeprom[i+10] & 0xff);
@@ -839,9 +838,9 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
 
 	/*  MAC Address is in window 2, write value from EEPROM to window 2 */
 
-        EL3WINDOW(dev, 2);
-        for (i = 0; i < 6; i++)
-                ETH_OUTB(dev, hw_addr[i], i);
+	EL3WINDOW(dev, 2);
+	for (i = 0; i < 6; i++)
+		ETH_OUTB(dev, hw_addr[i], i);
 
 	for (j = 0; j < ETH_ALEN; j+=2)
 	{
@@ -849,9 +848,9 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
 		hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff);
 	}
 
-	for (i=0;i<ETH_ALEN;i++) 
+	for (i=0;i<ETH_ALEN;i++)
 	{
-		if (hw_addr[i] != bis->bi_enetaddr[i]) 
+		if (hw_addr[i] != bis->bi_enetaddr[i])
 		{
 /* 			printf("Warning: HW address don't match:\n"); */
 /* 			printf("Address in 3Com Window 2 is         " */
@@ -870,9 +869,9 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
 			bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
 		    {
 
-			sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X", 
-				hw_addr[0], hw_addr[1], hw_addr[2], 
-				hw_addr[3], hw_addr[4], hw_addr[5]); 
+			sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
+				hw_addr[0], hw_addr[1], hw_addr[2],
+				hw_addr[3], hw_addr[4], hw_addr[5]);
 			setenv("ethaddr", buffer);
 		    }
 		}
@@ -883,4 +882,3 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
 Done:
 	return;
 }
-

board/MAI/AmigaOneG3SE/flash_new.c

@@ -27,11 +27,10 @@
 #include <common.h>
 #include <flash.h>
 #include <asm/io.h>
-#include "memio.h" 
+#include "memio.h"
 
 /*---------------------------------------------------------------------*/
 #undef DEBUG_FLASH
-//#define DEBUG_FLASH
 
 #ifdef DEBUG_FLASH
 #define DEBUGF(fmt,args...) printf(fmt ,##args)
@@ -68,7 +67,7 @@ static void flash_to_mem(void)
     unsigned char x;
 
     flash_xd_nest --;
-   
+
     if (flash_xd_nest == 0)
     {
 	DEBUGF("Flash on memory bus\n");
@@ -327,7 +326,7 @@ static int flash_get_offsets (ulong base, flash_info_t *info)
 			/* set sector offsets for uniform sector type	*/
 			for (i = 0; i < info->sector_count; i++) {
 				info->start[i] = base + i * info->size /
-				                            info->sector_count;
+							    info->sector_count;
 			}
 			break;
 		default:
@@ -478,7 +477,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 		}
 
 		if ((rc = write_word(info, wp, data)) != 0) {
-		        flash_to_mem();
+			flash_to_mem();
 			return (rc);
 		}
 		wp += 4;
@@ -493,7 +492,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 			data = (data << 8) | *src++;
 		}
 		if ((rc = write_word(info, wp, data)) != 0) {
-		        flash_to_mem();
+			flash_to_mem();
 			return (rc);
 		}
 		wp  += 4;
@@ -582,7 +581,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
  */
 static void flash_reset (ulong addr)
 {
-        flash_to_xd();
+	flash_to_xd();
 	out8(addr, 0xF0);	/* reset bank */
 	iobarrier_rw();
 	flash_to_mem();
@@ -633,10 +632,10 @@ void flash_print_info (flash_info_t *info)
 			info->size / 0x100000, info->sector_count);
 	} else if (info->size % 0x400 == 0) {
 		printf ("  Size: %ld KB in %d Sectors\n",
-		        info->size / 0x400, info->sector_count);
+			info->size / 0x400, info->sector_count);
 	} else {
 		printf ("  Size: %ld B in %d Sectors\n",
-		        info->size, info->sector_count);
+			info->size, info->sector_count);
 	}
 
 	printf ("  Sector Start Addresses:");

board/MAI/AmigaOneG3SE/i8259.c

@@ -75,16 +75,16 @@ void i8259_init(void)
 	char dummy;
 	PRINTF("Initializing Interrupt controller\n");
 	/* init master interrupt controller */
-	out8(0x20, 0x11); //0x19); // was: 0x11); /* Start init sequence */
+	out8(0x20, 0x11); /* 0x19); /###* Start init sequence */
 	out8(0x21, 0x00); /* Vector base */
 	out8(0x21, 0x04); /* edge tiggered, Cascade (slave) on IRQ2 */
-	out8(0x21, 0x11); // was: 0x01); /* Select 8086 mode */
+	out8(0x21, 0x11); /* was: 0x01); /###* Select 8086 mode */
 
 	/* init slave interrupt controller */
-	out8(0xA0, 0x11); //0x19); // was: 0x11); /* Start init sequence */
+	out8(0xA0, 0x11); /* 0x19); /###* Start init sequence */
 	out8(0xA1, 0x08); /* Vector base */
 	out8(0xA1, 0x02); /* edge triggered, Cascade (slave) on IRQ2 */
-	out8(0xA1, 0x11); // was: 0x01); /* Select 8086 mode */
+	out8(0xA1, 0x11); /* was: 0x01); /###* Select 8086 mode */
 
 	/* always read ISR */
 	out8(0x20, 0x0B);

board/MAI/AmigaOneG3SE/interrupts.c

@@ -73,7 +73,7 @@ get_msr(void)
 static __inline__ void
 set_msr(unsigned long msr)
 {
-	asm volatile("mtmsr %0" : : "r" (msr)); 
+	asm volatile("mtmsr %0" : : "r" (msr));
 }
 
 static __inline__ unsigned long
@@ -89,7 +89,7 @@ get_dec(void)
 static __inline__ void
 set_dec(unsigned long val)
 {
-	asm volatile("mtdec %0" : : "r" (val)); 
+	asm volatile("mtdec %0" : : "r" (val));
 }
 
 
@@ -167,8 +167,8 @@ external_interrupt(struct pt_regs *regs)
 
 	int irq, unmask = 1;
 
-	irq = i8259_irq(); //i8259_get_irq(regs);
-//	printf("irq = %d, handler at %p ack=%d\n", irq, irq_handlers[irq].handler, *(volatile unsigned char *)0xFEF00000);
+	irq = i8259_irq(); /*i8259_get_irq(regs); */
+/*	printf("irq = %d, handler at %p ack=%d\n", irq, irq_handlers[irq].handler, *(volatile unsigned char *)0xFEF00000); */
 	i8259_mask_and_ack(irq);
 
 	if (irq_handlers[irq].handler != NULL)
@@ -264,5 +264,3 @@ do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 {
 	puts("IRQ related functions are unimplemented currently.\n");
 }
-
-

board/MAI/AmigaOneG3SE/macros.h

@@ -5,20 +5,20 @@
 	/*
 	** Load a long integer into a register
 	*/
-      	.macro liw reg, value
-                lis \reg, \value@h
-                ori \reg, \reg, \value@l
-        .endm
+	.macro liw reg, value
+		lis \reg, \value@h
+		ori \reg, \reg, \value@l
+	.endm
 
 
-	/* 
+	/*
 	** Generate config_addr request
 	** This macro expects the values in registers:
 	** r3 - bus
 	** r4 - devfn
 	** r5 - offset
 	*/
-	.macro config_addr 	
+	.macro config_addr
 		rlwinm	r9, r5, 24, 0, 6
 		rlwinm	r8, r4, 16, 0, 31
 		rlwinm	r7, r3, 8, 0, 31
@@ -31,7 +31,7 @@
 		sync
 	.endm
 
-	
+
 	/*
 	** Generate config_data address
 	*/
@@ -45,40 +45,40 @@
 	/*
 	** Write a byte value to an output port
 	*/
-        .macro outb port, value
-                lis     r2, 0xfe00
-                li      r0, \value
-                stb     r0, \port(r2)
-        .endm
+	.macro outb port, value
+		lis     r2, 0xfe00
+		li      r0, \value
+		stb     r0, \port(r2)
+	.endm
 
 
 	/*
 	** Write a register byte value to an output port
 	*/
-        .macro outbr port, value
-                lis     r2, 0xfe00
-                stb     \value, \port(r2)
-        .endm
+	.macro outbr port, value
+		lis     r2, 0xfe00
+		stb     \value, \port(r2)
+	.endm
 
 
-	/* 
+	/*
 	** Read a byte value from a port into a specified register
 	*/
-        .macro inb reg, port
-                lis     r2, 0xfe00
-                lbz     \reg, \port(r2)
-        .endm
+	.macro inb reg, port
+		lis     r2, 0xfe00
+		lbz     \reg, \port(r2)
+	.endm
 
 
 	/*
 	** Write a byte to the SuperIO config area
 	*/
-        .macro siowb offset, value
-                li      r3, 0
-                li      r4, (7<<3)
-                li      r5, \offset
-                li      r6, \value
-                bl      pci_write_cfg_byte
-        .endm
+	.macro siowb offset, value
+		li      r3, 0
+		li      r4, (7<<3)
+		li      r5, \offset
+		li      r6, \value
+		bl      pci_write_cfg_byte
+	.endm
 
 #endif

board/MAI/AmigaOneG3SE/memio.S

@@ -1,9 +1,8 @@
 #include	"macros.h"
 
-	
 
 	.globl pci_read_cfg_byte
-	
+
 pci_read_cfg_byte:
 	config_addr
 	config_data	3
@@ -12,11 +11,10 @@ pci_read_cfg_byte:
 	lbz	r3, 0(r9)
 	blr
 
-	
 
 	.globl pci_write_cfg_byte
-	
-pci_write_cfg_byte:	
+
+pci_write_cfg_byte:
 	config_addr
 	config_data	3
 	stb	r6, 0(r9)
@@ -25,9 +23,8 @@ pci_write_cfg_byte:
 	blr
 
 
-
 	.globl pci_read_cfg_word
-	
+
 pci_read_cfg_word:
 	config_addr
 	config_data	2
@@ -37,9 +34,8 @@ pci_read_cfg_word:
 	blr
 
 
-	
 	.globl pci_write_cfg_word
-	
+
 pci_write_cfg_word:
 	config_addr
 	config_data	2
@@ -48,10 +44,9 @@ pci_write_cfg_word:
 	sync
 	blr
 
-	
 
 	.globl pci_read_cfg_long
-	
+
 pci_read_cfg_long:
 	config_addr
 	config_data	0
@@ -61,9 +56,8 @@ pci_read_cfg_long:
 	blr
 
 
-
 	.globl pci_write_cfg_long
-	
+
 pci_write_cfg_long:
 	config_addr
 	config_data	0
@@ -71,4 +65,3 @@ pci_write_cfg_long:
 	eieio
 	sync
 	blr
-

board/MAI/AmigaOneG3SE/memio.h

@@ -2,7 +2,7 @@
  * Memory mapped IO
  *
  * (C) Copyright 2002
- * Hyperion Entertainment, ThomasF@hyperion-entertainment.com 
+ * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -15,9 +15,9 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  *
- */ 
+ */
 
 #ifndef _MEMIO_H
 #define _MEMIO_H
@@ -97,8 +97,8 @@ static inline void write_long_big(volatile uint32 *to, uint32 x)
 
 #define CONFIG_ADDR(bus, devfn, offset) \
     write_long_big((uint32 *)0xFEC00CF8,           \
-                   ((offset & 0xFC)<<24) | (devfn << 16)  \
-                   | (bus<<8) | 0x80);
+		   ((offset & 0xFC)<<24) | (devfn << 16)  \
+		   | (bus<<8) | 0x80);
 #define CONFIG_DATA(offset,mask) ((void *)(0xFEE00CFC+(offset & mask)))
 
 

board/MAI/AmigaOneG3SE/nvram.c

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Thomas Frieden, Hyperion Entertainment 
+ * Thomas Frieden, Hyperion Entertainment
  * ThomasF@hyperion-entertainment.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -34,4 +34,3 @@ void disable_nvram(void)
 {
     pci_write_cfg_byte(0, 0, 0x56, 0x0);
 }
-

board/MAI/AmigaOneG3SE/ps2kbd.c

@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2002
  * John W. Linville, linville@tuxdriver.com
- * 
+ *
  * Modified from code for support of MIP405 and PIP405 boards.  Previous
  * copyright follows.
  *
@@ -48,7 +48,6 @@ void i8259_unmask_irq(unsigned int irq);
 
 
 #undef KBG_DEBUG
-//#define KBG_DEBUG
 
 #ifdef KBG_DEBUG
 #define	PRINTF(fmt,args...)	printf (fmt ,##args)
@@ -143,8 +142,6 @@ void i8259_unmask_irq(unsigned int irq);
 #define 	KBD_BUFFER_LEN 0x20  /* size of the keyboardbuffer */
 
 
-
-
 static volatile char kbd_buffer[KBD_BUFFER_LEN];
 static volatile int in_pointer = 0;
 static volatile int out_pointer = 0;
@@ -172,7 +169,7 @@ static unsigned char kbd_plain_xlate[] = {
 	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
 	'\r',0xff,0xff
 	};
-	  	  
+
 static unsigned char kbd_shift_xlate[] = {
 	0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t',	/* 0x00 - 0x0f */
 	 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S',	/* 0x10 - 0x1f */
@@ -194,7 +191,7 @@ static unsigned char kbd_ctrl_xlate[] = {
 	};
 
 /******************************************************************
- * Init 
+ * Init
  ******************************************************************/
 
 int isa_kbd_init(void)
@@ -252,7 +249,7 @@ int drv_isa_kbd_init (void)
 			error=console_assign(stdin,DEVNAME);
 			if(error==0)
 				return 1;
-			else 
+			else
 				return error;
 		}
 		return 1;
@@ -261,7 +258,7 @@ int drv_isa_kbd_init (void)
 }
 
 /******************************************************************
- * Queue handling 
+ * Queue handling
  ******************************************************************/
 /* puts character in the queue and sets up the in and out pointer */
 void kbd_put_queue(char data)
@@ -287,7 +284,7 @@ int kbd_testc(void)
 	if(in_pointer==out_pointer)
 		return(0); /* no data */
 	else
-		return(1);	
+		return(1);
 }
 /* gets the character from the queue */
 int kbd_getc(void)
@@ -295,13 +292,13 @@ int kbd_getc(void)
 	char c;
 
 	while(in_pointer==out_pointer);
-	if((out_pointer+1)==KBD_BUFFER_LEN) 
+	if((out_pointer+1)==KBD_BUFFER_LEN)
 		out_pointer=0;
 	else
 		out_pointer++;
 	c=kbd_buffer[out_pointer];
 	return (int)c;
-	
+
 }
 
 
@@ -324,7 +321,7 @@ void kbd_set_leds(void)
 	kbd_send_data(KBD_CMD_SET_LEDS);
 	kbd_send_data(leds);
 }
-	
+
 
 void handle_keyboard_event(unsigned char scancode)
 {
@@ -381,11 +378,11 @@ void handle_keyboard_event(unsigned char scancode)
 		console_changed = 1;
 	    }
 	    return;
-	case 0x2A: 
+	case 0x2A:
 		case 0x36: /* shift pressed */
 			shift=1;
 			return; /* do nothing else */
-		case 0xAA: 
+		case 0xAA:
 		case 0xB6: /* shift released */
 			shift=0;
 			return; /* do nothing else */
@@ -408,15 +405,15 @@ void handle_keyboard_event(unsigned char scancode)
 		case 0x3A: /* capslock pressed */
 			caps_lock=~caps_lock;
 			kbd_set_leds();
-			return; 
+			return;
 		case 0x45: /* numlock pressed */
 			num_lock=~num_lock;
 			kbd_set_leds();
-			return; 
+			return;
 		case 0xC6: /* scroll lock released */
 		case 0xC5: /* num lock released */
 		case 0xBA: /* caps lock released */
-			return; /* just swallow */ 
+			return; /* just swallow */
 	}
 	if((scancode&0x80)==0x80) /* key released */
 		return;
@@ -456,7 +453,7 @@ void handle_keyboard_event(unsigned char scancode)
 		PRINTF("unkown scancode %X\n",scancode);
 		return; /* swallow unknown codes */
 	}
-	
+
 	kbd_put_queue(keycode);
 	PRINTF("%x\n",keycode);
 }
@@ -494,30 +491,29 @@ unsigned char handle_kbd_event(void)
 }
 
 
-
 /******************************************************************************
  * Lowlevel Part of keyboard section
- */  
+ */
 unsigned char kbd_read_status(void)
 {
 	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
-} 
-  
+}
+
 unsigned char kbd_read_input(void)
 {
 	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
-} 
+}
 
 void kbd_write_command(unsigned char cmd)
 {
 	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
-} 
-  
+}
+
 void kbd_write_output(unsigned char data)
 {
 	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
-} 
- 
+}
+
 int kbd_read_data(void)
 {
 	int val;
@@ -537,7 +533,7 @@ int kbd_wait_for_input(void)
 {
 	unsigned long timeout;
 	int val;
-	
+
 	timeout = KBD_TIMEOUT;
 	val=kbd_read_data();
 	while(val < 0)
@@ -602,7 +598,7 @@ char * kbd_initialize(void)
 	 * If the test is successful a x55 is placed in the input buffer.
 	 */
 	kbd_write_command_w(KBD_CCMD_SELF_TEST);
-	if (kbd_wait_for_input() != 0x55) 
+	if (kbd_wait_for_input() != 0x55)
 		return "Kbd:   failed self test";
 	/*
 	 * Perform a keyboard interface test.  This causes the controller
@@ -610,7 +606,7 @@ char * kbd_initialize(void)
 	 * test are placed in the input buffer.
 	 */
 	kbd_write_command_w(KBD_CCMD_KBD_TEST);
-	if (kbd_wait_for_input() != 0x00) 
+	if (kbd_wait_for_input() != 0x00)
 		return "Kbd:   interface failed self test";
 	/*
 	 * Enable the keyboard by allowing the keyboard clock to run.
@@ -628,7 +624,7 @@ char * kbd_initialize(void)
 	do {
 		kbd_write_output_w(KBD_CMD_RESET);
 		status = kbd_wait_for_input();
-		if (status == KBD_REPLY_ACK) 
+		if (status == KBD_REPLY_ACK)
 			break;
 		if (status != KBD_REPLY_RESEND)
 		{
@@ -660,7 +656,7 @@ char * kbd_initialize(void)
 			      | KBD_MODE_DISABLE_MOUSE
 			      | KBD_MODE_KCC);
 
-	/* ibm powerpc portables need this to use scan-code set 1 -- Cort */
+	/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
 	kbd_write_command_w(KBD_CCMD_READ_MODE);
 	if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
 		/*
@@ -692,8 +688,3 @@ void kbd_interrupt(void)
 {
 	handle_kbd_event();
 }
-
-
-
-/* eof */
-

board/MAI/AmigaOneG3SE/ps2kbd.h

@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2002
  * John W. Linville, linville@tuxdriver.com
- * 
+ *
  * Modified from code for support of MIP405 and PIP405 boards.  Previous
  * copyright follows.
  *
@@ -30,7 +30,7 @@
 
 #ifndef _KBD_H_
 #define _KBD_H_
-   
+
 extern int kbd_testc(void);
 extern int kbd_getc(void);
 extern void kbd_interrupt(void);

board/MAI/AmigaOneG3SE/serial.c

@@ -4,6 +4,8 @@
 #include "memio.h"
 #include "articiaS.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CFG_NS16550
 static uint32 ComPort1;
 
@@ -150,8 +152,6 @@ const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2;
 
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint32 clock_divisor = 115200 / gd->baudrate;
 
 	NS16550_init (Com0, clock_divisor);
@@ -239,8 +239,6 @@ void serial_puts (const char *string)
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint32 clock_divisor = 115200 / gd->baudrate;
 
 	NS16550_init (Com0, clock_divisor);

board/MAI/AmigaOneG3SE/short_types.h

@@ -2,7 +2,7 @@
  * short type names
  *
  * (C) Copyright 2002
- * Hyperion Entertainment, ThomasF@hyperion-entertainment.com 
+ * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.

board/MAI/AmigaOneG3SE/smbus.c

@@ -26,18 +26,18 @@ void sm_write_byte(uint8 writeme)
 {
     int i;
     int level;
-    
+
     out_byte(0xA539, 0x00);
 
     level = 0;
 
     for (i=0; i<8; i++)
     {
-	if ((writeme & 0x80) == (level<<7)) 
-        {
+	if ((writeme & 0x80) == (level<<7))
+	{
 	    /* Bit did not change, rewrite strobe */
 	    out_byte(0xA539, level | 0x02);
-	    out_byte(0xA539, level); 
+	    out_byte(0xA539, level);
 	}
 	else
 	{
@@ -68,7 +68,7 @@ uint8 sm_read_byte(void)
     }
 
     return retme;
-} 
+}
 
 int sm_get_ack(void)
 {
@@ -106,36 +106,36 @@ void sm_send_stop(void)
 
 int sm_read_byte_from_device(uint8 addr, uint8 reg, uint8 *storage)
 {
-    // S Addr Wr
+    /* S Addr Wr */
     sm_write_mode();
     sm_send_start();
     sm_write_byte((addr<<1));
-    
-    // [A]
+
+    /* [A] */
     sm_read_mode();
     if (sm_get_ack() == FALSE) return FALSE;
 
-    // Comm
+    /* Comm */
     sm_write_mode();
     sm_write_byte(reg);
-    
-    // [A]
+
+    /* [A] */
     sm_read_mode();
     if (sm_get_ack() == FALSE) return FALSE;
 
-    // S Addr Rd
+    /* S Addr Rd */
     sm_write_mode();
     sm_send_start();
     sm_write_byte((addr<<1)|1);
-    
-    // [A]
+
+    /* [A] */
     sm_read_mode();
     if (sm_get_ack() == FALSE) return FALSE;
 
-    // [Data]
+    /* [Data] */
     *storage = sm_read_byte();
-    
-    // NA
+
+    /* NA */
     sm_write_mode();
     sm_write_nack();
     sm_send_stop();
@@ -144,10 +144,10 @@ int sm_read_byte_from_device(uint8 addr, uint8 reg, uint8 *storage)
 }
 
 void sm_init(void)
-{  
+{
     /* Switch to PMC mode */
     pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER));
- 
+
     /* Set GPIO Base */
     pci_write_cfg_long(0, 0, 0x40, 0xa500);
 
@@ -155,12 +155,12 @@ void sm_init(void)
     pci_write_cfg_byte(0, 0, 0x44, 0x11);
 
     /* Set both GPIO 0 and 1 as output */
-    out_byte(0xA53A, 0x03); 
+    out_byte(0xA53A, 0x03);
 }
 
 
 void sm_term(void)
-{  
+{
     /* Switch to normal mode */
     pci_write_cfg_byte(0, 0, REG_GROUP, 0);
 }
@@ -173,7 +173,7 @@ int sm_get_data(uint8 *DataArray, int dimm_socket)
 #if 0
     /* Switch to PMC mode */
     pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER));
- 
+
     /* Set GPIO Base */
     pci_write_cfg_long(0, 0, 0x40, 0xa500);
 
@@ -181,7 +181,7 @@ int sm_get_data(uint8 *DataArray, int dimm_socket)
     pci_write_cfg_byte(0, 0, 0x44, 0x11);
 
     /* Set both GPIO 0 and 1 as output */
-    out_byte(0xA53A, 0x03); 
+    out_byte(0xA53A, 0x03);
 #endif
 
     sm_init();

board/MAI/AmigaOneG3SE/start.txt

@@ -1,201 +1,198 @@
-
-	/*------------------------------------------------------*/
-        /*              TERON Articia / SDRAM Init              */
-        /*------------------------------------------------------*/
-
-*       XD_CTL  = 0x81000000			(0x74)
-
-*       HBUS_ACC_CTL_0 &= 0xFFFFFDFF		(0x5c)
-                       /* host bus access ctl reg 2(5e) */
-                       /* set - CPU read from memory data one clock after data is latched */
-
-*       GLOBL_INFO_0 |= 0x00004000		(0x50)
-                      /* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */
-
-        PCI_1_SB_CONFIG_0 |= 0x00000400         (0x80d0)
-                        /* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */
-
-        MEM_RAS_CTL_0 |= 0x3f000000		(0xcc)
-		      &= 0x3fffffff
-                      /* RAS park control reg 0(cc), park access enable is set */
-		      
-        HOST_RDBUF_CTL |= 0x10000000		(0x70)
-	               &= 0x10ffffff
-                      /* host read buffer control reg, enable prefetch for CPU read from DRAM control */
-
-        HBUS_ACC_CTL_0 |= 0x0100001f		(0x5c)
-		       &= 0xf1ffffff
-                      /* host bus access control register, enable CPU address bus pipe control	*/
-                      /* two outstanding requests,  *** changed to 2 from 3				*/
-                      /* enable line merge write control for CPU write to system memory, PCI 1	*/
-                      /* and PCI 0 bus memory; enable page merge write control for write to		*/
-                      /* PCI bus 0 & bus 1 memory							*/
-
-        SRAM_CTL |= 0x00004000			(0xc8)
-		 &= 0xffbff7ff
-                      /* DRAM detail timing control register 1 (ca), bit 3 set to 0	*/
-                      /* DRAM start access latency control - wait for one clock	*/
-                      /* ff9f changed to ffbf						*/
-    
-        DIM0_TIM_CTL_0 = 0x737d737d             (0xc9)
-                      /* DRAM timing control for dimm0 & dimm1; set wait one clock	*/
-                      /* cycle for next data access 					*/
-
-        DIM2_TIM_CTL_0 = 0x737d737d             (0xca)
-                      /* DRAM timing control for dimm2 & dimm3; set wait one clock	*/
-                      /* cycle for next data access 					*/
-
-        DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB    (0x90)
-	              /* set dimm0 bank0 for 128 MB	*/
-
-        DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB    (0x94)
-                      /* set dimm0 for  bank1		*/
-
-        DIM0_TIM_CTL_0 = 0xf3bf0000             (0xc9)
-                      /* dimm0 timing control register; RAS - CAS latency - 4 clock		*/
-                      /* CAS access latency - 3 wait; pre-charge latency - 3 wait		*/
-                      /* pre-charge command period control - 5 clock; wait one clock		*/
-                      /* cycle for next data access; read to write access latency control	*/
-                      /* - 2 clock cycles							*/
-
-        DRAM_GBL_CTL_0 |= 0x00000100            (0xc0)
-		       &= 0xffff01ff
-                      /* memory global control register - support buffer sdram on bank 0	*/
-
-        DRAM_ECC_CTL_0 |= 0x00260000		(0xc4)
-		       &= 0xff26ffff
-                      /* enable ECC; enable read, modify, write control	*/
- 
-        DRAM_REF_CTL_0 = DRAM_REF_DATA          (0xb8)
-		      /* set DRAM refresh parameters *** changed to 00940100	*/
-
-        nop
-        nop
-        nop
-        nop
-        nop
-
-        DRAM_ECC_CTL_0 |= 0x20243280		(0xc4)
-                      /* turn off ecc		*/
-                      /* for SDRAM bank 0	*/
-
-        DRAM_ECC_CTL_0 |= 0x20243290            (0xc4) ?
-                      /* for SDRAM bank 1	*/
- 
-
-/* Additional Stuff...*/
-
-        GLOBL_CTRL |= 0x20000b00		(0x54)
-
-        PCI_0_SB_CONFIG |= 0x04100007		(0xd0)
-                      /* PCI 0 Side band config reg*/
-
-        0x8000083c |= 0x00080000
-                      /* Disable VGA decode on PCI Bus 1 */
-
-
-/*End Additional Stuff..*/
-
-        /*--------------------------------------------------------------*/
-        /*              TERON serial port initialization code           */
-        /*--------------------------------------------------------------*/
-
-	0x84380080 |= 0x00030000
-                     /* enable super IO configuration VIA chip Register 85	*/
-		     /* Enable super I/O config mode */
-
-        0xfe0003f0 = 0xe2
-        bl delay1
-
-        0xfe0003f1 = 0x0f
-	bl delay1
-	            /* enable com1 & com2, parallel port disabled */ 
-	
-	0xfe0003f0 = 0xe7
-        bl delay1
-	            /* let's make com1 base as 0x3f8 */
-        
-        0xfe0003f1 = 0xfe
-        bl delay1
-
-        0xfe0003f0 = 0xe8
-        bl delay1           
-		    /* let's make com2 base as 0x2f8 */
-
-	0xfe0003f1 = 0xbe
-
-	0x84380080 &= 0xfffdffff
-                    /* closing super IO configuration VIA chip Register 85   */
-     
-
-/* -------------------------------*/
-
-        0xfe0003fb = 0x83
-	bl delay1
-                   /*latch enable word length -8 bit */         /* set mslab bit	*/
-        0xfe0003f8 = 0x0c
-	bl delay1
-                   /* set baud rate lsb for 9600 baud	*/
-        0xfe0003f9 = 0x0
-	bl delay1
-                   /* set baud rate msb for 9600 baud	*/
-        0xfe0003fb  = 0x03
-	bl delay1
-                      /* reset mslab	*/
-
-	/*--------------------------------------------------------------*/
-        /*              END TERON Serial Port Initialization Code       */
-        /*--------------------------------------------------------------*/
-
-   
-
-        /*--------------------------------------------------------------*/
-        /*      END TERON Articia / SDRAM Initialization code           */
-        /*--------------------------------------------------------------*/
-
-Proposed from Documentation:
-
-write dmem 0xfec00cf8 0x50000080
-write dmem 0xfee00cfc 0xc0305411
-
-      Writes to index 0x50-0x53. 
-      0x50: Global Information Register 0
-	    0xC0 = Little Endian CPU, Sequential order Burst
-      0x51: Global Information Register 1
-	    Read only, 0x30 = Provides PowerPC and X86 support
-      0x52: Global Information Register 2
-	    0x05 = 64/128 bit CPU bus support
-      0x53: Global Information Register 3
-	    0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted
-
-write dmem 0xfec00cf8 0x5c000080
-write dmem 0xfee00cfc 0xb300011F
-
-write dmem 0xfec00cf8 0xc8000080
-write dmem 0xfee00cfc 0x0020f100
-
-write dmem 0xfec00cf8 0x90000080
-write dmem 0xfee00cfc 0x007fe700
-
-write dmem 0xfec00cf8 0x9400080
-write dmem 0xfee00cfc 0x007fe700
-
-write dmem 0xfec00cf8 0xb0000080
-write dmem 0xfee00cfc 0x737d737d
-
-write dmem 0xfec00cf8 0xb4000080
-write dmem 0xfee00cfc 0x737d737d
-
-write dmem 0xfec00cf8 0xc0000080
-write dmem 0xfee00cfc 0x40005500
-
-write dmem 0xfec00cf8 0xb8000080
-write dmem 0xfee00cfc 0x00940100
-
-write dmem 0xfec00cf8 0xc4000080
-write dmem 0xfee00cfc 0x00003280
-
-write dmem 0xfec00cf8 0xc4000080
-write dmem 0xfee00cfc 0x00003290
-
-
+
+	/*------------------------------------------------------*/
+	/*              TERON Articia / SDRAM Init              */
+	/*------------------------------------------------------*/
+
+*       XD_CTL  = 0x81000000			(0x74)
+
+*       HBUS_ACC_CTL_0 &= 0xFFFFFDFF		(0x5c)
+		       /* host bus access ctl reg 2(5e) */
+		       /* set - CPU read from memory data one clock after data is latched */
+
+*       GLOBL_INFO_0 |= 0x00004000		(0x50)
+		      /* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */
+
+	PCI_1_SB_CONFIG_0 |= 0x00000400         (0x80d0)
+			/* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */
+
+	MEM_RAS_CTL_0 |= 0x3f000000		(0xcc)
+		      &= 0x3fffffff
+		      /* RAS park control reg 0(cc), park access enable is set */
+
+	HOST_RDBUF_CTL |= 0x10000000		(0x70)
+		       &= 0x10ffffff
+		      /* host read buffer control reg, enable prefetch for CPU read from DRAM control */
+
+	HBUS_ACC_CTL_0 |= 0x0100001f		(0x5c)
+		       &= 0xf1ffffff
+		      /* host bus access control register, enable CPU address bus pipe control	*/
+		      /* two outstanding requests,  *** changed to 2 from 3				*/
+		      /* enable line merge write control for CPU write to system memory, PCI 1	*/
+		      /* and PCI 0 bus memory; enable page merge write control for write to		*/
+		      /* PCI bus 0 & bus 1 memory							*/
+
+	SRAM_CTL |= 0x00004000			(0xc8)
+		 &= 0xffbff7ff
+		      /* DRAM detail timing control register 1 (ca), bit 3 set to 0	*/
+		      /* DRAM start access latency control - wait for one clock	*/
+		      /* ff9f changed to ffbf						*/
+
+	DIM0_TIM_CTL_0 = 0x737d737d             (0xc9)
+		      /* DRAM timing control for dimm0 & dimm1; set wait one clock	*/
+		      /* cycle for next data access 					*/
+
+	DIM2_TIM_CTL_0 = 0x737d737d             (0xca)
+		      /* DRAM timing control for dimm2 & dimm3; set wait one clock	*/
+		      /* cycle for next data access 					*/
+
+	DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB    (0x90)
+		      /* set dimm0 bank0 for 128 MB	*/
+
+	DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB    (0x94)
+		      /* set dimm0 for  bank1		*/
+
+	DIM0_TIM_CTL_0 = 0xf3bf0000             (0xc9)
+		      /* dimm0 timing control register; RAS - CAS latency - 4 clock		*/
+		      /* CAS access latency - 3 wait; pre-charge latency - 3 wait		*/
+		      /* pre-charge command period control - 5 clock; wait one clock		*/
+		      /* cycle for next data access; read to write access latency control	*/
+		      /* - 2 clock cycles							*/
+
+	DRAM_GBL_CTL_0 |= 0x00000100            (0xc0)
+		       &= 0xffff01ff
+		      /* memory global control register - support buffer sdram on bank 0	*/
+
+	DRAM_ECC_CTL_0 |= 0x00260000		(0xc4)
+		       &= 0xff26ffff
+		      /* enable ECC; enable read, modify, write control	*/
+
+	DRAM_REF_CTL_0 = DRAM_REF_DATA          (0xb8)
+		      /* set DRAM refresh parameters *** changed to 00940100	*/
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	DRAM_ECC_CTL_0 |= 0x20243280		(0xc4)
+		      /* turn off ecc		*/
+		      /* for SDRAM bank 0	*/
+
+	DRAM_ECC_CTL_0 |= 0x20243290            (0xc4) ?
+		      /* for SDRAM bank 1	*/
+
+
+/* Additional Stuff...*/
+
+	GLOBL_CTRL |= 0x20000b00		(0x54)
+
+	PCI_0_SB_CONFIG |= 0x04100007		(0xd0)
+		      /* PCI 0 Side band config reg*/
+
+	0x8000083c |= 0x00080000
+		      /* Disable VGA decode on PCI Bus 1 */
+
+
+/*End Additional Stuff..*/
+
+	/*--------------------------------------------------------------*/
+	/*              TERON serial port initialization code           */
+	/*--------------------------------------------------------------*/
+
+	0x84380080 |= 0x00030000
+		     /* enable super IO configuration VIA chip Register 85	*/
+		     /* Enable super I/O config mode */
+
+	0xfe0003f0 = 0xe2
+	bl delay1
+
+	0xfe0003f1 = 0x0f
+	bl delay1
+		    /* enable com1 & com2, parallel port disabled */
+
+	0xfe0003f0 = 0xe7
+	bl delay1
+		    /* let's make com1 base as 0x3f8 */
+
+	0xfe0003f1 = 0xfe
+	bl delay1
+
+	0xfe0003f0 = 0xe8
+	bl delay1
+		    /* let's make com2 base as 0x2f8 */
+
+	0xfe0003f1 = 0xbe
+
+	0x84380080 &= 0xfffdffff
+		    /* closing super IO configuration VIA chip Register 85   */
+
+
+/* -------------------------------*/
+
+	0xfe0003fb = 0x83
+	bl delay1
+		   /*latch enable word length -8 bit */         /* set mslab bit	*/
+	0xfe0003f8 = 0x0c
+	bl delay1
+		   /* set baud rate lsb for 9600 baud	*/
+	0xfe0003f9 = 0x0
+	bl delay1
+		   /* set baud rate msb for 9600 baud	*/
+	0xfe0003fb  = 0x03
+	bl delay1
+		      /* reset mslab	*/
+
+	/*--------------------------------------------------------------*/
+	/*              END TERON Serial Port Initialization Code       */
+	/*--------------------------------------------------------------*/
+
+
+	/*--------------------------------------------------------------*/
+	/*      END TERON Articia / SDRAM Initialization code           */
+	/*--------------------------------------------------------------*/
+
+Proposed from Documentation:
+
+write dmem 0xfec00cf8 0x50000080
+write dmem 0xfee00cfc 0xc0305411
+
+      Writes to index 0x50-0x53.
+      0x50: Global Information Register 0
+	    0xC0 = Little Endian CPU, Sequential order Burst
+      0x51: Global Information Register 1
+	    Read only, 0x30 = Provides PowerPC and X86 support
+      0x52: Global Information Register 2
+	    0x05 = 64/128 bit CPU bus support
+      0x53: Global Information Register 3
+	    0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted
+
+write dmem 0xfec00cf8 0x5c000080
+write dmem 0xfee00cfc 0xb300011F
+
+write dmem 0xfec00cf8 0xc8000080
+write dmem 0xfee00cfc 0x0020f100
+
+write dmem 0xfec00cf8 0x90000080
+write dmem 0xfee00cfc 0x007fe700
+
+write dmem 0xfec00cf8 0x9400080
+write dmem 0xfee00cfc 0x007fe700
+
+write dmem 0xfec00cf8 0xb0000080
+write dmem 0xfee00cfc 0x737d737d
+
+write dmem 0xfec00cf8 0xb4000080
+write dmem 0xfee00cfc 0x737d737d
+
+write dmem 0xfec00cf8 0xc0000080
+write dmem 0xfee00cfc 0x40005500
+
+write dmem 0xfec00cf8 0xb8000080
+write dmem 0xfee00cfc 0x00940100
+
+write dmem 0xfec00cf8 0xc4000080
+write dmem 0xfee00cfc 0x00003280
+
+write dmem 0xfec00cf8 0xc4000080
+write dmem 0xfee00cfc 0x00003290

board/MAI/AmigaOneG3SE/u-boot.lds

@@ -63,7 +63,7 @@ SECTIONS
     cpu/74xx_7xx/start.o	(.text)
 /* store the environment in a seperate sector in the boot flash */
 /*    . = env_offset; */
-    common/environment.o(.text) 
+    common/environment.o(.text)
 
     *(.text)
     *(.fixup)
@@ -75,6 +75,8 @@ SECTIONS
   {
     *(.rodata)
     *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
   }
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
@@ -86,7 +88,7 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    *(.got) 
+    *(.got)
     _GOT2_TABLE_ = .;
     *(.got2)
     _FIXUP_TABLE_ = .;
@@ -107,6 +109,13 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
   __start___ex_table = .;
   __ex_table : { *(__ex_table) }
   __stop___ex_table = .;

board/MAI/AmigaOneG3SE/usb_uhci.c

@@ -83,7 +83,7 @@
 #define USB_MAX_TEMP_INT_TD  32   /* number of temporary TDs for Interrupt transfers */
 
 
-//#define USB_UHCI_DEBUG
+/*#define USB_UHCI_DEBUG */
 
 #ifdef	USB_UHCI_DEBUG
 #define	USB_UHCI_PRINTF(fmt,args...)	printf (fmt ,##args)
@@ -599,7 +599,7 @@ int usb_lowlevel_init(void)
 		printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID);
 		return -1;
 	}
-	
+
 #if 1
 	s = getenv("usb_irq");
 	if (s)
@@ -1115,7 +1115,6 @@ static void usb_display_wValue(unsigned short wValue,unsigned short wIndex)
 #endif
 
 
-
 #ifdef	USB_UHCI_DEBUG
 
 static int usb_display_td(uhci_td_t *td)

board/MAI/AmigaOneG3SE/usb_uhci.h

@@ -190,5 +190,3 @@ struct virt_root_hub {
 
 
 #endif /* _USB_UHCI_H_ */
-
-

board/MAI/AmigaOneG3SE/via686.c

@@ -28,6 +28,8 @@
 #include "via686.h"
 #include "i8259.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef VIA_DEBUG
 
 #ifdef  VIA_DEBUG
@@ -211,48 +213,46 @@ void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_c
 
 __asm         ("    .globl via_calibrate_time_base \n"
 	       "via_calibrate_time_base: 	   \n"
-               "   lis     9, 0xfe00		   \n"
-               "   li      0, 0x00		   \n"
+	       "   lis     9, 0xfe00		   \n"
+	       "   li      0, 0x00		   \n"
 	       "   mttbu   0			   \n"
 	       "   mttbl   0			   \n"
 	       "ctb_loop:			   \n"
-               "   lbz     0, 0x61(9)		   \n"
-               "   eieio			   \n"
-               "   andi.   0, 0, 0x20		   \n"
-               "   beq     ctb_loop		   \n"
-               "ctb_done:			   \n"
-               "   mftb    3			   \n"
-               "   blr");
+	       "   lbz     0, 0x61(9)		   \n"
+	       "   eieio			   \n"
+	       "   andi.   0, 0, 0x20		   \n"
+	       "   beq     ctb_loop		   \n"
+	       "ctb_done:			   \n"
+	       "   mftb    3			   \n"
+	       "   blr");
 
 extern unsigned long via_calibrate_time_base(void);
 
-void via_calibrate_bus_freq(void)
+void via_calibrate_bus_freq (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long tb;
 
-    unsigned long tb;
+	/* This is 20 microseconds */
+#define CALIBRATE_TIME 28636
 
-    /* This is 20 microseconds */
-    #define CALIBRATE_TIME 28636
+	/* Enable the timer (and disable speaker) */
+	unsigned char c;
 
+	c = in_byte (0x61);
+	out_byte (0x61, ((c & ~0x02) | 0x01));
 
-    /* Enable the timer (and disable speaker) */
-    unsigned char c;
-    c = in_byte(0x61);
-    out_byte(0x61, ((c & ~0x02) | 0x01));
+	/* Set timer 2 to low/high writing */
+	out_byte (0x43, 0xb0);
+	out_byte (0x42, CALIBRATE_TIME & 0xff);
+	out_byte (0x42, CALIBRATE_TIME >> 8);
 
-    /* Set timer 2 to low/high writing */
-    out_byte(0x43, 0xb0);
-    out_byte(0x42, CALIBRATE_TIME & 0xff);
-    out_byte(0x42, CALIBRATE_TIME >>8);
+	/* Read the time base */
+	tb = via_calibrate_time_base ();
 
-    /* Read the time base */
-    tb = via_calibrate_time_base();
-
-    if (tb >= 700000)
-	gd->bus_clk = 133333333;
-    else
-	gd->bus_clk = 100000000;
+	if (tb >= 700000)
+		gd->bus_clk = 133333333;
+	else
+		gd->bus_clk = 100000000;
 
 }
 

board/MAI/AmigaOneG3SE/video.c

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com 
+ * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,6 +26,8 @@
 #include "memio.h"
 #include <part.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 unsigned char *cursor_position;
 unsigned int cursor_row;
 unsigned int cursor_col;
@@ -100,7 +102,7 @@ int drv_video_init(void)
     video_inited = 1;
     video_init();
     memset (&vgadev, 0, sizeof(vgadev));
-    
+
     strcpy(vgadev.name, VIDEO_NAME);
     vgadev.flags =  DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
     vgadev.putc = video_putc;
@@ -108,7 +110,7 @@ int drv_video_init(void)
     vgadev.getc = NULL;
     vgadev.tstc = NULL;
     vgadev.start = video_start;
-    
+
     error = device_register (&vgadev);
 
     if (error == 0)
@@ -129,11 +131,11 @@ int drv_video_init(void)
 
 int video_init(void)
 {
-    cursor_position = VIDEO_BASE; // Color text display base
+    cursor_position = VIDEO_BASE; /* Color text display base */
     cursor_row = 0;
     cursor_col = 0;
-    current_attr = video_get_attr(); // Currently selected value for attribute.
-//    video_test();
+    current_attr = video_get_attr(); /* Currently selected value for attribute. */
+/*    video_test(); */
     video_set_color(current_attr);
 
     return 0;
@@ -283,7 +285,7 @@ void video_bios_print_string(char *s, int x, int y, int attr, int count)
 
 void video_draw_box(int style, int attr, char *title, int separate, int x, int y, int w, int h)
 {
-    unsigned char *fb, *fb2; 
+    unsigned char *fb, *fb2;
     unsigned char *st = (style == SINGLE_BOX)?video_single_box : video_double_box;
     unsigned char *ti = (style == SINGLE_BOX)?video_single_title : video_double_title;
     int i;
@@ -324,11 +326,11 @@ void video_draw_box(int style, int attr, char *title, int separate, int x, int y
 	*fb = st[3];
 	*(fb+1) = attr; fb += 2*VIDEO_COLS;
 
-	*fb2 = st[4]; 
+	*fb2 = st[4];
 	*(fb2+1) = attr; fb2 += 2*VIDEO_COLS;
     }
-    
-    // Draw title
+
+    /* Draw title */
     if (title)
     {
 	if (separate == 0)
@@ -370,7 +372,7 @@ void video_draw_box(int style, int attr, char *title, int separate, int x, int y
 		fb += 2;
 	    }
 	    fb = video_addr(x+2, y+1);
-	    
+
 	    while (*title)
 	    {
 		*fb = *title;
@@ -414,7 +416,7 @@ void video_save_rect(int x, int y, int w, int h, void *save_area, int clearchar,
 }
 
 void video_restore_rect(int x, int y, int w, int h, void *save_area)
-{   
+{
     unsigned char *save = (unsigned char *)save_area;
     unsigned char *fb = video_addr(x,y);
     int i,j;
@@ -480,11 +482,10 @@ extern char version_string[];
 void video_banner(void)
 {
     block_dev_desc_t *ide;
-    DECLARE_GLOBAL_DATA_PTR;
     int i;
     char *s;
     int maxdev;
-    
+
 
     if (video_inited == 0) return;
 #ifdef EASTEREGG

board/MAI/bios_emulator/bios.c

@@ -130,14 +130,14 @@ static void X86API int1A(int intno)
 
     switch(M.x86.R_AX)
     {
-    case 0xB101: // PCI Bios Present?
+    case 0xB101: /* PCI Bios Present? */
 	M.x86.R_AL  = 0x00;
 	M.x86.R_EDX = 0x20494350;
 	M.x86.R_BX  = 0x0210;
 	M.x86.R_CL  = 3;
 	CLEAR_FLAG(F_CF);
 	break;
-    case 0xB102: // Find device
+    case 0xB102: /* Find device */
 	device = mypci_find_device(M.x86.R_DX, M.x86.R_CX, M.x86.R_SI);
 	if (device != -1)
 	{
@@ -151,52 +151,52 @@ static void X86API int1A(int intno)
 	}
 	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
 	break;
-    case 0xB103: // Find PCI class code
+    case 0xB103: /* Find PCI class code */
 	M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND;
-	//printf("Find by class not yet implmented");
+	/*printf("Find by class not yet implmented"); */
 	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
 	break;
-    case 0xB108: // read config byte
+    case 0xB108: /* read config byte */
 	M.x86.R_CL = mypci_read_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI);
 	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
 	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
-	//printf("read_config_byte %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI,
-	//	    M.x86.R_CL);
+	/*printf("read_config_byte %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*	    M.x86.R_CL); */
 	break;
-    case 0xB109: // read config word
+    case 0xB109: /* read config word */
 	M.x86.R_CX = mypci_read_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI);
 	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
 	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
-	//printf("read_config_word %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI,
-	//	    M.x86.R_CX);
+	/*printf("read_config_word %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*	    M.x86.R_CX); */
 	break;
-    case 0xB10A: // read config dword
+    case 0xB10A: /* read config dword */
 	M.x86.R_ECX = mypci_read_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI);
 	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
 	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
-	//printf("read_config_long %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI,
-	//    M.x86.R_ECX);
+	/*printf("read_config_long %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*    M.x86.R_ECX); */
 	break;
-    case 0xB10B: // write config byte
+    case 0xB10B: /* write config byte */
 	mypci_write_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CL);
 	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
 	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
-	//printf("write_config_byte %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI,
-	//    M.x86.R_CL);
+	/*printf("write_config_byte %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*    M.x86.R_CL); */
 	break;
-    case 0xB10C: // write config word
+    case 0xB10C: /* write config word */
 	mypci_write_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CX);
 	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
 	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
-	//printf("write_config_word %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI,
-	//	    M.x86.R_CX);
+	/*printf("write_config_word %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*	    M.x86.R_CX); */
 	break;
-    case 0xB10D: // write config dword
+    case 0xB10D: /* write config dword */
 	mypci_write_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_ECX);
 	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
 	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
-	//printf("write_config_long %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI,
-	//	    M.x86.R_ECX);
+	/*printf("write_config_long %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*	    M.x86.R_ECX); */
 	break;
     default:
 	PRINTF("BIOS int %xh: Unknown function AX=%04xh\n", intno, M.x86.R_AX);
@@ -208,7 +208,7 @@ void bios_init(void)
 {
     int i;
     X86EMU_intrFuncs bios_intr_tab[256];
-    
+
     for (i=0; i<256; i++)
     {
 	write_long_little(M.mem_base+i*4, BIOS_SEG<<16);
@@ -221,7 +221,7 @@ void bios_init(void)
     bios_intr_tab[0x15] = int15;
 
     bios_intr_tab[0x6D] = int42;
-    
+
     X86EMU_setupIntrFuncs(bios_intr_tab);
     video_init();
 }
@@ -252,14 +252,14 @@ unsigned char setup_bw[] =
 
 unsigned char * setup_modes[] =
 {
-    setup_40x25,     // mode 0: 40x25 bw text
-    setup_40x25,     // mode 1: 40x25 col text
-    setup_80x25,     // mode 2: 80x25 bw text
-    setup_80x25,     // mode 3: 80x25 col text
-    setup_graphics,  // mode 4: 320x200 col graphics
-    setup_graphics,  // mode 5: 320x200 bw graphics
-    setup_graphics,  // mode 6: 640x200 bw graphics
-    setup_bw         // mode 7: 80x25 mono text
+    setup_40x25,     /* mode 0: 40x25 bw text */
+    setup_40x25,     /* mode 1: 40x25 col text */
+    setup_80x25,     /* mode 2: 80x25 bw text */
+    setup_80x25,     /* mode 3: 80x25 col text */
+    setup_graphics,  /* mode 4: 320x200 col graphics */
+    setup_graphics,  /* mode 5: 320x200 bw graphics */
+    setup_graphics,  /* mode 6: 640x200 bw graphics */
+    setup_bw         /* mode 7: 80x25 mono text */
 };
 
 unsigned int setup_cols[] =
@@ -280,13 +280,13 @@ unsigned int setup_bufsize[] =
 void bios_set_mode(int mode)
 {
     int i;
-    unsigned char mode_set = setup_modesets[mode]; // Control register value
-    unsigned char *setup_regs = setup_modes[mode]; // Register 3D4 Array
+    unsigned char mode_set = setup_modesets[mode]; /* Control register value */
+    unsigned char *setup_regs = setup_modes[mode]; /* Register 3D4 Array */
 
-    // Switch video off
+    /* Switch video off */
     out_byte(0x3D8, mode_set & 0x37);
 
-    // Set up parameters at 3D4h
+    /* Set up parameters at 3D4h */
     for (i=0; i<16; i++)
     {
 	out_byte(0x3D4, (unsigned char)i);
@@ -294,10 +294,10 @@ void bios_set_mode(int mode)
 	setup_regs++;
     }
 
-    // Enable video
+    /* Enable video */
     out_byte(0x3D8, mode_set);
 
-    // Set overscan
+    /* Set overscan */
     if (mode == 6) out_byte(0x3D9, 0x3F);
     else           out_byte(0x3D9, 0x30);
 }

board/MAI/bios_emulator/glue.c

@@ -401,7 +401,7 @@ int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size)
 {
     int i = 0;
     unsigned char *rom = (unsigned char *)rom_address;
-    /* if (*rom != 0x55 || *(rom+1) != 0xAA) return 0; // No bios rom this is, yes. */
+    /* if (*rom != 0x55 || *(rom+1) != 0xAA) return 0; /* No bios rom this is, yes. */ */
 
     for (;;)
     {
@@ -479,7 +479,6 @@ void show_bat_mapping(void)
 }
 
 
-
 void remove_init_data(void)
 {
     char *s;
@@ -497,19 +496,19 @@ void remove_init_data(void)
     }
     else if (s)
     {
-        if (strcmp(s, "dcache")==0)
-        {
-            dcache_enable();
-        }
-        else if (strcmp(s, "icache") == 0)
-        {
-            icache_enable();
-        }
-        else if (strcmp(s, "on")== 0 || strcmp(s, "both") == 0)
-        {
-            dcache_enable();
-            icache_enable();
-        }
+	if (strcmp(s, "dcache")==0)
+	{
+	    dcache_enable();
+	}
+	else if (strcmp(s, "icache") == 0)
+	{
+	    icache_enable();
+	}
+	else if (strcmp(s, "on")== 0 || strcmp(s, "both") == 0)
+	{
+	    dcache_enable();
+	    icache_enable();
+	}
     }
 
     /*   show_bat_mapping();*/