Add missing board/dave/B2/B2.c file.

Add support for NFS for file download

* Minor code cleanup

CHANGELOG

@@ -1,7 +1,853 @@
 ======================================================================
-Changes for U-Boot 0.4.7:
+Changes for U-Boot 1.0.2:
 ======================================================================
 
+* Patch by Masami Komiy, 22 Feb 2004:
+  Add support for NFS for file download
+
+* Patch by Andrea Scian, 17 Feb 2004:
+  Add support for S3C44B0 processor and DAVE B2 board
+
+* Patch by Steven Scholz, 20 Feb 2004:
+  - Add support for MII commands on AT91RM9200 boards
+  - some cleanup in AT91RM9200 ethernet code
+
+* Patch by Peter Ryser, 20 Feb 2004:
+  Add support for the Xilinx ML300 platform
+
+* Patch by Stephan Linz, 17 Feb 2004:
+  Fix watchdog support for NIOS
+
+* Patch by Josh Fryman, 16 Feb 2004:
+  Fix byte-swapping for cfi_flash.c for different bus widths
+
+* Patch by Jon Diekema, 14 Jeb 2004:
+  Remove duplicate "FPGA Support" notes from the README file
+
+* Patches by Reinhard Meyer, 14 Feb 2004:
+  - update board/emk tree; use common flash driver
+  - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c
+    [adapted for other PPC CPUs -- wd]
+  - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c
+
+* Patch by Jon Diekema, 13 Feb 2004:
+  Call show_boot_progress() whenever POST "FAILED" is printed.
+
+* Patch by Nishant Kamat, 13 Feb 2004:
+  Add support for TI OMAP1610 H2 Board
+  Fixes for cpu/arm926ejs/interrupt.c
+	(based on Richard Woodruff's patch for arm925, 16 Oct 03)
+  Fix for a timer bug in OMAP1610 Innovator
+  Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2
+
+* Patches by Stephan Linz, 12 Feb 2004:
+  - add support for NIOS timer with variable period preload counter value
+  - prepare POST framework support for NIOS targets
+
+* Patch by Denis Peter, 11 Feb 2004:
+  add POST support for the MIP405 board
+
+* Patch by Laurent Mohin, 10 Feb 2004:
+  Fix buffer overflow in common/usb.c
+
+* Patch by Tolunay Orkun, 10 Feb 2004:
+  Add support for Cogent CSB272 board
+
+* Patch by Thomas Elste, 10 Feb 2004:
+  Add support for NET+50 CPU and ModNET50 board
+
+* Patch by Sam Song, 10 Feb 2004:
+  Fix typos in cfi_flash.c
+
+* Patch by Leon Kukovec, 10 Feb 2004
+  Fixed long dir entry slot id calculation in get_vfatname
+
+* Patch by Robin Gilks, 10 Feb 2004:
+  add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==,
+  !=, <>, <, >, <=, >=)
+
+* Fix problem with side effects in macros in include/usb.h
+
+* Patch by David Benson, 13 Nov 2003:
+  bug 841358 - fix TFTP download size limit
+
+* Fixing bug 850768:
+  improper flush_cache() in load_serial()
+
+* Fixing bug 834943:
+  MPC8540 - missing volatile declarations
+
+* Patch by Stephen Williams, 09 Feb 2004:
+  Add support for Xilinx SystemACE chip:
+  - New files common/cmd_ace.c and include/systemace.h
+  - Hook systemace support into cmd_fat and the partition manager
+
+* Patch by Travis Sawyer, 09 Feb 2004:
+  Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux
+
+* Patch by Travis Sawyer, 09 Feb 2004:
+  o 440GX:
+    - Fix PCI Indirect access for type 1 config cycles with ppc440.
+    - Add phymode for 440 enet
+    - fix pci pre init
+  o XPedite1K:
+    - Change board_pre_init to board_early_init_f
+    - Add user flash to bus controller setup
+    - Fix pci pre init
+    - Fix is_pci_host to check GPIO for monarch bit
+    - Force xpedite1k to pci conventional mode (via #define option)
+
+* Patch by Brad Kemp, 4 Feb 2004:
+  - handle the machine check that is generated during the PCI scans
+    on 82xx processors.
+  - define the registers used in the IMMR by the PCI subsystem.
+
+* Patch by Pierre Aubert, 03 Feb 2004:
+  cpu/mpc5xxx/start.S: copy MBAR into SPR311
+
+* Patch by Jeff Angielski, 03 Feb 2004:
+  Fix copy & paste error in cpu/mpc8260/pci.c
+
+* Patch by Reinhard Meyer, 24 Jan 2004:
+  Fix typo in cpu/mpc5xxx/pci_mpc5200.c
+
+* Add Auto-MDIX support for INCA-IP
+
+* Some code cleanup
+
+* Patch by Josef Baumgartner, 10 Feb 2004:
+  Fixes for Coldfire port
+
+* Patch by Brad Kemp, 11 Feb 2004:
+  Fix CFI flash driver problems
+
+* Make sure to use a bus clock divider of 2 only when running TQM8xxM
+  modules at CPU clock frequencies above 66 MHz.
+
+* Optimize flash programming speed for LWMON (by another 100% :-)
+
+* Patch by Jian Zhang, 3 Feb 2004:
+  - Changed the incorrect FAT12BUFSIZE
+  - data_begin in fsdata can be negative. Changed it to be short.
+
+* Patches by Stephan Linz, 30 Jan 2004:
+  1: - board/altera/common/flash.c:flash_erase():
+       o allow interrupts befor get_timer() call
+       o check-up each erased sector and avoid unexpected timeouts
+     - board/altera/dk1c20/dk1s10.c:board_early_init_f():
+       o enclose sevenseg_set() in cpp condition
+     - remove the ASMI configuration for DK1S10_standard_32 (never present)
+     - fix some typed in mistakes in the NIOS documentation
+  2: - split DK1C20 configuration into several header files:
+       o two new files for each NIOS CPU description
+       o U-Boot related part is remaining in DK1C20.h
+  3: - split DK1S10 configuration into several header files:
+       o two new files for each NIOS CPU description
+       o U-Boot related part is remaining in DK1S10.h
+  4: - Add support for the Microtronix Linux Development Kit
+       NIOS CPU configuration at the Altera Nios Development Kit,
+       Stratix Edition (DK-1S10)
+  5: - Add documentation for the Altera Nios Development Kit,
+       Stratix Edition (DK-1S10)
+  6: - Add support for the Nios Serial Peripharel Interface (SPI)
+       (master only)
+  7: - Add support for the common U-Boot SPI framework at
+       RTC driver DS1306
+
+* Patch by Rahul Shanbhag, 28 Jan 2004:
+  Fix flash protection/locking handling for OMAP1610 innovator board.
+
+* Patch by Rolf Peukert, 28 Jan 2004:
+  fix flash write problems on CSB226 board (write with 32 bit bus width)
+
+* Patches by Mark Jonas, 16 Jan 2004:
+  - fix rounding error when calculating baudrates for MPC5200 PSCs
+  - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same
+    time which is not supported
+
+* Patch by Yuli Barcohen, 26 Jan 2004:
+  Allow bzip2 compression for small memory footprint boards
+
+* Patch by Brad Kemp, 21 Jan 2004:
+  Add support for CFI flash driver for both the Intel and the AMD
+  command sets.
+
+* Patch by Travis Sawyer, 20 Jan 2004:
+  Fix pci bridge auto enumeration of sibling p2p bridges.
+
+* Patch by Tolunay Orkun, 12 Jan 2004:
+  Add some delays as needed for Intel LXT971A PHY support
+
+* Patches by Stephan Linz, 09 Jan 2004:
+  - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c
+  - make DK1C20 board configuration related to ASMI conform to
+    documentation
+
+* Patch by Anders Larsen, 09 Jan 2004:
+
+  ARM memory layout fixes: the abort-stack is now set up in the
+  correct RAM area, and the BSS is zeroed out as it should be.
+
+  Furthermore, the magic variables 'armboot_end' and 'armboot_end_data'
+  of the linker scripts are replaced by '__bss_start' and '_end',
+  resp., which is a further step to eliminate unnecessary differences
+  between the implementation of the CPU architectures.
+
+* Patch by liang a lei, 9 Jan 2004:
+  Fix Intel 28F128J3 ID in include/flash.h
+
+* Patch by Masami Komiya, 09 Jan 2004:
+  add support for TB0229 board (NEC VR4131 MIPS processor)
+
+* Patch by Leon Kukovec, 12 Dec 2003:
+  changed extern __inline__ into static __inline__ in
+  include/linux/byteorder/swab.h
+
+* Patch by Travis Sawyer, 30 Dec 2003:
+  Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
+  select MDI port based on enabled EMAC device.
+  Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX
+  base PrPMC board.
+
+* Patch by Wolter Kamphuis, 15 Dec 2003:
+  made CONFIG_SILENT_CONSOLE usable on all architectures
+
+* Disable date command on TQM866M - there is no RTC on MPC866
+
+* Fix variable CPU clock for MPC859/866 systems for low CPU clocks
+
+* Implement adaptive SDRAM timing configuration based on actual CPU
+  clock frequency for INCA-IP; fix problem with board hanging when
+  switching from 150MHz to 100MHz
+
+* Add PCMCIA CS support for BMS2003 board
+
+* Add variable CPU clock for MPC859/866 systems (so far only TQM866M):
+  see doc/README.MPC866 for details;
+  implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866;
+  calculate CPU clock frequency from PLL register values.
+
+* Add support for 128 MB RAM on TQM8xxL/M modules
+
+* Fix PS/2 keyboard problem caused by statically initialized variable
+  pointing to a location in flash
+
+* Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130.
+
+* The PS/2 mux on the BMS2003 board needs 450 ms after power on
+  before we can access it; add delay in case we are faster (with no
+  CF card inserted)
+
+* Cleanup of some init functions
+
+* Make sure SCC Ethernet is always stopped by the time we boot Linux
+  to avoid Linux crashes by early packets coming in.
+
+* Accelerate flash accesses on LWMON board by using buffered writes
+
+* Fix typo in Makefile;
+  fix problem with PARTNUM detection
+
+* Patch by Reinhard Meyer, 09 Jan 2004:
+  - add RTC support for MPC5200 based boards (requires RTC_XTAL)
+
+* Add support for IDE LED on BMS2003 board
+  (exclusive with status LED!)
+
+* Add support for PS/2 keyboard (used with PS/2 multiplexor on
+  BMS2003 board)
+
+* Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004:
+  Add common files for "emk" boards
+
+* Add a common get_ram_size() function and modify the the
+  board-specific files to invoke that common implementation.
+
+======================================================================
+Changes for U-Boot 1.0.1:
+======================================================================
+
+* Set default clock for INCA-IP to 150 MHz
+
+* Make BMS2003 use a separate config file to avoid #ifdef mess;
+  add I2C support; add support for DS1337 RTC
+
+* Add CompactFlash support  for BMS2003 board
+
+* Add support for status LED on BMS2003 board
+
+* Patch by Scott McNutt, 02 Jan 2004:
+  Add support for the Nios Active Serial Memory Interface (ASMI)
+  on Cyclone devices
+
+* Patch by Andrea Marson, 16 Dec 2003:
+  Add support for the PPChameleon ME and HI modules
+
+* Patch by Yuli Barcohen, 22 Dec 2003:
+  Add support for Motorola DUET ADS board (MPC87x/88x)
+
+* Patch by Robert Schwebel, 15 Dec 2003:
+  add support for cramfs (uses JFFS2 command interface)
+
+* Patches by Stephan Linz, 11 Dec 2003:
+  - more documentation for NIOS port
+  - new struct nios_pio_t, struct nios_spi_t
+  - Reconfiguration for NIOS Development Kit DK1C20:
+    o move board related code from board/dk1c20
+      to board/altera/dk1c20
+    o create a new common source path board/altera/common
+      and move generic flash access stuff into it
+    o change/expand configuration file DK1C20.h
+  - Add support for NIOS Development Kit DK1S10
+  - Add status LED support for NIOS systems
+  - Add dual 7-segment LED support for Altera NIOS DevKits
+
+* Patch by Ronen Shitrit, 10 Dec 2003:
+  Add support for the Marvell DB64360 / DB64460 development boards
+
+* Patch by Detlev Zundel, 10 Dec 2003:
+  fix dependency problem in examples/Makefile
+
+* Patch by Denis Peter, 8 Dec 2003
+  - add support for the PATI board (MPC555)
+  - add SPI support for the MPC5xx
+
+* Patch by Anders Larsen, 08 Dec 2003:
+  add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG
+  to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target;
+  cleanup some redundand #defines
+
+* Patch by Andr<64> Schwarz, 8 Dec 2003:
+  fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
+  - TX and RX deskriptors must be quad-word aligned
+  - does not work with only one TX deskriptor
+  - standard reset method does not work
+
+* Patch by Masami Komiya, 08 Dec 2003:
+  add RTL8139 ethernet driver
+
+* Patches by Ed Okerson, 07 Dec 2003:
+  - fix ethernet for the AU1x00 processors in little-endian mode.
+  - extend memsetup.S for the AU1x00 processors in BE and LE modes
+
+* Minor code cleanup (coding style)
+
+* Patch by Reinhard Meyer, 30 Dec 2003:
+  - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
+  - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
+  - turned debug print of PHY registers into a function (called in two places)
+  - added support for EMK MPC5200 based modules
+
+* Fix MPC8xx PLPRCR_MFD_SHIFT typo
+
+* Add support for TQM866M modules
+
+* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)
+
+* Fix a few compiler warnings
+
+* Patch by Reinhard Meyer, 28 Dec 2003:
+  Add initial support for TOP5200 board
+
+* Make CPU clock on ICA-IP board controllable by a "cpuclk"
+  environment variable which can set to "100", "133", or "150". The
+  CPU clock will be configured accordingly upon next reboot. Other
+  values are ignored. In case of an invalid or undefined "cpuclk"
+  value, the compile-time default CPU clock speed will be used.
+
+* Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory
+  window that is used to access the UART registers by the Linux driver)
+
+* Patch by Reinhard Meyer, 20 Dec 2003:
+  Fix clock calculation for the MPC5200 for higher clock frequencies
+  (above 2**32 / 10 = 429.5 MHz).
+
+* Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration
+
+* Fix IceCube CLKIN configuration (it's 33.000000MHz)
+
+* Add new configuration for IceCube board with DDR memory
+
+* Update TRAB memory configurations
+
+* Add JFFS2 support for INCA-IP board
+
+* Patch by Bill Hargen, 09 Dec 2003:
+  - BUBINGA405EP: changed flash driver to protect top sector containing
+    first instruction.
+  - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM.
+  - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access).
+  - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1).
+  - 405EP: added/fixed support for "reginfo" command.
+  - 4xx: removed spurious MII error messages on "mii info" command.
+
+* Patch by Bernhard Kuhn, 28 Nov 2003:
+  add support for Coldfire CPU
+  add support for Motorola M5272C3 and M5282EVB boards
+
+* Patch by Pierre Aubert, 24 Nov 2003:
+  - add a return value for the fpga command
+  - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT
+    is defined. If ide_preinit fails, ide_init is aborted.
+  - fix an endianess problem in fat.h
+
+* Patch by Wolter Kamphuis, 05 Dec 2003:
+  Add support for SNMC's QS850/QS823/QS860T boards
+
+* Patch by Yuli Barcohen, 3 Dec 2003:
+  "revive" U-Boot support for old Motorola MPC860ADS board
+
+* Patch by Cam(ilo?), 03 Dec 2003:
+  make examples build even with broken Montavista objcopy
+
+* Patch by Pavel Bartusek, 27 Nov 2003:
+  fix conversion problem with "bootretry" evironment variable
+
+* Patch by Andre Schwarz, 24 Nov 2003:
+  add support for mvblue (mvBlueLYNX and mvBlueBOX) boards
+
+* Patch by Pavel Bartusek, 21 Nov 2003:
+  set ZMII bridge speed on 440
+
+* Patch by Anders Larsen, 17 Nov 2003:
+  Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h
+
+* Patches by David M<>ller, 14 Nov 2003:
+  - board/mpl/common/common_util.c
+    * implement support for BZIP2 compressed images
+    * various cleanups (printf -> puts, ...)
+  - board/mpl/common/flash.c
+    * report correct errors to upper layers
+    * check the erase fail and VPP low bits in status reg
+  - board/mpl/vcma9/cmd_vcma9.c
+  - board/mpl/vcma9/flash.c
+    * various cleanups (printf -> puts, ...)
+  - common/cmd_usb.c
+    * fix typo in comment
+  - cpu/arm920t/usb_ohci.c
+    * support for S3C2410 is missing in #if line
+  - drivers/cs8900.c
+    * reinit some registers in case of error (cable missing, ...)
+  - fs/fat/fat.c
+    * support for USB/MMC devices is missing in #if line
+  - include/configs/MIP405.h
+  - include/configs/PIP405.h
+    * enable BZIP2 support
+    * enlarge malloc space to 1MiB because of BZIP2 support
+  - include/configs/VCMA9.h
+    * enable BZIP2 support
+    * enlarge malloc space to 1MiB because of BZIP2 support
+    * enable USB support
+  - lib_arm/armlinux.c
+    * change calling convention of ARM Linux kernel as
+      described on http://www.arm.linux.org.uk/developer/booting.php
+
+* Patch by Thomas Lange, 14 Nov 2003:
+  Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to
+  support all these AMD boards.
+
+* Patch by Thomas Lange, 14 Nov 2003:
+  Workaround for mips au1x00 physical memory accesses (the au1x00
+  uses a 36 bit bus internally and cannot access physical memory
+  directly. Use the uncached SDRAM address instead of the physical
+  one.)
+
+* Patch by Xue Ligong (Joe), 13 Nov 2003:
+  add Realtek 8019 ethernet driver
+
+* Patch by Yuli Barcohen, 13 Nov 2003:
+  MPC826xADS/PQ2FADS  cleanup
+
+* Patch by Anders Larsen, 12 Nov 2003:
+  Update README to mark the PORTIO commands non-standard
+
+* Patch by Nicolas Lacressonni<6E>re, 12 Nov 2003:
+  update for for Atmel AT91RM9200DK development kit:
+  - support for environment variables in DataFlash
+  - Atmel DataFlash AT45DB1282 support
+
+* Patch by Jeff Carr, 11 Nov 2003:
+  add support for new version of 8270 processors
+
+* Patches by George G. Davis, 05 Nov 2003:
+  - only pass the ARM linux initrd tag to the kernel when an initrd
+    is actually present
+  - update omap1510inn configuration file
+
+* Patches by Stephan Linz, 3 Nov 2003:
+  - more endianess fixes for LAN91C111 driver
+  - CFG_HZ configuration patch for NIOS Cyclone board
+
+* Patch by Stephan Linz, 28 Oct 2003:
+  fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c
+
+* Patch by Steven Scholz, 20 Oct 2003:
+  - make "mii info <addr>" show infor for PHY at "addr" only
+  - Endian fix for miiphy_info()
+
+* Patch by Gleb Natapov, 19 Sep 2003:
+  Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c
+
+* Patch by Anders Larsen, 17 Sep 2003:
+  Bring ARM memory layout in sync with the documentation:
+  stack and malloc-heap are now located _below_ the U-Boot code
+
+* Accelerate booting on TRAB board: read and check  autoupdate  image
+  headers first instead of always reading the whole images.
+
+* Fix type in MPC5XXX code (pointed out by Victor Wren)
+
+* Enabled password check on RMU board
+
+* Fix configuration problem with IceCube in LOWBOOT configuration:
+  envrionment got embedded, corrupting the image layout.
+
+* Fix NEC display names (it's 6440 [for 640x480], not 6640).
+
+* Added BMS2003 board
+  add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display
+
+* Fix flash driver for TRAB board (must use Unlock Bypass Reset
+  command to exit Unlock Bypass Mode); adjust timings for flash, SRAM
+  and CPLD
+
+* Use "-fPIC" instead of "-mrelocatable" to prevent problems with
+  recent tools
+
+* Add checksum verification to 'imls' command
+
+* Add bd_info fields needed for 4xx Linux I2C driver
+
+* Patch by Martin Krause, 4 Nov. 2003:
+  Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap)
+
+* Print used network interface when CONFIG_NET_MULTI is set
+
+* Patch by Bernhard Kuhn, 28 Oct 2003:
+  Add low boot support for MPC5200
+
+* Fix problem with dual PCMCIA support (NSCU)
+
+* Fix MPC5200 I2C initialization function
+
+======================================================================
+Changes for U-Boot 1.0.0:
+======================================================================
+
+* Fix parameter passing to standalone images with bootm command
+
+* Patch by Kyle Harris, 30 Oct 2003:
+  Fix build errors for ixdp425 board
+
+* Patch by David M. Horn, 29 Oct 2003:
+  Fixes to build under CYGWIN
+
+* Get IceCube MGT5100 working (again)
+
+* Fix problems in memory test on some boards (which was not
+  non-destructive as intended)
+
+* Patch by Gary Jennejohn, 28 Oct 2003:
+  Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack
+  to prevent stack overflow on ARM systems
+
+* Patch by Stephan Linz, 28 Oct 2003:
+  fix init sequence error for NIOS port
+
+* Allow lowercase spelling for IceCube_5200; support MPC5200LITE name
+
+* Add CONFIG_VERSION_VARIABLE to TRAB configuration
+
+* Patch by Xiao Xianghua, 23 Oct 2003:
+  small patch for mpc85xx
+
+* Fix small problem in MPC5200 I2C driver
+
+* Fix FCC3 support on ATC board
+
+* Correct header printing for multi-image files in do_bootm()
+
+* Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED
+
+* Fix PCI problems on PPChameleon board
+
+* Patch by Steven Scholz, 18 Oct 2003:
+  Fix AT91RM9200 ethernet driver
+
+* Patch by Nye Liu, 17 Oct 2003:
+  Fix typo in include/mpc8xx.h
+
+* Patch by Richard Woodruff, 16 Oct 03:
+  Fixes for cpu/arm925/interrupt.c
+  - Initialize timestamp & lastdec vars.
+  - fix timestamp overflows.
+  - fix lastdec overflow.
+  - smarter normalization to allow udelay() below 1ms to work.
+
+* Patch by Scott McNutt, 16 Oct
+  add networking support for the Altera Nios Development Kit,
+  Cyclone Edition (DK-1C20)
+
+* Patch by Jon Diekema, 14 Oct 2003:
+  add hint about doc/README.silent to README file
+
+* Add CompactFlash support for NSCU
+
+* Fix PCI problems on PPChameleonEVB
+
+* TRAB auto-update: Base decision if we have to strip the image
+  header on image type as encoded in the header
+  (include image type patch by Martin Krause, 17 Oct 2003)
+
+* Patches by Xianghua Xiao, 15 Oct 2003:
+
+  - Added Motorola CPU 8540/8560 support (cpu/85xx)
+  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
+  - Added Motorola MPC8560ADS board support (board/mpc8560ads)
+
+* Fix flash timings on TRAB board
+
+* Make sure HUSH is initialized for running auto-update scripts
+
+* Make 5200 reset command _really_ reset the board, without running
+  any other code after it
+
+* Fix errors with flash erase when range spans  across banks
+  that are mapped in reverse order
+
+* Fix flash mapping and display on P3G4 board
+
+* Patch by Kyle Harris, 15 Jul 2003:
+  - add support for Intel IXP425 CPU
+  - add support for IXDP425 eval board
+
+* Added config option CONFIG_SILENT_CONSOLE.  See doc/README.silent
+  for more information
+
+* Patch by Steven Scholz, 10 Oct 2003
+  - Add support for Altera FPGA ACEX1K
+
+* Patches by Thomas Lange, 09 Oct 2003:
+  - fix cmd_ide.c for non ppc boards (read/write functions did not
+    add ATA base address)
+  - fix for shannon board
+  - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code
+  - Endian swap ATA identity for all big endian CPUs, not just PPC
+  - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
+    args to linux
+  - add support for dbau1x00 board (MIPS32)
+
+* Patch by Sangmoon Kim, 07 Oct 2003:
+  add support for debris board
+
+* Patch by Martin Krause, 09 Oct 2003:
+  Fixes for TRAB board
+  - /board/trab/rs485.c: correct baudrate
+  - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
+    udelay(); fix some timing problems with adc controller
+  - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power;
+    modify commands: touch and buzzer
+
+* Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE
+  (quick & dirty workaround for rogue pointer problem in get_vfatname());
+  Use direct function calls for auto_update instead of hush commands
+
+* Patch by Scott McNutt, 04 Oct 2003:
+  - add support for Altera Nios-32 CPU
+  - add support for Nios Cyclone Development Kit (DK-1C20)
+
+* Patch by Steven Scholz, 29 Sep 2003:
+  - A second parameter for bootm overwrites the load address for
+    "Standalone Application" images.
+  - bootm sets environment variable "filesize" to the resulting
+    (uncompressed) data length for "Standalone Application" images
+    when autostart is set to "no". Now you can do something like
+	if bootm $fpgadata $some_free_ram ; then
+		fpga load 0 $some_free_ram $filesize
+	fi
+
+* Patch by Denis Peter, 25 Sept 2003:
+  add support for the MIP405 Rev. C board
+
+* Patch by Yuli Barcohen, 25 Sep 2003:
+  add support for Zephyr Engineering ZPC.1900 board
+
+* Patch by Anders Larsen, 23 Sep 2003:
+  add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only
+  implemented for the x86 architecture)
+
+* Patch by Sangmoon Kim, 23 Sep 2003:
+  fix pll_pci_to_mem_multiplier table for MPC8245
+
+* Patch by Anders Larsen, 22 Sep 2003:
+  enable timed autoboot on PXA
+
+* Patch by David M<>ller, 22 Sep 2003:
+  - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver
+    returns correct libgcc file path
+  - "latency" reduction of busy-loop waiting to improve "U-Boot" boot
+    time on s3c24x0 systems
+
+* Patch by Jon Diekema, 19 Sep 2003:
+  - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet
+    link state to the fault LED.
+  - In NetLoop, make the Fault LED reflect the link status.  The link
+    status gets updated on entry, and on timeouts.
+
+* Patch by Anders Larsen, 18 Sep 2003:
+  allow mkimage to build and run on Cygwin-hosted systems
+
+* Patch by Frank M<>ller, 18 Sep 2003:
+  use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in
+  cpu/mpc8xx/fec.c
+
+* Patch by Pantelis Antoniou, 16 Sep 2003:
+  add tool to compute fileds in the PLPRCR register for MPC86x
+
+* Use IH_TYPE_FILESYSTEM for TRAB "disk" images.
+
+* Fix build problems under FreeBSD
+
+* Add generic filesystem image type
+
+* Make fatload set filesize environment variable
+
+* enable basic / medium / high-end configurations for PPChameleonEVB
+  board; fix NAND code
+
+* enable TFTP client code to specify to the server the desired
+  timeout value (see RFC-2349)
+
+* Improve SDRAM setup for TRAB board
+
+* Suppress all output with splashscreen configured only if "splashimage"
+  is set
+
+* Fix problems with I2C support for mpc5200
+
+* Adapt TRAB configuration and auto_update to new memory layout
+
+* Add configuration for wtk board
+
+* Add support for the Sharp LQ065T9DR51U LCD display
+
+* Patch by Rune Torgersen, 17 Sep 2003:
+  - Fixes for MPC8266 default config
+  - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
+
+* Patches by Jon Diekema, 17 Sep 2003:
+  - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and
+    env_common.c)
+  - sbc8260 tweaks
+  - adjust "help" output
+
+* Patches by Anders Larsen, 17 Sep 2003:
+  - fix spelling errors
+  - set GD_FLG_DEVINIT flag only after device function pointers
+    are valid
+  - Allow CFG_ALT_MEMTEST on systems where address zero isn't
+    writeable
+  - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs
+  - trigger watchdog while waiting in serial driver
+
+* Add auto-update code for TRAB board using USB memory sticks,
+  support new configuration with more memory
+
+* disable MPC5200 bus pipelining as workaround for bus contention
+
+* Modify XLB arbiter priorities on MPC5200 so all devices use same
+  priority; configure critical interrupts to be handled like external
+  interrupts
+
+* Make IPB clock on MGT5100/MPC5200 configurable in board config file;
+  go back to 66 MHz for stability
+
+* Patches by Jon Diekema, 15 Sep 2003:
+  - add description for missing CFG_CMD_* entries in the README file
+  - sacsng tweaks
+
+* Patch by Gleb Natapov, 14 Sep 2003:
+  enable watchdog support for all MPC824x boards that have a watchdog
+
+* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
+  "Non-octet Aligned Frame" errors we see at 100 Mbps
+
+* Patch by Sharad Gupta, 14 Sep 2003:
+  fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
+
+* Patch by llandre, 11 Sep 2003:
+  update configuration for PPChameleonEVB board
+
+* Patch by David M<>ller, 13 Sep 2003:
+  various changes to VCMA9 board specific files
+
+* Add I2C support for MGT5100 / MPC5200
+
+* Patch by Rune Torgersen, 11 Sep 2003:
+  Changed default memory option on MPC8266ADS to NOT be Page Based
+  Interleave, since this doesn't work very well with the standard
+  16MB DIMM
+
+* Patch by George G. Davis, 12 Sep 2003:
+  fix Makefile settings for sk98 driver
+
+* Patch by Stefan Roese, 12 Sep 2003:
+  - new boards added: DP405, HUB405, PLU405, VOH405
+  - some esd boards updated
+  - cpu/ppc4xx/sdram.c: disable memory controller before setting
+    first values
+  - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems
+
+* Patch by Martin Krause, 11 Sep 2003:
+  add burn-in tests for TRAB board
+
+* Enable instruction cache on MPC5200 board
+
+* Patch by Denis Peter, 11 Sep 2003:
+  - fix USB data pointer assignment for bulk only transfer.
+  - prevent to display erased directories in FAT filesystem.
+
+* Change output format for NAND flash - make it look like for other
+  memory, too
+
+======================================================================
+Changes for U-Boot 0.4.8:
+======================================================================
+
+* Add I2C and RTC support for RMU board
+
+* Patches by Denis Peter, 9 Sep 2003:
+  add FAT support for IDE, SCSI and USB
+
+* Patches by Gleb Natapov, 2 Sep 2003:
+  - cleanup of POST code for unsupported architectures
+  - MPC824x locks way0 of data cache for use as initial RAM;
+    this patch unlocks it after relocation to RAM and invalidates
+    the locked entries.
+
+* Patch by Gleb Natapov, 30 Aug 2003:
+  new I2C driver for mpc107 bridge. Now works from flash.
+
+* Patch by Dave Ellis, 11 Aug 2003:
+  - JFFS2: fix typo in common/cmd_jffs2.c
+  - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
+  - JFFS2: remove node version 0 warning
+  - JFFS2: accept JFFS2 PADDING nodes
+  - SXNI855T: add AM29LV800 support
+  - SXNI855T: move environment from EEPROM to flash
+  - SXNI855T: boot from JFFS2 in NOR or NAND flash
+
+* Patch by Bill Hargen, 11 Aug 2003:
+  fixes for I2C on MPC8240
+  - fix i2c_write routine
+  - fix iprobe command
+  - eliminates use of global variables, plus dead code, cleanup.
+
+* Add support for USB Mass Storage Devices (BBB)
+  (tested with USB memory sticks only)
+
+* Avoid flicker on TRAB's VFD
+
 * Add support for SK98xx driver
 
 * Add PCI support for SL8245 board
@@ -27,6 +873,10 @@ Changes for U-Boot 0.4.7:
 * Patch by Yuli Barcohen, 7 Aug 2003:
   check BCSR to detect if the board is configured in PCI mode
 
+======================================================================
+Changes for U-Boot 0.4.7:
+======================================================================
+
 * Patch by Raghu Krishnaprasad, 7 Aug 2003:
   add support for Adder II MPC852T module
 
@@ -263,7 +1113,7 @@ Changes for U-Boot 0.4.1:
   - PIC on LWMON board needs delay after power-on
   - Add missing RSR definitions for MPC8xx
   - Improve log buffer handling: guarantee clean reset after power-on
-  - Add support for EXBITGEN board
+  - Add support for EXBITGEN board (aka "genie")
   - Add support for SL8245 board
 
 * Code cleanup:

CREDITS

@@ -18,14 +18,14 @@ N: Dr. Bruno Achauer
 E: bruno@exet-ag.de
 D: Support for NetBSD (both as host and target system)
 
-N: Swen Anderson
-E: sand@peppercon.de
-D: ERIC Support
-
 N: Guillaume Alexandre
 E: guillaume.alexandre@gespac.ch
 D: Add PCIPPC6 configuration
 
+N: Swen Anderson
+E: sand@peppercon.de
+D: ERIC Support
+
 N: Pantelis Antoniou
 E: panto@intracom.gr
 D: NETVIA board support, ARTOS support.
@@ -75,7 +75,7 @@ E: clark@esteem.com
 D: ESTEEM192E support
 
 N: Magnus Damm
-E: eramdam@kieray1.p.y.ki.era.ericsson.se
+E: damm@opensource.se
 D: 8xxrom
 
 N: Arun Dharankar
@@ -182,19 +182,37 @@ N: Brad Kemp
 E: Brad.Kemp@seranoa.com
 D: Port to Windriver ppmc8260 board
 
+N: Sangmoon Kim
+E: dogoil@etinsys.com
+D: Support for debris board
+
 N: Thomas Koeller
 E: tkoeller@gmx.net
 D: Port to Motorola Sandpoint 3 (MPC8240)
 
+N: Raghu Krishnaprasad
+E: Raghu.Krishnaprasad@fci.com
+D: Support for Adder-II MPC852T evaluation board
+W: http://www.forcecomputers.com
+
+N: Bernhard Kuhn
+E: bkuhn@metrowerks.com
+D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards
+
 N: Thomas Lange
-E: thomas@corelatus.com
-D: Support for GTH board; lots of PCMCIA fixes
+E: thomas@corelatus.se
+D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
 
 N: The LEOX team
 E: team@leox.org
 D: Support for LEOX boards, DS164x RTC
 W: http://www.leox.org
 
+N: Stephan Linz
+E: linz@li-pro.net
+D: Support for Nios Stratix Development Kit (DK-1S10)
+W: http://www.li-pro.net
+
 N: Raymond Lo
 E: lo@routefree.com
 D: Support for DOS partitions
@@ -219,6 +237,10 @@ N: David M
 E: d.mueller@elsoft.ch
 D: Support for Samsung ARM920T SMDK2410 eval board
 
+N: Scott McNutt
+E: smcnutt@psyent.com
+D: Support for Altera Nios-32 CPU, for Nios Cyclone Development Kit (DK-1C20)
+
 N: Rolf Offermanns
 E: rof@sysgo.de
 D: Initial support for SSV-DNP1110, SMC91111 driver
@@ -254,6 +276,10 @@ N: Neil Russell
 E: caret@c-side.com
 D: Author of LiMon-1.4.2, which contributed some ideas
 
+N: Travis B. Sawyer
+E: travis.sawyer@sandburst.com
+D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board.
+
 N: Paolo Scaffardi
 E: arsenio@tin.it
 D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
@@ -299,6 +325,6 @@ E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com
 
-N: Pantelis Antoniou
-E: panto@intracom.gr
-D: NETVIA board support, ARTOS support.
+N: Xianghua Xiao
+E: x.xiao@motorola.com
+D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.

MAINTAINERS

@@ -25,6 +25,10 @@ Pantelis Antoniou <panto@intracom.gr>
 
 	NETVIA			MPC8xx
 
+Yuli Barcohen <yuli@arabellasw.com>
+
+	ZPC1900			MPC8265
+
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 
 	sacsng			MPC8260
@@ -89,6 +93,7 @@ Wolfgang Denk <wd@denx.de>
 	TQM8255			MPC8255
 
 	CPU86			MPC8260
+	PM825			MPC8250
 	PM826			MPC8260
 	TQM8260			MPC8260
 
@@ -130,6 +135,10 @@ Howard Gray <mvsensor@matrix-vision.de>
 
 	MVS1			MPC823
 
+Bill Hargen <Bill_Hargen@Jabil.com>
+
+	BUBINGA405EP		PPC405EP
+
 Klaus Heydeck <heydeck@kieback-peter.de>
 
 	KUP4K			MPC855
@@ -145,11 +154,19 @@ Brad Kemp <Brad.Kemp@seranoa.com>
 
 	ppmc8260		MPC8260
 
+Sangmoon Kim <dogoil@etinsys.com>
+
+	debris			MPC8245
+
+Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
+
+	ADDERII			MPC852T
+
 Nye Liu <nyet@zumanetworks.com>
 
 	ZUMA			MPC7xx_74xx
 
-Thomas Lange <thomas@corelatus.com>
+Thomas Lange <thomas@corelatus.se>
 
 	GTH			MPC860
 
@@ -163,12 +180,16 @@ Eran Man <eran@nbase.co.il>
 
 Reinhard Meyer <r.meyer@emk-elektronik.de>
 
-	TOP860			MPC860
+	TOP860			MPC860T
+	TOP5200			MPC5200
 
 Scott McNutt <smcnutt@artesyncp.com>
 
 	EBONY			PPC440GP
 
+Tolunay Orkun <torkun@nextio.com>
+	csb272			PPC4xx
+
 Keith Outwater <Keith_Outwater@mvis.com>
 
 	GEN860T			MPC860T
@@ -195,11 +216,15 @@ Stefan Roese <stefan.roese@esd-electronics.com>
 	CPCI440			PPC440GP
 	CPCIISER4		PPC405GP
 	DASA_SIM		IOP480 (PPC401)
+	DP405			PPC405EP
 	DU405			PPC405GP
+	HUB405			PPC405EP
 	OCRTC			PPC405GP
 	ORSG			PPC405GP
 	PCI405			PPC405GP
+	PLU405			PPC405EP
 	PMC405			PPC405GP
+	VOH405			PPC405EP
 
 Peter De Schrijver <p2@mind.be>
 
@@ -223,6 +248,11 @@ John Zhan <zhanz@sinovee.com>
 
 	svm_sc8xx		MPC8xx
 
+Xianghua Xiao <x.xiao@motorola.com>
+
+	MPC8540ADS		MPC8540
+	MPC8560ADS		MPC8560
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -272,6 +302,7 @@ Kyle Harris <kharris@nexus-tech.net>
 
 	lubbock			xscale
 	cradle			xscale
+	ixdp425			xscale
 
 Gary Jennejohn <gj@denx.de>
 
@@ -279,9 +310,14 @@ Gary Jennejohn <gj@denx.de>
 	trab			ARM920T
 
 Kshitij Gupta <kshitij@ti.com>
+
 	omap1510inn		ARM925T
 	omap1610inn		ARM926EJS
 
+Nishant Kamat <nskamat@ti.com>
+
+	omap1610h2		ARM926EJS
+
 David M<>ller <d.mueller@elsoft.ch>
 
 	smdk2410		ARM920T
@@ -324,6 +360,24 @@ Wolfgang Denk <wd@denx.de>
 	incaip			MIPS32 4Kc
 	purple			MIPS64 5Kc
 
+Thomas Lange <thomas@corelatus.se>
+	dbau1x00		MIPS32 Au1000
+
+#########################################################################
+# Nios-32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Stephan Linz <linz@li-pro.net>
+
+	DK1S10			Nios-32
+
+Scott McNutt <smcnutt@psyent.com>
+
+	DK1C20			Nios-32
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################

MAKEALL

@@ -1,5 +1,7 @@
 #!/bin/sh
 
+: ${JOBS:=}
+
 if [ "${CROSS_COMPILE}" ] ; then
 	MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
 else
@@ -23,7 +25,7 @@ LIST_5xx="	\
 #########################################################################
 
 LIST_5xxx="	\
-	IceCube_5100	IceCube_5200					\
+	IceCube_5100	IceCube_5200	EVAL5200	\
 "
 
 #########################################################################
@@ -32,15 +34,16 @@ LIST_5xxx="	\
 
 LIST_8xx="	\
 	AdderII		ADS860		AMX860		c2mon		\
-	CCM		cogent_mpc8xx	ESTEEM192E	ETX094		\
-	ELPT860		FADS823		FADS850SAR	FADS860T	\
-	FLAGADM		FPS850L		GEN860T		GEN860T_SC	\
-	GENIETV		GTH		hermes		IAD210		\
-	ICU862_100MHz	IP860		IVML24		IVML24_128	\
-	IVML24_256	IVMS8		IVMS8_128	IVMS8_256	\
-	KUP4K           LANTEC	        lwmon   	MBX		\
-	MBX860T		MHPC		MPC86xADS	MVS1		\
-	NETVIA		NETVIA_V2	NX823		pcu_e		\
+	CCM		cogent_mpc8xx	DUET_ADS	ESTEEM192E	\
+	ETX094		ELPT860		FADS823		FADS850SAR	\
+	FADS860T	FLAGADM		FPS850L		GEN860T		\
+	GEN860T_SC	GENIETV		GTH		hermes		\
+	IAD210		ICU862_100MHz	IP860		IVML24		\
+	IVML24_128	IVML24_256	IVMS8		IVMS8_128	\
+	IVMS8_256	KUP4K		LANTEC		lwmon		\
+	MBX		MBX860T		MHPC		MPC86xADS	\
+	MVS1		NETVIA		NETVIA_V2	NX823		\
+	pcu_e		QS823		QS850		QS860T		\
 	R360MPI		RBC823		rmu		RPXClassic	\
 	RPXlite		RRvision	SM850		SPD823TS	\
 	svm_sc8xx	SXNI855T	TOP860		TQM823L		\
@@ -53,13 +56,15 @@ LIST_8xx="	\
 #########################################################################
 
 LIST_4xx="	\
-	ADCIOP		AR405		ASH405          BUBINGA405EP    \
-	CANBT		CPCI405		CPCI4052 	CPCI405AB       \
-	CPCI440         CPCIISER4	CRAYL1  	DASA_SIM	\
-	DU405    	EBONY           ERIC  		EXBITGEN	\
-	MIP405  	MIP405T		ML2		OCRTC		\
-	ORSG		PCI405		PIP405		PMC405          \
-	PPChameleonEVB	W7OLMC		W7OLMG          WALNUT405	\
+	ADCIOP		AR405		ASH405		BUBINGA405EP	\
+	CANBT		CPCI405		CPCI4052	CPCI405AB	\
+	CPCI440		CPCIISER4	CRAYL1		csb272		\
+	DASA_SIM	DP405		DU405		EBONY		\
+	ERIC		EXBITGEN	HUB405		MIP405		\
+	MIP405T		ML2		ml300		OCRTC		\
+	ORSG		PCI405		PIP405		PLU405		\
+	PMC405		PPChameleonEVB	VOH405		W7OLMC		\
+	W7OLMG		WALNUT405	XPEDITE1K			\
 "
 
 #########################################################################
@@ -67,9 +72,10 @@ LIST_4xx="	\
 #########################################################################
 
 LIST_824x="	\
-	A3000           BMW		CPC45		CU824		\
-	MOUSSE          MUSENKI    	OXC		PN62		\
-	Sandpoint8240   Sandpoint8245	SL8245		utx8245		\
+	A3000		BMW		CPC45		CU824		\
+	debris		MOUSSE		MUSENKI		MVBLUE		\
+	OXC		PN62		Sandpoint8240	Sandpoint8245	\
+	SL8245		utx8245						\
 "
 
 #########################################################################
@@ -81,7 +87,15 @@ LIST_8260="	\
 	gw8260		hymod		IPHASE4539	MPC8260ADS	\
 	MPC8266ADS	PM826		ppmc8260	RPXsuper	\
 	rsdproto	sacsng		sbc8260		SCM		\
-	TQM8260_AC	TQM8260_AD	TQM8260_AE			\
+	TQM8260_AC	TQM8260_AD	TQM8260_AE	ZPC1900		\
+"
+
+#########################################################################
+## MPC85xx Systems (includes 8540, 8560 etc.)
+#########################################################################
+
+LIST_85xx="	\
+	MPC8540ADS	MPC8560ADS					\
 "
 
 #########################################################################
@@ -89,8 +103,8 @@ LIST_8260="	\
 #########################################################################
 
 LIST_74xx="	\
-	EVB64260	P3G4		PCIPPC2		PCIPPC6		\
-	ZUMA								\
+	DB64360		DB64460		EVB64260	P3G4		\
+	PCIPPC2		PCIPPC6		ZUMA				\
 "
 
 LIST_7xx="	\
@@ -100,6 +114,7 @@ LIST_7xx="	\
 LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
 	  ${LIST_8xx}  \
 	  ${LIST_824x} ${LIST_8260} \
+	  ${LIST_85xx}	\
 	  ${LIST_4xx}		    \
 	  ${LIST_74xx} ${LIST_7xx}"
 
@@ -113,14 +128,14 @@ LIST_SA="dnp1110 lart shannon"
 ## ARM7 Systems
 #########################################################################
 
-LIST_ARM7="ep7312 impa7"
+LIST_ARM7="B2 ep7312 impa7"
 
 #########################################################################
 ## ARM9 Systems
 #########################################################################
 
 LIST_ARM9="	\
-	at91rm9200dk	omap1510inn	omap1610inn			\
+	at91rm9200dk	omap1510inn	omap1610h2	omap1610inn	\
 	smdk2400	smdk2410	trab				\
 	VCMA9								\
 "
@@ -131,18 +146,22 @@ LIST_ARM9="	\
 
 LIST_pxa="cradle csb226 innokom lubbock wepep250"
 
+LIST_ixp="ixdp425"
 
-LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa}"
+
+LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa} ${LIST_ixp}"
 
 #########################################################################
-## MIPS 4Kc Systems
+## MIPS Systems
 #########################################################################
 
 LIST_mips4kc="incaip"
 
 LIST_mips5kc="purple"
 
-LIST_mips="${LIST_mips4kc} ${LIST_mips5kc}"
+LIST_au1x00="dbau1000 dbau1100 dbau1500"
+
+LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1x00}"
 
 #########################################################################
 ## i386 Systems
@@ -152,6 +171,15 @@ LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel"
 
 LIST_x86="${LIST_I486}"
 
+#########################################################################
+## NIOS Systems
+#########################################################################
+
+LIST_nios="	\
+	DK1C20 DK1C20_standard_32					\
+	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20			\
+"
+
 #-----------------------------------------------------------------------
 
 #----- for now, just run PPC by default -----
@@ -164,7 +192,7 @@ build_target() {
 
 	${MAKE} distclean >/dev/null
 	${MAKE} ${target}_config
-	${MAKE} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
+	${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
 	${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
 }
 
@@ -174,7 +202,11 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	5xx|5xxx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips|I486|x86)
+	ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
+	arm|SA|ARM7|ARM9|pxa|ixp| \
+	mips| \
+	nios| \
+	x86|I486)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}

Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -69,45 +69,37 @@ endif
 ifeq ($(ARCH),mips)
 CROSS_COMPILE = mips_4KC-
 endif
+ifeq ($(ARCH),nios)
+CROSS_COMPILE = nios-elf-
+endif
+ifeq ($(ARCH),m68k)
+CROSS_COMPILE = m68k-elf-
+endif
 endif
 endif
 
 export	CROSS_COMPILE
 
-# The "tools" are needed early, so put this first
-SUBDIRS	= tools \
-	  lib_generic \
-	  lib_$(ARCH) \
-	  cpu/$(CPU) \
-	  board/$(BOARDDIR) \
-	  common \
-	  disk \
-	  fs \
-	  net \
-	  rtc \
-	  dtt \
-	  drivers \
-	  drivers/sk98lin \
-	  post \
-	  post/cpu \
-	  examples
-
 #########################################################################
 # U-Boot objects....order is important (i.e. start must be first)
 
-OBJS  =	cpu/$(CPU)/start.o
+OBJS  = cpu/$(CPU)/start.o
 ifeq ($(CPU),i386)
-OBJS +=	cpu/$(CPU)/start16.o
-OBJS +=	cpu/$(CPU)/reset.o
+OBJS += cpu/$(CPU)/start16.o
+OBJS += cpu/$(CPU)/reset.o
 endif
 ifeq ($(CPU),ppc4xx)
-OBJS +=	cpu/$(CPU)/resetvec.o
+OBJS += cpu/$(CPU)/resetvec.o
+endif
+ifeq ($(CPU),mpc85xx)
+OBJS += cpu/$(CPU)/resetvec.o
 endif
 
-LIBS  =	board/$(BOARDDIR)/lib$(BOARD).a
+LIBS  = lib_generic/libgeneric.a
+LIBS += board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
 LIBS += lib_$(ARCH)/lib$(ARCH).a
-LIBS += fs/jffs2/libjffs2.a fs/fdos/libfdos.a fs/fat/libfat.a
+LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a
 LIBS += net/libnet.a
 LIBS += disk/libdisk.a
 LIBS += rtc/librtc.a
@@ -116,7 +108,18 @@ LIBS += drivers/libdrivers.a
 LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
-LIBS += lib_generic/libgeneric.a
+.PHONY : $(LIBS)
+
+# Add GCC lib
+PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+
+# The "tools" are needed early, so put this first
+# Don't include stuff already done in $(LIBS)
+SUBDIRS	= tools \
+	  examples \
+	  post \
+	  post/cpu
+.PHONY : $(SUBDIRS)
 
 #########################################################################
 #########################################################################
@@ -141,14 +144,17 @@ u-boot.img:	u-boot.bin
 u-boot.dis:	u-boot
 		$(OBJDUMP) -d $< > $@
 
-u-boot:		depend subdirs $(OBJS) $(LIBS) $(LDSCRIPT)
+u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
 		UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
 		$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
 			--start-group $(LIBS) $(PLATFORM_LIBS) --end-group \
 			-Map u-boot.map -o u-boot
 
-subdirs:
-		@for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir || exit 1 ; done
+$(LIBS):
+		$(MAKE) -C `dirname $@`
+
+$(SUBDIRS):
+		$(MAKE) -C $@ all
 
 gdbtools:
 		$(MAKE) -C tools/gdb || exit 1
@@ -192,22 +198,50 @@ unconfig:
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi
 
+PATI_config:unconfig
+	@./mkconfig $(@:_config=) ppc mpc5xx pati mpl
+
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
-IceCube_5200_config	\
+MPC5200LITE_config		\
+MPC5200LITE_LOWBOOT_config	\
+MPC5200LITE_LOWBOOT08_config	\
+icecube_5200_DDR_LOWBOOT_config	\
+icecube_5200_DDR_config		\
+IceCube_5200_DDR_config		\
+icecube_5200_config		\
+IceCube_5200_config		\
 IceCube_5100_config:		unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _5200,$@)" ] || \
+	@[ -z "$(findstring LOWBOOT,$@)" ] || \
+		{ echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+		  echo "... with LOWBOOT configuration" ; \
+		}
+	@[ -z "$(findstring LOWBOOT08,$@)" ] || \
+		{ echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
+		  echo "... with 8 MB flash only" ; \
+		}
+	@[ -z "$(findstring DDR,$@)" ] || \
+		{ echo "#define CONFIG_MPC5200_DDR"	>>include/config.h ; \
+		  echo "... DDR memory revision" ; \
+		}
+	@[ -z "$(findstring 5200,$@)" ] || \
 		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
 		  echo "... with MPC5200 processor" ; \
 		}
-	@[ -z "$(findstring _5100,$@)" ] || \
+	@[ -z "$(findstring 5100,$@)" ] || \
 		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
 		  echo "... with MGT5100 processor" ; \
 		}
 	@./mkconfig -a IceCube ppc mpc5xxx icecube
 
+MINI5200_config	\
+EVAL5200_config	\
+TOP5200_config:	unconfig
+	@ echo "#define CONFIG_$(@:_config=) 1"	>include/config.h
+	@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
+
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
@@ -215,12 +249,20 @@ IceCube_5100_config:		unconfig
 AdderII_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx adderII
 
-ADS860_config:	unconfig
+ADS860_config     \
+DUET_ADS_config   \
+FADS823_config    \
+FADS850SAR_config \
+MPC86xADS_config  \
+FADS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx fads
 
 AMX860_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx amx860 westel
 
+bms2003_config	:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
+
 c2mon_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx c2mon
 
@@ -239,12 +281,6 @@ ESTEEM192E_config:	unconfig
 ETX094_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx etx094
 
-FADS823_config	\
-FADS850SAR_config \
-MPC86xADS_config \
-FADS860T_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx fads
-
 FLAGADM_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx flagadm
 
@@ -355,6 +391,15 @@ NX823_config:		unconfig
 pcu_e_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx pcu_e siemens
 
+QS850_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc
+
+QS823_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc
+
+QS860T_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx qs860t snmc
+
 R360MPI_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx r360mpi
 
@@ -399,7 +444,7 @@ TOP860_config:		unconfig
 # All boards can come with 50 MHz (default), 66MHz, 80MHz or 100 MHz clock,
 # but only 855 and 860 boards may come with FEC
 # and 823 boards may have LCD support
-xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _LCD,,$(subst _config,,$1)))))
+xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _133MHz,,$(subst _LCD,,$(subst _config,,$1))))))
 
 FPS850L_config		\
 FPS860L_config		\
@@ -437,7 +482,8 @@ TQM860M_80MHz_config	\
 TQM862M_config		\
 TQM862M_66MHz_config	\
 TQM862M_80MHz_config	\
-TQM862M_100MHz_config:	unconfig
+TQM862M_100MHz_config	\
+TQM866M_config:		unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _66MHz,$@)" ] || \
 		{ echo "#define CONFIG_66MHz"		>>include/config.h ; \
@@ -451,9 +497,13 @@ TQM862M_100MHz_config:	unconfig
 		{ echo "#define CONFIG_100MHz"		>>include/config.h ; \
 		  echo "... with 100MHz system clock" ; \
 		}
+	@[ -z "$(findstring _133MHz,$@)" ] || \
+		{ echo "#define CONFIG_133MHz"		>>include/config.h ; \
+		  echo "... with 133MHz system clock" ; \
+		}
 	@[ -z "$(findstring _LCD,$@)" ] || \
 		{ echo "#define CONFIG_LCD"		>>include/config.h ; \
-		  echo "#define CONFIG_NEC_NL6648BC20"	>>include/config.h ; \
+		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
 		  echo "... with LCD display" ; \
 		}
 	@./mkconfig -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx
@@ -468,9 +518,15 @@ v37_config:	unconfig
 	@echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h
 	@./mkconfig $(@:_config=) ppc mpc8xx v37
 
+wtk_config:	unconfig
+	@echo "#define CONFIG_LCD" >include/config.h
+	@echo "#define CONFIG_SHARP_LQ065T9DR51U" >>include/config.h
+	@./mkconfig -a TQM823L ppc mpc8xx tqm8xx
+
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
+xtract_4xx = $(subst _MODEL_BA,,$(subst _MODEL_ME,,$(subst _MODEL_HI,,$(subst _config,,$1))))
 
 ADCIOP_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
@@ -502,9 +558,15 @@ CPCIISER4_config:	unconfig
 CRAYL1_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx L1 cray
 
+csb272_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx csb272
+
 DASA_SIM_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd
 
+DP405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx dp405 esd
+
 DU405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx du405 esd
 
@@ -517,6 +579,9 @@ ERIC_config:unconfig
 EXBITGEN_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx exbitgen
 
+HUB405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx hub405 esd
+
 MIP405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
 
@@ -528,6 +593,9 @@ MIP405T_config:unconfig
 ML2_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ml2
 
+ml300_config:unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx
+
 OCRTC_config		\
 ORSG_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ocrtc esd
@@ -538,11 +606,33 @@ PCI405_config:	unconfig
 PIP405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
 
+PLU405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx plu405 esd
+
 PMC405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd
 
+PPChameleonEVB_MODEL_BA_config	\
+PPChameleonEVB_MODEL_ME_config	\
+PPChameleonEVB_MODEL_HI_config	\
 PPChameleonEVB_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx PPChameleonEVB dave
+	@ >include/config.h
+	@[ -z "$(findstring _MODEL_BA,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
+		  echo "... BASIC model" ; \
+		}
+	@[ -z "$(findstring _MODEL_ME,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>include/config.h ; \
+		  echo "... MEDIUM model" ; \
+		}
+	@[ -z "$(findstring _MODEL_HI,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
+		  echo "... HIGH-END model" ; \
+		}
+	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+
+VOH405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
 
 W7OLMC_config	\
 W7OLMG_config: unconfig
@@ -551,6 +641,9 @@ W7OLMG_config: unconfig
 WALNUT405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx walnut405
 
+XPEDITE1K_config:unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
+
 #########################################################################
 ## MPC824x Systems
 #########################################################################
@@ -584,6 +677,9 @@ MOUSSE_config: unconfig
 MUSENKI_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x musenki
 
+MVBLUE_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc824x mvblue
+
 OXC_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x oxc
 
@@ -606,6 +702,9 @@ utx8245_config: unconfig
 ## MPC8260 Systems
 #########################################################################
 
+atc_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8260 atc
+
 cogent_mpc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 cogent
 
@@ -729,8 +828,31 @@ TQM8265_AA_config:  unconfig
 	fi
 	@./mkconfig -a TQM8260 ppc mpc8260 tqm8260
 
-atc_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8260 atc
+ZPC1900_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
+
+#========================================================================
+# M68K
+#========================================================================
+#########################################################################
+## Coldfire
+#########################################################################
+
+M5272C3_config :		unconfig
+	@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
+
+M5282EVB_config :		unconfig
+	@./mkconfig $(@:_config=) m68k mcf52x2 m5282evb
+
+#########################################################################
+## MPC85xx Systems
+#########################################################################
+
+MPC8540ADS_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
+
+MPC8560ADS_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
 
 #########################################################################
 ## 74xx/7xx Systems
@@ -739,24 +861,33 @@ atc_config:	unconfig
 AmigaOneG3SE_config:	unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx AmigaOneG3SE MAI
 
+BAB7xx_config: unconfig
+	@./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec
+
+DB64360_config:  unconfig
+	@./mkconfig DB64360 ppc 74xx_7xx db64360 Marvell
+
+DB64460_config:  unconfig
+	@./mkconfig DB64460 ppc 74xx_7xx db64460 Marvell
+
+debris_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc824x debris etin
+
+ELPPC_config: unconfig
+	@./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec
+
 EVB64260_config	\
 EVB64260_750CX_config:	unconfig
 	@./mkconfig EVB64260 ppc 74xx_7xx evb64260
 
-ZUMA_config:	unconfig
+P3G4_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
 
 PCIPPC2_config \
 PCIPPC6_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx pcippc2
 
-BAB7xx_config: unconfig
-	@./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec
-
-ELPPC_config: unconfig
-	@./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec
-
-P3G4_config: unconfig
+ZUMA_config:	unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
 
 #========================================================================
@@ -782,13 +913,27 @@ shannon_config	:	unconfig
 ## ARM92xT Systems
 #########################################################################
 
-xtract_trab = $(subst _big_flash,,$(subst _config,,$1))
+xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))
+
+xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
 
 omap1510inn_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm925t omap1510inn
 
-omap1610inn_config :	unconfig
-	@./mkconfig $(@:_config=) arm arm926ejs omap1610inn
+omap1610inn_config \
+omap1610inn_cs0boot_config \
+omap1610inn_cs3boot_config \
+omap1610h2_config \
+omap1610h2_cs0boot_config \
+omap1610h2_cs3boot_config :	unconfig
+	@if [ "$(findstring _cs0boot_, $@)" ] ; then \
+		echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
+		echo "Configured for CS0 boot"; \
+	else \
+		echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
+		echo "Configured for CS3 boot"; \
+	fi;
+	@./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
 
 smdk2400_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2400
@@ -796,18 +941,42 @@ smdk2400_config	:	unconfig
 smdk2410_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2410
 
+# TRAB default configuration:	8 MB Flash, 32 MB RAM
 trab_config \
-trab_big_flash_config:	unconfig
+trab_bigram_config \
+trab_bigflash_config \
+trab_old_config:	unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _big_flash,$@)" ] || \
-		{ echo "#define CONFIG_BIG_FLASH" >>include/config.h ; \
-		  echo "... with big flash support" ; \
+	@[ -z "$(findstring _bigram,$@)" ] || \
+		{ echo "#define CONFIG_FLASH_8MB"  >>include/config.h ; \
+		  echo "#define CONFIG_RAM_32MB"   >>include/config.h ; \
+		  echo "... with 8 MB Flash, 32 MB RAM" ; \
+		}
+	@[ -z "$(findstring _bigflash,$@)" ] || \
+		{ echo "#define CONFIG_FLASH_16MB" >>include/config.h ; \
+		  echo "#define CONFIG_RAM_16MB"   >>include/config.h ; \
+		  echo "... with 16 MB Flash, 16 MB RAM" ; \
+		  echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \
+		}
+	@[ -z "$(findstring _old,$@)" ] || \
+		{ echo "#define CONFIG_FLASH_8MB"  >>include/config.h ; \
+		  echo "#define CONFIG_RAM_16MB"   >>include/config.h ; \
+		  echo "... with 8 MB Flash, 16 MB RAM" ; \
+		  echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \
 		}
 	@./mkconfig -a $(call xtract_trab,$@) arm arm920t trab
 
 VCMA9_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t vcma9 mpl
 
+
+#########################################################################
+## S3C44B0 Systems
+#########################################################################
+
+B2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm s3c44b0 B2 dave
+
 #########################################################################
 ## ARM720T Systems
 #########################################################################
@@ -818,6 +987,9 @@ impa7_config	:	unconfig
 ep7312_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm720t ep7312
 
+modnet50_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm720t modnet50
+
 #########################################################################
 ## XScale Systems
 #########################################################################
@@ -831,6 +1003,9 @@ csb226_config	:	unconfig
 innokom_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa innokom
 
+ixdp425_config	:	unconfig
+	@./mkconfig $(@:_config=) arm ixp ixdp425
+
 lubbock_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa lubbock
 
@@ -883,6 +1058,9 @@ incaip_config: unconfig
 		}
 	@./mkconfig -a $(call xtract_incaip,$@) mips mips incaip
 
+tb0229_config: unconfig
+	@./mkconfig $(@:_config=) mips mips tb0229
+
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################
@@ -890,6 +1068,73 @@ incaip_config: unconfig
 purple_config :		unconfig
 	@./mkconfig $(@:_config=) mips mips purple
 
+#========================================================================
+# Nios
+#========================================================================
+#########################################################################
+## Nios32
+#########################################################################
+
+DK1C20_safe_32_config		\
+DK1C20_standard_32_config	\
+DK1C20_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring _safe_32,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \
+		  echo "... NIOS 'safe_32' configuration" ; \
+		}
+	@[ -z "$(findstring _standard_32,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
+		  echo "... NIOS 'standard_32' configuration" ; \
+		}
+	@[ -z "$(findstring DK1C20_config,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
+		  echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
+		}
+	@./mkconfig -a DK1C20 nios nios dk1c20 altera
+
+DK1S10_safe_32_config		\
+DK1S10_standard_32_config	\
+DK1S10_mtx_ldk_20_config	\
+DK1S10_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring _safe_32,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \
+		  echo "... NIOS 'safe_32' configuration" ; \
+		}
+	@[ -z "$(findstring _standard_32,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
+		  echo "... NIOS 'standard_32' configuration" ; \
+		}
+	@[ -z "$(findstring _mtx_ldk_20,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>include/config.h ; \
+		  echo "... NIOS 'mtx_ldk_20' configuration" ; \
+		}
+	@[ -z "$(findstring DK1S10_config,$@)" ] || \
+		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
+		  echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
+		}
+	@./mkconfig -a DK1S10 nios nios dk1s10 altera
+
+
+#########################################################################
+## MIPS32 AU1X00
+#########################################################################
+dbau1000_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1000 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
+dbau1100_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1100 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
+dbau1500_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
 #########################################################################
 #########################################################################
 
@@ -907,6 +1152,7 @@ clean:
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
 	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
+	rm -f board/trab/trab_fkt board/*/config.tmp
 
 clobber:	clean
 	find . -type f \

README

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000 - 2002
+# (C) Copyright 2000 - 2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -141,30 +141,31 @@ Directory Hierarchy:
 
 - cpu/74xx_7xx	Files specific to Motorola MPC74xx and 7xx CPUs
 - cpu/arm925t	Files specific to ARM	   925	   CPUs
-- cpu/arm926ejs	Files specific to ARM	926	CPUs
+- cpu/arm926ejs Files specific to ARM	926	CPUs
 - cpu/mpc5xx	Files specific to Motorola MPC5xx  CPUs
 - cpu/mpc8xx	Files specific to Motorola MPC8xx  CPUs
 - cpu/mpc824x	Files specific to Motorola MPC824x CPUs
 - cpu/mpc8260	Files specific to Motorola MPC8260 CPU
+- cpu/mpc85xx	Files specific to Motorola MPC85xx CPUs
 - cpu/ppc4xx	Files specific to IBM	   4xx	   CPUs
 
 
-- board/LEOX/   Files specific to boards manufactured by The LEOX team
+- board/LEOX/	Files specific to boards manufactured by The LEOX team
 - board/LEOX/elpt860	Files specific to ELPT860 boards
 - board/RPXClassic
 		Files specific to RPXClassic boards
-- board/RPXlite	Files specific to RPXlite    boards
+- board/RPXlite Files specific to RPXlite    boards
 - board/at91rm9200dk Files specific to AT91RM9200DK boards
 - board/c2mon	Files specific to c2mon	     boards
-- board/cmi	Files specific to cmi        boards
+- board/cmi	Files specific to cmi	     boards
 - board/cogent	Files specific to Cogent     boards
 		(need further configuration)
 		Files specific to CPCIISER4  boards
-- board/cpu86	Files specific to CPU86      boards
+- board/cpu86	Files specific to CPU86	     boards
 - board/cray/	Files specific to boards manufactured by Cray
-- board/cray/L1		Files specific to L1         boards
+- board/cray/L1		Files specific to L1	     boards
 - board/cu824	Files specific to CU824	     boards
-- board/ebony   Files specific to IBM Ebony board
+- board/ebony	Files specific to IBM Ebony board
 - board/eric	Files specific to ERIC	     boards
 - board/esd/	Files specific to boards manufactured by ESD
 - board/esd/adciop	Files specific to ADCIOP     boards
@@ -174,8 +175,8 @@ Directory Hierarchy:
 - board/esd/cpciiser4	Files specific to CPCIISER4  boards
 - board/esd/common	Common files for ESD boards
 - board/esd/dasa_sim	Files specific to DASA_SIM   boards
-- board/esd/du405	Files specific to DU405      boards
-- board/esd/ocrtc	Files specific to OCRTC      boards
+- board/esd/du405	Files specific to DU405	     boards
+- board/esd/ocrtc	Files specific to OCRTC	     boards
 - board/esd/pci405	Files specific to PCI405     boards
 - board/esteem192e
 		Files specific to ESTEEM192E boards
@@ -196,48 +197,59 @@ Directory Hierarchy:
 - board/ivm	Files specific to IVMS8/IVML24 boards
 - board/lantec	Files specific to LANTEC     boards
 - board/lwmon	Files specific to LWMON	     boards
+- board/Marvell Files specific to Marvell development boards
+- board/Marvell/db64360 Files specific to db64360 board
+- board/Marvell/db64460 Files specific to db64460 board
 - board/mbx8xx	Files specific to MBX	     boards
 - board/mpc8260ads
-		Files specific to MPC8260ADS and PQ2FADS-ZU boards
+		Files specific to MPC826xADS and PQ2FADS-ZU/VR boards
+- board/mpc8540ads
+		Files specific to MPC8540ADS boards
+- board/mpc8560ads
+		Files specific to MPC8560ADS boards
 - board/mpl/	Files specific to boards manufactured by MPL
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
 - board/mpl/mip405	Files specific to MIP405     boards
-- board/musenki	Files specific to MUSEKNI    boards
-- board/mvs1	Files specific to MVS1       boards
-- board/nx823   Files specific to NX823      boards
-- board/oxc	Files specific to OXC        boards
+- board/mpl/vcma9	Files specific to VCMA9	     boards
+- board/musenki Files specific to MUSEKNI    boards
+- board/mvs1	Files specific to MVS1	     boards
+- board/nx823	Files specific to NX823	     boards
+- board/oxc	Files specific to OXC	     boards
 - board/omap1510inn
 		Files specific to OMAP 1510 Innovator boards
-- board/omap1610inn  
-		Files specific to OMAP 1610 Innovator boards
-- board/pcippc2	Files specific to PCIPPC2/PCIPPC6 boards
-- board/pm826	Files specific to PM826      boards
+- board/omap1610inn
+		Files specific to OMAP 1610 Innovator and H2 boards
+- board/pcippc2 Files specific to PCIPPC2/PCIPPC6 boards
+- board/pm826	Files specific to PM826	     boards
 - board/ppmc8260
 		Files specific to PPMC8260   boards
+- board/snmc/qs850	Files specific to QS850/823  boards
+- board/snmc/qs860t	Files specific to QS860T     boards
 - board/rpxsuper
 		Files specific to RPXsuper   boards
 - board/rsdproto
 		Files specific to RSDproto   boards
 - board/sandpoint
 		Files specific to Sandpoint  boards
-- board/sbc8260	Files specific to SBC8260    boards
+- board/sbc8260 Files specific to SBC8260    boards
 - board/sacsng	Files specific to SACSng     boards
 - board/siemens Files specific to boards manufactured by Siemens AG
 - board/siemens/CCM	Files specific to CCM	     boards
 - board/siemens/IAD210	Files specific to IAD210     boards
-- board/siemens/SCM	Files specific to SCM        boards
+- board/siemens/SCM	Files specific to SCM	     boards
 - board/siemens/pcu_e	Files specific to PCU_E	     boards
 - board/sixnet	Files specific to SIXNET     boards
 - board/spd8xx	Files specific to SPD8xxTS   boards
 - board/tqm8260 Files specific to TQM8260    boards
 - board/tqm8xx	Files specific to TQM8xxL    boards
-- board/w7o	Files specific to W7O        boards
+- board/w7o	Files specific to W7O	     boards
 - board/walnut405
 		Files specific to Walnut405  boards
-- board/westel/	Files specific to boards manufactured by Westel Wireless
+- board/westel/ Files specific to boards manufactured by Westel Wireless
 - board/westel/amx860	Files specific to AMX860     boards
-- board/utx8245	Files specific to UTX8245   boards
+- board/utx8245 Files specific to UTX8245   boards
+- board/zpc1900 Files specific to Zephyr Engineering ZPC.1900 board
 
 Software Configuration:
 =======================
@@ -304,6 +316,7 @@ The following options need to be configured:
 		CONFIG_MPC823,	CONFIG_MPC850,	CONFIG_MPC855,	CONFIG_MPC860
 	or	CONFIG_MPC5xx
 	or	CONFIG_MPC824X, CONFIG_MPC8260
+	or	CONFIG_MPC85xx
 	or	CONFIG_IOP480
 	or	CONFIG_405GP
 	or	CONFIG_405EP
@@ -323,47 +336,51 @@ The following options need to be configured:
 		PowerPC based boards:
 		---------------------
 
-		CONFIG_ADCIOP,     CONFIG_ICU862      CONFIG_RPXsuper,
-		CONFIG_ADS860,     CONFIG_IP860,      CONFIG_SM850,
-		CONFIG_AMX860,     CONFIG_IPHASE4539, CONFIG_SPD823TS,
-		CONFIG_AR405,      CONFIG_IVML24,     CONFIG_SXNI855T,
-		CONFIG_BAB7xx,     CONFIG_IVML24_128, CONFIG_Sandpoint8240,
-		CONFIG_CANBT,      CONFIG_IVML24_256, CONFIG_Sandpoint8245,
-		CONFIG_CCM,        CONFIG_IVMS8,      CONFIG_TQM823L,
-		CONFIG_CPCI405,    CONFIG_IVMS8_128,  CONFIG_TQM850L,
+		CONFIG_ADCIOP,	   CONFIG_ICU862      CONFIG_RPXsuper,
+		CONFIG_ADS860,	   CONFIG_IP860,      CONFIG_SM850,
+		CONFIG_AMX860,	   CONFIG_IPHASE4539, CONFIG_SPD823TS,
+		CONFIG_AR405,	   CONFIG_IVML24,     CONFIG_SXNI855T,
+		CONFIG_BAB7xx,	   CONFIG_IVML24_128, CONFIG_Sandpoint8240,
+		CONFIG_CANBT,	   CONFIG_IVML24_256, CONFIG_Sandpoint8245,
+		CONFIG_CCM,	   CONFIG_IVMS8,      CONFIG_TQM823L,
+		CONFIG_CPCI405,	   CONFIG_IVMS8_128,  CONFIG_TQM850L,
 		CONFIG_CPCI4052,   CONFIG_IVMS8_256,  CONFIG_TQM855L,
 		CONFIG_CPCIISER4,  CONFIG_LANTEC,     CONFIG_TQM860L,
-		CONFIG_CPU86,      CONFIG_MBX,        CONFIG_TQM8260,
-		CONFIG_CRAYL1,     CONFIG_MBX860T,    CONFIG_TTTech,
-		CONFIG_CU824,      CONFIG_MHPC,       CONFIG_UTX8245,
+		CONFIG_CPU86,	   CONFIG_MBX,	      CONFIG_TQM8260,
+		CONFIG_CRAYL1,	   CONFIG_MBX860T,    CONFIG_TTTech,
+		CONFIG_CU824,	   CONFIG_MHPC,	      CONFIG_UTX8245,
 		CONFIG_DASA_SIM,   CONFIG_MIP405,     CONFIG_W7OLMC,
-		CONFIG_DU405,      CONFIG_MOUSSE,     CONFIG_W7OLMG,
-		CONFIG_ELPPC,      CONFIG_MPC8260ADS, CONFIG_WALNUT405,
-		CONFIG_ERIC,       CONFIG_MUSENKI,    CONFIG_ZUMA,
-		CONFIG_ESTEEM192E, CONFIG_MVS1,       CONFIG_c2mon,
-		CONFIG_ETX094,     CONFIG_NX823,      CONFIG_cogent_mpc8260,
+		CONFIG_DU405,	   CONFIG_MOUSSE,     CONFIG_W7OLMG,
+		CONFIG_ELPPC,	   CONFIG_MPC8260ADS, CONFIG_WALNUT405,
+		CONFIG_ERIC,	   CONFIG_MUSENKI,    CONFIG_ZUMA,
+		CONFIG_ESTEEM192E, CONFIG_MVS1,	      CONFIG_c2mon,
+		CONFIG_ETX094,	   CONFIG_NX823,      CONFIG_cogent_mpc8260,
 		CONFIG_EVB64260,   CONFIG_OCRTC,      CONFIG_cogent_mpc8xx,
-		CONFIG_FADS823,    CONFIG_ORSG,       CONFIG_ep8260,
-		CONFIG_FADS850SAR, CONFIG_OXC,        CONFIG_gw8260,
+		CONFIG_FADS823,	   CONFIG_ORSG,	      CONFIG_ep8260,
+		CONFIG_FADS850SAR, CONFIG_OXC,	      CONFIG_gw8260,
 		CONFIG_FADS860T,   CONFIG_PCI405,     CONFIG_hermes,
-		CONFIG_FLAGADM,    CONFIG_PCIPPC2,    CONFIG_hymod,
-		CONFIG_FPS850L,    CONFIG_PCIPPC6,    CONFIG_lwmon,
-		CONFIG_GEN860T,    CONFIG_PIP405,     CONFIG_pcu_e,
-		CONFIG_GENIETV,    CONFIG_PM826,      CONFIG_ppmc8260,
-		CONFIG_GTH,        CONFIG_RPXClassic, CONFIG_rsdproto,
-		CONFIG_IAD210,     CONFIG_RPXlite,    CONFIG_sbc8260,
-		CONFIG_EBONY,      CONFIG_sacsng,     CONFIG_FPS860L,
-		CONFIG_V37,        CONFIG_ELPT860,    CONFIG_CMI,
-		CONFIG_NETVIA,     CONFIG_RBC823
+		CONFIG_FLAGADM,	   CONFIG_PCIPPC2,    CONFIG_hymod,
+		CONFIG_FPS850L,	   CONFIG_PCIPPC6,    CONFIG_lwmon,
+		CONFIG_GEN860T,	   CONFIG_PIP405,     CONFIG_pcu_e,
+		CONFIG_GENIETV,	   CONFIG_PM826,      CONFIG_ppmc8260,
+		CONFIG_GTH,	   CONFIG_RPXClassic, CONFIG_rsdproto,
+		CONFIG_IAD210,	   CONFIG_RPXlite,    CONFIG_sbc8260,
+		CONFIG_EBONY,	   CONFIG_sacsng,     CONFIG_FPS860L,
+		CONFIG_V37,	   CONFIG_ELPT860,    CONFIG_CMI,
+		CONFIG_NETVIA,	   CONFIG_RBC823,     CONFIG_ZPC1900,
+		CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850,
+		CONFIG_QS823,	   CONFIG_QS860T,     CONFIG_DB64360,
+		CONFIG_DB64460,	   CONFIG_DUET_ADS
 
 		ARM based boards:
 		-----------------
 
-		CONFIG_HHP_CRADLE,  CONFIG_DNP1110,    CONFIG_EP7312,
-		CONFIG_IMPA7,       CONFIG_LART,       CONFIG_LUBBOCK,
-		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610
-		CONFIG_SHANNON,     CONFIG_SMDK2400,   CONFIG_SMDK2410,
-		CONFIG_TRAB,	    CONFIG_AT91RM9200DK
+		CONFIG_HHP_CRADLE,  CONFIG_DNP1110,	CONFIG_EP7312,
+		CONFIG_IMPA7,	    CONFIG_LART,	CONFIG_LUBBOCK,
+		CONFIG_INNOVATOROMAP1510,      CONFIG_INNOVATOROMAP1610,
+		CONFIG_H2_OMAP1610, CONFIG_SHANNON,	CONFIG_SMDK2400,
+		CONFIG_SMDK2410,    CONFIG_TRAB,	CONFIG_VCMA9,
+		CONFIG_AT91RM9200DK
 
 
 - CPU Module Type: (if CONFIG_COGENT is defined)
@@ -391,20 +408,37 @@ The following options need to be configured:
 		CONFIG_ADSTYPE
 		Possible values are:
 			CFG_8260ADS	- original MPC8260ADS
-			CFG_8266ADS	- MPC8266ADS (untested)
-			CFG_PQ2FADS	- PQ2FADS-ZU
+			CFG_8266ADS	- MPC8266ADS
+			CFG_PQ2FADS	- PQ2FADS-ZU or PQ2FADS-VR
 
 
 - MPC824X Family Member (if CONFIG_MPC824X is defined)
-	Define exactly one of
-	CONFIG_MPC8240, CONFIG_MPC8245
+		Define exactly one of
+		CONFIG_MPC8240, CONFIG_MPC8245
 
-- 8xx CPU Options: (if using an 8xx cpu)
+- 8xx CPU Options: (if using an MPC8xx cpu)
 		Define one or more of
-		CONFIG_8xx_GCLK_FREQ	- if get_gclk_freq() can not work e.g.
-					  no 32KHz reference PIT/RTC clock
+		CONFIG_8xx_GCLK_FREQ	- if get_gclk_freq() cannot work
+					  e.g. if there is no 32KHz
+					  reference PIT/RTC clock
 
-- Clock Interface:
+- 859/866 CPU options: (if using a MPC859 or MPC866 CPU):
+		CFG_866_OSCCLK
+		CFG_866_CPUCLK_MIN
+		CFG_866_CPUCLK_MAX
+		CFG_866_CPUCLK_DEFAULT
+			See doc/README.MPC866
+
+		CFG_MEASURE_CPUCLK
+
+		Define this to measure the actual CPU clock instead
+		of relying on the correctness of the configured
+		values. Mostly useful for board bringup to make sure
+		the PLL is locked at the intended frequency. Note
+		that this requires a (stable) reference clock (32 kHz
+		RTC clock),
+
+- Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 
 		U-Boot stores all clock information in Hz
@@ -414,11 +448,16 @@ The following options need to be configured:
 		"clocks_in_mhz" can be defined so that U-Boot
 		converts clock data to MHZ before passing it to the
 		Linux kernel.
-
 		When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
 		"clocks_in_mhz=1" is  automatically  included  in  the
 		default environment.
 
+		CONFIG_MEMSIZE_IN_BYTES		[relevant for MIPS only]
+
+		When transfering memsize parameter to linux, some versions
+		expect it to be in bytes, others in MB.
+		Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
+
 - Console Interface:
 		Depending on board, define exactly one serial port
 		(like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
@@ -441,11 +480,11 @@ The following options need to be configured:
 						bit-blit (cf. smiLynxEM)
 			VIDEO_VISIBLE_COLS	visible pixel columns
 						(cols=pitch)
-			VIDEO_VISIBLE_ROWS      visible pixel rows
-			VIDEO_PIXEL_SIZE        bytes per pixel
+			VIDEO_VISIBLE_ROWS	visible pixel rows
+			VIDEO_PIXEL_SIZE	bytes per pixel
 			VIDEO_DATA_FORMAT	graphic data format
 						(0-5, cf. cfb_console.c)
-			VIDEO_FB_ADRS           framebuffer address
+			VIDEO_FB_ADRS		framebuffer address
 			VIDEO_KBD_INIT_FCT	keyboard int fct
 						(i.e. i8042_kbd_init())
 			VIDEO_TSTC_FCT		test char fct
@@ -472,10 +511,16 @@ The following options need to be configured:
 		default i/o. Serial console can be forced with
 		environment 'console=serial'.
 
+		When CONFIG_SILENT_CONSOLE is defined, all console
+		messages (by U-Boot and Linux!) can be silenced with
+		the "silent" environment variable. See
+		doc/README.silent for more information.
+
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
 		CFG_BAUDRATE_TABLE, see below.
+		CFG_BRGCLK_PRESCALE, baudrate prescale
 
 - Interrupt driven serial port input:
 		CONFIG_SERIAL_SOFTWARE_FIFO
@@ -572,13 +617,18 @@ The following options need to be configured:
 		#define enables commands:
 		-------------------------
 		CFG_CMD_ASKENV	* ask for env variable
+		CFG_CMD_AUTOSCRIPT Autoscript Support
 		CFG_CMD_BDI	  bdinfo
 		CFG_CMD_BEDBUG	  Include BedBug Debugger
+		CFG_CMD_BMP	* BMP support
 		CFG_CMD_BOOTD	  bootd
 		CFG_CMD_CACHE	  icache, dcache
 		CFG_CMD_CONSOLE	  coninfo
 		CFG_CMD_DATE	* support for RTC, date/time...
 		CFG_CMD_DHCP	  DHCP support
+		CFG_CMD_DIAG	* Diagnostics
+		CFG_CMD_DOC	* Disk-On-Chip Support
+		CFG_CMD_DTT	  Digital Therm and Thermostat
 		CFG_CMD_ECHO	* echo arguments
 		CFG_CMD_EEPROM	* EEPROM read/write support
 		CFG_CMD_ELF	  bootelf, bootvx
@@ -588,27 +638,38 @@ The following options need to be configured:
 		CFG_CMD_FDOS	* Dos diskette Support
 		CFG_CMD_FLASH	  flinfo, erase, protect
 		CFG_CMD_FPGA	  FPGA device initialization support
+		CFG_CMD_HWFLOW	* RTS/CTS hw flow control
 		CFG_CMD_I2C	* I2C serial bus support
 		CFG_CMD_IDE	* IDE harddisk support
 		CFG_CMD_IMI	  iminfo
+		CFG_CMD_IMLS	  List all found images
 		CFG_CMD_IMMAP	* IMMR dump support
 		CFG_CMD_IRQ	* irqinfo
+		CFG_CMD_ITEST	* Integer/string test of 2 values
+		CFG_CMD_JFFS2	* JFFS2 Support
 		CFG_CMD_KGDB	* kgdb
 		CFG_CMD_LOADB	  loadb
 		CFG_CMD_LOADS	  loads
 		CFG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 				  loop, mtest
+		CFG_CMD_MISC	  Misc functions like sleep etc
 		CFG_CMD_MMC	  MMC memory mapped support
 		CFG_CMD_MII	  MII utility commands
+		CFG_CMD_NAND	* NAND support
 		CFG_CMD_NET	  bootp, tftpboot, rarpboot
 		CFG_CMD_PCI	* pciinfo
 		CFG_CMD_PCMCIA	* PCMCIA support
+		CFG_CMD_PING	* send ICMP ECHO_REQUEST to network host
+		CFG_CMD_PORTIO	* Port I/O
 		CFG_CMD_REGINFO * Register dump
 		CFG_CMD_RUN	  run command in env variable
+		CFG_CMD_SAVES	  save S record dump
 		CFG_CMD_SCSI	* SCSI Support
+		CFG_CMD_SDRAM	* print SDRAM configuration information
 		CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
 		CFG_CMD_SPI	* SPI serial bus support
 		CFG_CMD_USB	* USB support
+		CFG_CMD_VFD	* VFD support (TRAB)
 		CFG_CMD_BSP	* Board SPecific functions
 		-----------------------------------------------
 		CFG_CMD_ALL	all
@@ -791,9 +852,9 @@ The following options need to be configured:
 		Following modes are supported  (* is default):
 
 			    800x600  1024x768  1280x1024
-	      256  (8bit)     303*      305       307
-	    65536 (16bit)     314       317       31a
-	16,7 Mill (24bit)     315       318       31b
+	      256  (8bit)     303*	305	  307
+	    65536 (16bit)     314	317	  31a
+	16,7 Mill (24bit)     315	318	  31b
 		(i.e. setenv videomode 317; saveenv; reset;)
 
 		CONFIG_VIDEO_SED13806
@@ -815,13 +876,18 @@ The following options need to be configured:
 		display); also select one of the supported displays
 		by defining one of these:
 
-		CONFIG_NEC_NL6648AC33:
+		CONFIG_NEC_NL6448AC33:
 
-			NEC NL6648AC33-18. Active, color, single scan.
+			NEC NL6448AC33-18. Active, color, single scan.
 
-		CONFIG_NEC_NL6648BC20
+		CONFIG_NEC_NL6448BC20
 
-			NEC NL6648BC20-08. 6.5", 640x480.
+			NEC NL6448BC20-08. 6.5", 640x480.
+			Active, color, single scan.
+
+		CONFIG_NEC_NL6448BC33_54
+
+			NEC NL6448BC33-54. 10.4", 640x480.
 			Active, color, single scan.
 
 		CONFIG_SHARP_16x9
@@ -870,9 +936,9 @@ The following options need to be configured:
 		images is included. If not, only uncompressed and gzip
 		compressed images are supported.
 
-                NOTE: the bzip2 algorithm requires a lot of RAM, so
-                the malloc area (as defined by CFG_MALLOC_LEN) should
-                be at least 4MB.
+		NOTE: the bzip2 algorithm requires a lot of RAM, so
+		the malloc area (as defined by CFG_MALLOC_LEN) should
+		be at least 4MB.
 
 - Ethernet address:
 		CONFIG_ETHADDR
@@ -967,7 +1033,7 @@ The following options need to be configured:
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 
-		CONFIG_HARD_I2C	selects the CPM hardware driver for I2C.
+		CONFIG_HARD_I2C selects the CPM hardware driver for I2C.
 
 		CONFIG_SOFT_I2C configures u-boot to use a software (aka
 		bit-banging) driver instead of CPM or similar hardware
@@ -997,7 +1063,7 @@ The following options need to be configured:
 		(Optional). Any commands necessary to enable the I2C
 		controller or configure ports.
 
-		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=  PB_SCL)
+		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)
 
 		I2C_PORT
 
@@ -1035,7 +1101,7 @@ The following options need to be configured:
 
 		eg: #define I2C_SDA(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
 
 		I2C_SCL(bit)
 
@@ -1044,7 +1110,7 @@ The following options need to be configured:
 
 		eg: #define I2C_SCL(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
 
 		I2C_DELAY
 
@@ -1093,60 +1159,6 @@ The following options need to be configured:
 
 		CONFIG_FPGA
 
-		Used to specify the types of FPGA devices. For
-		example,
-		#define CONFIG_FPGA  CFG_XILINX_VIRTEX2
-
-		CFG_FPGA_PROG_FEEDBACK
-
-		Enable printing of hash marks during FPGA
-		configuration.
-
-		CFG_FPGA_CHECK_BUSY
-
-		Enable checks on FPGA configuration interface busy
-		status by the configuration function. This option
-		will require a board or device specific function to
-		be written.
-
-		CONFIG_FPGA_DELAY
-
-		If defined, a function that provides delays in the
-		FPGA configuration driver.
-
-		CFG_FPGA_CHECK_CTRLC
-
-		Allow Control-C to interrupt FPGA configuration
-
-		CFG_FPGA_CHECK_ERROR
-
-		Check for configuration errors during FPGA bitfile
-		loading. For example, abort during Virtex II
-		configuration if the INIT_B line goes low (which
-		indicated a CRC error).
-
-		CFG_FPGA_WAIT_INIT
-
-		Maximum time to wait for the INIT_B line to deassert
-		after PROB_B has been deasserted during a Virtex II
-		FPGA configuration sequence. The default time is 500 mS.
-
-		CFG_FPGA_WAIT_BUSY
-
-		Maximum time to wait for BUSY to deassert during
-		Virtex II FPGA configuration. The default is 5 mS.
-
-		CFG_FPGA_WAIT_CONFIG
-
-		Time to wait after FPGA configuration. The default is
-		200 mS.
-
-- FPGA Support:	CONFIG_FPGA_COUNT
-
-		Specify the number of FPGA devices to support.
-
-		CONFIG_FPGA
-
 		Used to specify the types of FPGA devices.  For example,
 		#define CONFIG_FPGA  CFG_XILINX_VIRTEX2
 
@@ -1313,7 +1325,7 @@ The following options need to be configured:
 		of the backslashes before semicolons and special
 		symbols.
 
-- Default Environment
+- Default Environment:
 		CONFIG_EXTRA_ENV_SETTINGS
 
 		Define this to contain any number of null terminated
@@ -1339,14 +1351,28 @@ The following options need to be configured:
 		the environment like the autoscript function or the
 		boot command first.
 
-- DataFlash Support
+- DataFlash Support:
 		CONFIG_HAS_DATAFLASH
 
 		Defining this option enables DataFlash features and
 		allows to read/write in Dataflash via the standard
 		commands cp, md...
 
-- Show boot progress
+- SystemACE Support:
+		CONFIG_SYSTEMACE
+
+		Adding this option adds support for Xilinx SystemACE
+		chips attached via some sort of local bus. The address
+		of the chip must alsh be defined in the
+		CFG_SYSTEMACE_BASE macro. For example:
+
+		#define CONFIG_SYSTEMACE
+		#define CFG_SYSTEMACE_BASE 0xf0000000
+
+		When SystemACE support is added, the "ace" device type
+		becomes available to the fat commands, i.e. fatls.
+
+- Show boot progress:
 		CONFIG_SHOW_BOOT_PROGRESS
 
 		Defining this option allows to add some board-
@@ -1358,11 +1384,11 @@ The following options need to be configured:
 
   Arg	Where			When
     1	common/cmd_bootm.c	before attempting to boot an image
-   -1	common/cmd_bootm.c	Image header has bad     magic number
+   -1	common/cmd_bootm.c	Image header has bad	 magic number
     2	common/cmd_bootm.c	Image header has correct magic number
-   -2	common/cmd_bootm.c	Image header has bad     checksum
+   -2	common/cmd_bootm.c	Image header has bad	 checksum
     3	common/cmd_bootm.c	Image header has correct checksum
-   -3	common/cmd_bootm.c	Image data   has bad     checksum
+   -3	common/cmd_bootm.c	Image data   has bad	 checksum
     4	common/cmd_bootm.c	Image data   has correct checksum
    -4	common/cmd_bootm.c	Image is for unsupported architecture
     5	common/cmd_bootm.c	Architecture check OK
@@ -1375,10 +1401,10 @@ The following options need to be configured:
     8	common/cmd_bootm.c	Image Type check OK
    -9	common/cmd_bootm.c	Unsupported OS (not Linux, BSD, VxWorks, QNX)
     9	common/cmd_bootm.c	Start initial ramdisk verification
-  -10	common/cmd_bootm.c	Ramdisk header has bad     magic number
-  -11	common/cmd_bootm.c	Ramdisk header has bad     checksum
+  -10	common/cmd_bootm.c	Ramdisk header has bad	   magic number
+  -11	common/cmd_bootm.c	Ramdisk header has bad	   checksum
    10	common/cmd_bootm.c	Ramdisk header is OK
-  -12	common/cmd_bootm.c	Ramdisk data   has bad     checksum
+  -12	common/cmd_bootm.c	Ramdisk data   has bad	   checksum
    11	common/cmd_bootm.c	Ramdisk data   has correct checksum
    12	common/cmd_bootm.c	Ramdisk verification complete, start loading
   -13	common/cmd_bootm.c	Wrong Image Type (not PPC Linux Ramdisk)
@@ -1386,6 +1412,10 @@ The following options need to be configured:
    14	common/cmd_bootm.c	No initial ramdisk, no multifile, continue.
    15	common/cmd_bootm.c	All preparation done, transferring control to OS
 
+  -30   lib_ppc/board.c	        Fatal error, hang the system
+  -31   post/post.c	        POST test failed, detected by post_output_backlog()
+  -32   post/post.c	        POST test failed, detected by post_run_single()
+
    -1	common/cmd_doc.c	Bad usage of "doc" command
    -1	common/cmd_doc.c	No boot device
    -1	common/cmd_doc.c	Unknown Chip ID on boot device
@@ -1400,7 +1430,13 @@ The following options need to be configured:
    -1	common/cmd_ide.c	Read Error on boot device
    -1	common/cmd_ide.c	Image header has bad magic number
 
-   -1	common/cmd_nvedit.c	Environment not changable, but has bad CRC
+   -1	common/cmd_nand.c	Bad usage of "nand" command
+   -1	common/cmd_nand.c	No boot device
+   -1	common/cmd_nand.c	Unknown Chip ID on boot device
+   -1	common/cmd_nand.c	Read Error on boot device
+   -1	common/cmd_nand.c	Image header has bad magic number
+
+   -1	common/env_common.c	Environment has a bad CRC, using default
 
 
 Modem Support:
@@ -1420,6 +1456,19 @@ Modem Support:
 		Enables debugging stuff (char screen[1024], dbg())
 		for modem support. Useful only with BDI2000.
 
+- Interrupt support (PPC):
+
+		There are common interrupt_init() and timer_interrupt()
+		for all PPC archs. interrupt_init() calls interrupt_init_cpu()
+		for cpu specific initialization. interrupt_init_cpu()
+		should set decrementer_count to appropriate value. If
+		cpu resets decrementer automatically after interrupt
+		(ppc4xx) it should set decrementer_count to zero.
+		timer_interrupt() calls timer_interrupt_cpu() for cpu
+		specific handling. If board has watchdog / status_led
+		/ other_activity_monitor it works automatically from
+		general timer_interrupt().
+
 - General:
 
 		In the target system modem support is enabled when a
@@ -1482,6 +1531,10 @@ Configuration Settings:
 - CFG_ALT_MEMTEST:
 		Enable an alternate, more extensive memory test.
 
+- CFG_MEMTEST_SCRATCH:
+		Scratch address used by the alternate memory test
+		You only need to set this if address zero isn't writeable
+
 - CFG_TFTP_LOADADDR:
 		Default load address for network file downloads
 
@@ -1556,7 +1609,11 @@ Configuration Settings:
 
 - CFG_FLASH_CFI:
 		Define if the flash driver uses extra elements in the
-		common flash structure for storing flash geometry
+		common flash structure for storing flash geometry.
+
+- CFG_FLASH_CFI_DRIVER
+		This option also enables the building of the cfi_flash driver
+		in the drivers directory
 
 - CFG_RX_ETH_BUFFER:
 		Defines the number of ethernet receive buffers. On some
@@ -1687,7 +1744,7 @@ to save the current settings.
 
 	- CFG_EEPROM_PAGE_WRITE_DELAY_MS:
 	  If defined, the number of milliseconds to delay between
-	  page writes.  The default is zero milliseconds.
+	  page writes.	The default is zero milliseconds.
 
 	- CFG_I2C_EEPROM_ADDR_LEN:
 	  The length in bytes of the EEPROM memory array address.  Note
@@ -1697,6 +1754,20 @@ to save the current settings.
 	  The size in bytes of the EEPROM device.
 
 
+- CFG_ENV_IS_IN_DATAFLASH:
+
+	Define this if you have a DataFlash memory device which you
+	want to use for the environment.
+
+	- CFG_ENV_OFFSET:
+	- CFG_ENV_ADDR:
+	- CFG_ENV_SIZE:
+
+	  These three #defines specify the offset and size of the
+	  environment area within the total memory of your DataFlash placed
+	  at the specified address.
+
+
 - CFG_SPI_INIT_OFFSET
 
 	Defines offset to the initial SPI buffer area in DPRAM. The
@@ -1723,6 +1794,14 @@ Note: once the monitor has been relocated, then it will complain if
 the default environment is used; a new CRC is computed as soon as you
 use the "saveenv" command to store a valid environment.
 
+- CFG_FAULT_ECHO_LINK_DOWN:
+		Echo the inverted Ethernet link state to the fault LED.
+
+		Note: If this option is active, then CFG_FAULT_MII_ADDR
+		      also needs to be defined.
+
+- CFG_FAULT_MII_ADDR:
+		MII address of the PHY to check for the Ethernet link state.
 
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
@@ -1733,9 +1812,9 @@ Low Level (hardware related) configuration options:
 - CFG_DEFAULT_IMMR:
 		Default address of the IMMR after system reset.
 
-                Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
-                and RPXsuper) to be able to adjust the position of
-                the IMMR register after a reset.
+		Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
+		and RPXsuper) to be able to adjust the position of
+		the IMMR register after a reset.
 
 - Floppy Disk Support:
 		CFG_FDC_DRIVE_NUMBER
@@ -1883,7 +1962,7 @@ change it to:
 	CROSS_COMPILE = ppc_4xx-
 
 
-U-Boot is intended to be  simple  to  build.  After  installing  the
+U-Boot is intended to be  simple  to  build.  After  installing	 the
 sources	 you must configure U-Boot for one specific board type. This
 is done by typing:
 
@@ -1909,7 +1988,10 @@ configurations; the following names are supported:
     GEN860T_config	  EBONY_config		FPS860L_config
     ELPT860_config	  cmi_mpc5xx_config	NETVIA_config
     at91rm9200dk_config	  omap1510inn_config	MPC8260ADS_config
-    omap1610inn_config
+    omap1610inn_config	  ZPC1900_config	MPC8540ADS_config
+    MPC8560ADS_config	  QS850_config		QS823_config
+    QS860T_config	  DUET_ADS_config	omap1610h2_config
+
 Note: for some board special configuration names may exist; check  if
       additional  information is available from the board vendor; for
       instance, the TQM8xxL systems run normally at 50 MHz and use  a
@@ -2024,15 +2106,15 @@ mw	- memory write (fill)
 cp	- memory copy
 cmp	- memory compare
 crc32	- checksum calculation
-imd     - i2c memory display
-imm     - i2c memory modify (auto-incrementing)
-inm     - i2c memory modify (constant address)
-imw     - i2c memory write (fill)
-icrc32  - i2c checksum calculation
-iprobe  - probe to discover valid I2C chip addresses
-iloop   - infinite loop on address range
-isdram  - print SDRAM configuration information
-sspi    - SPI utility commands
+imd	- i2c memory display
+imm	- i2c memory modify (auto-incrementing)
+inm	- i2c memory modify (constant address)
+imw	- i2c memory write (fill)
+icrc32	- i2c checksum calculation
+iprobe	- probe to discover valid I2C chip addresses
+iloop	- infinite loop on address range
+isdram	- print SDRAM configuration information
+sspi	- SPI utility commands
 base	- print or set address offset
 printenv- print environment variables
 setenv	- set environment variables
@@ -2275,8 +2357,8 @@ defines the following image properties:
   LynxOS, pSOS, QNX, RTEMS, ARTOS;
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS).
 * Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
-  IA64, MIPS, MIPS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: PowerPC).
+  IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, Intel x86, MIPS, NIOS, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -2361,7 +2443,7 @@ Example:
 	make uImage
 
 The "uImage" build target uses a special tool (in 'tools/mkimage') to
-encapsulate a compressed Linux kernel image with header  information,
+encapsulate a compressed Linux kernel image with header	 information,
 CRC32 checksum etc. for use with U-Boot. This is what we are doing:
 
 * build a standard "vmlinux" kernel image (in ELF binary format):
@@ -2748,9 +2830,9 @@ use "cu" for S-Record download ("loads" command).
 Nevertheless, if you absolutely want to use it try adding this
 configuration to your "File transfer protocols" section:
 
-	   Name    Program                      Name U/D FullScr IO-Red. Multi
-	X  kermit  /usr/bin/kermit -i -l %l -s   Y    U    Y       N      N
-	Y  kermit  /usr/bin/kermit -i -l %l -r   N    D    Y       N      N
+	   Name	   Program			Name U/D FullScr IO-Red. Multi
+	X  kermit  /usr/bin/kermit -i -l %l -s	 Y    U	   Y	   N	  N
+	Y  kermit  /usr/bin/kermit -i -l %l -r	 N    D	   Y	   N	  N
 
 
 NetBSD Notes:
@@ -2806,7 +2888,7 @@ models provide on-chip memory (like the IMMR area on MPC8xx and
 MPC826x processors), on others (parts of) the data cache can be
 locked as (mis-) used as memory, etc.
 
-	Chris Hallinan posted a good summary of  these  issues  to  the
+	Chris Hallinan posted a good summary of	 these	issues	to  the
 	u-boot-users mailing list:
 
 	Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
@@ -2875,7 +2957,7 @@ For PowerPC, the following registers have specific use:
 	R1:	stack pointer
 	R2:	TOC pointer
 	R3-R4:	parameter passing and return values
-	R5-R10:	parameter passing
+	R5-R10: parameter passing
 	R13:	small data area pointer
 	R30:	GOT pointer
 	R31:	frame pointer
@@ -3018,7 +3100,7 @@ int main (int argc, char *argv[])
 
 	while (learning) {
 		Read the README file in the top level directory;
-		Read http://www.denx.de/re/DPLG.html
+		Read http://www.denx.de/twiki/bin/view/DULG/Manual ;
 		Read the source, Luke;
 	}
 
@@ -3062,6 +3144,13 @@ Please note that U-Boot is implemented in C (and to some small parts
 in Assembler); no C++ is used, so please do not use C++ style
 comments (//) in your code.
 
+Please also stick to the following formatting rules:
+- remove any trailing white space
+- use TAB characters for indentation, not spaces
+- make sure NOT to use DOS '\r\n' line feeds
+- do not add more than 2 empty lines to source files
+- do not add trailing empty lines to source files
+
 Submissions which do not conform to the standards may be returned
 with a request to reformat the changes.
 

board/LEOX/elpt860/elpt860.c

@@ -33,7 +33,7 @@
 /*
 ** Note 1: In this file, you have to provide the following functions:
 ** ------
-**              int             board_pre_init(void)
+**              int             board_early_init_f(void)
 **              int             checkboard(void)
 **              long int        initdram(int board_type)
 ** called from 'board_init_f()' into 'common/board.c'
@@ -53,89 +53,87 @@ static long int dram_size (long int, long int *, long int);
 
 #define	_NOT_USED_	0xFFFFFFFF
 
-const uint init_sdram_table[] =
-{
-  /*
-   * Single Read. (Offset 0 in UPMA RAM)
-   */
-  0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
-  0xFFFFFC04, /* last */
-  /*
-   * SDRAM Initialization (offset 5 in UPMA RAM)
-   *
-   * This is no UPM entry point. The following definition uses
-   * the remaining space to establish an initialization
-   * sequence, which is executed by a RUN command.
-   *
-   */
-  0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,  /* last */
-  /*
-   * Burst Read. (Offset 8 in UPMA RAM)
-   */
-  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-  0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
-  0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
-  /*
-   * Single Write. (Offset 18 in UPMA RAM)
-   */
-  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
-  0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
-  /*
-   * Burst Write. (Offset 20 in UPMA RAM)
-   */
-  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-  0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
-  0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
-  0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
+const uint init_sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
+	0xFFFFFC04,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,	/* last */
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04,	/* last */
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
+	0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05,	/* last */
 };
 
-const uint sdram_table[] =
-{
-  /*
-   * Single Read. (Offset 0 in UPMA RAM)
-   */
-  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
-  0xFF0FFC00, /* last */
-  /*
-   * SDRAM Initialization (offset 5 in UPMA RAM)
-   *
-   * This is no UPM entry point. The following definition uses
-   * the remaining space to establish an initialization
-   * sequence, which is executed by a RUN command.
-   *
-   */
-  0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
-  /*
-   * Burst Read. (Offset 8 in UPMA RAM)
-   */
-  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
-  0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
-  0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
-  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
-  /*
-   * Single Write. (Offset 18 in UPMA RAM)
-   */
-  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
-  0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
-  _NOT_USED_,
-  /*
-   * Burst Write. (Offset 20 in UPMA RAM)
-   */
-  0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
-  0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
-  0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
-  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
-  /*
-   * Refresh  (Offset 30 in UPMA RAM)
-   */
-  0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-  0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
-  0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
-  /*
-   * Exception. (Offset 3c in UPMA RAM)
-   */
-  0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+	0xFF0FFC00,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+	0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
+	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
+	0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05,	/* last */
+	_NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
+	0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
+	0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04,	/* last */
 };
 
 /* ------------------------------------------------------------------------- */
@@ -147,19 +145,18 @@ const uint sdram_table[] =
 /*
  * Very early board init code (fpga boot, etc.)
  */
-int
-board_pre_init (void)
+int board_early_init_f (void)
 {
-  volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
-  /*
-   * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
-   */
-  immr->im_ioport.iop_pcdat &= ~CFG_DS1;   /* PCDAT (DS1 = 0)                */
-  immr->im_ioport.iop_pcpar &= ~CFG_DS1;   /* PCPAR (0=general purpose I/O)  */
-  immr->im_ioport.iop_pcdir |=  CFG_DS1;   /* PCDIR (I/O: 0=input, 1=output) */
+	/*
+	 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
+	 */
+	immr->im_ioport.iop_pcdat &= ~CFG_DS1;	/* PCDAT (DS1 = 0)                */
+	immr->im_ioport.iop_pcpar &= ~CFG_DS1;	/* PCPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_pcdir |= CFG_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
 
-  return ( 0 );    /* success */
+	return (0);		/* success */
 }
 
 /*
@@ -170,150 +167,143 @@ board_pre_init (void)
  * Return 1 if no second DRAM bank, otherwise returns 0
  */
 
-int
-checkboard (void)
+int checkboard (void)
 {
-    unsigned char *s = getenv("serial#");
+	unsigned char *s = getenv ("serial#");
 
-    if ( !s || strncmp(s, "ELPT860", 7) )
-      printf ("### No HW ID - assuming ELPT860\n");
+	if (!s || strncmp (s, "ELPT860", 7))
+		printf ("### No HW ID - assuming ELPT860\n");
 
-    return ( 0 );    /* success */
+	return (0);		/* success */
 }
 
 /* ------------------------------------------------------------------------- */
 
-long int
-initdram (int board_type)
+long int initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
-    long int              size8, size9;
-    long int              size_b0 = 0;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
 
-    /*
-     * This sequence initializes SDRAM chips on ELPT860 board
-     */
-    upmconfig(UPMA, (uint *)init_sdram_table,
-	      sizeof(init_sdram_table)/sizeof(uint));
+	/*
+	 * This sequence initializes SDRAM chips on ELPT860 board
+	 */
+	upmconfig (UPMA, (uint *) init_sdram_table,
+		   sizeof (init_sdram_table) / sizeof (uint));
 
-    memctl->memc_mptpr = 0x0200;
-    memctl->memc_mamr  = 0x18002111;
+	memctl->memc_mptpr = 0x0200;
+	memctl->memc_mamr = 0x18002111;
 
-    memctl->memc_mar   = 0x00000088;
-    memctl->memc_mcr   = 0x80002000;	/* CS1: SDRAM bank 0 */
+	memctl->memc_mar = 0x00000088;
+	memctl->memc_mcr = 0x80002000;	/* CS1: SDRAM bank 0 */
 
-    upmconfig(UPMA, (uint *)sdram_table,
-	      sizeof(sdram_table)/sizeof(uint));
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
 
-    /*
-     * Preliminary prescaler for refresh (depends on number of
-     * banks): This value is selected for four cycles every 62.4 us
-     * with two SDRAM banks or four cycles every 31.2 us with one
-     * bank. It will be adjusted after memory sizing.
-     */
-    memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
 
-    /*
-     * The following value is used as an address (i.e. opcode) for
-     * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
-     * the port size is 32bit the SDRAM does NOT "see" the lower two
-     * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
-     * MICRON SDRAMs:
-     * ->    0 00 010 0 010
-     *       |  |   | |   +- Burst Length = 4
-     *       |  |   | +----- Burst Type   = Sequential
-     *       |  |   +------- CAS Latency  = 2
-     *       |  +----------- Operating Mode = Standard
-     *       +-------------- Write Burst Mode = Programmed Burst Length
-     */
-    memctl->memc_mar   = 0x00000088;
+	/*
+	 * The following value is used as an address (i.e. opcode) for
+	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+	 * the port size is 32bit the SDRAM does NOT "see" the lower two
+	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+	 * MICRON SDRAMs:
+	 * ->    0 00 010 0 010
+	 *       |  |   | |   +- Burst Length = 4
+	 *       |  |   | +----- Burst Type   = Sequential
+	 *       |  |   +------- CAS Latency  = 2
+	 *       |  +----------- Operating Mode = Standard
+	 *       +-------------- Write Burst Mode = Programmed Burst Length
+	 */
+	memctl->memc_mar = 0x00000088;
 
-    /*
-     * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
-     * preliminary addresses - these have to be modified after the
-     * SDRAM size has been determined.
-     */
-    memctl->memc_or1   = CFG_OR1_PRELIM;
-    memctl->memc_br1   = CFG_BR1_PRELIM;
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
 
-    memctl->memc_mamr  = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
-    udelay (200);
+	udelay (200);
 
-    /* perform SDRAM initializsation sequence */
+	/* perform SDRAM initializsation sequence */
 
-    memctl->memc_mcr   = 0x80002105;	/* CS1: SDRAM bank 0 */
-    udelay (1);
-    memctl->memc_mcr   = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
-    udelay (1);
+	memctl->memc_mcr = 0x80002105;	/* CS1: SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
+	udelay (1);
 
-    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
 
-    udelay (1000);
-
-    /*
-     * Check Bank 0 Memory Size for re-configuration
-     *
-     * try 8 column mode
-     */
-    size8 = dram_size (CFG_MAMR_8COL,
-		       (ulong *) SDRAM_BASE1_PRELIM,
-		       SDRAM_MAX_SIZE);
-
-    udelay (1000);
-
-    /*
-     * try 9 column mode
-     */
-    size9 = dram_size (CFG_MAMR_9COL,
-		       (ulong *) SDRAM_BASE1_PRELIM,
-		       SDRAM_MAX_SIZE);
-
-    if ( size8 < size9 )    /* leave configuration at 9 columns	*/
-      {
-	size_b0 = size9;
-	/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
-      }
-    else                  /* back to 8 columns			*/
-      {
-	size_b0 = size8;
-	memctl->memc_mamr = CFG_MAMR_8COL;
-	udelay (500);
-	/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
-      }
-
-    udelay (1000);
-
-    /*
-     * Adjust refresh rate depending on SDRAM type, both banks
-     * For types > 128 MBit leave it at the current (fast) rate
-     */
-    if ( size_b0 < 0x02000000 )
-      {
-	/* reduce to 15.6 us (62.4 us / quad) */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
 	udelay (1000);
-      }
 
-    /*
-     * Final mapping: map bigger bank first
-     */
-    memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-    memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL,
+			   (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 
-    {
-      unsigned long reg;
+	udelay (1000);
 
-      /* adjust refresh rate depending on SDRAM type, one bank */
-      reg = memctl->memc_mptpr;
-      reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
-      memctl->memc_mptpr = reg;
-    }
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL,
+			   (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 
-    udelay(10000);
+	if (size8 < size9) {	/* leave configuration at 9 columns       */
+		size_b0 = size9;
+		/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
+	} else {		/* back to 8 columns                      */
 
-    return (size_b0);
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if (size_b0 < 0x02000000) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	{
+		unsigned long reg;
+
+		/* adjust refresh rate depending on SDRAM type, one bank */
+		reg = memctl->memc_mptpr;
+		reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+		memctl->memc_mptpr = reg;
+	}
+
+	udelay (10000);
+
+	return (size_b0);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -327,54 +317,14 @@ initdram (int board_type)
  */
 
 static long int
-dram_size (long int   mamr_value,
-	   long int  *base,
-	   long int   maxsize)
+dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-  volatile memctl8xx_t *memctl = &immap->im_memctl;
-  volatile long int    *addr;
-  ulong                 cnt, val;
-  ulong                 save[32];    /* to make test non-destructive */
-  unsigned char         i = 0;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
-  memctl->memc_mamr = mamr_value;
+	memctl->memc_mamr = mamr_value;
 
-  for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1)
-    {
-      addr = base + cnt;    /* pointer arith! */
-
-      save[i++] = *addr;
-      *addr     = ~cnt;
-    }
-
-  /* write 0 to base address */
-  addr    = base;
-  save[i] = *addr;
-  *addr   = 0;
-
-  /* check at base address */
-  if ( (val = *addr) != 0 )
-    {
-      *addr = save[i];
-
-      return (0);
-    }
-
-  for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1)
-    {
-      addr = base + cnt;    /* pointer arith! */
-
-      val   = *addr;
-      *addr = save[--i];
-
-      if ( val != (~cnt) )
-	{
-	  return (cnt * sizeof(long));
-	}
-    }
-
-  return (maxsize);
+	return (get_ram_size (base, maxsize));
 }
 
 /* ------------------------------------------------------------------------- */
@@ -384,16 +334,15 @@ dram_size (long int   mamr_value,
 
 #define CFG_LBKs    (CFG_PA2 | CFG_PA1)
 
-void
-reset_phy (void)
+void reset_phy (void)
 {
-  volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
-  /*
-   * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
-   *                                          and no AUI loopback
-   */
-  immr->im_ioport.iop_padat &= ~CFG_LBKs;  /* PADAT (LBK eth 1&2 = 0)        */
-  immr->im_ioport.iop_papar &= ~CFG_LBKs;  /* PAPAR (0=general purpose I/O)  */
-  immr->im_ioport.iop_padir |=  CFG_LBKs;  /* PADIR (I/O: 0=input, 1=output) */
+	/*
+	 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
+	 *                                          and no AUI loopback
+	 */
+	immr->im_ioport.iop_padat &= ~CFG_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
+	immr->im_ioport.iop_papar &= ~CFG_LBKs;	/* PAPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_padir |= CFG_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
 }

board/MAI/AmigaOneG3SE/articiaS.c

@@ -675,7 +675,7 @@ static __inline__ void set_msr (unsigned long msr)
 	asm volatile ("mtmsr %0"::"r" (msr));
 }
 
-int board_pre_init (void)
+int board_early_init_f (void)
 {
 	unsigned char c_value = 0;
 	unsigned long msr;

board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross

@@ -63,7 +63,7 @@ $(TARGETDEBUGLIB): $(DEBUGOBJS)
 	$(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
 
 INCS   = -I. -Ix86emu -I../../include
-CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -mrelocatable -ffixed-r14 -meabi -mrelocatable -ffixed-r14 -meabi
+CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -fPIC -ffixed-r14 -meabi
 CDEBUGFLAGS = -DDEBUG
 
 .c.o:

board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot

@@ -61,7 +61,7 @@ $(TARGETDEBUGLIB): $(DEBUGOBJS)
 	$(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
 
 INCS   = -I. -Ix86emu -I../../include
-CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -mrelocatable -ffixed-r14 -meabi -mrelocatable -ffixed-r14 -meabi
+CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -fPIC -ffixed-r14 -meabi
 CDEBUGFLAGS = -DDEBUG
 
 .c.o:

board/Marvell/common/bootseq.txt

@@ -0,0 +1,94 @@
+(cpu/mpc7xxx/start.S)
+
+start:
+    b boot_cold
+
+start_warm:
+    b boot_warm
+
+
+boot_cold:
+boot_warm:
+    clear bats
+    init l2 (if enabled)
+    init altivec (if enabled)
+    invalidate l2 (if enabled)
+    setup bats (from defines in config_EVB)
+    enable_addr_trans: (if MMU enabled)
+	enable MSR_IR and MSR_DR
+    jump to in_flash
+
+in_flash:
+    enable l1 dcache
+    gal_low_init: (board/evb64260/sdram_init.S)
+	config SDRAM (CFG, TIMING, DECODE)
+	init scratch regs (810 + 814)
+
+	detect DIMM0 (bank 0 only)
+	config SDRAM_PARA0 to 256/512Mbit
+	bl sdram_op_mode
+	detect bank0 width
+	    write scratch reg 810
+	config SDRAM_PARA0 with results
+	config SDRAM_PARA1 with results
+
+	detect DIMM1 (bank 2 only)
+	config SDRAM_PARA2 to 256/512Mbit
+	detect bank2 width
+	    write scratch reg 814
+	config SDRAM_PARA2 with results
+	config SDRAM_PARA3 with results
+
+	setup device bus timings/width
+	setup boot device timings/width
+
+	setup CPU_CONF (0x0)
+	setup cpu master control register 0x160
+	setup PCI0 TIMEOUT
+	setup PCI1 TIMEOUT
+	setup PCI0 BAR
+	setup PCI1 BAR
+
+	setup MPP control 0-3
+	setup GPP level control
+	setup Serial ports multiplex
+
+    setup stack pointer (r1)
+    setup GOT
+    call cpu_init_f
+    	debug leds
+    board_init_f: (common/board.c)
+	board_early_init_f:
+	    remap gt regs?
+	    map PCI mem/io
+	    map device space
+	    clear out interupts
+	init_timebase
+	env_init
+	serial_init
+	console_init_f
+	display_options
+	initdram: (board/evb64260/evb64260.c)
+	    detect memory
+	    for each bank:
+		dram_size()
+		setup PCI slave memory mappings
+		setup SCS
+   	setup monitor
+	alloc board info struct
+	init bd struct
+	relocate_code: (cpu/mpc7xxx/start.S)
+	    copy,got,clearbss
+	    board_init_r(bd, dest_addr) (common/board.c)
+		setup bd function pointers
+		trap_init
+		flash_init: (board/evb64260/flash.c)
+		setup bd flash info
+		cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
+		    nothing
+		mem_malloc_init
+		malloc_bin_reloc
+		spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
+		env_relocated
+		misc_init_r(bd): (board/evb64260/evb64260.c)
+		    mpsc_init2

board/Marvell/common/ecctest.c

@@ -0,0 +1,133 @@
+indent: Standard input:49: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+/*
+ * (C) Copyright 2001
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef ECC_TEST
+static inline void ecc_off (void)
+{
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
+}
+
+static inline void ecc_on (void)
+{
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
+}
+
+static int putshex (const char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		printf ("%02x", buf[i]);
+	}
+	return 0;
+}
+
+static int char_memcpy (void *d, const void *s, int len)
+{
+	int i;
+	char *cd = d;
+	const char *cs = s;
+
+	for (i = 0; i < len; i++) {
+		*(cd++) = *(cs++);
+	}
+	return 0;
+}
+
+static int memory_test (char *buf)
+{
+	const char src[][16] = {
+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+		{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+		 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
+		{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+		 0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
+		{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+		 0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
+		{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+		 0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
+		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+		 0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
+		{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+		 0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
+		{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+		 0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
+		{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+		 0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
+		{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+		 0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
+		{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+		 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
+		{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+	};
+	const int foo[] = { 0 };
+	int i, j, a;
+
+	printf ("\ntest @ %d %p\n", foo[0], buf);
+	for (i = 0; i < 12; i++) {
+		for (a = 0; a < 8; a++) {
+			const char *s = src[i] + a;
+			int align = (unsigned) (s) & 0x7;
+
+			/* ecc_off(); */
+			memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+			/* ecc_off(); */
+			char_memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+		}
+	}
+
+	return 0;
+}
+#endif

board/Marvell/common/i2c.c

@@ -0,0 +1,532 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ * extra improvments by Brain Waite
+ */
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include "../include/mv_gen_reg.h"
+#include "../include/core.h"
+
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
+#undef	DEBUG_I2C
+/*#define DEBUG_I2C*/
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+static void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CFG_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+/* gtI2cMasterInit */
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 2 << n;	/* power = 2^(n+1) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+/* gtI2cReset */
+	GT_REG_WRITE (I2C_SOFT_RESET, 0);
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	DP (puts ("set baudrate\n"));
+
+	GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
+
+	udelay (I2C_DELAY * 10);
+
+	DP (puts ("read control, baudrate\n"));
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	GT_REG_READ (I2C_CONTROL, &control);
+}
+
+static uchar i2c_start (void)
+{				/* DB64360 checked -> ok */
+	unsigned int control, status;
+	int count = 0;
+
+	DP (puts ("i2c_start\n"));
+
+	/* Set the start bit */
+
+/* gtI2cGenerateStartBit() */
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |= (0x1 << 5);	/* generate the I2C_START_BIT */
+	GT_REG_WRITE (I2C_CONTROL, control);
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+
+	count = 0;
+	while ((status & 0xff) != 0x08) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	GT_REG_WRITE (I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS (I2C_CONTROL, BIT3);
+
+	udelay (I2C_DELAY);
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	count = 0;
+	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+
+		udelay (I2C_DELAY * 5);
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x50) {
+			udelay (I2C_DELAY);
+			if (count > 2) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				return 0;
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		GT_REG_READ (I2C_DATA, &data);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+	}
+	RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
+	while ((status & 0xff) != 0x58) {
+		udelay (I2C_DELAY);
+		if (count > 200) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/* stop */
+
+	return (0);
+}
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		temp = (unsigned int) (*temp_ptr);
+		GT_REG_WRITE (I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+
+		udelay (I2C_DELAY);
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* 11-14-2002 Paul Marchese */
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+	/* set the interrupt bit in the control register */
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
+	udelay (I2C_DELAY * 10);
+	return (0);
+}
+
+/* 11-14-2002 Paul Marchese */
+/* created this function to get the i2c_write() */
+/* function working properly. */
+/* function to write bytes out on the i2c bus */
+/* this is identical to the function i2c_write_data() */
+/* except that it requires a buffer that is an */
+/* unsigned character array.  You can't use */
+/* i2c_write_data() to send an array of unsigned characters */
+/* since the byte of interest ends up on the wrong end of the bus */
+/* aah, the joys of big endian versus little endian! */
+/* */
+/* returns 0 = success */
+/*         anything other than zero is failure */
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		GT_REG_WRITE (I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+
+		udelay (I2C_DELAY);
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+/*	GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */
+	/* set the interrupt bit in the control register */
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
+	udelay (I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+/* initialize the table of address offset bytes */
+/* utilized for 2 byte address offsets */
+/* NOTE: the order is high byte first! */
+	table[1] = offset & 0xff;	/* low byte */
+	table[0] = offset / 0x100;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+uchar
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency again */
+
+	status = i2c_start ();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+/* 11-14-2002 Paul Marchese */
+/* Function to set the I2C stop bit */
+void i2c_stop (void)
+{
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
+}
+
+/* 11-14-2002 Paul Marchese */
+/* I2C write function */
+/* dev_addr = device address */
+/* offset = address offset */
+/* alen = length in bytes of the address offset */
+/* data = pointer to buffer to read data into */
+/* len = # of bytes to read */
+/* */
+/* returns 0 = succesful */
+/*         anything but zero is failure */
+uchar
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+	}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+/* 11-14-2002 Paul Marchese */
+/* function to determine if an I2C device is present */
+/* chip = device address of chip to check for */
+/* */
+/* returns 0 = sucessful, the device exists */
+/*         anything other than zero is failure, no device */
+int i2c_probe (uchar chip)
+{
+
+	/* We are just looking for an <ACK> back. */
+	/* To see if the device/chip is there */
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}

board/Marvell/common/i2c.h

@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ */
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif

board/Marvell/common/intel_flash.c

@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "../include/mv_gen_reg.h"
+#include "../include/memory.h"
+#include "intel_flash.h"
+
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+static void bank_reset (flash_info_t * info, int sect)
+{
+	bank_addr_t addrw, eaddrw;
+
+	addrw = (bank_addr_t) info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD (addrw);
+
+	while (addrw < eaddrw) {
+#ifdef FLASH_DEBUG
+		printf ("  writing reset cmd to addr 0x%08lx\n",
+			(unsigned long) addrw);
+#endif
+		*addrw = BANK_CMD_RST;
+		addrw++;
+	}
+}
+
+static void bank_erase_init (flash_info_t * info, int sect)
+{
+	bank_addr_t addrw, saddrw, eaddrw;
+	int flag;
+
+#ifdef FLASH_DEBUG
+	printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
+	printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
+	printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
+	printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
+	printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
+	printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
+	printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
+#endif
+
+	saddrw = (bank_addr_t) info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
+
+#ifdef FLASH_DEBUG
+	printf ("erasing sector %d, start addr = 0x%08lx "
+		"(bank next word addr = 0x%08lx)\n", sect,
+		(unsigned long) saddrw, (unsigned long) eaddrw);
+#endif
+
+	/* Disable intrs which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+#ifdef FLASH_DEBUG
+		printf ("  writing erase cmd to addr 0x%08lx\n",
+			(unsigned long) addrw);
+#endif
+		*addrw = BANK_CMD_ERASE1;
+		*addrw = BANK_CMD_ERASE2;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+}
+
+static int bank_erase_poll (flash_info_t * info, int sect)
+{
+	bank_addr_t addrw, saddrw, eaddrw;
+	int sectdone, haderr;
+
+	saddrw = (bank_addr_t) info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
+
+	sectdone = 1;
+	haderr = 0;
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+		bank_word_t stat = *addrw;
+
+#ifdef FLASH_DEBUG
+		printf ("  checking status at addr "
+			"0x%08x [0x%08x]\n", (unsigned long) addrw, stat);
+#endif
+		if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
+			sectdone = 0;
+		else if ((stat & BANK_STAT_ERR) != 0) {
+			printf (" failed on sector %d "
+				"(stat = 0x%08x) at "
+				"address 0x%p\n", sect, stat, addrw);
+			*addrw = BANK_CMD_CLR_STAT;
+			haderr = 1;
+		}
+	}
+
+	if (haderr)
+		return (-1);
+	else
+		return (sectdone);
+}
+
+int write_word_intel (bank_addr_t addr, bank_word_t value)
+{
+	bank_word_t stat;
+	ulong start;
+	int flag, retval;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = BANK_CMD_PROG;
+
+	*addr = value;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	retval = 0;
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	do {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			retval = 1;
+			goto done;
+		}
+		stat = *addr;
+	} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
+
+	if ((stat & BANK_STAT_ERR) != 0) {
+		printf ("flash program failed (stat = 0x%08lx) "
+			"at address 0x%08lx\n", (ulong) stat, (ulong) addr);
+		*addr = BANK_CMD_CLR_STAT;
+		retval = 3;
+	}
+
+      done:
+	/* reset to read mode */
+	*addr = BANK_CMD_RST;
+
+	return (retval);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
+{
+	int prot, sect, haderr;
+	ulong start, now, last;
+
+#ifdef FLASH_DEBUG
+	printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
+		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
+		(info - flash_info) + 1);
+	flash_print_info (info);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : ""));
+	}
+
+	start = get_timer (0);
+	last = 0;
+	haderr = 0;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			ulong estart;
+			int sectdone;
+
+			bank_erase_init (info, sect);
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			estart = get_timer (start);
+
+			do {
+				now = get_timer (start);
+
+				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout (sect %d)\n", sect);
+					haderr = 1;
+					break;
+				}
+#ifndef FLASH_DEBUG
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+#endif
+
+				sectdone = bank_erase_poll (info, sect);
+
+				if (sectdone < 0) {
+					haderr = 1;
+					break;
+				}
+
+			} while (!sectdone);
+
+			if (haderr)
+				break;
+		}
+	}
+
+	if (haderr > 0)
+		printf (" failed\n");
+	else
+		printf (" done\n");
+
+	/* reset to read mode */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			bank_reset (info, sect);
+		}
+	}
+	return haderr;
+}

board/Marvell/common/intel_flash.h

@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ */
+
+/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
+
+/*
+ * acceptable chips types are:
+ *
+ *	28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
+ */
+
+/* register addresses, valid only following an CHIP_CMD_RD_ID command */
+#define CHIP_ADDR_REG_MAN	0x000000	/* manufacturer's id */
+#define CHIP_ADDR_REG_DEV	0x000001	/* device id */
+#define CHIP_ADDR_REG_CFGM	0x000003	/* master lock config */
+#define CHIP_ADDR_REG_CFG(b)	(((b)<<16)|2)	/* lock config for block b */
+
+/* Commands */
+#define CHIP_CMD_RST		0xFF		/* reset flash */
+#define CHIP_CMD_RD_ID		0x90		/* read the id and lock bits */
+#define CHIP_CMD_RD_QUERY	0x98		/* read device capabilities */
+#define CHIP_CMD_RD_STAT	0x70		/* read the status register */
+#define CHIP_CMD_CLR_STAT	0x50		/* clear the staus register */
+#define CHIP_CMD_WR_BUF		0xE8		/* clear the staus register */
+#define CHIP_CMD_PROG		0x40		/* program word command */
+#define CHIP_CMD_ERASE1		0x20		/* 1st word for block erase */
+#define CHIP_CMD_ERASE2		0xD0		/* 2nd word for block erase */
+#define CHIP_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
+#define CHIP_CMD_LOCK		0x60		/* 1st word for all lock cmds */
+#define CHIP_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
+#define CHIP_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
+#define CHIP_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
+
+/* status register bits */
+#define CHIP_STAT_DPS		0x02		/* Device Protect Status */
+#define CHIP_STAT_VPPS		0x08		/* VPP Status */
+#define CHIP_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
+#define CHIP_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
+#define CHIP_STAT_ESS		0x40		/* Erase Suspend Status */
+#define CHIP_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
+
+#define CHIP_STAT_ERR		(CHIP_STAT_VPPS | CHIP_STAT_DPS | \
+				    CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
+
+/* ID and Lock Configuration */
+#define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
+#define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
+#define CHIP_RD_ID_DEV		CFG_FLASH_ID
+
+/* dimensions */
+#define CHIP_WIDTH		2		/* chips are in 16 bit mode */
+#define CHIP_WSHIFT		1		/* (log2 of CHIP_WIDTH) */
+#define CHIP_NBLOCKS		128
+#define CHIP_BLKSZ		(128 * 1024)	/* of 128Kbytes each */
+#define CHIP_SIZE		(CHIP_BLKSZ * CHIP_NBLOCKS)
+
+/********************** DEFINES for Hymod Flash ******************************/
+
+/*
+ * The hymod board has 2 x 28F320J5 chips running in
+ * 16 bit mode, for a 32 bit wide bank.
+ */
+
+typedef unsigned short bank_word_t;		/* 8/16/32/64bit unsigned int */
+typedef volatile bank_word_t *bank_addr_t;
+typedef unsigned long bank_size_t;		/* want this big - >= 32 bit */
+
+#define BANK_CHIP_WIDTH		1		/* each bank is 1 chip wide */
+#define BANK_CHIP_WSHIFT	0		/* (log2 of BANK_CHIP_WIDTH) */
+
+#define BANK_WIDTH		(CHIP_WIDTH * BANK_CHIP_WIDTH)
+#define BANK_WSHIFT		(CHIP_WSHIFT + BANK_CHIP_WSHIFT)
+#define BANK_NBLOCKS		CHIP_NBLOCKS
+#define BANK_BLKSZ		(CHIP_BLKSZ * BANK_CHIP_WIDTH)
+#define BANK_SIZE		(CHIP_SIZE * BANK_CHIP_WIDTH)
+
+#define MAX_BANKS		1		/* only one bank possible */
+
+/* align bank addresses and sizes to bank word boundaries */
+#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_WIDTH - 1)))
+#define BANK_SIZE_WORD_ALIGN(s)	((bank_size_t)BANK_ADDR_WORD_ALIGN( \
+				    (bank_size_t)(s) + (BANK_WIDTH - 1)))
+
+/* align bank addresses and sizes to bank block boundaries */
+#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_BLKSZ - 1)))
+#define BANK_SIZE_BLK_ALIGN(s)	((bank_size_t)BANK_ADDR_BLK_ALIGN( \
+				    (bank_size_t)(s) + (BANK_BLKSZ - 1)))
+
+/* align bank addresses and sizes to bank boundaries */
+#define BANK_ADDR_BANK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_SIZE - 1)))
+#define BANK_SIZE_BANK_ALIGN(s)	((bank_size_t)BANK_ADDR_BANK_ALIGN( \
+				    (bank_size_t)(s) + (BANK_SIZE - 1)))
+
+/* add an offset to a bank address */
+#define BANK_ADDR_OFFSET(a, o)	(bank_addr_t)((bank_size_t)(a) + \
+				    (bank_size_t)(o))
+
+/* get base address of bank b, given flash base address a */
+#define BANK_ADDR_BASE(a, b)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    (bank_size_t)(b) * BANK_SIZE)
+
+/* adjust a bank address to start of next word, block or bank */
+#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
+				    BANK_WIDTH)
+#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
+				    BANK_BLKSZ)
+#define BANK_ADDR_NEXT_BANK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    BANK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define BANK_ADDR_REG(a, r)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    ((bank_size_t)(r) << BANK_WSHIFT))
+
+/* make a bank address for each chip register address */
+
+#define BANK_ADDR_REG_MAN(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
+#define BANK_ADDR_REG_DEV(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
+#define BANK_ADDR_REG_CFGM(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
+#define BANK_ADDR_REG_CFG(b,a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the bank_word_t type, and take into account the
+ * chip width and bank layout
+ */
+
+#define BANK_FILL_WORD(o)	((bank_word_t)(o))
+
+/* make a bank word value for each chip cmd/stat/rd value */
+
+/* Commands */
+#define BANK_CMD_RST		BANK_FILL_WORD(CHIP_CMD_RST)
+#define BANK_CMD_RD_ID		BANK_FILL_WORD(CHIP_CMD_RD_ID)
+#define BANK_CMD_RD_STAT	BANK_FILL_WORD(CHIP_CMD_RD_STAT)
+#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
+#define BANK_CMD_ERASE1		BANK_FILL_WORD(CHIP_CMD_ERASE1)
+#define BANK_CMD_ERASE2		BANK_FILL_WORD(CHIP_CMD_ERASE2)
+#define BANK_CMD_PROG		BANK_FILL_WORD(CHIP_CMD_PROG)
+#define BANK_CMD_LOCK		BANK_FILL_WORD(CHIP_CMD_LOCK)
+#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
+#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
+#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define BANK_STAT_DPS		BANK_FILL_WORD(CHIP_STAT_DPS)
+#define BANK_STAT_PSS		BANK_FILL_WORD(CHIP_STAT_PSS)
+#define BANK_STAT_VPPS		BANK_FILL_WORD(CHIP_STAT_VPPS)
+#define BANK_STAT_PSLBS		BANK_FILL_WORD(CHIP_STAT_PSLBS)
+#define BANK_STAT_ECLBS		BANK_FILL_WORD(CHIP_STAT_ECLBS)
+#define BANK_STAT_ESS		BANK_FILL_WORD(CHIP_STAT_ESS)
+#define BANK_STAT_RDY		BANK_FILL_WORD(CHIP_STAT_RDY)
+
+#define BANK_STAT_ERR		BANK_FILL_WORD(CHIP_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define BANK_RD_ID_LOCK		BANK_FILL_WORD(CHIP_RD_ID_LOCK)
+#define BANK_RD_ID_MAN		BANK_FILL_WORD(CHIP_RD_ID_MAN)
+#define BANK_RD_ID_DEV		BANK_FILL_WORD(CHIP_RD_ID_DEV)

board/Marvell/common/misc.S

@@ -0,0 +1,235 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include "version.h"
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include "../include/mv_gen_reg.h"
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CFG_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CFG_MONITOR_LEN@h
+	ori	r8, r8, CFG_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11: gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CFG_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CFG_DFL_GT_REGS@h
+	ori	r3, r3, CFG_DFL_GT_REGS@l
+	lis	r4, CFG_GT_REGS@h
+	ori	r4, r4, CFG_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
+/*	rlwinm	r7, r4, 8, 16, 31
+	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
+	rlwinm	r7, r4, 16, 16, 31
+	/* -----------------------------------------------------*/
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0_relocated
+led_on0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC80
+	ori	r18, r18, 0x8000
+	stw	r21, 0x0(r18)
+/*	  stw	  r18, 0x0(r18) */
+	sync
+	blr
+
+	.global led_off0_relocated
+led_off0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC81
+	ori	r18, r18, 0x4000
+	stw	r21, 0x0(r18)
+/*	  stw	  r18, 0x0(r18) */
+	sync
+	blr
+
+	.global led_on0
+led_on0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0x8000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_off0
+led_off0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x4000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0xc000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_off1
+led_off1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x8000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x0000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_off2
+led_off2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0xc000
+	stw	r18, 0x0(r18)
+	sync
+	blr

board/Marvell/common/ns16550.c

@@ -0,0 +1,66 @@
+/*
+ * COM1 NS16550 support
+ * originally from linux source (arch/ppc/boot/ns16550.c)
+ * modified to use CFG_ISA_MEM and new defines
+ *
+ * further modified by Josh Huber <huber@mclx.com> to support
+ * the DUART on the Galileo Eval board. (db64360)
+ */
+
+#include <config.h>
+#include "ns16550.h"
+
+#ifdef ZUMA_NTL
+/* no 16550 device */
+#else
+const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0),
+	(NS16550_t) (CFG_DUART_IO + 0x20)
+};
+
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
+{
+	volatile struct NS16550 *com_port;
+
+	com_port = (struct NS16550 *) COM_PORTS[chan];
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
+
+	/* Clear & enable FIFOs */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
+	return (com_port);
+}
+
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
+{
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
+
+	/* Clear & enable FIFOs */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
+}
+
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
+{
+	while ((com_port->lsr & LSR_THRE) == 0);
+	com_port->thr = c;
+}
+
+unsigned char NS16550_getc (volatile struct NS16550 *com_port)
+{
+	while ((com_port->lsr & LSR_DR) == 0);
+	return (com_port->rbr);
+}
+
+int NS16550_tstc (volatile struct NS16550 *com_port)
+{
+	return ((com_port->lsr & LSR_DR) != 0);
+}
+#endif

board/Marvell/common/ns16550.h

@@ -0,0 +1,102 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/ppc/boot/ns16550.h)
+ * modified slightly to
+ * have addresses as offsets from CFG_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ *
+ * further modified to support the DUART in the Galileo eval board
+ * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ */
+
+#ifndef __NS16550_H__
+#define __NS16550_H__
+
+/* the padding is necessary because on the galileo board the UART is
+   wired in with the 3 address lines shifted over by 2 bits */
+struct NS16550
+{
+	unsigned char rbr;  /* 0 = 0-3*/
+	int pad1:24;
+
+	unsigned char ier;  /* 1 = 4-7*/
+	int pad2:24;
+
+	unsigned char fcr;  /* 2 = 8-b*/
+	int pad3:24;
+
+	unsigned char lcr;  /* 3 = c-f*/
+	int pad4:24;
+
+	unsigned char mcr;  /* 4 = 10-13*/
+	int pad5:24;
+
+	unsigned char lsr;  /* 5 = 14-17*/
+	int pad6:24;
+
+	unsigned char msr;  /* 6 =18-1b*/
+	int pad7:24;
+
+	unsigned char scr;  /* 7 =1c-1f*/
+	int pad8:24;
+} __attribute__ ((packed));
+
+/* aliases */
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+#define FCR_FIFO_EN     0x01    /*fifo enable*/
+#define FCR_RXSR        0x02    /*reciever soft reset*/
+#define FCR_TXSR        0x04    /*transmitter soft reset*/
+
+
+#define MCR_DTR         0x01
+#define MCR_RTS         0x02
+#define MCR_DMA_EN      0x04
+#define MCR_TX_DFR      0x08
+
+
+#define LCR_WLS_MSK 0x03    /* character length slect mask*/
+#define LCR_WLS_5   0x00    /* 5 bit character length */
+#define LCR_WLS_6   0x01    /* 6 bit character length */
+#define LCR_WLS_7   0x02    /* 7 bit character length */
+#define LCR_WLS_8   0x03    /* 8 bit character length */
+#define LCR_STB     0x04    /* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN     0x08    /* Parity eneble*/
+#define LCR_EPS     0x10    /* Even Parity Select*/
+#define LCR_STKP    0x20    /* Stick Parity*/
+#define LCR_SBRK    0x40    /* Set Break*/
+#define LCR_BKSE    0x80    /* Bank select enable*/
+
+#define LSR_DR      0x01    /* Data ready */
+#define LSR_OE      0x02    /* Overrun */
+#define LSR_PE      0x04    /* Parity error */
+#define LSR_FE      0x08    /* Framing error */
+#define LSR_BI      0x10    /* Break */
+#define LSR_THRE    0x20    /* Xmit holding register empty */
+#define LSR_TEMT    0x40    /* Xmitter empty */
+#define LSR_ERR     0x80    /* Error */
+
+/* useful defaults for LCR*/
+#define LCR_8N1     0x03
+
+
+#define COM1 0x03F8
+#define COM2 0x02F8
+
+volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
+void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
+unsigned char NS16550_getc(volatile struct NS16550 *com_port);
+int NS16550_tstc(volatile struct NS16550 *com_port);
+void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
+
+typedef struct NS16550 *NS16550_t;
+
+extern const NS16550_t COM_PORTS[];
+
+#endif

board/Marvell/common/ppc_error_no.h

@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
+ */
+#ifndef _MV_PPC_ERRNO_H
+#define _MV_PPC_ERRNO_H
+
+#define	EPERM		 1	/* Operation not permitted */
+#define	ENOENT		 2	/* No such file or directory */
+#define	ESRCH		 3	/* No such process */
+#define	EINTR		 4	/* Interrupted system call */
+#define	EIO		 5	/* I/O error */
+#define	ENXIO		 6	/* No such device or address */
+#define	E2BIG		 7	/* Arg list too long */
+#define	ENOEXEC		 8	/* Exec format error */
+#define	EBADF		 9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+#define	EDEADLOCK	58	/* File locking deadlock error */
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+/* Should never be seen by user programs */
+#define ERESTARTSYS	512
+#define ERESTARTNOINTR	513
+#define ERESTARTNOHAND	514	/* restart if no handler.. */
+#define ENOIOCTLCMD	515	/* No ioctl command */
+
+#define _LAST_ERRNO	515
+
+#endif

board/Marvell/common/serial.c

@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * serial.c - serial support for the gal ev board
+ */
+
+/* supports both the 16650 duart and the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include "../include/memory.h"
+#include "serial.h"
+
+#ifdef CONFIG_DB64360
+#include "../db64360/mpsc.h"
+#endif
+
+#ifdef CONFIG_DB64460
+#include "../db64460/mpsc.h"
+#endif
+
+#include "ns16550.h"
+
+#ifdef CONFIG_MPSC
+
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+	int clock_divisor = 230400 / gd->baudrate;
+#endif
+
+	mpsc_init (gd->baudrate);
+
+	/* init the DUART chans so that KGDB in the kernel can use them */
+#ifdef CFG_INIT_CHAN1
+	NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		mpsc_putchar ('\r');
+
+	mpsc_putchar (c);
+}
+
+int serial_getc (void)
+{
+	return mpsc_getchar ();
+}
+
+int serial_tstc (void)
+{
+	return mpsc_test_char ();
+}
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+#else  /* ! CONFIG_MPSC */
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = 230400 / gd->baudrate;
+
+#ifdef CFG_INIT_CHAN1
+	(void) NS16550_init (0, clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	(void) NS16550_init (1, clock_divisor);
+#endif
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
+
+	NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
+}
+
+int serial_getc (void)
+{
+	return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
+}
+
+int serial_tstc (void)
+{
+	return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
+}
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = 230400 / gd->baudrate;
+
+#ifdef CFG_INIT_CHAN1
+	NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+}
+
+#endif /* CONFIG_MPSC */
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif /* CFG_CMD_KGDB */

board/Marvell/common/serial.h

@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* serial.h - mostly useful for DUART serial_init in serial.c */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#if 0
+
+#define B230400         1
+#define B115200         2
+#define B57600          4
+#define B38400          82
+#define B19200          163
+#define B9600           24
+#define B4800           651
+#define B2400           1302
+#define B1200           2604
+#define B600            5208
+#define B300            10417
+#define B150            20833
+#define B110            28409
+#define BDEFAULT        B115200
+
+				/* this stuff is important to initialize
+				the DUART channels */
+
+#define	Scale		0x01L		/* distance between port addresses */
+#define	COM1		0x000003f8		/* Keyboard */
+#define COM2		0x000002f8		/* Host */
+
+
+/* Port Definitions relative to base COM port addresses */
+#define DataIn	(0x00*Scale)	/* data input port */
+#define DataOut	(0x00*Scale)	/* data output port */
+#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
+#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
+#define	Ier	(0x01*Scale)	/* interrupt enable register */
+#define	Iir	(0x02*Scale)	/* interrupt identification register */
+#define	Lcr	(0x03*Scale)	/* line control register */
+#define	Mcr	(0x04*Scale)	/* modem control register */
+#define	Lsr	(0x05*Scale)	/* line status register */
+#define	Msr	(0x06*Scale)	/* modem status register */
+
+/* Bit Definitions for above ports */
+#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
+#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
+
+#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
+#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
+#define	McrDflt	(McrRts|McrDtr)
+
+#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
+			/* b6: transmitter empty */
+#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
+
+#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
+#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
+#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
+
+#define IerRda	0xf	/* b0: Enable received data available interrupt */
+
+#endif
+
+#endif /* __SERIAL_H__ */

board/Marvell/db64360/64360.h

@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the Galileo Eval board DB64360.
+ */
+
+#ifndef __64360_H__
+#define __64360_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64360_H__ */

board/Marvell/db64360/Makefile

@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+SOBJS	= ../common/misc.o
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
+	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
+	  sdram_init.o ../common/intel_flash.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/Marvell/db64360/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EVB64360 boards
+#
+
+TEXT_BASE = 0xfff00000

board/Marvell/db64360/db64360.c

@@ -0,0 +1,936 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
+ */
+
+/*
+ * db64360.c - main board support/init for the Galileo Eval board.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../include/memory.h"
+#include "../include/pci.h"
+#include "../include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+extern void flush_data_cache (void);
+extern void invalidate_l1_instruction_cache (void);
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+int display_mem_map (void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+
+/* original ppcboot 1.1.6 source
+
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+original ppcboot 1.1.6 source end */
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
+
+	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
+									     <<
+									     18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen- add write to pci remap registers for 64460.
+	   in 64360 when writing to pci base go and overide remap automaticaly,
+	   in 64460 it doesn't */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+/*ronen update the pci internal registers base address.*/
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++)
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, CFG_GT_REGS);
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+
+	/* set the SINGLE_CPU bit  see MV64360 P.399 */
+#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+
+	tmp |= CPU_CONF_PIPELINE;
+
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+	uchar sram_boot = 0;
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+
+	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+
+	/* No PCI in first release of Port To_do: enable it. */
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in MV6436x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	/* does not exist in MV6436x
+	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
+	   --------------------- */
+
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM   ????
+	 * 1 - RTC      ????
+	 * 2 - UART     ????
+	 * 3 - Flash    checked 32Bit Intel Strata
+	 * boot - BootCS checked 8Bit 29LV040B
+	 *
+	 * Zuma
+	 * 0 - Flash
+	 * boot - BootCS
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
+		sram_boot = 1;
+	if (!sram_boot)
+		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+
+	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+
+
+	/* configure device timing */
+#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
+	if (!sram_boot)
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+#endif
+
+#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+#endif
+#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+#endif
+
+#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
+			      CFG_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+#endif
+
+
+	gt_cpu_config ();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	DEBUG_LED0_ON ();
+	DEBUG_LED1_ON ();
+	DEBUG_LED2_ON ();
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	icache_enable ();
+#ifdef CFG_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+#if 0
+	/* disable the dcache and MMU */
+	dcache_lock ();
+#endif
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+	/* check to see if we booted from the sram.  If so, move things
+	 * back to the way they should be. (we're running from main
+	 * memory at this point now */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
+		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
+	}
+	display_mem_map ();
+	/* now, jump to the main ppcboot board init code */
+	board_init_r (gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	return (l_type);
+}
+
+/* utility functions */
+void debug_led (int led, int mode)
+{
+	volatile int *addr = 0;
+	int dummy;
+
+	if (mode == 1) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x08000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x0c000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x10000);
+			break;
+		}
+	} else if (mode == 0) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x14000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x18000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x1c000);
+			break;
+		}
+	}
+
+	dummy = *addr;
+}
+
+int display_mem_map (void)
+{
+	int i, j;
+	unsigned int base, size, width;
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0) {
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+		}
+	}
+
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		for (j = 0;
+		     j <=
+		     PCI_REGION0
+		     /*ronen currently only first PCI MEM is used 3 */ ;
+		     j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
+		}
+	}
+
+	/* Devices */
+	printf ("\nDEVICES\n");
+	for (i = 0; i <= DEVICE3; i++) {
+		base = memoryGetDeviceBaseAddress (i);
+		size = memoryGetDeviceSize (i);
+		width = memoryGetDeviceWidth (i) * 8;
+		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
+		if (i == 0)
+			printf ("\t- EXT SRAM (actual - 1M)\n");
+		else if (i == 1)
+			printf ("\t- RTC\n");
+		else if (i == 2)
+			printf ("\t- UART\n");
+		else
+			printf ("\t- LARGE FLASH\n");
+	}
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\n",
+		base, size >> 20, width);
+	return (0);
+}
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CFG_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CFG_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaa,
+	0xcccccccccccccccc,
+	0xf0f0f0f0f0f0f0f0,
+	0xff00ff00ff00ff00,
+	0xffff0000ffff0000,
+	0xffffffff00000000,
+	0x00000000ffffffff,
+	0x0000ffff0000ffff,
+	0x00ff00ff00ff00ff,
+	0x0f0f0f0f0f0f0f0f,
+	0x3333333333333333,
+	0x5555555555555555
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long temp64;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_DATA */
+
+#if defined (CFG_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CFG_MEMTEST_START;
+	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_ADDRESS */
+
+#if defined (CFG_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CFG_MEMTEST_START;
+	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata, runaddress, runwalk;
+
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+
+/*    rundata = 1; */
+/*    runaddress = 0; */
+/*    runwalk = 0; */
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+	}
+#ifdef CFG_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed\n");
+	}
+	return 0;
+
+}
+#endif /* CFG_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function           */
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.                                            */
+/*  - we diable and invalidate the icache and dcache.                   */
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
+
+void board_prebootm_init ()
+{
+
+/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
+		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
+
+/* Stop GigE Rx DMA engines */
+	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
+	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
+/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
+
+/* Relocate MV64360 internal regs */
+	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+
+	icache_disable ();
+	invalidate_l1_instruction_cache ();
+	flush_data_cache ();
+	dcache_disable ();
+}

board/Marvell/db64360/eth.h

@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64360_ETH_H__
+#define __EVB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+
+int db64360_eth0_poll(void);
+int db64360_eth0_transmit(unsigned int s, volatile char *p);
+void db64360_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+
+#endif /* __EVB64360_ETH_H__ */

board/Marvell/db64360/mpsc.h

@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT 		  (1 << 15)
+#define SDMA_TX_ABORT 		  (1 << 31)
+#define MPSC_TX_ABORT 		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */

board/Marvell/db64360/mv_eth.h

@@ -0,0 +1,844 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64360_ETH_H__
+#define __DB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include "../common/ppc_error_no.h"
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64360_TX_QUEUE_NUM 1
+#define MV64360_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#else
+#define MV64360_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#else
+#define MV64360_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64360_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64360_TX_BUFFER_SIZE 1600
+#endif
+
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64360_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+/* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+};
+
+
+int mv64360_eth_init (struct eth_device *dev);
+int mv64360_eth_stop (struct eth_device *dev);
+int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
+/*	return db64360_eth0_poll(); */
+
+int mv64360_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64360_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64360_ETH_ */

board/Marvell/db64360/pci.c

@@ -0,0 +1,940 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#include <pci.h>
+
+#include "../include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*                    - Make sure the GT is configured as a master before writing
+*                      to another device on the PCI.
+*                    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*                   (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*                    - Make sure the GT is configured as a master before reading
+*                     from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*                               the agent is placed on another Bus. For more
+*                               information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*           GT spec (or any other PCI device spec).
+*           unsigned int pciDevNum - The device number needs to be addressed.
+*           unsigned int busNum - On which bus does the Target agent connect
+*                                 to.
+*           unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*                               the agent target locate on another PCI bus.
+*                             - Make sure the GT is configured as a master
+*                               before reading from another device on the PCI.
+*                             - The function takes care of Big/Little endian
+*                               conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec). (configuration register offset.)
+*           pciDevNum: The device number needs to be addressed.
+*           busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*           - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*                         feature bits given as an input.
+*                       - Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*         unsigned int features - See file: pci.h there are defintion for those
+*                                 region features.
+*         unsigned int baseAddress - The region base Address.
+*         unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*                           to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*                      disable the park on last mechanism for each agent.
+*                      disabling this option for all agents results parking
+*                      on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*                       respond to grant assertion within a window specified in
+*                       the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*                       grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*                           Detection mechanism.
+*                           NOTE: This operation may cause a dead lock on the
+*                           pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*                 For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*                                      Boundry.
+*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*                                      Boundry.
+*          unsigned int busNum - The CPI bus number to which the PCI interface
+*                                      is connected.
+*          unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*                          supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*         snoopType - There is four optional Types:
+*                        1. No Snoop.
+*                        2. Snoop to WT region.
+*                        3. Snoop to WB region.
+*                        4. Snoop & Invalidate to WB region.
+*         baseAddress - Base Address of this region.
+*         regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+					0x0);
+		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+				       &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					bar_value);
+	}
+}
+
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CFG_PCI0_IO_SPACE_PCI,
+			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	pciArbiterEnable (PCI_HOST0);
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CFG_PCI1_IO_SPACE_PCI,
+			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}

board/Marvell/db64360/u-boot.lds

@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/Marvell/db64460/64460.h

@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the Galileo Eval board DB64460.
+ */
+
+#ifndef __64460_H__
+#define __64460_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64460_H__ */

board/Marvell/db64460/Makefile

@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+SOBJS	= ../common/misc.o
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
+	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
+	  sdram_init.o ../common/intel_flash.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/Marvell/db64460/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EVB64460 boards
+#
+
+TEXT_BASE = 0xfff00000

board/Marvell/db64460/db64460.c

@@ -0,0 +1,936 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
+ */
+
+/*
+ * db64460.c - main board support/init for the Galileo Eval board.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../include/memory.h"
+#include "../include/pci.h"
+#include "../include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64460.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+extern void flush_data_cache (void);
+extern void invalidate_l1_instruction_cache (void);
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+int display_mem_map (void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+
+/* original ppcboot 1.1.6 source
+
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+original ppcboot 1.1.6 source end */
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
+
+	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
+									     <<
+									     18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen- add write to pci remap registers for 64460.
+	   in 64360 when writing to pci base go and overide remap automaticaly,
+	   in 64460 it doesn't */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+/*ronen update the pci internal registers base address.*/
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++)
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, CFG_GT_REGS);
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+
+	/* set the SINGLE_CPU bit  see MV64460 P.399 */
+#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+
+	tmp |= CPU_CONF_PIPELINE;
+
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+	uchar sram_boot = 0;
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+
+	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+
+	/* No PCI in first release of Port To_do: enable it. */
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in MV6446x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	/* does not exist in MV6446x
+	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
+	   --------------------- */
+
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM   ????
+	 * 1 - RTC      ????
+	 * 2 - UART     ????
+	 * 3 - Flash    checked 32Bit Intel Strata
+	 * boot - BootCS checked 8Bit 29LV040B
+	 *
+	 * Zuma
+	 * 0 - Flash
+	 * boot - BootCS
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
+		sram_boot = 1;
+	if (!sram_boot)
+		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+
+	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+
+
+	/* configure device timing */
+#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
+	if (!sram_boot)
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+#endif
+
+#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+#endif
+#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+#endif
+
+#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
+			      CFG_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+#endif
+
+
+	gt_cpu_config ();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	DEBUG_LED0_ON ();
+	DEBUG_LED1_ON ();
+	DEBUG_LED2_ON ();
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	icache_enable ();
+#ifdef CFG_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+#if 0
+	/* disable the dcache and MMU */
+	dcache_lock ();
+#endif
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+	/* check to see if we booted from the sram.  If so, move things
+	 * back to the way they should be. (we're running from main
+	 * memory at this point now */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
+		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
+	}
+	display_mem_map ();
+	/* now, jump to the main ppcboot board init code */
+	board_init_r (gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	return (l_type);
+}
+
+/* utility functions */
+void debug_led (int led, int mode)
+{
+	volatile int *addr = 0;
+	int dummy;
+
+	if (mode == 1) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x08000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x0c000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x10000);
+			break;
+		}
+	} else if (mode == 0) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x14000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x18000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x1c000);
+			break;
+		}
+	}
+
+	dummy = *addr;
+}
+
+int display_mem_map (void)
+{
+	int i, j;
+	unsigned int base, size, width;
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0) {
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+		}
+	}
+
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		for (j = 0;
+		     j <=
+		     PCI_REGION0
+		     /*ronen currently only first PCI MEM is used 3 */ ;
+		     j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
+		}
+	}
+
+	/* Devices */
+	printf ("\nDEVICES\n");
+	for (i = 0; i <= DEVICE3; i++) {
+		base = memoryGetDeviceBaseAddress (i);
+		size = memoryGetDeviceSize (i);
+		width = memoryGetDeviceWidth (i) * 8;
+		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
+		if (i == 0)
+			printf ("\t- EXT SRAM (actual - 1M)\n");
+		else if (i == 1)
+			printf ("\t- RTC\n");
+		else if (i == 2)
+			printf ("\t- UART\n");
+		else
+			printf ("\t- LARGE FLASH\n");
+	}
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\n",
+		base, size >> 20, width);
+	return (0);
+}
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CFG_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CFG_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaa,
+	0xcccccccccccccccc,
+	0xf0f0f0f0f0f0f0f0,
+	0xff00ff00ff00ff00,
+	0xffff0000ffff0000,
+	0xffffffff00000000,
+	0x00000000ffffffff,
+	0x0000ffff0000ffff,
+	0x00ff00ff00ff00ff,
+	0x0f0f0f0f0f0f0f0f,
+	0x3333333333333333,
+	0x5555555555555555
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long temp64;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_DATA */
+
+#if defined (CFG_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CFG_MEMTEST_START;
+	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_ADDRESS */
+
+#if defined (CFG_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CFG_MEMTEST_START;
+	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata, runaddress, runwalk;
+
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+
+/*    rundata = 1; */
+/*    runaddress = 0; */
+/*    runwalk = 0; */
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+	}
+#ifdef CFG_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed\n");
+	}
+	return 0;
+
+}
+#endif /* CFG_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function           */
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.                                            */
+/*  - we diable and invalidate the icache and dcache.                   */
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
+
+void board_prebootm_init ()
+{
+
+/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
+		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
+
+/* Stop GigE Rx DMA engines */
+	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
+	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
+	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
+
+/* Relocate MV64460 internal regs */
+	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+
+	icache_disable ();
+	invalidate_l1_instruction_cache ();
+	flush_data_cache ();
+	dcache_disable ();
+}

board/Marvell/db64460/eth.h

@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64460_ETH_H__
+#define __EVB64460_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+int db64460_eth0_poll(void);
+int db64460_eth0_transmit(unsigned int s, volatile char *p);
+void db64460_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+#endif /* __EVB64460_ETH_H__ */

board/Marvell/db64460/mpsc.h

@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT 		  (1 << 15)
+#define SDMA_TX_ABORT 		  (1 << 31)
+#define MPSC_TX_ABORT 		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */

board/Marvell/db64460/mv_eth.h

@@ -0,0 +1,840 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64460_ETH_H__
+#define __DB64460_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include "../common/ppc_error_no.h"
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64460_TX_QUEUE_NUM 1
+#define MV64460_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
+#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
+#else
+#define MV64460_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64460_ETH_RXQUEUE_SIZE
+#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
+#else
+#define MV64460_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64460_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64460_TX_BUFFER_SIZE 1600
+#endif
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64460_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+/* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+};
+
+int mv64460_eth_init (struct eth_device *dev);
+int mv64460_eth_stop (struct eth_device *dev);
+int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
+/*	return db64460_eth0_poll(); */
+
+int mv64460_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64460_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64460_ETH_ */

board/Marvell/db64460/pci.c

@@ -0,0 +1,940 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#include <pci.h>
+
+#include "../include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*                    - Make sure the GT is configured as a master before writing
+*                      to another device on the PCI.
+*                    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*                   (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*                    - Make sure the GT is configured as a master before reading
+*                     from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*                               the agent is placed on another Bus. For more
+*                               information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*           GT spec (or any other PCI device spec).
+*           unsigned int pciDevNum - The device number needs to be addressed.
+*           unsigned int busNum - On which bus does the Target agent connect
+*                                 to.
+*           unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*                               the agent target locate on another PCI bus.
+*                             - Make sure the GT is configured as a master
+*                               before reading from another device on the PCI.
+*                             - The function takes care of Big/Little endian
+*                               conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec). (configuration register offset.)
+*           pciDevNum: The device number needs to be addressed.
+*           busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*           - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*                         feature bits given as an input.
+*                       - Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*         unsigned int features - See file: pci.h there are defintion for those
+*                                 region features.
+*         unsigned int baseAddress - The region base Address.
+*         unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*                           to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*                      disable the park on last mechanism for each agent.
+*                      disabling this option for all agents results parking
+*                      on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*                       respond to grant assertion within a window specified in
+*                       the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*                       grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*                           Detection mechanism.
+*                           NOTE: This operation may cause a dead lock on the
+*                           pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*                 For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*                                      Boundry.
+*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*                                      Boundry.
+*          unsigned int busNum - The CPI bus number to which the PCI interface
+*                                      is connected.
+*          unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*                          supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*         snoopType - There is four optional Types:
+*                        1. No Snoop.
+*                        2. Snoop to WT region.
+*                        3. Snoop to WB region.
+*                        4. Snoop & Invalidate to WB region.
+*         baseAddress - Base Address of this region.
+*         regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+					0x0);
+		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+				       &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					bar_value);
+	}
+}
+
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CFG_PCI0_IO_SPACE_PCI,
+			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	pciArbiterEnable (PCI_HOST0);
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CFG_PCI1_IO_SPACE_PCI,
+			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}

board/Marvell/db64460/u-boot.lds

@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/Marvell/include/core.h

@@ -0,0 +1,238 @@
+/* Core.h - Basic core logic functions and definitions */
+
+/* Copyright Galileo Technology. */
+
+/*
+DESCRIPTION
+This header file contains simple read/write macros for addressing
+the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
+space). The macros take care of Big/Little endian conversions.
+*/
+
+#ifndef __INCcoreh
+#define __INCcoreh
+
+#include "mv_gen_reg.h"
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/****************************************/
+/*	    GENERAL Definitions			*/
+/****************************************/
+
+#define NO_BIT		0x00000000
+#define BIT0		0x00000001
+#define BIT1		0x00000002
+#define BIT2		0x00000004
+#define BIT3		0x00000008
+#define BIT4		0x00000010
+#define BIT5		0x00000020
+#define BIT6		0x00000040
+#define BIT7		0x00000080
+#define BIT8		0x00000100
+#define BIT9		0x00000200
+#define BIT10		0x00000400
+#define BIT11		0x00000800
+#define BIT12		0x00001000
+#define BIT13		0x00002000
+#define BIT14		0x00004000
+#define BIT15		0x00008000
+#define BIT16		0x00010000
+#define BIT17		0x00020000
+#define BIT18		0x00040000
+#define BIT19		0x00080000
+#define BIT20		0x00100000
+#define BIT21		0x00200000
+#define BIT22		0x00400000
+#define BIT23		0x00800000
+#define BIT24		0x01000000
+#define BIT25		0x02000000
+#define BIT26		0x04000000
+#define BIT27		0x08000000
+#define BIT28		0x10000000
+#define BIT29		0x20000000
+#define BIT30		0x40000000
+#define BIT31		0x80000000
+
+#define _1K		0x00000400
+#define _2K		0x00000800
+#define _4K		0x00001000
+#define _8K		0x00002000
+#define _16K		0x00004000
+#define _32K		0x00008000
+#define _64K		0x00010000
+#define _128K		0x00020000
+#define _256K		0x00040000
+#define _512K		0x00080000
+
+#define _1M		0x00100000
+#define _2M		0x00200000
+#define _3M		0x00300000
+#define _4M		0x00400000
+#define _5M		0x00500000
+#define _6M		0x00600000
+#define _7M		0x00700000
+#define _8M		0x00800000
+#define _9M		0x00900000
+#define _10M		0x00a00000
+#define _11M		0x00b00000
+#define _12M		0x00c00000
+#define _13M		0x00d00000
+#define _14M		0x00e00000
+#define _15M		0x00f00000
+#define _16M		0x01000000
+
+#define _32M		0x02000000
+#define _64M		0x04000000
+#define _128M		0x08000000
+#define _256M		0x10000000
+#define _512M		0x20000000
+
+#define _1G		0x40000000
+#define _2G		0x80000000
+
+typedef enum _bool{false,true} bool;
+
+/* Little to Big endian conversion macros */
+
+#ifdef LE /* Little Endian */
+#define SHORT_SWAP(X) (X)
+#define WORD_SWAP(X) (X)
+#define LONG_SWAP(X) ((l64)(X))
+
+#else	 /* Big Endian */
+#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
+
+#define WORD_SWAP(X) (((X)&0xff)<<24)+	    \
+		    (((X)&0xff00)<<8)+	    \
+		    (((X)&0xff0000)>>8)+    \
+		    (((X)&0xff000000)>>24)
+
+#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+		\
+			    (((X)&0xff00ULL)<<40)+		\
+			    (((X)&0xff0000ULL)<<24)+		\
+			    (((X)&0xff000000ULL)<<8)+		\
+			    (((X)&0xff00000000ULL)>>8)+		\
+			    (((X)&0xff0000000000ULL)>>24)+	\
+			    (((X)&0xff000000000000ULL)>>40)+	\
+			    (((X)&0xff00000000000000ULL)>>56))
+
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/* Those two definitions were defined to be compatible with MIPS */
+#define NONE_CACHEABLE		0x00000000
+#define CACHEABLE			0x00000000
+
+/* 750 cache line */
+#define CACHE_LINE_SIZE 32
+#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
+#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
+
+/* Read/Write to/from GT`s internal registers */
+#define GT_REG_READ(offset, pData)					    \
+*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE |			    \
+		INTERNAL_REG_BASE_ADDR | (offset))) ) ;						     \
+*pData = WORD_SWAP(*pData)
+
+#define GTREGREAD(offset)						    \
+	 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE |	     \
+		   INTERNAL_REG_BASE_ADDR | (offset))) ))
+
+#define GT_REG_WRITE(offset, data)					    \
+*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) =		    \
+		    WORD_SWAP(data)
+
+/* Write 32/16/8 bit */
+#define WRITE_CHAR(address, data)					    \
+	*((unsigned char *)(address)) = data
+#define WRITE_SHORT(address, data)					    \
+	*((unsigned short *)(address)) = data
+#define WRITE_WORD(address, data)					    \
+	*((unsigned int *)(address)) = data
+
+#define GT_WRITE_CHAR(address, data)	 WRITE_CHAR(address, data)
+
+/* Write 32/16/8 bit NonCacheable */
+/*
+#define GT_WRITE_CHAR(address, data)					       \
+	(*((unsigned char *)NONE_CACHEABLE(address))) = data
+#define GT_WRITE_SHORT(address, data)					       \
+	(*((unsigned short *)NONE_CACHEABLE(address))) = data
+#define GT_WRITE_WORD(address, data)					       \
+	(*((unsigned int *)NONE_CACHEABLE(address))) = data
+*/
+ /*#define GT_WRITE_CHAR(address, data)	  ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */
+
+ /*#define GT_WRITE_SHORT(address, data)   ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */
+
+ /*#define GT_WRITE_WORD(address, data)	 ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */
+
+
+/* Read 32/16/8 bits - returns data in variable. */
+#define READ_CHAR(address, pData)					    \
+	*pData = *((volatile unsigned char *)(address))
+
+#define READ_SHORT(address, pData)					    \
+	*pData = *((volatile unsigned short *)(address))
+
+#define READ_WORD(address, pData)					    \
+	*pData = *((volatile unsigned int *)(address))
+
+/* Read 32/16/8 bit - returns data direct. */
+#define READCHAR(address)						    \
+	*((volatile unsigned char *)((address) | NONE_CACHEABLE))
+
+#define READSHORT(address)						    \
+	*((volatile unsigned short *)((address) | NONE_CACHEABLE))
+
+#define READWORD(address)						    \
+	*((volatile unsigned int *)((address) | NONE_CACHEABLE))
+
+/* Those two Macros were defined to be compatible with MIPS */
+#define VIRTUAL_TO_PHY(x)    (((unsigned int)x) & 0xffffffff)
+#define PHY_TO_VIRTUAL(x)    (((unsigned int)x) | NONE_CACHEABLE)
+
+/*  SET_REG_BITS(regOffset,bits) -
+   gets register offset and bits: a 32bit value. It set to logic '1' in the
+   internal register the bits which given as an input example:
+   SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '1' in register 0x840 while the other bits stays as is. */
+#define SET_REG_BITS(regOffset,bits) \
+	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR |  \
+	regOffset) |= (unsigned int)WORD_SWAP(bits)
+
+/*  RESET_REG_BITS(regOffset,bits) -
+   gets register offset and bits: a 32bit value. It set to logic '0' in the
+   internal register the bits which given as an input example:
+   RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '0' in register 0x840 while the other bits stays as is. */
+#define RESET_REG_BITS(regOffset,bits) \
+	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR   \
+	| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
+/* gets register offset and bits: a 32bit value. It set to logic '1' in the
+   internal register the bits which given as an input example:
+   GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '1' in register 0x840 while the other bits stays as is. */
+ /*#define GT_SET_REG_BITS(regOffset,bits)	((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */
+ /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */
+#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits)
+/* gets register offset and bits: a 32bit value. It set to logic '0' in the
+   internal register the bits which given as an input example:
+   GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
+   logic '0' in register 0x840 while the other bits stays as is. */
+ /*#define GT_RESET_REG_BITS(regOffset,bits)	((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) |  (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */
+#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)
+
+
+#define DEBUG_LED0_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0)
+#define DEBUG_LED1_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0)
+#define DEBUG_LED2_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0)
+#define DEBUG_LED0_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0)
+#define DEBUG_LED1_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0)
+#define DEBUG_LED2_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0)
+
+#endif /* __INCcoreh */

board/Marvell/include/memory.h

@@ -0,0 +1,173 @@
+/* Memory.h - Memory mappings and remapping functions declarations */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCmemoryh
+#define __INCmemoryh
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+#define DONT_MODIFY	0xffffffff
+#define PARITY_SUPPORT	0x40000000
+#define MINIMUM_MEM_BANK_SIZE		0x10000
+#define MINIMUM_DEVICE_WINDOW_SIZE	0x10000
+#define MINIMUM_PCI_WINDOW_SIZE		0x10000
+#define MINIMUM_ACCESS_WIN_SIZE		0x10000
+
+#define _8BIT		0x00000000
+#define _16BIT		0x00100000
+#define _32BIT		0x00200000
+#define _64BIT		0x00300000
+
+/* typedefs */
+
+ typedef struct deviceParam
+{						/* boundary values  */
+    unsigned int    turnOff;			/* 0x0 - 0xf	    */
+    unsigned int    acc2First;			/* 0x0 - 0x1f	    */
+    unsigned int    acc2Next;		/* 0x0 - 0x1f	    */
+    unsigned int    ale2Wr;			/* 0x0 - 0xf	    */
+    unsigned int    wrLow;			/* 0x0 - 0xf	    */
+    unsigned int    wrHigh;			/* 0x0 - 0xf	    */
+    unsigned int    badrSkew;		/* 0x0 - 0x2	   */
+    unsigned int    DPEn;			/* 0x0 - 0x1	   */
+    unsigned int    deviceWidth;	/* in Bytes  */
+} DEVICE_PARAM;
+
+
+typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
+typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
+
+/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2,	\
+				   MEM_REGION3,MEM_REGION4,MEM_REGION5,	      \
+				   MEM_REGION6,MEM_REGION7}		      \
+				   MEMORY_PROTECT_REGION;*/
+/* There are four possible windows that can be defined as protected */
+typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
+				  MEM_WINDOW3
+				 } MEMORY_PROTECT_WINDOW;
+/* When defining a protected window , this paramter indicates whether it
+   is accessible or not */
+typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN}	      \
+			    MEMORY_ACCESS;
+typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN}	      \
+			   MEMORY_ACCESS_WRITE;
+typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN}	      \
+				  MEMORY_CACHE_PROTECT;
+typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB}	      \
+			       MEMORY_SNOOP_TYPE;
+typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1,	      \
+				 MEM_SNOOP_REGION2,MEM_SNOOP_REGION3}	      \
+				 MEMORY_SNOOP_REGION;
+
+/* There are 21 memory windows dedicated for the varios interfaces (PCI,
+   devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
+   address decoding mechanism. */
+typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
+			    CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
+			    DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
+			    DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
+			    BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
+			    PCI_0_MEM0_WINDOW = BIT10,
+			    PCI_0_MEM1_WINDOW = BIT11,
+			    PCI_0_MEM2_WINDOW = BIT12,
+			    PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
+			    PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
+			    PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
+			    INTEGRATED_SRAM_WINDOW = BIT19,
+			    INTERNAL_SPACE_WINDOW = BIT20,
+			    ALL_WINDOWS = 0X1FFFFF
+			   } MEMORY_WINDOW;
+
+typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
+				 } MEMORY_WINDOW_STATUS;
+
+
+typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
+#ifdef INCLUDE_PCI_1
+			  ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
+#endif /* INCLUDE_PCI_1 */
+			  } PCI_MEM_WINDOW;
+
+
+/* -------------------------------------------------------------------------------------------------*/
+
+/* functions */
+unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
+unsigned int memoryGetDeviceBaseAddress(DEVICE device);
+/* New at MV6436x */
+unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
+unsigned int memoryGetBankSize(MEMORY_BANK bank);
+unsigned int memoryGetDeviceSize(DEVICE device);
+unsigned int memoryGetDeviceWidth(DEVICE device);
+/* New at MV6436x */
+unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
+
+/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
+bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
+/* Set a new base and size for one of the memory banks (CS0 - CS3) */
+bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
+			   unsigned int bankSize);
+bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
+
+/* Change the Internal Register Base Address to a new given Address. */
+bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
+/* returns internal Register Space Base Address. */
+unsigned int memoryGetInternalRegistersSpace(void);
+
+/* Returns the integrated SRAM Base Address. */
+unsigned int memoryGetInternalSramBaseAddr(void);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Set new base address for the integrated SRAM. */
+void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Delete a protection feature to a given space. */
+void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Writes a new remap value to the remap register */
+unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
+				      unsigned int remapValueHigh,
+				      unsigned int remapValueLow);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Configurate the protection feature to a given space. */
+bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
+			      MEMORY_ACCESS gtMemoryAccess,
+			      MEMORY_ACCESS_WRITE gtMemoryWrite,
+			      MEMORY_CACHE_PROTECT cacheProtection,
+			      unsigned int baseAddress,
+			      unsigned int size);
+
+/* Configurate the protection feature to a given space. */
+/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
+			    MEMORY_ACCESS memoryAccess,
+			    MEMORY_ACCESS_WRITE memoryWrite,
+			    MEMORY_CACHE_PROTECT cacheProtection,
+			    unsigned int baseAddress,
+			    unsigned int regionLength); */
+/* Configurate the snoop feature to a given space. */
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+			      MEMORY_SNOOP_TYPE snoopType,
+			      unsigned int baseAddress,
+			      unsigned int regionLength);
+
+bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
+bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+/* Set a new base and size for one of the PCI windows. */
+bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
+			  unsigned int pciWindowSize);
+
+/* Disable or enable one of the 21 windows dedicated for the CPU's
+   address decoding mechanism */
+void MemoryDisableWindow(MEMORY_WINDOW window);
+void MemoryEnableWindow (MEMORY_WINDOW window);
+MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
+#endif	/* __INCmemoryh */

board/Marvell/include/pci.h

@@ -0,0 +1,293 @@
+/* PCI.h - PCI functions header file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCpcih
+#define __INCpcih
+
+/* includes */
+
+#include"core.h"
+#include"memory.h"
+
+/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
+#define PCI_MAX_DEVICES 22
+
+
+/* Macros */
+
+/* The next Macros configurate the initiator board (SELF) or any any agent on
+   the PCI to become: MASTER, response to MEMORY transactions , response to
+   IO transactions or TWO both MEMORY_IO transactions. Those configuration
+   are for both PCI0 and PCI1. */
+
+#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |		     \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |		     \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host,		       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &		     \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
+
+#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |		     \
+	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host,	      \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &		     \
+	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define		MASTER_ENABLE			BIT2
+#define		MEMORY_ENABLE			BIT1
+#define		I_O_ENABLE			BIT0
+#define	    SELF		    32
+
+/* Agent on the PCI bus may have up to 6 BARS. */
+#define	    BAR0		    0x10
+#define	    BAR1		    0x14
+#define	    BAR2		    0x18
+#define	    BAR3		    0x1c
+#define	    BAR4		    0x20
+#define	    BAR5		    0x24
+#define		BAR_SEL_MEM_IO			BIT0
+#define		BAR_MEM_TYPE_32_BIT		NO_BIT
+#define		BAR_MEM_TYPE_BELOW_1M		       BIT1
+#define		BAR_MEM_TYPE_64_BIT			      BIT2
+#define		BAR_MEM_TYPE_RESERVED		      (BIT1 | BIT2)
+#define		BAR_MEM_TYPE_MASK		      (BIT1 | BIT2)
+#define		BAR_PREFETCHABLE				      BIT3
+#define		BAR_CONFIG_MASK			(BIT0 | BIT1 | BIT2 | BIT3)
+
+/* Defines for the access regions. */
+#define	    PREFETCH_ENABLE		    BIT12
+#define	    PREFETCH_DISABLE		    NO_BIT
+#define	    DELAYED_READ_ENABLE		    BIT13
+/* #define     CACHING_ENABLE		       BIT14 */
+/* aggressive prefetch: PCI slave prefetch two burst in advance*/
+#define	    AGGRESSIVE_PREFETCH		     BIT16
+/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define	    READ_LINE_AGGRESSIVE_PREFETCH   BIT17
+/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define	    READ_MULTI_AGGRESSIVE_PREFETCH  BIT18
+#define	    MAX_BURST_4			    NO_BIT
+#define	    MAX_BURST_8			    BIT20  /* Bits[21:20] = 01 */
+#define	    MAX_BURST_16		    BIT21  /* Bits[21:20] = 10 */
+#define	    PCI_BYTE_SWAP		    NO_BIT /* Bits[25:24] = 00 */
+#define	    PCI_NO_SWAP			    BIT24  /* Bits[25:24] = 01 */
+#define	    PCI_BYTE_AND_WORD_SWAP	    BIT25  /* Bits[25:24] = 10 */
+#define	    PCI_WORD_SWAP		   (BIT24 | BIT25) /* Bits[25:24] = 11 */
+#define	    PCI_ACCESS_PROTECT		    BIT28
+#define	    PCI_WRITE_PROTECT		    BIT29
+
+/* typedefs */
+
+typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
+				REGION6,REGION7} PCI_ACCESS_REGIONS;
+
+typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
+typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
+
+typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
+			    PCI_SNOOP_TYPE;
+typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
+			      PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
+			      PCI_SNOOP_REGION;
+
+typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
+typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
+			 PCI_REGION2,PCI_REGION3,
+			 PCI_IO}
+			 PCI_REGION;
+
+/*ronen 7/Dec/03 */
+typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
+			       PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
+			       PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
+			       PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
+			       PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
+			       PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
+			       PCI_LAST_BAR} PCI_INTERNAL_BAR;
+
+typedef struct pciBar {
+    unsigned int detectBase;
+    unsigned int base;
+    unsigned int size;
+    unsigned int type;
+} PCI_BAR;
+
+typedef struct pciDevice {
+    PCI_HOST	     host;
+    char	    type[40];
+    unsigned int    deviceNum;
+    unsigned int    venID;
+    unsigned int    deviceID;
+    PCI_BAR bar[6];
+} PCI_DEVICE;
+
+typedef struct pciSelfBars {
+    unsigned int    SCS0Base;
+    unsigned int    SCS0Size;
+    unsigned int    SCS1Base;
+    unsigned int    SCS1Size;
+    unsigned int    SCS2Base;
+    unsigned int    SCS2Size;
+    unsigned int    SCS3Base;
+    unsigned int    SCS3Size;
+    unsigned int    internalMemBase;
+    unsigned int    internalIOBase;
+    unsigned int    CS0Base;
+    unsigned int    CS0Size;
+    unsigned int    CS1Base;
+    unsigned int    CS1Size;
+    unsigned int    CS2Base;
+    unsigned int    CS2Size;
+    unsigned int    CS3Base;
+    unsigned int    CS3Size;
+    unsigned int    CSBootBase;
+    unsigned int    CSBootSize;
+    unsigned int    P2PMem0Base;
+    unsigned int    P2PMem0Size;
+    unsigned int    P2PMem1Base;
+    unsigned int    P2PMem1Size;
+    unsigned int    P2PIOBase;
+    unsigned int    P2PIOSize;
+    unsigned int    CPUBase;
+    unsigned int    CPUSize;
+} PCI_SELF_BARS;
+
+/* read/write configuration registers on local PCI bus. */
+void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
+		       unsigned int pciDevNum, unsigned int data);
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum);
+
+/* read/write configuration registers on another PCI bus. */
+void pciOverBridgeWriteConfigReg(PCI_HOST host,
+				 unsigned int regOffset,
+				 unsigned int pciDevNum,
+				 unsigned int busNum,unsigned int data);
+unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
+					unsigned int regOffset,
+					unsigned int pciDevNum,
+					unsigned int busNum);
+
+/* Performs full scane on both PCI and returns all detail possible on the
+   agents which exist on the bus. */
+void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
+		    unsigned int numberOfElment);
+
+/*	Master`s memory space	*/
+bool pciMapSpace(PCI_HOST host, PCI_REGION region,
+		unsigned int remapBase,
+		unsigned int deviceBase,
+		unsigned int deviceLength);
+unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
+unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
+
+/*	Slave`s memory space   */
+void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
+		      unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
+
+#if 0 /* GARBAGE routines - dont use till they get cleaned up */
+void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
+void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
+void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
+void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
+void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
+void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
+void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
+			       unsigned int pci0Dev0Length);
+void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
+			       unsigned int pci1Dev0Length);
+void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
+			       unsigned int pci0Dev1Length);
+void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
+			       unsigned int pci1Dev1Length);
+void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
+			       unsigned int pci0Dev2Length);
+void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
+			       unsigned int pci1Dev2Length);
+void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
+			       unsigned int pci0Dev3Length);
+void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
+			       unsigned int pci1Dev3Length);
+void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
+				  unsigned int pci0DevBootLength);
+void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
+				  unsigned int pci1DevBootLength);
+void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
+			 unsigned int pci0P2pMem0Length);
+void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
+			 unsigned int pci1P2pMem0Length);
+void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
+			 unsigned int pci0P2pMem1Length);
+void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
+			 unsigned int pci1P2pMem1Length);
+void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
+		       unsigned int pci0P2pIoLength);
+void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
+		       unsigned int pci1P2pIoLength);
+
+void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
+void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
+#endif
+
+/* PCI region options */
+
+bool  pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
+	unsigned int features, unsigned int baseAddress,
+	unsigned int regionLength);
+
+void  pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
+
+/* PCI arbiter */
+
+bool pciArbiterEnable(PCI_HOST host);
+bool pciArbiterDisable(PCI_HOST host);
+bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5);
+bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5);
+bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5);
+bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
+bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
+
+/* PCI-to-PCI (P2P) */
+
+bool pciP2PConfig(PCI_HOST host,
+		  unsigned int SecondBusLow,unsigned int SecondBusHigh,
+		  unsigned int busNum,unsigned int devNum);
+/* PCI Cache-coherency */
+
+bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength);
+
+PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
+
+#endif /* __INCpcih */

board/RPXClassic/RPXClassic.c

@@ -220,42 +220,10 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];			/* to make test non-destructive */
-	unsigned char i = 0;
 
 	memctl->memc_mamr = mamr_value;
 
-	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
-
-	/* write 0 to base address */
-	addr = base;
-	save[i] = *addr;
-	*addr = 0;
-
-	/* check at base address */
-	if ((val = *addr) != 0) {
-		*addr = save[i];
-		return (0);
-	}
-
-	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
-		addr = base + cnt;		/* pointer arith! */
-
-		val = *addr;
-		*addr = save[--i];
-
-		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
-		}
-	}
-	return (maxsize);
+	return (get_ram_size(base, maxsize));
 }
 /*-----------------------------------------------------------------------------
  * aschex_to_byte --

board/RPXlite/RPXlite.c

@@ -40,20 +40,19 @@ static long int dram_size (long int, long int *, long int);
 
 #define	_NOT_USED_	0xFFFFCC25
 
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
 	/*
 	 * Single Read. (Offset 00h in UPMA RAM)
 	 */
 	0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
-	0x3FBFCC27, /* last */
+	0x3FBFCC27,		/* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Burst Read. (Offset 08h in UPMA RAM)
 	 */
 	0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
-	0x3FBFCC27, /* last */
+	0x3FBFCC27,		/* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_,
@@ -62,14 +61,14 @@ const uint sdram_table[] =
 	 * Single Write. (Offset 18h in UPMA RAM)
 	 */
 	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
-	0x3FFFCC27, /* last */
+	0x3FFFCC27,		/* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Burst Write. (Offset 20h in UPMA RAM)
 	 */
 	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
-	0x0CFFCC00, 0x33FFCC27, /* last */
+	0x0CFFCC00, 0x33FFCC27,	/* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_,
@@ -78,7 +77,7 @@ const uint sdram_table[] =
 	 * Refresh. (Offset 30h in UPMA RAM)
 	 */
 	0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
-	0x3FFFCC27, /* last */
+	0x3FFFCC27,		/* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_,
 
@@ -97,49 +96,51 @@ const uint sdram_table[] =
 
 int checkboard (void)
 {
-	puts ("Board: RPXlite\n") ;
-	return (0) ;
+	puts ("Board: RPXlite\n");
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
 
 long int initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
-    long int size10 ;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size10;
 
-    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
 
 	/* Refresh clock prescalar */
-    memctl->memc_mptpr = CFG_MPTPR ;
+	memctl->memc_mptpr = CFG_MPTPR;
 
-    memctl->memc_mar  = 0x00000000;
+	memctl->memc_mar = 0x00000000;
 
 	/* Map controller banks 1 to the SDRAM bank */
-    memctl->memc_or1 = CFG_OR1_PRELIM;
-    memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
 
-    memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
+	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
 
-    udelay(200);
+	udelay (200);
 
-    /* perform SDRAM initializsation sequence */
+	/* perform SDRAM initializsation sequence */
 
-	memctl->memc_mcr  = 0x80002230 ; /* SDRAM bank 0 - refresh twice */
-    udelay(1);
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - refresh twice */
+	udelay (1);
 
-    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
 
-    udelay (1000);
+	udelay (1000);
 
 	/* Check Bank 0 Memory Size
 	 * try 10 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
+	size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
+			    SDRAM_MAX_SIZE);
 
-    return (size10);
+	return (size10);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -152,44 +153,13 @@ long int initdram (int board_type)
  * - short between data lines
  */
 
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
-    volatile long int	 *addr;
-    ulong		  cnt, val;
-    ulong		  save[32];	/* to make test non-destructive */
-    unsigned char	  i = 0;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
-    memctl->memc_mamr = mamr_value;
+	memctl->memc_mamr = mamr_value;
 
-    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
-	addr = base + cnt;	/* pointer arith! */
-
-	save[i++] = *addr;
-	*addr = ~cnt;
-    }
-
-    /* write 0 to base address */
-    addr = base;
-    save[i] = *addr;
-    *addr = 0;
-
-    /* check at base address */
-    if ((val = *addr) != 0) {
-	*addr = save[i];
-	return (0);
-    }
-
-    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
-	addr = base + cnt;	/* pointer arith! */
-
-	val = *addr;
-	*addr = save[--i];
-
-	if (val != (~cnt)) {
-	    return (cnt * sizeof(long));
-	}
-    }
-    return (maxsize);
+	return (get_ram_size (base, maxsize));
 }

board/RRvision/RRvision.c

@@ -229,40 +229,8 @@ static long int dram_size (long int mamr_value, long int *base,
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];			/* to make test non-destructive */
-	unsigned char i = 0;
 
 	memctl->memc_mamr = mamr_value;
 
-	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
-
-	/* write 0 to base address */
-	addr = base;
-	save[i] = *addr;
-	*addr = 0;
-
-	/* check at base address */
-	if ((val = *addr) != 0) {
-		*addr = save[i];
-		return (0);
-	}
-
-	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		val = *addr;
-		*addr = save[--i];
-
-		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
-		}
-	}
-	return (maxsize);
+	return (get_ram_size(base, maxsize));
 }

board/a3000/a3000.c

@@ -40,50 +40,24 @@ int checkboard (void)
 
 long int initdram (int board_type)
 {
-	int              i, cnt;
-	volatile uchar * base= CFG_SDRAM_BASE;
-	volatile ulong * addr;
-	ulong            save[32];
-	ulong            val, ret  = 0;
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
 
-	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
-		addr = (volatile ulong *)base + cnt;
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
 
-	addr = (volatile ulong *)base;
-	save[i] = *addr;
-	*addr = 0;
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
 
-	if (*addr != 0) {
-		*addr = save[i];
-		goto Done;
-	}
-
-	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
-		addr = (volatile ulong *)base + cnt;
-		val = *addr;
-		*addr = save[--i];
-		if (val != ~cnt) {
-			ulong new_bank0_end = cnt * sizeof(long) - 1;
-			ulong mear1  = mpc824x_mpc107_getreg(MEAR1);
-			ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
-			mear1 =  (mear1  & 0xFFFFFF00) |
-			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
-			emear1 = (emear1 & 0xFFFFFF00) |
-			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-			mpc824x_mpc107_setreg(MEAR1,  mear1);
-			mpc824x_mpc107_setreg(EMEAR1, emear1);
-
-			ret = cnt * sizeof(long);
-			goto Done;
-		}
-	}
-
-	ret = CFG_MAX_RAM_SIZE;
-Done:
-	return ret;
+	return (size);
 }
 
 /*

board/adderII/adderII.h

@@ -41,5 +41,3 @@
  * | 			   |
  * | ...                   |
  *****************************************************************************/
-
-

board/adderII/config.mk

@@ -26,4 +26,3 @@
 #
 
 TEXT_BASE = 0xFE000000
-

board/adderII/u-boot.lds

@@ -144,4 +144,3 @@ SECTIONS
   _end = . ;
   PROVIDE (end = .);
 }
-

board/altera/common/flash.c

@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <nios.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+	int i, k;
+	unsigned long size;
+	int erased;
+	volatile unsigned char *flash;
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+
+		/* Check if whole sector is erased */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned char *) info->start[i];
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		/* Print the info */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s", info->start[i], erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int prot, sect;
+	unsigned oldpri;
+	ulong start;
+
+	/* Some sanity checking */
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	for (sect = s_first; sect <= s_last; sect++) {
+		printf("- Erase: Sect: %i @ 0x%08x\n", sect,  info->start[sect]);
+	}
+#endif
+
+	/* NOTE: disabling interrupts on Nios can be very bad since it
+	 * also disables the LO_LIMIT exception. It's better here to
+	 * set the interrupt priority to 3 & restore it when we're done.
+	 */
+	oldpri = ipri (3);
+
+	/* It's ok to erase multiple sectors provided we don't delay more
+	 * than 50 usec between cmds ... at which point the erase time-out
+	 * occurs. So don't go and put printf() calls in the loop ... it
+	 * won't be very helpful ;-)
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			*addr = 0xaa;
+			*addr = 0x55;
+			*addr = 0x80;
+			*addr = 0xaa;
+			*addr = 0x55;
+			*addr2 = 0x30;
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait. Here we have to grant
+			 * timer interrupts. Otherwise get_timer() can't
+			 * work right. */
+			ipri(oldpri);
+			start = get_timer (0);
+			while (*addr2 != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+			oldpri = ipri (3); /* disallow non important irqs again */
+		}
+	}
+
+	printf ("\n");
+
+	/* Restore interrupt priority */
+	ipri (oldpri);
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+
+	vu_char *cmd = (vu_char *) info->start[0];
+	vu_char *dst = (vu_char *) addr;
+	unsigned char b;
+	unsigned oldpri;
+	ulong start;
+
+	while (cnt) {
+		/* Check for sufficient erase */
+		b = *src;
+		if ((*dst & b) != b) {
+			printf ("%02x : %02x\n", *dst, b);
+			return (2);
+		}
+
+		/* Disable interrupts other than window underflow
+		 * (interrupt priority 2)
+		 */
+		oldpri = ipri (3);
+		*cmd = 0xaa;
+		*cmd = 0x55;
+		*cmd = 0xa0;
+		*dst = b;
+
+		/* Verify write */
+		start = get_timer (0);
+		while (*dst != b) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				ipri (oldpri);
+				return 1;
+			}
+		}
+		dst++;
+		src++;
+		cnt--;
+		ipri (oldpri);
+	}
+
+	return (0);
+}

board/altera/common/sevenseg.c

@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * common/sevenseg.c
+ *
+ * NIOS PIO based seven segment led support functions
+ */
+
+#include <common.h>
+#include <nios-io.h>
+
+#ifdef	CONFIG_SEVENSEG
+
+#define SEVENDEG_MASK_DP	((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP)
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+#if (SEVENSEG_ACTIVE == 0)
+static unsigned int sevenseg_portval = ~0;
+#else
+static unsigned int sevenseg_portval = 0;
+#endif
+#endif
+
+static int sevenseg_init_done = 0;
+
+static inline void __sevenseg_set_masked (unsigned int mask, int value)
+{
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+
+#if (SEVENSEG_ACTIVE == 0)
+	if (value)
+		sevenseg_portval &= ~mask;
+	else
+		sevenseg_portval |= mask;
+#else
+	if (value)
+		sevenseg_portval |= mask;
+	else
+		sevenseg_portval &= ~mask;
+#endif
+
+	piop->data = sevenseg_portval;
+
+#else	/* !SEVENSEG_WRONLY */
+
+#if (SEVENSEG_ACTIVE == 0)
+	if (value)
+		piop->data &= ~mask;
+	else
+		piop->data |= mask;
+#else
+	if (value)
+		piop->data |= mask;
+	else
+		piop->data &= ~mask;
+#endif
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+static inline void __sevenseg_toggle_masked (unsigned int mask)
+{
+	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+
+	sevenseg_portval ^= mask;
+	piop->data = sevenseg_portval;
+
+#else	/* !SEVENSEG_WRONLY */
+
+	piop->data ^= mask;
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+static inline void __sevenseg_set (unsigned int value)
+{
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+
+#if (SEVENSEG_ACTIVE == 0)
+	sevenseg_portval = (sevenseg_portval &   SEVENDEG_MASK_DP)
+		         | ((~value)         & (~SEVENDEG_MASK_DP));
+#else
+	sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
+		         | (value);
+#endif
+
+	piop->data = sevenseg_portval;
+
+#else	/* !SEVENSEG_WRONLY */
+
+#if (SEVENSEG_ACTIVE == 0)
+	piop->data = (piop->data &   SEVENDEG_MASK_DP)
+		   | ((~value)   & (~SEVENDEG_MASK_DP));
+#else
+	piop->data = (piop->data & SEVENDEG_MASK_DP)
+		   | (value);
+#endif
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+static inline void __sevenseg_init (void)
+{
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
+
+	__sevenseg_set(0);
+
+#ifndef	SEVENSEG_WRONLY	/* setup direction */
+
+	piop->direction |= mask;
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+
+void sevenseg_set(int value)
+{
+	unsigned char	digits[] = {
+		SEVENSEG_DIGITS_0,
+		SEVENSEG_DIGITS_1,
+		SEVENSEG_DIGITS_2,
+		SEVENSEG_DIGITS_3,
+		SEVENSEG_DIGITS_4,
+		SEVENSEG_DIGITS_5,
+		SEVENSEG_DIGITS_6,
+		SEVENSEG_DIGITS_7,
+		SEVENSEG_DIGITS_8,
+		SEVENSEG_DIGITS_9,
+		SEVENSEG_DIGITS_A,
+		SEVENSEG_DIGITS_B,
+		SEVENSEG_DIGITS_C,
+		SEVENSEG_DIGITS_D,
+		SEVENSEG_DIGITS_E,
+		SEVENSEG_DIGITS_F
+	};
+
+	if (!sevenseg_init_done) {
+		__sevenseg_init();
+		sevenseg_init_done++;
+	}
+
+	switch (value & SEVENSEG_MASK_CTRL) {
+
+		case SEVENSEG_RAW:
+			__sevenseg_set( (
+				(digits[((value & SEVENSEG_MASK_VAL) >>  4)] << 8) |
+				digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) );
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_OFF:
+			__sevenseg_set(0);
+			__sevenseg_set_masked(SEVENDEG_MASK_DP, 0);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_SET_DPL:
+			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_SET_DPH:
+			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_RES_DPL:
+			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_RES_DPH:
+			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_TOG_DPL:
+			__sevenseg_toggle_masked(SEVENSEG_DIGIT_DP);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_TOG_DPH:
+			__sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8));
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_LO:
+		case SEVENSEG_HI:
+		case SEVENSEG_STR:
+		default:
+			break;
+	}
+}
+
+#endif	/* CONFIG_SEVENSEG */

board/altera/common/sevenseg.h

@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * common/sevenseg.h
+ *
+ * NIOS PIO based seven segment led support functions
+ */
+
+#ifndef __DK1S10_SEVENSEG_H__
+#define __DK1S10_SEVENSEG_H__
+
+#ifdef	CONFIG_SEVENSEG
+
+/*
+ *  15                    8 7      0
+ * |-----------------------|--------|
+ * |   controll value      |  value |
+ * ----------------------------------
+ */
+#define	SEVENSEG_RAW		(int)(0)	/* write out byte value (hex) */
+#define	SEVENSEG_OFF		(int)( 1 << 8)	/* display switch off */
+#define	SEVENSEG_SET_DPL	(int)( 2 << 8)	/* set dp low  nibble */
+#define	SEVENSEG_SET_DPH	(int)( 3 << 8)	/* set dp high nibble */
+#define	SEVENSEG_RES_DPL	(int)( 4 << 8)	/* reset dp low  nibble */
+#define	SEVENSEG_RES_DPH	(int)( 5 << 8)	/* reset dp high nibble */
+#define	SEVENSEG_TOG_DPL	(int)( 6 << 8)	/* toggle dp low  nibble */
+#define	SEVENSEG_TOG_DPH	(int)( 7 << 8)	/* toggle dp high nibble */
+#define	SEVENSEG_LO		(int)( 8 << 8)	/* write out low nibble only */
+#define	SEVENSEG_HI		(int)( 9 << 8)	/* write out high nibble only */
+#define	SEVENSEG_STR		(int)(10 << 8)	/* write out a string */
+
+#define	SEVENSEG_MASK_VAL	(0xff)		/* only used by SEVENSEG_RAW */
+#define	SEVENSEG_MASK_CTRL	(~SEVENSEG_MASK_VAL)
+
+#ifdef	SEVENSEG_DIGIT_HI_LO_EQUAL
+
+#define	SEVENSEG_DIGITS_0	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	)
+#define	SEVENSEG_DIGITS_1	(	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	)
+#define	SEVENSEG_DIGITS_2	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_3	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_4	(	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_5	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_6	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_7	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	)
+#define	SEVENSEG_DIGITS_8	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_9	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_A	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_B	(	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_C	(	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_D	(	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_E	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_F	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+
+#else	/* !SEVENSEG_DIGIT_HI_LO_EQUAL */
+#error SEVENSEG: different pin asssignments not supported
+#endif
+
+void sevenseg_set(int value);
+
+#endif	/* CONFIG_SEVENSEG */
+
+#endif	/* __DK1S10_SEVENSEG_H__ */

board/altera/dk1c20/Makefile

@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o misc.o
+
+SOBJS  = vectors.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/altera/dk1c20/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2003
+# Psyent Corporation
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x018c0000
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif

board/altera/dk1c20/dk1c20.c

@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if	defined(CONFIG_SEVENSEG)
+#include "../common/sevenseg.h"
+#endif
+
+void _default_hdlr (void)
+{
+	printf ("default_hdlr\n");
+}
+
+int board_early_init_f (void)
+{
+#if	defined(CONFIG_SEVENSEG)
+	/* init seven segment led display and switch off */
+	sevenseg_set(SEVENSEG_OFF);
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Altera Nios 1C20 Development Kit\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}

board/altera/dk1c20/flash.c

@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <nios.h>
+
+/*
+ * include common flash code (for altera boards)
+ */
+#include "../common/flash.c"
+
+/*----------------------------------------------------------------------*/
+#define BANKSZ		CFG_FLASH_SIZE
+#define SECTSZ		(64 * 1024)
+#define USERFLASH	(2 * 1024 * 1024)	/* bottom 2 MB for user	*/
+
+/*----------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = BANKSZ;
+	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
+
+	addr = CFG_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+
+		/* Protect all but 2 MByte user area */
+		if (addr < (CFG_FLASH_BASE + USERFLASH))
+			fli->protect[i] = 0;
+		else
+			fli->protect[i] = 1;
+	}
+
+	return (BANKSZ);
+}

board/altera/dk1c20/misc.c

@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * board/altera/dk1s10/misc.c
+ *
+ * miscellaneous board interfaces / drivers
+ */
+
+#include <common.h>
+
+#if	defined(CONFIG_SEVENSEG)
+#include "../common/sevenseg.h"
+#include "../common/sevenseg.c"
+#endif

board/altera/dk1c20/u-boot.lds

@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-nios")
+OUTPUT_ARCH(nios)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios/start.o (.text)
+	  *(.text)
+	}
+	__text_end = .;
+
+	. = ALIGN(4);
+	.rodata :
+	{
+		*(.rodata)
+	}
+	__rodata_end = .;
+
+	. = ALIGN(4);
+	.data :
+	{
+		*(.data)
+	}
+	. = ALIGN(4);
+	__data_end = .;
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	__bss_start = .;
+	. = ALIGN(4);
+	.bss :
+	{
+		*(.bss)
+	}
+	. = ALIGN(4);
+	__bss_end = .;
+}

board/altera/dk1c20/vectors.S

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*************************************************************************
+ * Exception Vector Table
+ *
+ * This could have gone in the cpu soure tree, but the whole point of
+ * Nios is customization -- and polluting the cpu source tree with
+ * board-specific ifdef's really defeats the purpose, no? With this in
+ * the board-specific tree, each board has the freedom to organize
+ * vectors/traps, etc anyway it wants. The init code copies this table
+ * to the proper location.
+ *
+ * Each board can do what it likes here. But there are four "standard"
+ * handlers availble:
+ *
+ *	_cwp_lolimit	-Handles register window underflows.
+ *	_cwp_hilimit	-Handles register window overflows.
+ *	_timebase_int	-Increments the timebase.
+ *	_def_xhandler	-Default exception handler.
+ *
+ * _timebase_int handles a Nios Timer interrupt and increments the
+ * timestamp used for the get_timer(), reset_timer(), etc. routines. It
+ * expects the timer to be configured like the standard-32 low priority
+ * timer.
+ *
+ * _def_xhandler dispatches exceptions/traps via the external_interrupt()
+ * routine. This lets you use the irq_install_handler() and handle your
+ * interrupts/traps with code written in C.
+ ************************************************************************/
+
+	.data
+	.global _vectors
+	.align	4
+_vectors:
+
+	.long	_def_xhandler@h		/* Vector 0  - NMI */
+	.long	_cwp_lolimit@h		/* Vector 1  -  underflow */
+	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
+
+	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 4 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 6 - future reserved */
+	.long	_def_xhandler@h		/* Vector 7 - future reserved */
+	.long	_def_xhandler@h		/* Vector 8 - future reserved */
+	.long	_def_xhandler@h		/* Vector 9 - future reserved */
+	.long	_def_xhandler@h		/* Vector 10 - future reserved */
+	.long	_def_xhandler@h		/* Vector 11 - future reserved */
+	.long	_def_xhandler@h		/* Vector 12 - future reserved */
+	.long	_def_xhandler@h		/* Vector 13 - future reserved */
+	.long	_def_xhandler@h		/* Vector 14 - future reserved */
+	.long	_def_xhandler@h		/* Vector 15 - future reserved */
+	.long	_def_xhandler@h		/* Vector 16 */
+	.long	_def_xhandler@h		/* Vector 17 */
+	.long	_def_xhandler@h		/* Vector 18 */
+	.long	_def_xhandler@h		/* Vector 19 */
+	.long	_def_xhandler@h		/* Vector 20 */
+	.long	_def_xhandler@h		/* Vector 21 */
+	.long	_def_xhandler@h		/* Vector 22 */
+	.long	_def_xhandler@h		/* Vector 23 */
+	.long	_def_xhandler@h		/* Vector 24 */
+	.long	_def_xhandler@h		/* Vector 25 */
+	.long	_def_xhandler@h		/* Vector 26 */
+	.long	_def_xhandler@h		/* Vector 27 */
+	.long	_def_xhandler@h		/* Vector 28 */
+	.long	_def_xhandler@h		/* Vector 29 */
+	.long	_def_xhandler@h		/* Vector 30 */
+	.long	_def_xhandler@h		/* Vector 31 */
+	.long	_def_xhandler@h		/* Vector 32 */
+	.long	_def_xhandler@h		/* Vector 33 */
+	.long	_def_xhandler@h		/* Vector 34 */
+	.long	_def_xhandler@h		/* Vector 35 */
+	.long	_def_xhandler@h		/* Vector 36 */
+	.long	_def_xhandler@h		/* Vector 37 */
+	.long	_def_xhandler@h		/* Vector 38 */
+	.long	_def_xhandler@h		/* Vector 39 */
+	.long	_def_xhandler@h		/* Vector 40 */
+	.long	_def_xhandler@h		/* Vector 41 */
+	.long	_def_xhandler@h		/* Vector 42 */
+	.long	_def_xhandler@h		/* Vector 43 */
+	.long	_def_xhandler@h		/* Vector 44 */
+	.long	_def_xhandler@h		/* Vector 45 */
+	.long	_def_xhandler@h		/* Vector 46 */
+	.long	_def_xhandler@h		/* Vector 47 */
+	.long	_def_xhandler@h		/* Vector 48 */
+	.long	_def_xhandler@h		/* Vector 49 */
+	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
+	.long	_def_xhandler@h		/* Vector 51 */
+	.long	_def_xhandler@h		/* Vector 52 */
+	.long	_def_xhandler@h		/* Vector 53 */
+	.long	_def_xhandler@h		/* Vector 54 */
+	.long	_def_xhandler@h		/* Vector 55 */
+	.long	_def_xhandler@h		/* Vector 56 */
+	.long	_def_xhandler@h		/* Vector 57 */
+	.long	_def_xhandler@h		/* Vector 58 */
+	.long	_def_xhandler@h		/* Vector 59 */
+	.long	_def_xhandler@h		/* Vector 60 */
+	.long	_def_xhandler@h		/* Vector 61 */
+	.long	_def_xhandler@h		/* Vector 62 */
+	.long	_def_xhandler@h		/* Vector 63 */

board/altera/dk1s10/Makefile

@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o misc.o
+
+SOBJS  = vectors.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/altera/dk1s10/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2003
+# Psyent Corporation
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x018c0000
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif

board/altera/dk1s10/dk1s10.c

@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if	defined(CONFIG_SEVENSEG)
+#include "../common/sevenseg.h"
+#endif
+
+void _default_hdlr (void)
+{
+	printf ("default_hdlr\n");
+}
+
+int board_early_init_f (void)
+{
+#if	defined(CONFIG_SEVENSEG)
+	/* init seven segment led display and switch off */
+	sevenseg_set(SEVENSEG_OFF);
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Altera Nios 1S10 Development Kit\n");
+#if     defined(CONFIG_NIOS_SAFE_32)
+	puts ("Conf.: Altera Safe 32 (safe_32)\n");
+#elif   defined(CONFIG_NIOS_STANDARD_32)
+	puts ("Conf.: Altera Standard 32 (standard_32)\n");
+#elif   defined(CONFIG_NIOS_MTX_LDK_20)
+	puts ("Conf.: Microtronix LDK 2.0 (LDK2)\n");
+#endif
+
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}

board/altera/dk1s10/flash.c

@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <nios.h>
+
+/*
+ * include common flash code (for altera boards)
+ */
+#include "../common/flash.c"
+
+/*---------------------------------------------------------------------*/
+#define BANKSZ	(8 * 1024 * 1024)
+#define SECTSZ	(64 * 1024)
+#define USERFLASH (2 * 1024 * 1024)	/* bottom 2 MB for user */
+
+/*---------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = BANKSZ;
+	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
+
+	addr = CFG_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+
+		/* Protect all but 2 MByte user area */
+		if (addr < (CFG_FLASH_BASE + USERFLASH))
+			fli->protect[i] = 0;
+		else
+			fli->protect[i] = 1;
+	}
+
+	return (BANKSZ);
+}

board/altera/dk1s10/misc.c

@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * board/altera/dk1s10/misc.c
+ *
+ * miscellaneous board interfaces / drivers
+ */
+
+#include <common.h>
+
+#if	defined(CONFIG_SEVENSEG)
+#include "../common/sevenseg.h"
+#include "../common/sevenseg.c"
+#endif

board/altera/dk1s10/u-boot.lds

@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-nios")
+OUTPUT_ARCH(nios)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios/start.o (.text)
+	  *(.text)
+	}
+	__text_end = .;
+
+	. = ALIGN(4);
+	.rodata :
+	{
+		*(.rodata)
+	}
+	__rodata_end = .;
+
+	. = ALIGN(4);
+	.data :
+	{
+		*(.data)
+	}
+	. = ALIGN(4);
+	__data_end = .;
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	__bss_start = .;
+	. = ALIGN(4);
+	.bss :
+	{
+		*(.bss)
+	}
+	. = ALIGN(4);
+	__bss_end = .;
+}

board/altera/dk1s10/vectors.S

@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+
+/*************************************************************************
+ * Exception Vector Table
+ *
+ * This could have gone in the cpu soure tree, but the whole point of
+ * Nios is customization -- and polluting the cpu source tree with
+ * board-specific ifdef's really defeats the purpose, no? With this in
+ * the board-specific tree, each board has the freedom to organize
+ * vectors/traps, etc anyway it wants. The init code copies this table
+ * to the proper location.
+ *
+ * Each board can do what it likes here. But there are four "standard"
+ * handlers availble:
+ *
+ *	_cwp_lolimit	-Handles register window underflows.
+ *	_cwp_hilimit	-Handles register window overflows.
+ *	_timebase_int	-Increments the timebase.
+ *	_def_xhandler	-Default exception handler.
+ *
+ * _timebase_int handles a Nios Timer interrupt and increments the
+ * timestamp used for the get_timer(), reset_timer(), etc. routines. It
+ * expects the timer to be configured like the standard-32 low priority
+ * timer.
+ *
+ * _def_xhandler dispatches exceptions/traps via the external_interrupt()
+ * routine. This lets you use the irq_install_handler() and handle your
+ * interrupts/traps with code written in C.
+ ************************************************************************/
+
+	.data
+	.global _vectors
+	.align	4
+_vectors:
+
+#if	defined(CFG_NIOS_CPU_OCI_BASE)
+	/* OCI does the reset job */
+	.long	_def_xhandler@h		/* Vector 0  - NMI / Reset */
+#else
+	/* there is no OCI, so we have to do a direct reset jump here */
+	.long	CFG_NIOS_CPU_RST_VECT	/* Vector 0  - Reset to GERMS */
+#endif
+	.long	_cwp_lolimit@h		/* Vector 1  - underflow */
+	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
+
+	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 4 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 6 - future reserved */
+	.long	_def_xhandler@h		/* Vector 7 - future reserved */
+	.long	_def_xhandler@h		/* Vector 8 - future reserved */
+	.long	_def_xhandler@h		/* Vector 9 - future reserved */
+	.long	_def_xhandler@h		/* Vector 10 - future reserved */
+	.long	_def_xhandler@h		/* Vector 11 - future reserved */
+	.long	_def_xhandler@h		/* Vector 12 - future reserved */
+	.long	_def_xhandler@h		/* Vector 13 - future reserved */
+	.long	_def_xhandler@h		/* Vector 14 - future reserved */
+	.long	_def_xhandler@h		/* Vector 15 - future reserved */
+#if	(CFG_NIOS_TMRIRQ == 16)
+	.long	_timebase_int@h		/* Vector 16 - lopri timer*/
+#else
+	.long	_def_xhandler@h		/* Vector 16 */
+#endif
+	.long	_def_xhandler@h		/* Vector 17 */
+	.long	_def_xhandler@h		/* Vector 18 */
+	.long	_def_xhandler@h		/* Vector 19 */
+	.long	_def_xhandler@h		/* Vector 20 */
+	.long	_def_xhandler@h		/* Vector 21 */
+	.long	_def_xhandler@h		/* Vector 22 */
+	.long	_def_xhandler@h		/* Vector 23 */
+	.long	_def_xhandler@h		/* Vector 24 */
+	.long	_def_xhandler@h		/* Vector 25 */
+	.long	_def_xhandler@h		/* Vector 26 */
+	.long	_def_xhandler@h		/* Vector 27 */
+	.long	_def_xhandler@h		/* Vector 28 */
+	.long	_def_xhandler@h		/* Vector 29 */
+	.long	_def_xhandler@h		/* Vector 30 */
+	.long	_def_xhandler@h		/* Vector 31 */
+	.long	_def_xhandler@h		/* Vector 32 */
+	.long	_def_xhandler@h		/* Vector 33 */
+	.long	_def_xhandler@h		/* Vector 34 */
+	.long	_def_xhandler@h		/* Vector 35 */
+	.long	_def_xhandler@h		/* Vector 36 */
+	.long	_def_xhandler@h		/* Vector 37 */
+	.long	_def_xhandler@h		/* Vector 38 */
+	.long	_def_xhandler@h		/* Vector 39 */
+	.long	_def_xhandler@h		/* Vector 40 */
+	.long	_def_xhandler@h		/* Vector 41 */
+	.long	_def_xhandler@h		/* Vector 42 */
+	.long	_def_xhandler@h		/* Vector 43 */
+	.long	_def_xhandler@h		/* Vector 44 */
+	.long	_def_xhandler@h		/* Vector 45 */
+	.long	_def_xhandler@h		/* Vector 46 */
+	.long	_def_xhandler@h		/* Vector 47 */
+	.long	_def_xhandler@h		/* Vector 48 */
+	.long	_def_xhandler@h		/* Vector 49 */
+#if	(CFG_NIOS_TMRIRQ == 50)
+	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
+#else
+	.long	_def_xhandler@h		/* Vector 50 */
+#endif
+	.long	_def_xhandler@h		/* Vector 51 */
+	.long	_def_xhandler@h		/* Vector 52 */
+	.long	_def_xhandler@h		/* Vector 53 */
+	.long	_def_xhandler@h		/* Vector 54 */
+	.long	_def_xhandler@h		/* Vector 55 */
+	.long	_def_xhandler@h		/* Vector 56 */
+	.long	_def_xhandler@h		/* Vector 57 */
+	.long	_def_xhandler@h		/* Vector 58 */
+	.long	_def_xhandler@h		/* Vector 59 */
+	.long	_def_xhandler@h		/* Vector 60 */
+	.long	_def_xhandler@h		/* Vector 61 */
+	.long	_def_xhandler@h		/* Vector 62 */
+	.long	_def_xhandler@h		/* Vector 63 */

board/at91rm9200dk/at91rm9200dk.c

@@ -66,7 +66,7 @@ int dram_init (void)
  * The NAND lives in the CS2* space
  */
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern void nand_probe (ulong physadr);
+extern ulong nand_probe (ulong physadr);
 
 #define AT91_SMARTMEDIA_BASE 0x40000000	/* physical address to access memory on NCS3 */
 void nand_init (void)
@@ -103,10 +103,12 @@ void nand_init (void)
 	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */
 
 	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
-		printf ("No ");
-	printf ("SmartMedia card inserted\n");
+		printf ("  No SmartMedia card inserted\n");
+#ifdef DEBUG
+	printf ("  SmartMedia card inserted\n");
 
 	printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
-	nand_probe (AT91_SMARTMEDIA_BASE);
+#endif
+	printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
 }
 #endif

board/at91rm9200dk/config.mk

@@ -1 +1 @@
-TEXT_BASE = 0x21f00000
+TEXT_BASE = 0x21f80000

board/at91rm9200dk/flash.c

@@ -160,7 +160,7 @@ ulong flash_init (void)
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
-			panic ("configured to many flash banks!\n");
+			panic ("configured too many flash banks!\n");
 
 		sector = 0;
 		start_address = flashbase;

board/at91rm9200dk/u-boot.lds

@@ -45,14 +45,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }

board/atc/atc.c

@@ -92,20 +92,20 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
-	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
-	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
-	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
-	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
-	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
-	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
-	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
-	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
-	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
-	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
-	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
-	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
-	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
 	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
 	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
 	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
@@ -128,8 +128,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
 	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
 	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
-	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
 #if 0
 	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
 #else
@@ -269,13 +269,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 			  ulong orx, volatile uchar * base)
 {
 	volatile uchar c = 0xff;
-	ulong cnt, val;
-	volatile ulong *addr;
 	volatile uint *sdmr_ptr;
 	volatile uint *orx_ptr;
+	ulong maxsize, size;
 	int i;
-	ulong save[32];		/* to make test non-destructive */
-	ulong maxsize;
 
 	/* We must be able to test a location outsize the maximum legal size
 	 * to find out THAT we are outside; but this address still has to be
@@ -325,41 +322,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
 
-	/*
-	 * Check memory range for valid RAM. A simple memory test determines
-	 * the actually available RAM size between addresses `base' and
-	 * `base + maxsize'. Some (not all) hardware errors are detected:
-	 * - short between address lines
-	 * - short between data lines
-	 */
-	i = 0;
-	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
-		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
+	size = get_ram_size((long *)base, maxsize);
 
-	addr = (volatile ulong *) base;
-	save[i] = *addr;
-	*addr = 0;
+	*orx_ptr = orx | ~(size - 1);
 
-	if ((val = *addr) != 0) {
-		*addr = save[i];
-		return (0);
-	}
-
-	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
-		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
-		val = *addr;
-		*addr = save[--i];
-		if (val != ~cnt) {
-			/* Write the actual size to ORx
-			 */
-			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
-			return (cnt * sizeof (long));
-		}
-	}
-	return (maxsize);
+	return (size);
 }
 
 int misc_init_r(void)

board/bmw/ns16550.c

@@ -9,49 +9,49 @@
 
 typedef struct NS16550 *NS16550_t;
 
-const NS16550_t COM_PORTS[] = { (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), (NS16550_t) ((CFG_EUMB_ADDR) + 0x4600)};
+const NS16550_t COM_PORTS[] =
+	{ (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500),
+(NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) };
 
-volatile struct NS16550 *
-NS16550_init(int chan, int baud_divisor)
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
 {
- volatile struct NS16550 *com_port;
- com_port = (struct NS16550 *) COM_PORTS[chan];
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE;              /* Access baud rate */
- com_port->dll = baud_divisor & 0xff;   /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1;               /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_RTS;     /* RTS/DTR */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;                  /* Clear & enable FIFOs */
-return (com_port);
+	volatile struct NS16550 *com_port;
+
+	com_port = (struct NS16550 *) COM_PORTS[chan];
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_RTS;	/* RTS/DTR */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
+	return (com_port);
 }
 
-void
-NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor)
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
 {
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE;              /* Access baud rate */
- com_port->dll = baud_divisor & 0xff;   /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1;               /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_RTS;     /* RTS/DTR */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;                  /* Clear & enable FIFOs */
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_RTS;	/* RTS/DTR */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
 }
 
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c)
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
 {
- while ((com_port->lsr & LSR_THRE) == 0) ;
- com_port->thr = c;
+	while ((com_port->lsr & LSR_THRE) == 0);
+	com_port->thr = c;
 }
 
-unsigned char
-NS16550_getc(volatile struct NS16550 *com_port)
+unsigned char NS16550_getc (volatile struct NS16550 *com_port)
 {
- while ((com_port->lsr & LSR_DR) == 0) ;
- return (com_port->rbr);
+	while ((com_port->lsr & LSR_DR) == 0);
+	return (com_port->rbr);
 }
 
-int NS16550_tstc(volatile struct NS16550 *com_port)
+int NS16550_tstc (volatile struct NS16550 *com_port)
 {
- return ((com_port->lsr & LSR_DR) != 0);
+	return ((com_port->lsr & LSR_DR) != 0);
 }

board/bmw/ns16550.h

@@ -12,20 +12,19 @@
  */
 
 
-struct NS16550
- {
-  unsigned char rbrthrdlb;  /* 0 */
-  unsigned char ierdmb;     /* 1 */
-  unsigned char iirfcrafr;  /* 2 */
-  unsigned char lcr;         /* 3 */
-  unsigned char mcr;         /* 4 */
-  unsigned char lsr;         /* 5 */
-  unsigned char msr;         /* 6 */
-  unsigned char scr;         /* 7 */
-  unsigned char reserved[2]; /* 8 & 9 */
-  unsigned char dsr;         /* 10 */
-  unsigned char dcr;         /* 11 */
- };
+struct NS16550 {
+	unsigned char rbrthrdlb;	/* 0 */
+	unsigned char ierdmb;		/* 1 */
+	unsigned char iirfcrafr;	/* 2 */
+	unsigned char lcr;		/* 3 */
+	unsigned char mcr;		/* 4 */
+	unsigned char lsr;		/* 5 */
+	unsigned char msr;		/* 6 */
+	unsigned char scr;		/* 7 */
+	unsigned char reserved[2];	/* 8 & 9 */
+	unsigned char dsr;		/* 10 */
+	unsigned char dcr;		/* 11 */
+};
 
 
 #define rbr rbrthrdlb
@@ -37,44 +36,44 @@ struct NS16550
 #define fcr iirfcrafr
 #define afr iirfcrafr
 
-#define FCR_FIFO_EN     0x01    /*fifo enable*/
-#define FCR_RXSR        0x02    /*reciever soft reset*/
-#define FCR_TXSR        0x04    /*transmitter soft reset*/
-#define FCR_DMS		0x08    /* DMA Mode Select */
+#define FCR_FIFO_EN     0x01	/*fifo enable */
+#define FCR_RXSR        0x02	/*reciever soft reset */
+#define FCR_TXSR        0x04	/*transmitter soft reset */
+#define FCR_DMS		0x08	/* DMA Mode Select */
 
-#define MCR_RTS         0x02    /* Readyu to Send */
+#define MCR_RTS         0x02	/* Readyu to Send */
 #define MCR_LOOP	0x10	/* Local loopback mode enable */
 /* #define MCR_DTR         0x01    noton 8245 duart */
 /* #define MCR_DMA_EN      0x04    noton 8245 duart */
 /* #define MCR_TX_DFR      0x08    noton 8245 duart */
 
-#define LCR_WLS_MSK 0x03    /* character length slect mask*/
-#define LCR_WLS_5   0x00    /* 5 bit character length */
-#define LCR_WLS_6   0x01    /* 6 bit character length */
-#define LCR_WLS_7   0x02    /* 7 bit character length */
-#define LCR_WLS_8   0x03    /* 8 bit character length */
-#define LCR_STB     0x04    /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN     0x08    /* Parity eneble*/
-#define LCR_EPS     0x10    /* Even Parity Select*/
-#define LCR_STKP    0x20    /* Stick Parity*/
-#define LCR_SBRK    0x40    /* Set Break*/
-#define LCR_BKSE    0x80    /* Bank select enable - aka DLAB on 8245 */
+#define LCR_WLS_MSK 0x03	/* character length slect mask */
+#define LCR_WLS_5   0x00	/* 5 bit character length */
+#define LCR_WLS_6   0x01	/* 6 bit character length */
+#define LCR_WLS_7   0x02	/* 7 bit character length */
+#define LCR_WLS_8   0x03	/* 8 bit character length */
+#define LCR_STB     0x04	/* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN     0x08	/* Parity eneble */
+#define LCR_EPS     0x10	/* Even Parity Select */
+#define LCR_STKP    0x20	/* Stick Parity */
+#define LCR_SBRK    0x40	/* Set Break */
+#define LCR_BKSE    0x80	/* Bank select enable - aka DLAB on 8245 */
 
-#define LSR_DR      0x01    /* Data ready */
-#define LSR_OE      0x02    /* Overrun */
-#define LSR_PE      0x04    /* Parity error */
-#define LSR_FE      0x08    /* Framing error */
-#define LSR_BI      0x10    /* Break */
-#define LSR_THRE    0x20    /* Xmit holding register empty */
-#define LSR_TEMT    0x40    /* Xmitter empty */
-#define LSR_ERR     0x80    /* Error */
+#define LSR_DR      0x01	/* Data ready */
+#define LSR_OE      0x02	/* Overrun */
+#define LSR_PE      0x04	/* Parity error */
+#define LSR_FE      0x08	/* Framing error */
+#define LSR_BI      0x10	/* Break */
+#define LSR_THRE    0x20	/* Xmit holding register empty */
+#define LSR_TEMT    0x40	/* Xmitter empty */
+#define LSR_ERR     0x80	/* Error */
 
 /* useful defaults for LCR*/
 #define LCR_8N1     0x03
 
 
-volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc(volatile struct NS16550 *com_port);
-int NS16550_tstc(volatile struct NS16550 *com_port);
-void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor);
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c);
+unsigned char NS16550_getc (volatile struct NS16550 *com_port);
+int NS16550_tstc (volatile struct NS16550 *com_port);
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor);

board/bubinga405ep/bubinga405ep.c

@@ -23,11 +23,10 @@
 long int spd_sdram (void);
 
 #include <common.h>
-#include "bubinga405ep.h"
 #include <asm/processor.h>
 
 
-int board_pre_init (void)
+int board_early_init_f (void)
 {
 	mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
 	mtdcr (uicer, 0x00000000);      /* disable all ints */
@@ -80,20 +79,12 @@ int board_pre_init (void)
 int checkboard (void)
 {
 	unsigned char *s = getenv ("serial#");
-	unsigned char *e;
 
-	puts ("Board: ");
+	puts ("Board: IBM 405EP Eval Board");
 
-	if (!s || strncmp (s, "BUBINGA405EP", 9)) {
-		puts ("### No HW ID - assuming WALNUT405");
-	} else {
-		for (e = s; *e; ++e) {
-			if (*e == ' ')
-				break;
-		}
-		for (; s < e; ++s) {
-			putc (*s);
-		}
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
 	}
 	putc ('\n');
 

board/bubinga405ep/flash.c

@@ -77,138 +77,144 @@ unsigned long flash_init (void)
 	unsigned long base_b0, base_b1;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+	size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
+			size_b0, size_b0 << 20);
 	}
 
 	/* Only one bank */
-	if (CFG_MAX_FLASH_BANKS == 1)
-	  {
-	    /* Setup offsets */
-	    flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+	if (CFG_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
 
-	    /* Monitor protection ON by default */
-	    (void)flash_protect(FLAG_PROTECT_SET,
-				FLASH_BASE0_PRELIM,
-				FLASH_BASE0_PRELIM+CFG_MONITOR_LEN-1,
-				&flash_info[0]);
-	    size_b1 = 0 ;
-	    flash_info[0].size = size_b0;
-	  }
+		/* Monitor protection ON by default */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      FLASH_BASE0_PRELIM,
+				      FLASH_BASE0_PRELIM + CFG_MONITOR_LEN - 1,
+				      &flash_info[0]);
+		/* Also protect sector containing initial power-up instruction */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+		size_b1 = 0;
+		flash_info[0].size = size_b0;
+	}
 
 	/* 2 banks */
-	else
-	  {
-	    size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+	else {
+		size_b1 = flash_get_size ((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1]);
 
-	    /* Re-do sizing to get full correct info */
+		/* Re-do sizing to get full correct info */
 
-	    if (size_b1)
-	      {
-		mtdcr(ebccfga, pb0cr);
-		pbcr = mfdcr(ebccfgd);
-		mtdcr(ebccfga, pb0cr);
-		base_b1 = -size_b1;
-		pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
-		mtdcr(ebccfgd, pbcr);
-		/*          printf("pb1cr = %x\n", pbcr); */
-	      }
+		if (size_b1) {
+			mtdcr (ebccfga, pb0cr);
+			pbcr = mfdcr (ebccfgd);
+			mtdcr (ebccfga, pb0cr);
+			base_b1 = -size_b1;
+			pbcr = (pbcr & 0x0001ffff) | base_b1 |
+				(((size_b1 / 1024 / 1024) - 1) << 17);
+			mtdcr (ebccfgd, pbcr);
+			/*          printf("pb1cr = %x\n", pbcr); */
+		}
 
-	    if (size_b0)
-	      {
-		mtdcr(ebccfga, pb1cr);
-		pbcr = mfdcr(ebccfgd);
-		mtdcr(ebccfga, pb1cr);
-		base_b0 = base_b1 - size_b0;
-		pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
-		mtdcr(ebccfgd, pbcr);
-		/*            printf("pb0cr = %x\n", pbcr); */
-	      }
+		if (size_b0) {
+			mtdcr (ebccfga, pb1cr);
+			pbcr = mfdcr (ebccfgd);
+			mtdcr (ebccfga, pb1cr);
+			base_b0 = base_b1 - size_b0;
+			pbcr = (pbcr & 0x0001ffff) | base_b0 |
+				(((size_b0 / 1024 / 1024) - 1) << 17);
+			mtdcr (ebccfgd, pbcr);
+			/*            printf("pb0cr = %x\n", pbcr); */
+		}
 
-	    size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
+		size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
 
-	    flash_get_offsets (base_b0, &flash_info[0]);
+		flash_get_offsets (base_b0, &flash_info[0]);
 
-	    /* monitor protection ON by default */
-	    (void)flash_protect(FLAG_PROTECT_SET,
-				base_b0+size_b0-CFG_MONITOR_LEN,
-				base_b0+size_b0-1,
-				&flash_info[0]);
+		/* monitor protection ON by default */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      base_b0 + size_b0 - CFG_MONITOR_LEN,
+				      base_b0 + size_b0 - 1, &flash_info[0]);
+		/* Also protect sector containing initial power-up instruction */
+		/* (flash_protect() checks address range - other call ignored) */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
 
-	    if (size_b1) {
-	      /* Re-do sizing to get full correct info */
-	      size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
+		if (size_b1) {
+			/* Re-do sizing to get full correct info */
+			size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
 
-	      flash_get_offsets (base_b1, &flash_info[1]);
+			flash_get_offsets (base_b1, &flash_info[1]);
 
-	      /* monitor protection ON by default */
-	      (void)flash_protect(FLAG_PROTECT_SET,
-				  base_b1+size_b1-CFG_MONITOR_LEN,
-				  base_b1+size_b1-1,
-				  &flash_info[1]);
-	      /* monitor protection OFF by default (one is enough) */
-	      (void)flash_protect(FLAG_PROTECT_CLEAR,
-				  base_b0+size_b0-CFG_MONITOR_LEN,
-				  base_b0+size_b0-1,
-				  &flash_info[0]);
-	    } else {
-	      flash_info[1].flash_id = FLASH_UNKNOWN;
-	      flash_info[1].sector_count = -1;
-	    }
+			/* monitor protection ON by default */
+			(void) flash_protect (FLAG_PROTECT_SET,
+					      base_b1 + size_b1 - CFG_MONITOR_LEN,
+					      base_b1 + size_b1 - 1,
+					      &flash_info[1]);
+			/* monitor protection OFF by default (one is enough) */
+			(void) flash_protect (FLAG_PROTECT_CLEAR,
+					      base_b0 + size_b0 - CFG_MONITOR_LEN,
+					      base_b0 + size_b0 - 1,
+					      &flash_info[0]);
+		} else {
+			flash_info[1].flash_id = FLASH_UNKNOWN;
+			flash_info[1].sector_count = -1;
+		}
 
-	    flash_info[0].size = size_b0;
-	    flash_info[1].size = size_b1;
-	  }/* else 2 banks */
+		flash_info[0].size = size_b0;
+		flash_info[1].size = size_b1;
+	}			/* else 2 banks */
 	return (size_b0 + size_b1);
 }
 
 
 /*-----------------------------------------------------------------------
  */
-static void flash_get_offsets (ulong base, flash_info_t *info)
+static void flash_get_offsets (ulong base, flash_info_t * info)
 {
 	int i;
 
 	/* set up sector start address table */
 	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id  == FLASH_AM040)){
-	    for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00010000);
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
 	} else {
-	    if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
 		}
-	    } else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	    }
 	}
 }
 
 /*-----------------------------------------------------------------------
  */
-void flash_print_info  (flash_info_t *info)
+void flash_print_info (flash_info_t * info)
 {
 	int i;
 	int k;
@@ -259,39 +265,35 @@ void flash_print_info  (flash_info_t *info)
 		info->size >> 10, info->sector_count);
 
 	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
+	for (i = 0; i < info->sector_count; ++i) {
 		/*
 		 * Check if whole sector is erased
 		 */
-		if (i != (info->sector_count-1))
-		  size = info->start[i+1] - info->start[i];
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
 		else
-		  size = info->start[0] + info->size - info->start[i];
+			size = info->start[0] + info->size - info->start[i];
 		erased = 1;
-		flash = (volatile unsigned long *)info->start[i];
-		size = size >> 2;        /* divide by 4 for longword access */
-		for (k=0; k<size; k++)
-		  {
-		    if (*flash++ != 0xffffffff)
-		      {
-			erased = 0;
-			break;
-		      }
-		  }
+		flash = (volatile unsigned long *) info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
 
 		if ((i % 5) == 0)
 			printf ("\n   ");
-#if 0 /* test-only */
+#if 0				/* test-only */
 		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
+			info->start[i], info->protect[i] ? " (RO)" : "     "
 #else
 		printf (" %08lX%s%s",
 			info->start[i],
-			erased ? " E" : "  ",
-			info->protect[i] ? "RO " : "   "
+			erased ? " E" : "  ", info->protect[i] ? "RO " : "   "
 #endif
-		);
+			);
 	}
 	printf ("\n");
 	return;
@@ -307,17 +309,17 @@ void flash_print_info  (flash_info_t *info)
 /*
  * The following code cannot be run from FLASH!
  */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 {
 	short i;
 	FLASH_WORD_SIZE value;
-	ulong base = (ulong)addr;
-	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
-	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
-	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
 
 #ifdef CONFIG_ADCIOP
 	value = addr2[2];
@@ -326,126 +328,126 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 #endif
 
 	switch (value) {
-	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-	case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
-	case (FLASH_WORD_SIZE)SST_MANUFACT:
+	case (FLASH_WORD_SIZE) SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
 		info->size = 0;
-		return (0);			/* no or unknown flash	*/
+		return (0);	/* no or unknown flash  */
 	}
 
 #ifdef CONFIG_ADCIOP
-	value = addr2[0];			/* device ID		*/
+	value = addr2[0];	/* device ID            */
 	/*        printf("\ndev_code=%x\n", value); */
 #else
-	value = addr2[1];			/* device ID		*/
+	value = addr2[1];	/* device ID            */
 #endif
 
 	switch (value) {
-	case (FLASH_WORD_SIZE)AMD_ID_F040B:
+	case (FLASH_WORD_SIZE) AMD_ID_F040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
-		info->size = 0x0080000; /* => 512 ko */
+		info->size = 0x0080000;	/* => 512 ko */
 		break;
-	case (FLASH_WORD_SIZE)AMD_ID_LV400T:
+	case (FLASH_WORD_SIZE) AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00080000;
-		break;				/* => 0.5 MB		*/
+		break;		/* => 0.5 MB            */
 
-	case (FLASH_WORD_SIZE)AMD_ID_LV400B:
+	case (FLASH_WORD_SIZE) AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00080000;
-		break;				/* => 0.5 MB		*/
+		break;		/* => 0.5 MB            */
 
-	case (FLASH_WORD_SIZE)AMD_ID_LV800T:
+	case (FLASH_WORD_SIZE) AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
+		break;		/* => 1 MB              */
 
-	case (FLASH_WORD_SIZE)AMD_ID_LV800B:
+	case (FLASH_WORD_SIZE) AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
+		break;		/* => 1 MB              */
 
-	case (FLASH_WORD_SIZE)AMD_ID_LV160T:
+	case (FLASH_WORD_SIZE) AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
+		break;		/* => 2 MB              */
 
-	case (FLASH_WORD_SIZE)AMD_ID_LV160B:
+	case (FLASH_WORD_SIZE) AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-#if 0	/* enable when device IDs are available */
-	case (FLASH_WORD_SIZE)AMD_ID_LV320T:
+		break;		/* => 2 MB              */
+#if 0				/* enable when device IDs are available */
+	case (FLASH_WORD_SIZE) AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 67;
 		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
+		break;		/* => 4 MB              */
 
-	case (FLASH_WORD_SIZE)AMD_ID_LV320B:
+	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 67;
 		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
+		break;		/* => 4 MB              */
 #endif
-	case (FLASH_WORD_SIZE)SST_ID_xF800A:
+	case (FLASH_WORD_SIZE) SST_ID_xF800A:
 		info->flash_id += FLASH_SST800A;
 		info->sector_count = 16;
 		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
+		break;		/* => 1 MB              */
 
-	case (FLASH_WORD_SIZE)SST_ID_xF160A:
+	case (FLASH_WORD_SIZE) SST_ID_xF160A:
 		info->flash_id += FLASH_SST160A;
 		info->sector_count = 32;
 		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
+		break;		/* => 2 MB              */
 
 	default:
 		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
+		return (0);	/* => no or unknown flash */
 
 	}
 
 	/* set up sector start address table */
 	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id  == FLASH_AM040)){
-	    for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00010000);
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
 	} else {
-	    if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
 		}
-	    } else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	    }
 	}
 
 	/* check for protected sectors */
@@ -453,14 +455,14 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
 #ifdef CONFIG_ADCIOP
-		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
 		info->protect[i] = addr2[4] & 1;
 #else
-		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-		  info->protect[i] = 0;
+			info->protect[i] = 0;
 		else
-		  info->protect[i] = addr2[2] & 1;
+			info->protect[i] = addr2[2] & 1;
 #endif
 	}
 
@@ -468,52 +470,52 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	 * Prevent writes to uninitialized FLASH.
 	 */
 	if (info->flash_id != FLASH_UNKNOWN) {
-#if 0 /* test-only */
+#if 0				/* test-only */
 #ifdef CONFIG_ADCIOP
-		addr2 = (volatile unsigned char *)info->start[0];
+		addr2 = (volatile unsigned char *) info->start[0];
 		addr2[ADDR0] = 0xAA;
 		addr2[ADDR1] = 0x55;
-		addr2[ADDR0] = 0xF0;  /* reset bank */
+		addr2[ADDR0] = 0xF0;	/* reset bank */
 #else
-		addr2 = (FLASH_WORD_SIZE *)info->start[0];
-		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+		addr2 = (FLASH_WORD_SIZE *) info->start[0];
+		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
 #endif
-#else /* test-only */
-		addr2 = (FLASH_WORD_SIZE *)info->start[0];
-		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+#else  /* test-only */
+		addr2 = (FLASH_WORD_SIZE *) info->start[0];
+		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
 #endif /* test-only */
 	}
 
 	return (info->size);
 }
 
-int wait_for_DQ7(flash_info_t *info, int sect)
+int wait_for_DQ7 (flash_info_t * info, int sect)
 {
 	ulong start, now, last;
-	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[sect]);
 
 	start = get_timer (0);
-    last  = start;
-    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
-	    printf ("Timeout\n");
-	    return -1;
+	last = 0;
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
 	}
-	/* show that we're waiting */
-	if ((now - last) > 1000) {  /* every second */
-	    putc ('.');
-	    last = now;
-	}
-    }
 	return 0;
 }
 
 /*-----------------------------------------------------------------------
  */
 
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
-	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
 	volatile FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	int i;
@@ -533,15 +535,14 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	}
 
 	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
+	for (sect = s_first; sect <= s_last; ++sect) {
 		if (info->protect[sect]) {
 			prot++;
 		}
 	}
 
 	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
 	} else {
 		printf ("\n");
 	}
@@ -549,46 +550,46 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	l_sect = -1;
 
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();
 
 	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
+	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-		    addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
-		    printf("Erasing sector %p\n", addr2);	/* CLH */
+			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+			printf ("Erasing sector %p\n", addr2);	/* CLH */
 
-		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
-			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
-			addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
-			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
-			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
-			addr2[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
-			for (i=0; i<50; i++)
-				udelay(1000);  /* wait 1 ms */
-		    } else {
-			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
-			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
-			addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
-			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
-			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
-			addr2[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
-		    }
-		    l_sect = sect;
-		    /*
-		     * Wait for each sector to complete, it's more
-		     * reliable.  According to AMD Spec, you must
-		     * issue all erase commands within a specified
-		     * timeout.  This has been seen to fail, especially
-		     * if printf()s are included (for debug)!!
-		     */
-		    wait_for_DQ7(info, sect);
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay (1000);	/* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7 (info, sect);
 		}
 	}
 
 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();
 
 	/* wait at least 80us - let's wait 1 ms */
 	udelay (1000);
@@ -599,13 +600,13 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	 */
 	if (l_sect < 0)
 		goto DONE;
-	wait_for_DQ7(info, l_sect);
+	wait_for_DQ7 (info, l_sect);
 
-DONE:
+      DONE:
 #endif
 	/* reset to read mode */
-	addr = (FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
 
 	printf (" done\n");
 	return 0;
@@ -618,7 +619,7 @@ DONE:
  * 2 - Flash not erased
  */
 
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	ulong cp, wp, data;
 	int i, l, rc;
@@ -630,19 +631,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	if ((l = addr - wp) != 0) {
 		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
 		}
-		for (; i<4 && cnt>0; ++i) {
+		for (; i < 4 && cnt > 0; ++i) {
 			data = (data << 8) | *src++;
 			--cnt;
 			++cp;
 		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
 		}
 
-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_word (info, wp, data)) != 0) {
 			return (rc);
 		}
 		wp += 4;
@@ -653,13 +654,13 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	while (cnt >= 4) {
 		data = 0;
-		for (i=0; i<4; ++i) {
+		for (i = 0; i < 4; ++i) {
 			data = (data << 8) | *src++;
 		}
-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_word (info, wp, data)) != 0) {
 			return (rc);
 		}
-		wp  += 4;
+		wp += 4;
 		cnt -= 4;
 	}
 
@@ -671,15 +672,15 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle unaligned tail bytes
 	 */
 	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
 		data = (data << 8) | *src++;
 		--cnt;
 	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
 	}
 
-	return (write_word(info, wp, data));
+	return (write_word (info, wp, data));
 }
 
 /*-----------------------------------------------------------------------
@@ -698,7 +699,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
 
 	/* Check if Flash is (sufficiently) erased */
 	if ((*((volatile FLASH_WORD_SIZE *) dest) &
-	    (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
 		return (2);
 	}
 

board/c2mon/c2mon.c

@@ -227,40 +227,8 @@ static long int dram_size (long int mamr_value, long int *base,
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];			/* to make test non-destructive */
-	unsigned char i = 0;
 
 	memctl->memc_mamr = mamr_value;
 
-	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
-
-	/* write 0 to base address */
-	addr = base;
-	save[i] = *addr;
-	*addr = 0;
-
-	/* check at base address */
-	if ((val = *addr) != 0) {
-		*addr = save[i];
-		return (0);
-	}
-
-	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		val = *addr;
-		*addr = save[--i];
-
-		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
-		}
-	}
-	return (maxsize);
+	return (get_ram_size(base, maxsize));
 }

board/cogent/lcd.c

@@ -229,3 +229,17 @@ lcd_heartbeat(void)
     if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0]))
 	rotator_index = 0;
 }
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void board_show_activity (ulong timestamp)
+{
+#ifdef CONFIG_STATUS_LED
+	if ((timestamp % (CFG_HZ / 2) == 0)
+		lcd_heartbeat ();
+#endif
+}
+
+void show_activity(int arg)
+{
+}
+#endif

board/cogent/mb.c

@@ -43,152 +43,166 @@
 
 const iop_conf_t iop_conf_tab[4][32] = {
 
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PA9  */ {   1,   1,   0,   1,   0,   0   },	/* SMC2 TXD */
-	/* PA8  */ {   1,   1,   0,   0,   0,   0   },	/* SMC2 RXD */
-	/* PA7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA3  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA2  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA1  */ {   0,   0,   0,   0,   0,   0   },
-	/* PA0  */ {   0,   0,   0,   0,   0,   0   }
-    },
+	/* Port A configuration */
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PA31 */ {0, 0, 0, 0, 0, 0},
+	 /* PA30 */ {0, 0, 0, 0, 0, 0},
+	 /* PA29 */ {0, 0, 0, 0, 0, 0},
+	 /* PA28 */ {0, 0, 0, 0, 0, 0},
+	 /* PA27 */ {0, 0, 0, 0, 0, 0},
+	 /* PA26 */ {0, 0, 0, 0, 0, 0},
+	 /* PA25 */ {0, 0, 0, 0, 0, 0},
+	 /* PA24 */ {0, 0, 0, 0, 0, 0},
+	 /* PA23 */ {0, 0, 0, 0, 0, 0},
+	 /* PA22 */ {0, 0, 0, 0, 0, 0},
+	 /* PA21 */ {0, 0, 0, 0, 0, 0},
+	 /* PA20 */ {0, 0, 0, 0, 0, 0},
+	 /* PA19 */ {0, 0, 0, 0, 0, 0},
+	 /* PA18 */ {0, 0, 0, 0, 0, 0},
+	 /* PA17 */ {0, 0, 0, 0, 0, 0},
+	 /* PA16 */ {0, 0, 0, 0, 0, 0},
+	 /* PA15 */ {0, 0, 0, 0, 0, 0},
+	 /* PA14 */ {0, 0, 0, 0, 0, 0},
+	 /* PA13 */ {0, 0, 0, 0, 0, 0},
+	 /* PA12 */ {0, 0, 0, 0, 0, 0},
+	 /* PA11 */ {0, 0, 0, 0, 0, 0},
+	 /* PA10 */ {0, 0, 0, 0, 0, 0},
+					/* PA9  */ {1, 1, 0, 1, 0, 0},
+					/* SMC2 TXD */
+					/* PA8  */ {1, 1, 0, 0, 0, 0},
+					/* SMC2 RXD */
+	 /* PA7  */ {0, 0, 0, 0, 0, 0},
+	 /* PA6  */ {0, 0, 0, 0, 0, 0},
+	 /* PA5  */ {0, 0, 0, 0, 0, 0},
+	 /* PA4  */ {0, 0, 0, 0, 0, 0},
+	 /* PA3  */ {0, 0, 0, 0, 0, 0},
+	 /* PA2  */ {0, 0, 0, 0, 0, 0},
+	 /* PA1  */ {0, 0, 0, 0, 0, 0},
+	 /* PA0  */ {0, 0, 0, 0, 0, 0}
+	 },
 
 
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PB9  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB8  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PB31 */ {0, 0, 0, 0, 0, 0},
+	 /* PB30 */ {0, 0, 0, 0, 0, 0},
+	 /* PB29 */ {0, 0, 0, 0, 0, 0},
+	 /* PB28 */ {0, 0, 0, 0, 0, 0},
+	 /* PB27 */ {0, 0, 0, 0, 0, 0},
+	 /* PB26 */ {0, 0, 0, 0, 0, 0},
+	 /* PB25 */ {0, 0, 0, 0, 0, 0},
+	 /* PB24 */ {0, 0, 0, 0, 0, 0},
+	 /* PB23 */ {0, 0, 0, 0, 0, 0},
+	 /* PB22 */ {0, 0, 0, 0, 0, 0},
+	 /* PB21 */ {0, 0, 0, 0, 0, 0},
+	 /* PB20 */ {0, 0, 0, 0, 0, 0},
+	 /* PB19 */ {0, 0, 0, 0, 0, 0},
+	 /* PB18 */ {0, 0, 0, 0, 0, 0},
+	 /* PB17 */ {0, 0, 0, 0, 0, 0},
+	 /* PB16 */ {0, 0, 0, 0, 0, 0},
+	 /* PB15 */ {0, 0, 0, 0, 0, 0},
+	 /* PB14 */ {0, 0, 0, 0, 0, 0},
+	 /* PB13 */ {0, 0, 0, 0, 0, 0},
+	 /* PB12 */ {0, 0, 0, 0, 0, 0},
+	 /* PB11 */ {0, 0, 0, 0, 0, 0},
+	 /* PB10 */ {0, 0, 0, 0, 0, 0},
+	 /* PB9  */ {0, 0, 0, 0, 0, 0},
+	 /* PB8  */ {0, 0, 0, 0, 0, 0},
+	 /* PB7  */ {0, 0, 0, 0, 0, 0},
+	 /* PB6  */ {0, 0, 0, 0, 0, 0},
+	 /* PB5  */ {0, 0, 0, 0, 0, 0},
+	 /* PB4  */ {0, 0, 0, 0, 0, 0},
+					/* PB3  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB2  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB1  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB0  */ {0, 0, 0, 0, 0, 0}
+					/* pin doesn't exist */
+	 },
 
 
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC15 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC14 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PC9  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC8  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC3  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC2  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC1  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC0  */ {   0,   0,   0,   0,   0,   0   }
-    },
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PC31 */ {0, 0, 0, 0, 0, 0},
+	 /* PC30 */ {0, 0, 0, 0, 0, 0},
+	 /* PC29 */ {0, 0, 0, 0, 0, 0},
+	 /* PC28 */ {0, 0, 0, 0, 0, 0},
+	 /* PC27 */ {0, 0, 0, 0, 0, 0},
+	 /* PC26 */ {0, 0, 0, 0, 0, 0},
+	 /* PC25 */ {0, 0, 0, 0, 0, 0},
+	 /* PC24 */ {0, 0, 0, 0, 0, 0},
+	 /* PC23 */ {0, 0, 0, 0, 0, 0},
+	 /* PC22 */ {0, 0, 0, 0, 0, 0},
+	 /* PC21 */ {0, 0, 0, 0, 0, 0},
+	 /* PC20 */ {0, 0, 0, 0, 0, 0},
+	 /* PC19 */ {0, 0, 0, 0, 0, 0},
+	 /* PC18 */ {0, 0, 0, 0, 0, 0},
+	 /* PC17 */ {0, 0, 0, 0, 0, 0},
+	 /* PC16 */ {0, 0, 0, 0, 0, 0},
+	 /* PC15 */ {0, 0, 0, 0, 0, 0},
+	 /* PC14 */ {0, 0, 0, 0, 0, 0},
+	 /* PC13 */ {0, 0, 0, 0, 0, 0},
+	 /* PC12 */ {0, 0, 0, 0, 0, 0},
+	 /* PC11 */ {0, 0, 0, 0, 0, 0},
+	 /* PC10 */ {0, 0, 0, 0, 0, 0},
+	 /* PC9  */ {0, 0, 0, 0, 0, 0},
+	 /* PC8  */ {0, 0, 0, 0, 0, 0},
+	 /* PC7  */ {0, 0, 0, 0, 0, 0},
+	 /* PC6  */ {0, 0, 0, 0, 0, 0},
+	 /* PC5  */ {0, 0, 0, 0, 0, 0},
+	 /* PC4  */ {0, 0, 0, 0, 0, 0},
+	 /* PC3  */ {0, 0, 0, 0, 0, 0},
+	 /* PC2  */ {0, 0, 0, 0, 0, 0},
+	 /* PC1  */ {0, 0, 0, 0, 0, 0},
+	 /* PC0  */ {0, 0, 0, 0, 0, 0}
+	 },
 
 
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD30 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD29 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD28 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD27 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD26 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD25 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD24 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD23 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD22 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD21 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD20 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD19 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD18 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD17 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD16 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD15 */ {   1,   1,   1,   0,   0,   0   },	/* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   0,   0   },	/* I2C SCL */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   },
-	/* PD9  */ {   1,   1,   0,   1,   0,   0   },	/* SMC1 TXD */
-	/* PD8  */ {   1,   1,   0,   0,   0,   0   },	/* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD6  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD5  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD4  */ {   0,   0,   0,   0,   0,   0   },
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PD31 */ {0, 0, 0, 0, 0, 0},
+	 /* PD30 */ {0, 0, 0, 0, 0, 0},
+	 /* PD29 */ {0, 0, 0, 0, 0, 0},
+	 /* PD28 */ {0, 0, 0, 0, 0, 0},
+	 /* PD27 */ {0, 0, 0, 0, 0, 0},
+	 /* PD26 */ {0, 0, 0, 0, 0, 0},
+	 /* PD25 */ {0, 0, 0, 0, 0, 0},
+	 /* PD24 */ {0, 0, 0, 0, 0, 0},
+	 /* PD23 */ {0, 0, 0, 0, 0, 0},
+	 /* PD22 */ {0, 0, 0, 0, 0, 0},
+	 /* PD21 */ {0, 0, 0, 0, 0, 0},
+	 /* PD20 */ {0, 0, 0, 0, 0, 0},
+	 /* PD19 */ {0, 0, 0, 0, 0, 0},
+	 /* PD18 */ {0, 0, 0, 0, 0, 0},
+	 /* PD17 */ {0, 0, 0, 0, 0, 0},
+	 /* PD16 */ {0, 0, 0, 0, 0, 0},
+					/* PD15 */ {1, 1, 1, 0, 0, 0},
+					/* I2C SDA */
+					/* PD14 */ {1, 1, 1, 0, 0, 0},
+					/* I2C SCL */
+	 /* PD13 */ {0, 0, 0, 0, 0, 0},
+	 /* PD12 */ {0, 0, 0, 0, 0, 0},
+	 /* PD11 */ {0, 0, 0, 0, 0, 0},
+	 /* PD10 */ {0, 0, 0, 0, 0, 0},
+					/* PD9  */ {1, 1, 0, 1, 0, 0},
+					/* SMC1 TXD */
+					/* PD8  */ {1, 1, 0, 0, 0, 0},
+					/* SMC1 RXD */
+	 /* PD7  */ {0, 0, 0, 0, 0, 0},
+	 /* PD6  */ {0, 0, 0, 0, 0, 0},
+	 /* PD5  */ {0, 0, 0, 0, 0, 0},
+	 /* PD4  */ {0, 0, 0, 0, 0, 0},
+					/* PD3  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD2  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD1  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD0  */ {0, 0, 0, 0, 0, 0}
+					/* pin doesn't exist */
+	 }
 };
 
-#endif	/* CONFIG_8260 */
+#endif /* CONFIG_8260 */
 
 /* ------------------------------------------------------------------------- */
 
@@ -196,12 +210,11 @@ const iop_conf_t iop_conf_tab[4][32] = {
  * Check Board Identity:
  */
 
-int
-checkboard(void)
+int checkboard (void)
 {
-    puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
-	COGENT_CPU_MODULE " CPU Module\n");
-    return (0);
+	puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
+	      COGENT_CPU_MODULE " CPU Module\n");
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -213,46 +226,44 @@ checkboard(void)
 
 int misc_init_f (void)
 {
-    printf ("DIPSW: ");
-    dipsw_init();
-    return (0);
+	printf ("DIPSW: ");
+	dipsw_init ();
+	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
 
-long int
-initdram(int board_type)
+long int initdram (int board_type)
 {
 #if CONFIG_CMA111
-    return (32L * 1024L * 1024L);
+	return (32L * 1024L * 1024L);
 #else
-    unsigned char dipsw_val;
-    int dual, size0, size1;
-    long int memsize;
+	unsigned char dipsw_val;
+	int dual, size0, size1;
+	long int memsize;
 
-    dipsw_val = dipsw_cooked();
+	dipsw_val = dipsw_cooked ();
 
-    dual = dipsw_val & 0x01;
-    size0 = (dipsw_val & 0x08) >> 3;
-    size1 = (dipsw_val & 0x04) >> 2;
+	dual = dipsw_val & 0x01;
+	size0 = (dipsw_val & 0x08) >> 3;
+	size1 = (dipsw_val & 0x04) >> 2;
 
-    if (size0)
-	if (size1)
-	    memsize = 16L * 1024L * 1024L;
-	else
-	    memsize =  1L * 1024L * 1024L;
-    else
-	if (size1)
-	    memsize =  4L * 1024L * 1024L;
+	if (size0)
+		if (size1)
+			memsize = 16L * 1024L * 1024L;
+		else
+			memsize = 1L * 1024L * 1024L;
+	else if (size1)
+		memsize = 4L * 1024L * 1024L;
 	else {
-	    printf("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
-	    memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */
+		printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
+		memsize = 16L * 1024L * 1024L;	/* shouldn't happen - guess 16M */
 	}
 
-    if (dual)
-	memsize *= 2L;
+	if (dual)
+		memsize *= 2L;
 
-    return (memsize);
+	return (memsize);
 #endif
 }
 
@@ -265,21 +276,21 @@ initdram(int board_type)
 
 int misc_init_r (void)
 {
-    printf ("LCD:   ");
-    lcd_init();
+	printf ("LCD:   ");
+	lcd_init ();
 
 #if 0
-    printf ("RTC:   ");
-    rtc_init();
+	printf ("RTC:   ");
+	rtc_init ();
 
-    printf ("PAR:   ");
-    par_init();
+	printf ("PAR:   ");
+	par_init ();
 
-    printf ("KBM:   ");
-    kbm_init();
+	printf ("KBM:   ");
+	kbm_init ();
 
-    printf ("PCI:   ");
-    pci_init();
+	printf ("PCI:   ");
+	pci_init ();
 #endif
-    return (0);
+	return (0);
 }

board/cpc45/cpc45.c

@@ -32,7 +32,7 @@ extern void Plx9030Init(void);
 	/* We have to clear the initial data area here. Couldn't have done it
 	 * earlier because DRAM had not been initialized.
 	 */
-int board_pre_init(void)
+int board_early_init_f(void)
 {
 
 	/* enable DUAL UART Mode on CPC45 */
@@ -60,51 +60,24 @@ int checkboard(void)
 
 long int initdram(int board_type)
 {
-	int              i, cnt;
-	volatile uchar * base      = CFG_SDRAM_BASE;
-	volatile ulong * addr;
-	ulong            save[32];
-	ulong            val, ret  = 0;
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
 
-	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
 
-		addr = (volatile ulong *)base + cnt;
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
 
-	addr = (volatile ulong *)base;
-	save[i] = *addr;
-	*addr = 0;
-
-	if (*addr != 0) {
-		*addr = save[i];
-		goto Done;
-	}
-
-	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
-		addr = (volatile ulong *)base + cnt;
-		val = *addr;
-		*addr = save[--i];
-		if (val != ~cnt) {
-			ulong new_bank0_end = cnt * sizeof(long) - 1;
-			ulong mear1  = mpc824x_mpc107_getreg(MEAR1);
-			ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
-			mear1 =  (mear1  & 0xFFFFFF00) |
-			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
-			emear1 = (emear1 & 0xFFFFFF00) |
-			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-			mpc824x_mpc107_setreg(MEAR1,  mear1);
-			mpc824x_mpc107_setreg(EMEAR1, emear1);
-
-			ret = cnt * sizeof(long);
-			goto Done;
-		}
-	}
-
-	ret = CFG_MAX_RAM_SIZE;
-Done:
-	return ret;
+	return (size);
 }
 
 /*

board/cpu86/cpu86.c

@@ -213,13 +213,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 			  ulong orx, volatile uchar * base)
 {
 	volatile uchar c = 0xff;
-	ulong cnt, val;
-	volatile ulong *addr;
 	volatile uint *sdmr_ptr;
 	volatile uint *orx_ptr;
+	ulong maxsize, size;
 	int i;
-	ulong save[32];		/* to make test non-destructive */
-	ulong maxsize;
 
 	/* We must be able to test a location outsize the maximum legal size
 	 * to find out THAT we are outside; but this address still has to be
@@ -269,41 +266,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
 
-	/*
-	 * Check memory range for valid RAM. A simple memory test determines
-	 * the actually available RAM size between addresses `base' and
-	 * `base + maxsize'. Some (not all) hardware errors are detected:
-	 * - short between address lines
-	 * - short between data lines
-	 */
-	i = 0;
-	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
-		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
+	size = get_ram_size((long *)base, maxsize);
 
-	addr = (volatile ulong *) base;
-	save[i] = *addr;
-	*addr = 0;
+	*orx_ptr = orx | ~(size - 1);
 
-	if ((val = *addr) != 0) {
-		*addr = save[i];
-		return (0);
-	}
-
-	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
-		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
-		val = *addr;
-		*addr = save[--i];
-		if (val != ~cnt) {
-			/* Write the actual size to ORx
-			 */
-			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
-			return (cnt * sizeof (long));
-		}
-	}
-	return (maxsize);
+	return (size);
 }
 
 long int initdram (int board_type)

board/cradle/config.mk

@@ -1,2 +1,2 @@
-TEXT_BASE = 0xa0f08000
+TEXT_BASE = 0xa0f80000
 #TEXT_BASE = 0

board/cradle/cradle.c

@@ -170,7 +170,7 @@ init_sio (int led, unsigned long base)
 
 int
 /**********************************************************/
-board_post_init (void)
+board_late_init (void)
 /**********************************************************/
 {
 	return (0);

board/cradle/flash.c

@@ -59,7 +59,7 @@ ulong flash_init(void)
 		flashbase = PHYS_FLASH_2;
 		break;
 	 default:
-		panic("configured to many flash banks!\n");
+		panic("configured too many flash banks!\n");
 		break;
       }
       for (j = 0; j < flash_info[i].sector_count; j++)

board/cradle/u-boot.lds

@@ -44,17 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-   __u_boot_cmd_start = .;
-   .u_boot_cmd : { *(.u_boot_cmd) }
-   __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
-
+	_end = .;
 }

board/cray/L1/L1.c

@@ -109,7 +109,7 @@ extern char bootscript[];
 static void init_sdram (void);
 
 /* ------------------------------------------------------------------------- */
-int board_pre_init (void)
+int board_early_init_f (void)
 {
 	/* Running from ROM: global data is still READONLY */
 	init_sdram ();

board/csb226/flash.c

@@ -9,6 +9,9 @@
  * (C) Copyright 2002
  * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
  *
+ * (C) Copyright 2003 (2 x 16 bit Flash bank patches)
+ * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de>
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -19,7 +22,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -32,9 +35,9 @@
 #include <asm/arch/pxa-regs.h>
 
 #define FLASH_BANK_SIZE 0x02000000
-#define MAIN_SECT_SIZE  0x40000         /* 2x16 = 256k per sector */
+#define MAIN_SECT_SIZE	0x40000		/* 2x16 = 256k per sector */
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
 
 
 /**
@@ -51,19 +54,19 @@ ulong flash_init(void)
 	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 		flash_info[i].flash_id =
-	  		(INTEL_MANUFACT & FLASH_VENDMASK) |
-	  		(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
 		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
 		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
 
 		switch (i) {
-			case 0:
-				flashbase = PHYS_FLASH_1;
-				break;
-			default:
-				panic("configured to many flash banks!\n");
-				break;
+		case 0:
+			flashbase = PHYS_FLASH_1;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
 		}
 		for (j = 0; j < flash_info[i].sector_count; j++) {
 			flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
@@ -88,8 +91,6 @@ ulong flash_init(void)
 
 /**
  * flash_print_info: - print information about the flash situation
- *
- * @param info:
  */
 
 void flash_print_info  (flash_info_t *info)
@@ -99,23 +100,21 @@ void flash_print_info  (flash_info_t *info)
 	for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {
 
 		switch (info->flash_id & FLASH_VENDMASK) {
-
-			case (INTEL_MANUFACT & FLASH_VENDMASK):
-				printf("Intel: ");
-				break;
-			default:
-				printf("Unknown Vendor ");
-				break;
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf ("Intel: ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
 		}
 
 		switch (info->flash_id & FLASH_TYPEMASK) {
-
-			case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
-				printf("28F128J3 (128Mbit)\n");
-				break;
-			default:
-				printf("Unknown Chip Type\n");
-				return;
+		case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+			printf("28F128J3 (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			return;
 		}
 
 		printf("  Size: %ld MB in %d Sectors\n",
@@ -123,10 +122,10 @@ void flash_print_info  (flash_info_t *info)
 
 		printf("  Sector Start Addresses:");
 		for (i = 0; i < info->sector_count; i++) {
-			if ((i % 5) == 0) printf ("\n   ");
+			if ((i % 5) == 0) printf ("\n	");
 
 			printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
+				info->protect[i] ? " (RO)" : "	   ");
 		}
 		printf ("\n");
 		info++;
@@ -136,7 +135,6 @@ void flash_print_info  (flash_info_t *info)
 
 /**
  * flash_erase: - erase flash sectors
- *
  */
 
 int flash_erase(flash_info_t *info, int s_first, int s_last)
@@ -179,13 +177,13 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
 		/* arm simple, non interrupt dependent timer */
 		reset_timer_masked();
 
-		if (info->protect[sect] == 0) {	/* not protected */
+		if (info->protect[sect] == 0) { /* not protected */
 			u32 * volatile addr = (u32 * volatile)(info->start[sect]);
 
-			/* erase sector:                                    */
+			/* erase sector:				    */
 			/* The strata flashs are aligned side by side on    */
 			/* the data bus, so we have to write the commands   */
-			/* to both chips here:                              */
+			/* to both chips here:				    */
 
 			*addr = 0x00200020;	/* erase setup */
 			*addr = 0x00D000D0;	/* erase confirm */
@@ -198,19 +196,14 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
 					goto outahere;
 				}
 			}
-
 			*addr = 0x00500050; /* clear status register cmd.   */
-			*addr = 0x00FF00FF; /* resest to read mode          */
-
+			*addr = 0x00FF00FF; /* reset to read mode	    */
 		}
-
 		printf("ok.\n");
 	}
-
 	if (ctrlc()) printf("User Interrupt!\n");
 
-	outahere:
-
+outahere:
 	/* allow flash to settle - wait 10 ms */
 	udelay_masked(10000);
 
@@ -219,22 +212,19 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
 	return rc;
 }
 
-
 /**
- * write_word: - copy memory to flash
- *
- * @param info:
- * @param dest:
- * @param data:
- * @return:
+ * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each
  */
 
-static int write_word (flash_info_t *info, ulong dest, ushort data)
+static int write_long (flash_info_t *info, ulong dest, ulong data)
 {
 	u32 * volatile addr = (u32 * volatile)dest, val;
 	int rc = ERR_OK;
 	int flag;
 
+	/* read array command - just for the case... */
+	*addr = 0x00FF00FF;
+
 	/* Check if Flash is (sufficiently) erased */
 	if ((*addr & data) != data) return ERR_NOT_ERASED;
 
@@ -248,10 +238,10 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
 	flag = disable_interrupts();
 
 	/* clear status register command */
-	*addr = 0x50;
+	*addr = 0x00500050;
 
 	/* program set-up command */
-	*addr = 0x40;
+	*addr = 0x00400040;
 
 	/* latch address/data */
 	*addr = data;
@@ -260,28 +250,30 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
 	reset_timer_masked();
 
 	/* wait while polling the status register */
-	while(((val = *addr) & 0x80) != 0x80) {
+	while(((val = *addr) & 0x00800080) != 0x00800080) {
 		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
 			rc = ERR_TIMOUT;
-			*addr = 0xB0; /* suspend program command */
+			/* suspend program command */
+			*addr = 0x00B000B0;
 			goto outahere;
 		}
 	}
 
-	if(val & 0x1A) {	/* check for error */
+	/* check for errors */
+	if(val & 0x001A001A) {
 		printf("\nFlash write error %02x at address %08lx\n",
 			(int)val, (unsigned long)dest);
-		if(val & (1<<3)) {
+		if(val & 0x00080008) {
 			printf("Voltage range error.\n");
 			rc = ERR_PROG_ERROR;
 			goto outahere;
 		}
-		if(val & (1<<1)) {
+		if(val & 0x00020002) {
 			printf("Device protect error.\n");
 			rc = ERR_PROTECTED;
 			goto outahere;
 		}
-		if(val & (1<<4)) {
+		if(val & 0x00100010) {
 			printf("Programming error.\n");
 			rc = ERR_PROG_ERROR;
 			goto outahere;
@@ -290,9 +282,9 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
 		goto outahere;
 	}
 
-	outahere:
-
-	*addr = 0xFF; /* read array command */
+outahere:
+	/* read array command */
+	*addr = 0x00FF00FF;
 	if (flag) enable_interrupts();
 
 	return rc;
@@ -304,20 +296,21 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
  *
  * @param info:
  * @param src:	source of copy transaction
- * @param addr:	where to copy to
- * @param cnt: 	number of bytes to copy
+ * @param addr: where to copy to
+ * @param cnt:	number of bytes to copy
  *
  * @return	error code
  */
 
+/* "long" version, uses 32bit words */
 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
 	ulong cp, wp;
-	ushort data;
+	ulong data;
 	int l;
 	int i, rc;
 
-	wp = (addr & ~1);	/* get lower word aligned address */
+	wp = (addr & ~3);	/* get lower word aligned address */
 
 	/*
 	 * handle unaligned start bytes
@@ -325,35 +318,34 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	if ((l = addr - wp) != 0) {
 		data = 0;
 		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *)cp << 8);
+			data = (data >> 8) | (*(uchar *)cp << 24);
 		}
-		for (; i<2 && cnt>0; ++i) {
-			data = (data >> 8) | (*src++ << 8);
+		for (; i<4 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
 			--cnt;
 			++cp;
 		}
-		for (; cnt==0 && i<2; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *)cp << 8);
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
 		}
 
-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_long(info, wp, data)) != 0) {
 			return (rc);
 		}
-		wp += 2;
+		wp += 4;
 	}
 
 	/*
 	 * handle word aligned part
 	 */
-	while (cnt >= 2) {
-		/* data = *((vushort*)src); */
-		data = *((ushort*)src);
-		if ((rc = write_word(info, wp, data)) != 0) {
+	while (cnt >= 4) {
+		data = *((ulong*)src);
+		if ((rc = write_long(info, wp, data)) != 0) {
 			return (rc);
 		}
-		src += 2;
-		wp  += 2;
-		cnt -= 2;
+		src += 4;
+		wp  += 4;
+		cnt -= 4;
 	}
 
 	if (cnt == 0) return ERR_OK;
@@ -362,13 +354,13 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle unaligned tail bytes
 	 */
 	data = 0;
-	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
-		data = (data >> 8) | (*src++ << 8);
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
 		--cnt;
 	}
-	for (; i<2; ++i, ++cp) {
-		data = (data >> 8) | (*(uchar *)cp << 8);
+	for (; i<4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 24);
 	}
 
-	return write_word(info, wp, data);
+	return write_long(info, wp, data);
 }

board/csb226/u-boot.lds

@@ -44,16 +44,12 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-   __u_boot_cmd_start = .;
-   .u_boot_cmd : { *(.u_boot_cmd) }
-   __u_boot_cmd_end = .;
-
-	armboot_end_data = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
-	bss_start = .;
+	__bss_start = .;
 	.bss : { *(.bss) }
-	bss_end = .;
-
-	armboot_end = .;
+	_end = .;
 }