Cleanup

* Enable NAND flash support for NC650 board.
* Patch by Thomas Lange 07 Oct 2004: Updated README for DBAu1x00 boards to match current status
2004-10-11 23:10:30 +00:00 · 2004-10-11 23:03:10 +00:00 · 2004-10-11 22:51:13 +00:00 · 2004-10-11 22:43:02 +00:00 · 2004-10-11 22:25:49 +00:00 · 2004-10-10 23:27:33 +00:00
653 changed files with 69524 additions and 13560 deletions
--- a/663
+++ b/663
@ -1,7 +1,670 @@
+======================================================================
+Changes since U-Boot 1.1.1:
+======================================================================
+
+* Enable NAND flash support for NC650 board.
+
+* Patch by Thomas Lange 07 Oct 2004:
+  Updated README for DBAu1x00 boards to match current status
+
+* Patch by Philippe Robin, 28 Sept 2004:
+  Fix Flash support for Versatile.
+
+* Patch by Roger Blofeld, 16 Sep 2004:
+  Fix timeout for DHCP command retry
+
+* Patch by Pantelis Antoniou, 14 Sep 2004:
+  Fix early serial hang when CONFIG_SERIAL_MULTI is defined.
+
+* Patch by Pantelis Antoniou, 14 Sep 2004:
+  Kick watchdog when bz-decompressing
+
+* Fix CFG_HZ problems on AT91RM9200 systems
+  [Remember: CFG_HZ should be 1000 on ALL systems!]
+
+* Patch by Gridish Shlomi, 30 Aug 2004:
+  - Add support to revA version of PQ27 and PQ27E.
+  - Reverted MPC8260ADS baudrate back to original 115200
+
+* Patch by Hojin, 17 Sep 2004:
+  Fix typo in cfi_flash.c
+
+* Patch by Mark Jonas, 09 September 2004:
+  mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong
+  error message
+
+* Patch by Mark Jonas, 31 August 2004:
+  Added option CFG_XLB_PIPELINING to enable XLB pipelining. This
+  improves FTP performance for MPC5200 systems. Enabled for IceCube
+  by default.
+
+* Patch by Michael Bendzick, 30 Aug 2004:
+  - Improve platform.S code for omap1510inn that detects whether code
+    is running from SDRAM or not. Patch allows SDRAM to be configured
+    if code is running out of SRAM at 0x20000000.
+
+* Patch by Frederick Klatt, 30 Aug 2004:
+  Add support for the Wind River SBC8540/SBC8560 boards
+
+* Configure SX1 board to use drivers/cfi_flash.c
+
+* Patches by Michael Bendzick, 30 Aug 2004:
+  - Configure omap1510inn board to use drivers/cfi_flash.c
+  - Make drivers/cfi_flash.c protect environment and redundant
+    environment.
+
+* Patch by Steven Scholz, 23 Jun 2004:
+  - Add script (tools/img2brec.sh) to programm U-Boot into
+    (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L
+
+* Patches by Scott McNutt, 24 Aug 2004:
+  - Add support for Altera Nios-II processors.
+  - Add support for Psyent PCI-5441 board.
+  - Add support for Psyent PK1C20 board.
+
+* Patches by Jon Loeliger, 24 Aug 2004:
+  - Add support for the MPC8541 and MPC8555 CDS boards
+  - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
+  - Convert MPC85xxADS to use common CFI flash driver
+  - Fix PCI window on MPC85xx; remove unneeded PCI initialization
+    from board_early_init_f()
+  - Provide SW workaround for PCI initialization on 85xx CDS
+
+* Patches by George G. Davis, 24 Aug 2004:
+  - Enable ramdisk/initrd tagged param support for omap1610h2_config
+  - Remove static network setup defaults from mx1ads_config
+  - update ARM boards to use constants from mach-types.h
+
+* Patch by Gary Jennejohn, 04 Oct 2004:
+  - fix I2C on at91rm9200
+  - add support for Ricoh RS5C372A RTC
+
+* Patch by Gary Jennejohn, 01 Oct 2004:
+  - add support for CMC PU2 board
+  - add support for I2C on at91rm9200
+
+* Patch by Gary Jennejohn, 28 Sep 2004:
+  fix baudrate handling on at91rm9200
+
+* Patch by Yuli Barcohen, 22 Aug 2004:
+  - remove ZPC.1900 board-specific flash driver;
+    switch the port to generic CFI driver;
+  - port clean-up
+
+* Patch by Hinko Kocevar, 21 Aug 2004:
+  Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB
+
+* Clean up tools/bmp_logo.c to not add trailing white space
+
+* Patch by Hinko Kocevar, 21 Aug 2004:
+  - Group common framebuffer functions in common/lcd.c
+  - Group common framebuffer macros and #defines in include/lcd.h
+  - Provide calc_fbsize() for video ATAG
+
+* Patch by Sam Song, 21 August 2004:
+  - Fix a typo in README
+  - Align "(RO)" output for "flinfo" after "protect on"
+  - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency
+    ratio 1:1 when core frequency less than 50MHz
+
+* Patches by Hinko Kocevar, 21 Aug 2004:
+  - fix some "use of label at end of compound statement" warnings
+  - Define type of LCD panel on lubbock board if CONFIG_LCD is used
+
+* Patch by Steven Scholz, 16 Aug 2004:
+  - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)"
+  - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0
+  - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/
+  - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/
+    into cpu/arm920t/$(SOC)/
+
+* Patches by Sean Chang, 09 Aug 2004:
+  - Added support for both 8 and 16 bit mode access to System ACE CF
+    through MPU.
+  - Fixed missing System ACE CF device during get FAT partition info
+    in fat_register_device function.
+  - Enabled System ACE CF support on ML300.
+
+* Patch by Sean Chang, 09 Aug 2004:
+  Synch defines for saveenv and do_saveenv functions so they get
+  compiled under the same statement.
+
+* Patch by Sean Chang, 09 Aug 2004:
+  - Added I2C support for ML300.
+  - Added support for ML300 to read out its environment information
+    stored on the EEPROM.
+  - Added support to use board specific parameters as part of
+    U-Boot's environment information.
+  - Updated MLD files to support configuration for new features
+    above.
+
+* Patches by Travis Sawyer, 05 Aug 2004:
+  - Remove incorrect bridge settings for eth group 6
+  - Add call to setup bridge in ppc_440x_eth_initialize
+  - Fix ppc_440x_eth_init to reset the phy only if its the
+    first time through, otherwise, just check the phy for the
+    autonegotiated speed/duplex.  This allows the use of netconsole
+  - only print the speed/duplex the first time the phy is reset.
+
+* Patch by Shlomo Kut, 29 Mar 2004:
+  Add support for MKS Instruments "Quantum" board
+
+* Fix build problem with Cogent boards;
+  avoid using <asm/byteorder.h> when using the host compiler
+
+* Patch by Ganapathi C, 04 Aug 2004:
+  Fix NFS timeout issue
+
+* Patch by Yuli Barcohen, 19 Jul 2004:
+  - Fix host tools building in Cygwin environment
+  - Fix header files search order for host tools
+
+* Patch by Tom Armistead, 19 Jul 2004:
+  Fix kgdb.S support for 74xx_75x cpu
+
+* Patch by Jon Loeliger, 15 Jul 2004:
+  Fix MPC85xx I2C driver
+
+* Fix problems with CDROM drive as slave device on Lite5200 IDE bus.
+
+* Patch by Stephen Williams, 15 July 2004
+  Set the PCI class code for JSE board as part of PCI interface setup
+
+* Patch by Michael Bendzick, 15 Jul 2004:
+  Fix problem with writes with odd sizes in drivers/cfi_flash.c when
+  CFG_FLASH_USE_BUFFER_WRITE is set
+
+* Patch by Yuli Barcohen, 13 Jul 2004:
+  Allow clock setting on MPC866/MPC885 series chips according to
+  environment variable `cpuclk'
+
+* Patch by Yuli Barcohen, 20 Apr 2004:
+  Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
+
+* Patch by Vincent Dubey, 24 Sep 2004:
+  Add support for xaeniax board
+
+* Add comment about non-GPL character of standalone applications to
+  COPYING file
+
+* Fix FEC ethernet problem on NSCU board.
+
+* Patch by Gary Jennejohn, 09 Sep 2004:
+  allow to use USART1 as console port on at91rm9200dk boards
+
+* Patch by Stefan Roese, 16 Sep 2004:
+  Update AR405 board.
+
+* Fix SysClk handling for PPChameleon and CATcenter boards
+
+* Patch by Detlev Zundel, 08 Sep 2004:
+  Update etags build target
+
+* Improve NetConsole support: add support for broadcast destination
+  address and buffered input.
+
+* Cleanup compiler warnings for GCC 3.3.x and later
+
+* Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch
+
+* Add support for IDS "NC650" board
+
+* Add automatic update support for LWMON board
+
+* Clear Block Lock-Bits when erasing flash on LWMON board.
+
+* Fix return code of "fatload" command
+
+* Enable MSDOS/VFAT filesystem support for LWMON board
+
+* Patch by Martin Krause, 03 Aug 2004:
+  change timing for SM501 graphics controller on TQM5200 module
+
+* Patch by Mark Jonas, 13 July 2004:
+  - Total5200 LCD now run in little endian mode. Endianess conversion
+    is done in hardware.
+  - Removed last reference to "console" environment variable.
+
+* Patches by Lars Munch, 12 Jul 2004:
+  - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk
+    board specific
+  - split out the LXT971A PHY from ns_9750_eth.h
+  - split the dm9161 phy part out of at91rm9200_ether.c
+
+* Patch by Andreas Engel, 12 Jul 2004:
+  Replaced hardcoded PL011 clock frequency with config variable.
+  Fixed wrong CONFIG_CMD_DFL doc.
+
+* Patch by Thomas Viehweger, 09 Jun 2004:
+  make it possible to remove chpart when there is only one partition
+
+* Add support for console over UDP (compatible to Ingo Molnar's
+  netconsole patch under Linux)
+
+* Patch by Jon Loeliger, 16 Jul 2004:
+  - support larger DDR memories up to 2G on the PC8540/8560ADS and
+    STXGP3 boards
+  - Made MPC8540/8560ADS be 33Mhz PCI by default.
+  - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
+    and CONFIG_L2_INIT_RAM options.
+  - Refactor Local Bus initialization out of SDRAM setup.
+  - Re-implement new version of LBC11/DDR11 errata workarounds.
+  - Moved board specific PCI init parts out of CPU directory.
+  - Added TLB entry for PCI-1 IO Memory
+  - Updated README.mpc85xxads
+
+* Patch by Sascha Hauer, 28 Jun:
+  - add generic support for Motorola i.MX architecture
+  - add support for mx1ads, mx1fs2 and scb9328 boards
+
+* Patches by Marc Leeman, 23 Jul 2004:
+  - Add define for the PCI/Memory Buffer Configuration Register
+  - corrected comments in cpu/mpc824x/cpu_init.c
+
+* Add support for multiple serial interfaces
+  (for example to allow modem dial-in / dial-out)
+
+* Patch by Stefan Roese, 15 Jul 2004:
+  cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
+
+* Fix NSCU config; add ethernet wakeup code.
+
+* Add link for preloader for Motorola Coldfire to README.m68k
+
+* Patch by Michael Bendzick, 12 Jul 2004:
+  fix output formatting in drivers/cfi_flash.c
+
+* Patch by Mark Jonas, 02 Jul 2004:
+  Fix lowboot (again) on MPC5xxx
+
+* Patch by Curt Brune, 07 Jul 2004:
+  relocate exception vectors on arm720t if needed
+
+* Patch by George G. Davis, 06 Jul 2004:
+  - update mach-types.h to latest arm.linux.org.uk master list
+  - Set correct OMAP1610 bi_arch_number for build target
+
+* Patch by Curt Brune, 06 Jul 2004:
+  evb4510: add support for timer interrupt; cleanup
+
+* Patch by Dan Poirot, 06 Jul 2004:
+  Fix sbc8260 environment variables
+
+* Cleanup redundand "console" environment variable
+
+* Patch by Mark Jonas, 05 Jul 2004:
+  add support for the Total5100's and Total5200's LCD screen
+
+* Patches by Dan Eisenhut, 01 Jul 2004:
+  - README fixes.
+  - Move doc2000.h include to prevent compiler warning on some boards
+
+* Patch by Mark Jonas, 01 Jul 2004:
+  Added support for Total5100 and Total5200 (Rev.1 and Rev.2)
+  MGT5100 and MPC5200 based Freescale platforms.
+
+* Patch by Philippe Robin, 01 Jul 2004:
+  Add initialization for Integrator and versatile board files.
+
+* Patch by Hinko Kocevar, 01 Jun 2004:
+  Fix VFD FB allocation, add LCD FB allocation on ARM
+
+* Patch by Martin Krause, 30 Jun 2004:
+  Add support for TQM5200 board
+
+* Patch by Martin Krause, 29 Jun 2004:
+  Add loopw command: infinite write loop on address range
+
+* Patches by Yasushi Shoji, 29 Jun 2004:
+  - add empty include/asm-microblaze/processor.h
+  - add to CREDITS and MAINTAINERS
+  - add gd initialization
+  - add MicroBlaze and SUZAKU board to MAKEALL script
+  - add reset support for SUZAKU
+  - add flush_cache() for MicroBlaze
+  - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed
+    size flash memory on SUZAKU
+
+* Patch by Prakash Kumar, 27 Jun 2004:
+  Add support for the PXA250 based Intrinsyc Cerf board.
+
+* Patch by Yasushi Shoji, 27 Jun 2004:
+  fix comment in include/common.h
+
+* Rename SBC8560 into sbc8560 for consistency
+
+* Patch by Daniel Poirot, 24 Jun 2004:
+  Add support for Wind River's sbc8240 board
+
+* Patches by Yasushi Shoji, 26 Jun 2004:
+  - drivers/serial_xuartlite.c: fix "return 0" in void function
+  - add microblaze support to mkimage tool
+
+* Patch by Fred Klatt, 25 Jun 2004:
+  Add support for WindRiver's sbc8560 board
+
+* Patch by Nicolas Lacressonniere, 24 Jun 2004
+  Small Bugs fixes for "at91rm9200dk" board:
+  - Timing modifications for SPI DataFlash access
+  - Fix NAND flash detection bug
+
+* Patch by Nicolas Lacressonniere, 24 Jun 2004:
+  Add Support for Flash AT49BV6416 for AT91RM9200DK board
+
+* Patch by Jon Loeliger, 17 June 2004:
+  Completion of the 8540ADS/8560ADS updates:
+  Fix some PCI and Rapid I/O memory maps,
+  Initialize both TSEC 1 and 2,
+  Initialize SDRAM
+  Update MAINTAINER for 85xx boards and README.mpc85xxads
+
+* Patch by Yuli Barcohen, 16 Jun 2004:
+  Remove obsolete AdderII port which was superseded by unified
+  AdderII/Adder87x port
+
+* Patch by Ladislav Michl, 16 Jun 2004:
+  Fix gcc-3.3.3 warnings for smc91111.c
+
+* Patch by Stefan Roese, 02 Jul 2004:
+  - Fix bug in 405 ethernet driver; allocated data not cleared!
+  - Fix problem in 405 i2c driver; don't try to print without console!
+
+* Patch by Paul Ruhland, 11 Jun 2004:
+  Remove debug code from 'board/lpd7a40x/flash.c'
+
+* Patch by Andrea Marson, 11 Jun 2004:
+  Update for PPChameleon board:
+  - support for SysClk @ 25MHz
+  - support for Silicon Motion SM712 VGA controller
+  - some clean ups
+
+* Patches by Richard Woodruff, 10 Jun 2004:
+  - fix problems with examples/stubs.c for GCC >= 3.4
+  - fix problems with gd initialization
+
+* Patch by Curt Brune, 17 May 2004:
+  - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
+  - Add support for ESPD-Inc. EVB4510 Board
+
+* Patch by Marc Leeman, 11 May 2004:
+  Fix for MPC8245 - reading PPC Memory from another device with the
+  PPC as PCI target device corrupts data due to interenal hardware
+  buffering.
+
+* Fix "cls" command when used with splash screen
+
+* Increase NFS download timeout (now 1 min - 10 sec is to short for a
+  slow download of a big image)
+
+* Add "cls" function to MPC823 LCD driver so we can reinitialize the
+  display even after showing a bitmap
+
+* Patch by Josef Wagner, 04 Jun 2004:
+  - DDR Ram support for PM520 (MPC5200)
+  - support for different flash types (PM520)
+  - USB / IDE / CF-Card / DiskOnChip support for PM520
+  - 8 bit boot rom support for PM520/CE520
+  - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
+  - I2C and RTC support for CPC45
+  - support of new flash type (28F160C3T) for CPC45
+
+* Fix flash parameters passed to Linux for PPChameleon board
+
+* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
+
+* Patch by Paul Ruhland, 10 Jun 2004:
+  fix support for Logic SDK-LH7A404 board and clean up the
+  LH7A404 register macros.
+
+* Patch by Matthew McClintock, 10 Jun 2004:
+  Modify code to select correct serial clock on Sandpoint8245
+
+* Patch by Robert Schwebel, 10 Jun 2004:
+  Add support for Intel K3 strata flash.
+
+* Patch by Thomas Brand, 10 Jun 2004:
+  Fix "loads" command on DK1S10 board
+
+* Patch by Yuli Barcohen, 09 Jun 2004:
+  Add support for 8MB flash SIMM and JFFS2 file system on
+  Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS).
+
+* Patch by Yuli Barcohen, 09 Jun 2004:
+  Add support for Analogue&Micro Adder87x and the older AdderII board.
+
+* Patch by Ming-Len Wu, 09 Jun 2004:
+  Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
+
+* Patch by Sam Song, 09 Jun 2004:
+  - Add support for RPXlite_DW board
+  - Update FLASH driver for 4*AM29DL323DB90VI
+  - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board
+
+* Patch by Mark Jonas, 08 June 2004:
+  - Make MPC5200 boards evaluate the SVR to print processor name and
+    version in checkcpu() (cpu/mpc5xxx/cpu.c).
+
+* Patch by Kai-Uwe Bloem, 06 May 2004:
+  Fix endianess problem in cramfs code
+
+* Patch by Tom Armistead, 04 Jun 2004:
+  Add support for MAX6900 RTC
+
+* Patches by Ladislav Michl, 03 Jun 2004:
+  - fix cfi_flash.c on LE systems
+  - let 'make mrproper' delete u-boot.img as well
+  - turn printf into debug in cfi_flash.c
+
+* Patch by Kurt Stremerch, 28 May 2004:
+  Add support for Exys XSEngine board
+
+* Patch by Martin Krause, 27 May 2004:
+  Fix a MPC5xxx I2C timing issue in i2c_probe().
+
+* Patch by Leif Lindholm, 27 May 2004:
+  Fix board_init_f() for dbau1x00 board.
+
+* Patch by Imre Deak, 26 May 2004:
+  On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3).
+  Set flash base accordingly, and decide whether to do or skip board
+  specific setup steps.
+
+* Patch by Josef Baumgartner, 26 May 2004:
+  Add missing define in include/asm-m68k/global_data.h
+
+* Patch by Josef Baumgartner, 25 May 2004:
+  Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c
+
+* Patch by Paul Ruhland, 24 May 2004:
+  fix SDRAM initialization for LPD7A400 board.
+
+* Patch by Jian Zhang, 20 May 2004:
+  add support for environment in NAND flash
+
+* Patch by Yuli Barcohen, 20 May 2004:
+  Add support for Interphase iSPAN boards.
+
+* Patches by Paul Ruhland, 17 May 2004:
+  - Add I/O functions to the smc91111 ethernet driver to support the
+    Logic LPD7A40x boards.
+  - Add support for the Logic Zoom LH7A40x based SDK board(s),
+    specifically the LPD7A400.
+
+* Patches by Robert Schwebel, 15 May 2004:
+  - call MAC address reading code also for SMSC91C111;
+  - make SMSC91C111 timeout configurable, remove duplicate code
+  - fix get_timer() for PXA
+  - update doc/README.JFFS2
+  - use "bootfile" env variable also for jffs2
+
+* Patch by Tolunay Orkun, 14 May 2004:
+  Add support for Cogent CSB472 board (8MB Flash Rev)
+
+* Patch by Thomas Viehweger, 14 May 2004:
+  - flash.h: more flash types added
+  - immap_8260.h: some bits added (useful for RMII)
+  - cmd_coninfo.c: typo corrected, printf -> puts
+  - reduced size by replacing spaces with tab
+
+* Patch by Robert Schwebel, 13 May 2004:
+  Add 'imgextract' command: extract one part of a multi file image.
+
+* Patches by Jon Loeliger, 11 May 2004:
+  Dynamically handle REV1 and REV2 MPC85xx parts.
+    (Jon Loeliger, 10-May-2004).
+  New consistent memory map and Local Access Window across MPC85xx line.
+  New CCSRBAR at 0xE000_0000 now.
+  Add RAPID I/O memory map.
+  New memory map in README.MPC85xxads
+    (Kumar Gala, 10-May-2004)
+  Better board and CPU identification on MPC85xx boards at boot.
+    (Jon Loeliger, 10-May-2004)
+  SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
+  Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
+    (Jim Robertson, 10-May-2004)
+  Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
+  Supports multiple PHYs.
+    (Andy Fleming, 10-May-2004)
+  Some README.MPC85xxads updates.
+    (Kumar Gala, 10-May-2004)
+  Copyright updates for "Freescale"
+    (Andy Fleming, 10-May-2004)
+
+* Patch by Stephen Williams, 11 May 2004:
+  Add flash support for ST M29W040B
+  Reduce JSE specific flash.c to remove dead code.
+
+* Patch by Markus Pietrek, 04 May 2004:
+  Fix clear_bss code for ARM systems (all except s3c44b0 which
+  doesn't clear BSS at all?)
+
+* Fix "ping" problem on INC-IP board. Strange problem:
+  Sometimes the store word instruction hangs while writing to one of
+  the Switch registers, but only if the next instruction is 16-byte
+  aligned. Moving the instruction into a separate function somehow
+  makes the problem go away.
+
+* Patch by Rishi Bhattacharya, 08 May 2004:
+  Add support for TI OMAP5912 OSK Board
+
+* Patch by Sam Song May, 07 May 2004:
+  Fix typo of UPM table for rmu board
+
+* Patch by Pantelis Antoniou, 05 May 2004:
+  - Intracom board update.
+  - Add Codec POST.
+
+* Add support for the second Ethernet interface for the 'PPChameleon'
+  board.
+
+* Patch by Dave Peverley, 30 Apr 2004:
+  Add support for OMAP730 Perseus2 Development board
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+  Fix flash chip-select (OR0) option register setting on FADS boards.
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+  Report MII network speed and duplex setting properly when
+  auto-negotiate is not enabled.
+
+* Patch by Jarrett Redd, 29 Apr 2004:
+  Fix hang on reset on Ocotea board due to flash in wrong mode.
+
+* Patch by Dave Peverley, 29 Apr 2004:
+  add MAC address detection to smc91111 driver
+
+* Patch by David M<>ller, 28 Apr 2004:
+  fix typo in lib_arm/board.c
+
+* Patch by Tolunay Orkun, 20 Apr 2004:
+  - README update: add CONFIG_CSB272 and csb272_config
+  - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and
+    i2cfast environment variable
+
+* Patch by Yuli Barcohen, 19 Apr 2004:
+  - Rename DUET_ADS to MPC885ADS
+  - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
+  - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
+  - Clean up FADS family port to use the new defines
+
+* Fix PCI support on CPC45 board
+
+* Patch by Scott McNutt, 25 Apr 2004:
+  Add Nios GDB/JTAG Console support:
+  - Add stubs to support gdb via JTAG.
+  - Add support for console over JTAG.
+  - Minor cleanup.
+
+* Add support for CATcenter board (based on PPChameleon ME module)
+
+* Patch by Klaus Heydeck, 12 May 2004:
+  Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
+  load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;
+  various changes to KUP4 board specific files
+
+* Fix minor network problem on MPC5200: need some delay between
+  resetting the PHY and sending the first packet. Implemented in a
+  "natural" way by invoking the PHY reset and initialization code
+  only once after power on vs. each time the interface is brought up.
+
+* Add some limited support for low-speed devices to SL811 USB controller
+  (at least "usb reset" now passes successfully and "usb info" displays
+  correct information)
+
+* Change init sequence for multiple network interfaces: initialize
+  on-chip interfaces before external cards.
+
+* Fix memory leak in the NAND-specific JFFS2 code
+
+* Fix SL811 USB controller when attached to a USB hub
+
+* Fix config option spelling in PM520 config file
+
+* Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by
+  patches by Pantelis Antoniou, 30 Mar 2004)
+
+* Fix minor NAND JFFS2 related issue
+
+* Fixes for SL811 USB controller:
+  - implement workaround for broken memory stick
+  - improve error handling
+
+* Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better
+  cope with congested networks.
+
 ======================================================================
 Changes for U-Boot 1.1.1:
 ======================================================================

+* Patch by Travis Sawyer, 23 Apr 2004:
+  Fix VSC/CIS 8201 phy descrambler interoperability timing due to
+  errata from Vitesse Semiconductor.
+
+* Patch by Philippe Robin, 22 Apr 2004:
+  Fix ethernet configuration for "versatile" board
+
+* Patch by Kshitij Gupta, 21 Apr 2004:
+  Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards
+
+* Patch by Steven Scholz, 24 Feb 2004:
+  Fix a bug in AT91RM9200 ethernet driver:
+  The MII interface is now initialized before accessing the PHY.
+
+* Patch by John Kerl, 19 Apr 2004:
+  Use U-boot's miiphy.h for PHY register names, rather than
+  introducing a new header file.
+
+* Update pci_ids.h from linux-2.4.26
+
+* Patch by Masami Komiya, 19 Apr 2004:
+  Fix problem cause by VLAN function on little endian architecture
+  without VLAN environment
+
+* Clean up the TQM8xx_YYMHz configurations; allow to use the same
+  binary image for all clock frequencies. Implement run-time
+  optimization of flash access timing based on the actual bus
+  frequency.
+
 * Modify KUP4X board configuration to use SL811 driver for USB memory
  sticks (including FAT / VFAT filesystem support)

--- a/11
+++ b/11
@ -1,3 +1,14 @@
+  NOTE! This copyright does *not* cover the so-called "standalone"
+applications that use U-Boot services by means of the jump table
+provided by U-Boot exactly for this purpose - this is merely
+considered normal use of U-Boot, and does *not* fall under the
+heading of "derived work". Also note that the GPL below is
+copyrighted by the Free Software Foundation, but the instance of code
+that it refers to (the U-Boot source code) is copyrighted by me and
+others who actually wrote it. -- Wolfgang Denk
+
+=======================================================================
+
 		    GNU GENERAL PUBLIC LICENSE
 		       Version 2, June 1991

--- a/83
+++ b/83
@ -38,6 +38,8 @@ N: Yuli Barcohen
 E: yuli@arabellasw.com
 D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
 D: Support for Zephyr Engineering ZPC.1900 board.
+D: Support for Interphase iSPAN boards.
+D: Support for Analogue&Micro Adder boards.
 W: http://www.arabellasw.com

 N: Jerry van Baren
@ -73,6 +75,12 @@ N: Oliver Brown
 E: obrown@adventnetworks.com
 D: Port to the gw8260 board

+N: Curt Brune
+E: curt@cucy.com
+D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
+D: Added support for ESPD-Inc. EVB4510 Board
+W: http://www.cucy.com
+
 N: Jonathan De Bruyne
 E: jonathan.debruyne@siemens.atea.be
 D: Port to Siemens IAD210 board
@ -198,6 +206,15 @@ N: Yoo. Jonghoon
 E: yooth@ipone.co.kr
 D: Added port to the RPXlite board

+N: Mark Jonas
+E: mark.jonas@freescale.com
+D: Support for Freescale Total5200 platform
+W: http://www.mobilegt.com/
+
+N: Sam Song
+E: samsongshu@yahoo.com.cn
+D: Port to the RPXlite_DW board
+
 N: Brad Kemp
 E: Brad.Kemp@seranoa.com
 D: Port to Windriver ppmc8260 board
@ -206,6 +223,10 @@ N: Sangmoon Kim
 E: dogoil@etinsys.com
 D: Support for debris board

+N: Frederick W. Klatt
+E: fred.klatt@windriver.com
+D: Support for Wind River SBC8540/SBC8560 boards
+
 N: Thomas Koeller
 E: tkoeller@gmx.net
 D: Port to Motorola Sandpoint 3 (MPC8240)
@ -219,6 +240,10 @@ N: Bernhard Kuhn
 E: bkuhn@metrowerks.com
 D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards

+N: Prakash Kumar
+E: prakash@embedx.com
+D  Support for Intrinsyc CERF PXA250 board.
+
 N: Thomas Lange
 E: thomas@corelatus.se
 D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
@ -242,6 +267,11 @@ N: Dan Malek
 E: dan@netx4.com
 D: FADSROM, the grandfather of all of this

+N: Andrea "llandre" Marson
+E: andrea.marson@dave-tech.it
+D: Port to PPChameleonEVB board
+W: www.dave-tech.it
+
 N: Reinhard Meyer
 E: r.meyer@emk-elektronik.de
 D: Port to EMK TOP860 Module
@ -260,7 +290,10 @@ D: Support for Samsung ARM920T SMDK2410 eval board

 N: Scott McNutt
 E: smcnutt@psyent.com
-D: Support for Altera Nios-32 CPU, for Nios Cyclone Development Kit (DK-1C20)
+D: Support for Altera Nios-32 CPU
+D: Support for Altera Nios-II CPU
+D: Support for Nios Cyclone Development Kit (DK-1C20)
+W: http://www.psyent.com

 N: Rolf Offermanns
 E: rof@sysgo.de
@ -269,7 +302,7 @@ W: www.elinos.com

 N: Tolunay Orkun
 E: torkun@nextio.com
-D: Support for Cogent CSB272 board
+D: Support for Cogent CSB272 & CSB472 boards

 N: Keith Outwater
 E: keith_outwater@mvis.com
@ -285,10 +318,20 @@ D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ...
 D: Support for PIP405 board
 D: Support for MIP405 board

+N: Dave Peverley
+E: dpeverley@mpc-data.co.uk
+W: http://www.mpc-data.co.uk
+D: OMAP730 P2 board support
+
 N: Bill Pitts
 E: wlp@mindspring.com
 D: BedBug embedded debugger code

+N: Daniel Poirot
+E: dan.poirot@windriver.com
+D: Support for the sbc8240 board
+W: http://www.windriver.com
+
 N: Stefan Roese
 E: stefan.roese@esd-electronics.com
 D: IBM PPC401/403/405GP Support; Windows environment support
@ -297,6 +340,10 @@ N: Erwin Rol
 E: erwin@muffin.org
 D: boot support for RTEMS

+N: Paul Ruhland
+E: pruhland@rochester.rr.com
+D: Port to Logic Zoom LH7A40x SDK board(s)
+
 N: Neil Russell
 E: caret@c-side.com
 D: Author of LiMon-1.4.2, which contributed some ideas
@ -313,6 +360,19 @@ N: Robert Schwebel
 E: r.schwebel@pengutronix.de
 D: Support for csb226, logodl and innokom boards (PXA2xx)

+N: Yasushi Shoji
+E: yashi@atmark-techno.com
+D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
+
+N: Kurt Stremerch
+E: kurt@exys.be
+D: Support for Exys XSEngine board
+
+N: Andrea Scian
+E: andrea.scian@dave-tech.it
+D: Port to B2 board
+W: www.dave-tech.it
+
 N: Rob Taylor
 E: robt@flyingpig.com
 D: Port to MBX860T and Sandpoint8240
@ -333,13 +393,22 @@ N: David Updegraff
 E: dave@cray.com
 D: Port to Cray L1 board; DHCP vendor extensions

+N: Christian Vejlbo
+E: christian.vejlbo@tellabs.com
+D: FADS860T ethernet support
+
 N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board

-N: Christian Vejlbo
-E: christian.vejlbo@tellabs.com
-D: FADS860T ethernet support
+N: Ming-Len Wu
+E: minglen_wu@techware.com.tw
+D: Motorola MX1ADS board support
+W: http://www.techware.com.tw/
+
+N: Xianghua Xiao
+E: x.xiao@motorola.com
+D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.

 N: John Zhan
 E: zhanz@sinovee.com
@ -349,7 +418,3 @@ N: Alex Zuepke
 E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com
-
-N: Xianghua Xiao
-E: x.xiao@motorola.com
-D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
--- a/65
+++ b/65
@ -27,6 +27,8 @@ Pantelis Antoniou <panto@intracom.gr>

 Yuli Barcohen <yuli@arabellasw.com>

+	Adder			MPC87x/MPC852T
+	ISPAN			MPC8260
 	MPC8260ADS		MPC826x/MPC827x/MPC8280
 	ZPC1900			MPC8265

@ -56,13 +58,14 @@ Torsten Demke <torsten.demke@fci.com>

 Wolfgang Denk <wd@denx.de>

+	IceCube_5100		MGT5100
+	IceCube_5200		MPC5200
+
 	AMX860			MPC860
 	ETX094			MPC850
 	FPS850L			MPC850
 	FPS860L			MPC860
 	ICU862			MPC862
-	IceCube_5100		MGT5100
-	IceCube_5200		MPC5200
 	IP860			MPC860
 	IVML24			MPC860
 	IVML24_128		MPC860
@ -72,6 +75,7 @@ Wolfgang Denk <wd@denx.de>
 	IVMS8_256		MPC860
 	LANTEC			MPC850
 	LWMON			MPC823
+	NC650			MPC852
 	R360MPI			MPC823
 	RMU			MPC850
 	RRvision		MPC823
@ -98,7 +102,6 @@ Wolfgang Denk <wd@denx.de>
 	TQM8255			MPC8255

 	CPU86			MPC8260
-	PM825			MPC8250
 	PM826			MPC8260
 	TQM8260			MPC8260

@ -164,10 +167,6 @@ Sangmoon Kim <dogoil@etinsys.com>

 	debris			MPC8245

-Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
-
-	ADDERII			MPC852T
-
 Nye Liu <nyet@zumanetworks.com>

 	ZUMA			MPC7xx_74xx
@ -184,6 +183,10 @@ Eran Man <eran@nbase.co.il>

 	EVB64260_750CX		MPC750CX

+Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+
+	PPChameleonEVB	PPC405EP
+
 Reinhard Meyer <r.meyer@emk-elektronik.de>

 	TOP860			MPC860T
@ -194,7 +197,8 @@ Scott McNutt <smcnutt@artesyncp.com>
 	EBONY			PPC440GP

 Tolunay Orkun <torkun@nextio.com>
-	csb272			PPC4xx
+	csb272			PPC405GP
+	csb472			PPC405GP

 Keith Outwater <Keith_Outwater@mvis.com>

@ -255,6 +259,11 @@ Rune Torgersen <runet@innovsys.com>

 	MPC8266ADS		MPC8266

+Josef Wagner <Wagner@Microsys.de>
+
+	CPC45			MPC8245
+	PM520			MPC5200
+
 Stephen Williams <steve@icarus.com>

 	JSE			PPC405GPr
@ -263,7 +272,7 @@ John Zhan <zhanz@sinovee.com>

 	svm_sc8xx		MPC8xx

-Xianghua Xiao <x.xiao@motorola.com>
+Jon Loeliger <jdl@freescale.com>

 	MPC8540ADS		MPC8540
 	MPC8560ADS		MPC8560
@ -336,15 +345,26 @@ Gary Jennejohn <gj@denx.de>
 	smdk2400		ARM920T
 	trab			ARM920T

+Prakash Kumar <prakash@embedx.com>
+
+	cerf250			xscale
+
 Kshitij Gupta <kshitij@ti.com>

 	omap1510inn		ARM925T
 	omap1610inn		ARM926EJS

+Dave Peverley <dpeverley@mpc-data.co.uk>
+	omap730p2		ARM926EJS
+
 Nishant Kamat <nskamat@ti.com>

 	omap1610h2		ARM926EJS

+Rishi Bhattacharya <rishi@ti.com>
+
+	omap5912osk		ARM926EJS
+
 David M<>ller <d.mueller@elsoft.ch>

 	smdk2410		ARM920T
@ -359,6 +379,10 @@ Robert Schwebel <r.schwebel@pengutronix.de>
 	csb226			xscale
 	innokom			xscale

+Andrea Scian <andrea.scian@dave-tech.it>
+
+	B2				ARM7TDMI (S3C44B0X)
+
 Alex Z<>pke <azu@sysgo.de>

 	lart			SA1100
@ -406,6 +430,29 @@ Scott McNutt <smcnutt@psyent.com>

 	DK1C20			Nios-32

+#########################################################################
+# Nios-II Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Scott McNutt <smcnutt@psyent.com>
+
+	PCI5441			Nios-II
+	PK1C20			Nios-II
+
+#########################################################################
+# MicroBlaze Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Yasushi Shoji <yashi@atmark-techno.com>
+
+	SUZAKU			MicroBlaze
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
--- a/96
+++ b/96
@ -26,6 +26,7 @@ LIST_5xx="	\

 LIST_5xxx="	\
 	icecube_5100	icecube_5200	EVAL5200	PM520		\
+	Total5100	Total5200	Total5200_Rev2	TQM5200_AA	\
 "

 #########################################################################
@ -33,22 +34,24 @@ LIST_5xxx="	\
 #########################################################################

 LIST_8xx="	\
-	AdderII		ADS860		AMX860		c2mon		\
-	CCM		cogent_mpc8xx	DUET_ADS	ESTEEM192E	\
-	ETX094		ELPT860		FADS823		FADS850SAR	\
-	FADS860T	FLAGADM		FPS850L		GEN860T		\
-	GEN860T_SC	GENIETV		GTH		hermes		\
-	IAD210		ICU862_100MHz	IP860		IVML24		\
-	IVML24_128	IVML24_256	IVMS8		IVMS8_128	\
-	IVMS8_256	KUP4K		KUP4X		LANTEC		\
-	lwmon		MBX		MBX860T		MHPC		\
-	MPC86xADS	MVS1		NETVIA		NETVIA_V2	\
-	NX823		pcu_e		QS823		QS850		\
-	QS860T		R360MPI		RBC823		rmu		\
-	RPXClassic	RPXlite		RRvision	SM850		\
-	SPD823TS	svm_sc8xx	SXNI855T	TOP860		\
-	TQM823L		TQM823L_LCD	TQM850L		TQM855L		\
-	TQM860L		v37		NETTA		NETPHONE	\
+	Adder87x	GENIETV		MBX860T		R360MPI		\
+	AdderII		GTH		MHPC		RBC823		\
+	ADS860		hermes		MPC86xADS	rmu		\
+	AMX860		IAD210		MPC885ADS	RPXClassic	\
+	c2mon		ICU862_100MHz	MVS1		RPXlite		\
+	CCM		IP860		NETPHONE	RPXlite_DW	\
+	cogent_mpc8xx	IVML24		NETTA		RRvision	\
+	ELPT860		IVML24_128	NETTA2		SM850		\
+	ESTEEM192E	IVML24_256	NETTA_ISDN	SPD823TS	\
+	ETX094		IVMS8		NETVIA		svm_sc8xx	\
+	FADS823		IVMS8_128	NETVIA_V2	SXNI855T	\
+	FADS850SAR	IVMS8_256	NX823		TOP860		\
+	FADS860T	KUP4K		pcu_e		TQM823L		\
+	FLAGADM		KUP4X		QS823		TQM823L_LCD	\
+	FPS850L		LANTEC		QS850		TQM850L		\
+	GEN860T		lwmon		QS860T		TQM855L		\
+	GEN860T_SC	MBX		quantum		TQM860L		\
+							v37		\
 "

 #########################################################################
@ -59,13 +62,13 @@ LIST_4xx="	\
 	ADCIOP		AR405		ASH405		BUBINGA405EP	\
 	CANBT		CPCI405		CPCI4052	CPCI405AB	\
 	CPCI440		CPCIISER4	CRAYL1		csb272		\
-	DASA_SIM	DP405		DU405		EBONY		\
-	ERIC		EXBITGEN	HUB405		JSE		\
-	MIP405		MIP405T		ML2		ml300		\
-	OCOTEA		OCRTC		ORSG		PCI405		\
-	PIP405		PLU405		PMC405		PPChameleonEVB	\
-	VOH405		W7OLMC		W7OLMG		WALNUT405	\
-	XPEDITE1K							\
+	csb472		DASA_SIM	DP405		DU405		\
+	EBONY		ERIC		EXBITGEN	HUB405		\
+	JSE		MIP405		MIP405T		ML2		\
+	ml300		OCOTEA		OCRTC		ORSG		\
+	PCI405		PIP405		PLU405		PMC405		\
+	PPChameleonEVB	VOH405		W7OLMC		W7OLMG		\
+	WALNUT405	XPEDITE1K					\
 "

 #########################################################################
@ -76,7 +79,7 @@ LIST_824x="	\
 	A3000		BMW		CPC45		CU824		\
 	debris		eXalion		MOUSSE		MUSENKI		\
 	MVBLUE		OXC		PN62		Sandpoint8240	\
-	Sandpoint8245	SL8245		utx8245				\
+	Sandpoint8245	SL8245		utx8245		sbc8240	\
 "

 #########################################################################
@ -85,11 +88,11 @@ LIST_824x="	\

 LIST_8260="	\
 	atc		cogent_mpc8260	CPU86		ep8260		\
-	gw8260		hymod		IPHASE4539	MPC8260ADS	\
-	MPC8266ADS	MPC8272ADS	PM826		PM828		\
-	ppmc8260	PQ2FADS		RPXsuper	rsdproto	\
-	sacsng		sbc8260		SCM		TQM8260_AC	\
-	TQM8260_AD	TQM8260_AE	ZPC1900				\
+	gw8260		hymod		IPHASE4539	ISPAN		\
+	MPC8260ADS	MPC8266ADS	MPC8272ADS	PM826		\
+	PM828		ppmc8260	PQ2FADS		RPXsuper	\
+	rsdproto	sacsng		sbc8260		SCM		\
+	TQM8260_AC	TQM8260_AD	TQM8260_AE	ZPC1900		\
 "

 #########################################################################
@ -97,7 +100,8 @@ LIST_8260="	\
 #########################################################################

 LIST_85xx="	\
-	MPC8540ADS	MPC8560ADS	stxgp3				\
+	MPC8540ADS	MPC8541CDS	MPC8555CDS	MPC8560ADS	\
+	sbc8540		sbc8560		stxgp3				\
 "

 #########################################################################
@ -130,24 +134,29 @@ LIST_SA="assabet dnp1110 gcplus lart shannon"
 ## ARM7 Systems
 #########################################################################

-LIST_ARM7="B2 ep7312 impa7"
+LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"

 #########################################################################
 ## ARM9 Systems
 #########################################################################

 LIST_ARM9="	\
-	at91rm9200dk	integratorcp	integratorap			\
-	omap1510inn	omap1610h2	omap1610inn			\
-	smdk2400	smdk2410	trab				\
-	VCMA9		versatile					\
+	at91rm9200dk	cmc_pu2		integratorcp	integratorap 	\
+	lpd7a400	mx1ads		mx1fs2		omap1510inn	\
+	omap1610h2	omap1610inn	omap730p2	scb9328		\
+	smdk2400	smdk2410	trab		VCMA9		\
+	versatile							\
 "

 #########################################################################
 ## Xscale Systems
 #########################################################################

-LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250"
+LIST_pxa="	\
+	cerf250		cradle		csb226		innokom		\
+	lubbock		wepep250	xaeniax		xm250		\
+	xsengine							\
+"

 LIST_ixp="ixdp425"

@ -185,6 +194,18 @@ LIST_nios="	\
 	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20			\
 "

+#########################################################################
+## Nios-II Systems
+#########################################################################
+
+LIST_nios2="PCI5441 PK1C20"
+
+#########################################################################
+## MicroBlaze Systems
+#########################################################################
+
+LIST_microblaze="suzaku"
+
 #-----------------------------------------------------------------------

 #----- for now, just run PPC by default -----
@ -209,8 +230,9 @@ do
 	case "$arg" in
 	ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
 	arm|SA|ARM7|ARM9|pxa|ixp| \
+	microblaze| \
 	mips| \
-	nios| \
+	nios|nios2| \
 	x86|I486)
 			for target in `eval echo '$LIST_'${arg}`
 			do
--- a/432
+++ b/432
@ -45,7 +45,7 @@ export	TOPDIR
 ifeq (include/config.mk,$(wildcard include/config.mk))
 # load ARCH, BOARD, and CPU configuration
 include include/config.mk
-export	ARCH CPU BOARD VENDOR
+export	ARCH CPU BOARD VENDOR SOC
 # load other configuration
 include $(TOPDIR)/config.mk

@ -72,6 +72,9 @@ endif
 ifeq ($(ARCH),nios)
 CROSS_COMPILE = nios-elf-
 endif
+ifeq ($(ARCH),nios2)
+CROSS_COMPILE = nios2-elf-
+endif
 ifeq ($(ARCH),m68k)
 CROSS_COMPILE = m68k-elf-
 endif
@ -101,6 +104,9 @@ endif
 LIBS  = lib_generic/libgeneric.a
 LIBS += board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
+ifdef SOC
+LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a
+endif
 LIBS += lib_$(ARCH)/lib$(ARCH).a
 LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
 	fs/reiserfs/libreiserfs.a
@ -176,6 +182,9 @@ tags:

 etags:
 		etags -a `find $(SUBDIRS) include \
+				lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
+				fs/cramfs fs/fat fs/fdos fs/jffs2 \
+				net disk rtc dtt drivers drivers/sk98lin common \
 			\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`

 System.map:	u-boot
@ -249,27 +258,98 @@ icecube_5100_config:			unconfig
 		}
 	@./mkconfig -a IceCube ppc mpc5xxx icecube

+PM520_config \
+PM520_DDR_config \
+PM520_ROMBOOT_config \
+PM520_ROMBOOT_DDR_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring DDR,$@)" ] || \
+		{ echo "#define CONFIG_MPC5200_DDR"	>>include/config.h ; \
+		  echo "... DDR memory revision" ; \
+		}
+	@[ -z "$(findstring ROMBOOT,$@)" ] || \
+		{ echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
+		  echo "... booting from 8-bit flash" ; \
+		}
+	@./mkconfig -a PM520 ppc mpc5xxx pm520
+
 MINI5200_config	\
 EVAL5200_config	\
 TOP5200_config:	unconfig
 	@ echo "#define CONFIG_$(@:_config=) 1"	>include/config.h
 	@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk

-PM520_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc5xxx pm520
+Total5100_config		\
+Total5200_config		\
+Total5200_lowboot_config	\
+Total5200_Rev2_config		\
+Total5200_Rev2_lowboot_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring 5100,$@)" ] || \
+		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
+		  echo "... with MGT5100 processor" ; \
+		}
+	@[ -z "$(findstring 5200,$@)" ] || \
+		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
+		  echo "... with MPC5200 processor" ; \
+		}
+	@[ -n "$(findstring Rev,$@)" ] || \
+		{ echo "#define CONFIG_TOTAL5200_REV 1"	>>include/config.h ; \
+		  echo "... revision 1 board" ; \
+		}
+	@[ -z "$(findstring Rev2_,$@)" ] || \
+		{ echo "#define CONFIG_TOTAL5200_REV 2"	>>include/config.h ; \
+		  echo "... revision 2 board" ; \
+		}
+	@[ -z "$(findstring lowboot_,$@)" ] || \
+		{ echo "TEXT_BASE = 0xFE000000" >board/total5200/config.tmp ; \
+		  echo "... with lowboot configuration" ; \
+		}
+	@./mkconfig -a Total5200 ppc mpc5xxx total5200
+
+TQM5200_AA_config	\
+TQM5200_AB_config	\
+TQM5200_AC_config	\
+MiniFAP_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring MiniFAP,$@)" ] || \
+		{ echo "#define CONFIG_MINIFAP"	>>include/config.h ; \
+		  echo "#define CONFIG_TQM5200_AC"	>>include/config.h ; \
+		  echo "... TQM5200_AC on MiniFAP" ; \
+		}
+	@[ -z "$(findstring AA,$@)" ] || \
+		{ echo "#define CONFIG_TQM5200_AA"	>>include/config.h ; \
+		  echo "... with 4 MB Flash, 16 MB SDRAM, 32 kB EEPROM" ; \
+		}
+	@[ -z "$(findstring AB,$@)" ] || \
+		{ echo "#define CONFIG_TQM5200_AB"	>>include/config.h ; \
+		  echo "... with 64 MB Flash, 64 MB SDRAM, 32 kB EEPROM, 512 kB SRAM" ; \
+		  echo "... with Graphics Controller"; \
+		}
+	@[ -z "$(findstring AC,$@)" ] || \
+		{ echo "#define CONFIG_TQM5200_AC"	>>include/config.h ; \
+		  echo "... with 4 MB Flash, 128 MB SDRAM" ; \
+		  echo "... with Graphics Controller"; \
+		}
+	@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200

 #########################################################################
 ## MPC8xx Systems
 #########################################################################

-AdderII_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx adderII
+Adder_config    \
+Adder87x_config \
+AdderII_config  \
+	:		unconfig
+	$(if $(findstring AdderII,$@), \
+	@echo "#define CONFIG_MPC852T" > include/config.h)
+	@./mkconfig -a Adder ppc mpc8xx adder

 ADS860_config     \
-DUET_ADS_config   \
 FADS823_config    \
 FADS850SAR_config \
 MPC86xADS_config  \
+MPC885ADS_config  \
 FADS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx fads

@ -417,19 +497,53 @@ NETPHONE_config:	unconfig
 		 }
 	@./mkconfig -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone

-xtract_NETTA = $(subst _ISDN,,$(subst _config,,$1))
+xtract_NETTA = $(subst _SWAPHOOK,,$(subst _6412,,$(subst _ISDN,,$(subst _config,,$1))))

+NETTA_ISDN_6412_SWAPHOOK_config \
+NETTA_ISDN_SWAPHOOK_config \
+NETTA_6412_SWAPHOOK_config \
+NETTA_SWAPHOOK_config \
+NETTA_ISDN_6412_config \
 NETTA_ISDN_config \
+NETTA_6412_config \
 NETTA_config:		unconfig
 	@ >include/config.h
-	@[ -z "$(findstring NETTA_config,$@)" ] || \
-		 { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \
-		 }
-	@[ -z "$(findstring NETTA_ISDN_config,$@)" ] || \
+	@[ -z "$(findstring ISDN_,$@)" ] || \
 		 { echo "#define CONFIG_NETTA_ISDN 1" >>include/config.h ; \
 		 }
+	@[ -n "$(findstring ISDN_,$@)" ] || \
+		 { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring 6412_,$@)" ] || \
+		 { echo "#define CONFIG_NETTA_6412 1" >>include/config.h ; \
+		 }
+	@[ -n "$(findstring 6412_,$@)" ] || \
+		 { echo "#undef CONFIG_NETTA_6412" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring SWAPHOOK_,$@)" ] || \
+		 { echo "#define CONFIG_NETTA_SWAPHOOK 1" >>include/config.h ; \
+		 }
+	@[ -n "$(findstring SWAPHOOK_,$@)" ] || \
+		 { echo "#undef CONFIG_NETTA_SWAPHOOK" >>include/config.h ; \
+		 }
 	@./mkconfig -a $(call xtract_NETTA,$@) ppc mpc8xx netta

+xtract_NETTA2 = $(subst _V2,,$(subst _config,,$1))
+
+NETTA2_V2_config \
+NETTA2_config:		unconfig
+	@ >include/config.h
+	@[ -z "$(findstring NETTA2_config,$@)" ] || \
+		 { echo "#define CONFIG_NETTA2_VERSION 1" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring NETTA2_V2_config,$@)" ] || \
+		 { echo "#define CONFIG_NETTA2_VERSION 2" >>include/config.h ; \
+		 }
+	@./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
+
+NC650_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx nc650
+
 NX823_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx nx823

@ -445,6 +559,9 @@ QS823_config:	unconfig
 QS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx qs860t snmc

+quantum_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx quantum
+
 R360MPI_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx r360mpi

@ -457,6 +574,30 @@ RPXClassic_config:	unconfig
 RPXlite_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx RPXlite

+RPXlite_DW_64_config  		\
+RPXlite_DW_LCD_config 		\
+RPXlite_DW_64_LCD_config 	\
+RPXlite_DW_NVRAM_config		\
+RPXlite_DW_NVRAM_64_config      \
+RPXlite_DW_NVRAM_LCD_config	\
+RPXlite_DW_NVRAM_64_LCD_config  \
+RPXlite_DW_config:         unconfig
+	@ >include/config.h
+	@[ -z "$(findstring _64,$@)" ] || \
+		{ echo "#define RPXlite_64MHz"		>>include/config.h ; \
+		  echo "... with 64MHz system clock ..."; \
+		}
+	@[ -z "$(findstring _LCD,$@)" ] || \
+		{ echo "#define CONFIG_LCD"          	>>include/config.h ; \
+		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
+		  echo "... with LCD display ..."; \
+		}
+	@[ -z "$(findstring _NVRAM,$@)" ] || \
+		{ echo "#define  CFG_ENV_IS_IN_NVRAM" 	>>include/config.h ; \
+		  echo "... with ENV in NVRAM ..."; \
+		}
+	@./mkconfig -a RPXlite_DW ppc mpc8xx RPXlite_dw
+
 rmu_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx rmu

@ -486,66 +627,26 @@ TOP860_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx top860 emk

 # Play some tricks for configuration selection
-# All boards can come with 50 MHz (default), 66MHz, 80MHz or 100 MHz clock,
-# but only 855 and 860 boards may come with FEC
-# and 823 boards may have LCD support
-xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _133MHz,,$(subst _LCD,,$(subst _config,,$1))))))
+# Only 855 and 860 boards may come with FEC
+# and only 823 boards may have LCD support
+xtract_8xx = $(subst _LCD,,$(subst _config,,$1))

 FPS850L_config		\
 FPS860L_config		\
 NSCU_config		\
 TQM823L_config		\
-TQM823L_66MHz_config	\
-TQM823L_80MHz_config	\
 TQM823L_LCD_config	\
-TQM823L_LCD_66MHz_config \
-TQM823L_LCD_80MHz_config \
 TQM850L_config		\
-TQM850L_66MHz_config	\
-TQM850L_80MHz_config	\
 TQM855L_config		\
-TQM855L_66MHz_config	\
-TQM855L_80MHz_config	\
 TQM860L_config		\
-TQM860L_66MHz_config	\
-TQM860L_80MHz_config	\
 TQM862L_config		\
-TQM862L_66MHz_config	\
-TQM862L_80MHz_config	\
 TQM823M_config		\
-TQM823M_66MHz_config	\
-TQM823M_80MHz_config	\
 TQM850M_config		\
-TQM850M_66MHz_config	\
-TQM850M_80MHz_config	\
 TQM855M_config		\
-TQM855M_66MHz_config	\
-TQM855M_80MHz_config	\
 TQM860M_config		\
-TQM860M_66MHz_config	\
-TQM860M_80MHz_config	\
 TQM862M_config		\
-TQM862M_66MHz_config	\
-TQM862M_80MHz_config	\
-TQM862M_100MHz_config	\
 TQM866M_config:		unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _66MHz,$@)" ] || \
-		{ echo "#define CONFIG_66MHz"		>>include/config.h ; \
-		  echo "... with 66MHz system clock" ; \
-		}
-	@[ -z "$(findstring _80MHz,$@)" ] || \
-		{ echo "#define CONFIG_80MHz"		>>include/config.h ; \
-		  echo "... with 80MHz system clock" ; \
-		}
-	@[ -z "$(findstring _100MHz,$@)" ] || \
-		{ echo "#define CONFIG_100MHz"		>>include/config.h ; \
-		  echo "... with 100MHz system clock" ; \
-		}
-	@[ -z "$(findstring _133MHz,$@)" ] || \
-		{ echo "#define CONFIG_133MHz"		>>include/config.h ; \
-		  echo "... with 133MHz system clock" ; \
-		}
 	@[ -z "$(findstring _LCD,$@)" ] || \
 		{ echo "#define CONFIG_LCD"		>>include/config.h ; \
 		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
@ -571,7 +672,7 @@ wtk_config:	unconfig
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
-xtract_4xx = $(subst _MODEL_BA,,$(subst _MODEL_ME,,$(subst _MODEL_HI,,$(subst _config,,$1))))
+xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1))))))

 ADCIOP_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
@ -588,6 +689,21 @@ BUBINGA405EP_config:	unconfig
 CANBT_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx canbt esd

+CATcenter_config	\
+CATcenter_25_config	\
+CATcenter_33_config:	unconfig
+	@ echo "/* CATcenter uses PPChameleon Model ME */"  > include/config.h
+	@ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> include/config.h
+	@[ -z "$(findstring _25,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
+		  echo "SysClk = 25MHz" ; \
+		}
+	@[ -z "$(findstring _33,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
+		  echo "SysClk = 33MHz" ; \
+		}
+	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+
 CPCI405_config	\
 CPCI4052_config	\
 CPCI405AB_config:	unconfig
@ -606,6 +722,9 @@ CRAYL1_config:	unconfig
 csb272_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx csb272

+csb472_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx csb472
+
 DASA_SIM_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd

@ -663,23 +782,34 @@ PLU405_config:	unconfig
 PMC405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd

-PPChameleonEVB_MODEL_BA_config	\
-PPChameleonEVB_MODEL_ME_config	\
-PPChameleonEVB_MODEL_HI_config	\
-PPChameleonEVB_config:	unconfig
+PPChameleonEVB_config		\
+PPChameleonEVB_BA_25_config	\
+PPChameleonEVB_ME_25_config	\
+PPChameleonEVB_HI_25_config	\
+PPChameleonEVB_BA_33_config	\
+PPChameleonEVB_ME_33_config	\
+PPChameleonEVB_HI_33_config:	unconfig
 	@ >include/config.h
-	@[ -z "$(findstring _MODEL_BA,$@)" ] || \
+	@[ -z "$(findstring EVB_BA,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
 		  echo "... BASIC model" ; \
 		}
-	@[ -z "$(findstring _MODEL_ME,$@)" ] || \
+	@[ -z "$(findstring EVB_ME,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>include/config.h ; \
 		  echo "... MEDIUM model" ; \
 		}
-	@[ -z "$(findstring _MODEL_HI,$@)" ] || \
+	@[ -z "$(findstring EVB_HI,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
 		  echo "... HIGH-END model" ; \
 		}
+	@[ -z "$(findstring _25,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
+		  echo "SysClk = 25MHz" ; \
+		}
+	@[ -z "$(findstring _33,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
+		  echo "SysClk = 33MHz" ; \
+		}
 	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave

 VOH405_config:	unconfig
@ -749,6 +879,9 @@ Sandpoint8240_config: unconfig
 Sandpoint8245_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x sandpoint

+sbc8240_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc824x sbc8240
+
 SL8245_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x sl8245

@ -790,6 +923,13 @@ hymod_config:	unconfig
 IPHASE4539_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 iphase4539

+ISPAN_config		\
+ISPAN_REVB_config:	unconfig
+	@if [ "$(findstring _REVB_,$@)" ] ; then \
+		echo "#define CFG_REV_B" > include/config.h ; \
+	fi
+	@./mkconfig -a ISPAN ppc mpc8260 ispan
+
 MPC8260ADS_config	\
 MPC8260ADS_33MHz_config	\
 MPC8260ADS_40MHz_config	\
@ -944,13 +1084,43 @@ M5282EVB_config :		unconfig
 ## MPC85xx Systems
 #########################################################################

-MPC8540ADS_config:      unconfig
+MPC8540ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads

-MPC8560ADS_config:      unconfig
+MPC8560ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads

-stxgp3_config:      unconfig
+MPC8541CDS_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8541cds cds
+
+MPC8555CDS_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds
+
+sbc8540_config \
+sbc8540_33_config \
+sbc8540_66_config:	unconfig
+	@if [ "$(findstring _66_,$@)" ] ; then \
+		echo "#define CONFIG_PCI_66"	>>include/config.h ; \
+		echo "... 66 MHz PCI" ; \
+	else \
+		>include/config.h ; \
+		echo "... 33 MHz PCI" ; \
+	fi
+	@./mkconfig -a SBC8540 ppc mpc85xx sbc8560
+
+sbc8560_config \
+sbc8560_33_config \
+sbc8560_66_config:      unconfig
+	@if [ "$(findstring _66_,$@)" ] ; then \
+		echo "#define CONFIG_PCI_66"	>>include/config.h ; \
+		echo "... 66 MHz PCI" ; \
+	else \
+		>include/config.h ; \
+		echo "... 33 MHz PCI" ; \
+	fi
+	@./mkconfig -a sbc8560 ppc mpc85xx sbc8560
+
+stxgp3_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx stxgp3

 #########################################################################
@ -1014,10 +1184,9 @@ shannon_config	:	unconfig

 xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))

-xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
+xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1))))

-SX1_config :		unconfig
-	@./mkconfig $(@:_config=) arm arm925t sx1
+xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))

 integratorcp_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorcp
@ -1025,18 +1194,45 @@ integratorcp_config :	unconfig
 integratorap_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorap

-versatile_config :	unconfig
-	@./mkconfig $(@:_config=) arm arm926ejs versatile
+lpd7a400_config \
+lpd7a404_config:	unconfig
+	@./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
+
+mx1ads_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t mx1ads NULL imx
+
+mx1fs2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t mx1fs2 NULL imx

 omap1510inn_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm925t omap1510inn

+omap5912osk_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs omap5912osk
+
 omap1610inn_config \
 omap1610inn_cs0boot_config \
 omap1610inn_cs3boot_config \
+omap1610inn_cs_autoboot_config \
 omap1610h2_config \
 omap1610h2_cs0boot_config \
-omap1610h2_cs3boot_config :	unconfig
+omap1610h2_cs3boot_config \
+omap1610h2_cs_autoboot_config:	unconfig
+	@if [ "$(findstring _cs0boot_, $@)" ] ; then \
+		echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
+		echo "... configured for CS0 boot"; \
+	elif [ "$(findstring _cs_autoboot_, $@)" ] ; then \
+		echo "#define CONFIG_CS_AUTOBOOT" >> ./include/config.h ; \
+		echo "... configured for CS_AUTO boot"; \
+	else \
+		echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
+		echo "... configured for CS3 boot"; \
+	fi;
+	@./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
+
+omap730p2_config \
+omap730p2_cs0boot_config \
+omap730p2_cs3boot_config :	unconfig
 	@if [ "$(findstring _cs0boot_, $@)" ] ; then \
 		echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
 		echo "... configured for CS0 boot"; \
@ -1044,13 +1240,19 @@ omap1610h2_cs3boot_config :	unconfig
 		echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
 		echo "... configured for CS3 boot"; \
 	fi;
-	@./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
+	@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
+
+scb9328_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx

 smdk2400_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm920t smdk2400
+	@./mkconfig $(@:_config=) arm arm920t smdk2400 NULL s3c24x0

 smdk2410_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm920t smdk2410
+	@./mkconfig $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
+
+SX1_config :		unconfig
+	@./mkconfig $(@:_config=) arm arm925t sx1

 # TRAB default configuration:	8 MB Flash, 32 MB RAM
 trab_config \
@ -1075,11 +1277,13 @@ trab_old_config:	unconfig
 		  echo "... with 8 MB Flash, 16 MB RAM" ; \
 		  echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \
 		}
-	@./mkconfig -a $(call xtract_trab,$@) arm arm920t trab
+	@./mkconfig -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0

 VCMA9_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm920t vcma9 mpl
+	@./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0

+versatile_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs versatile

 #########################################################################
 ## S3C44B0 Systems
@ -1092,15 +1296,18 @@ B2_config	:	unconfig
 ## ARM720T Systems
 #########################################################################

-impa7_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm720t impa7
-
 ep7312_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm720t ep7312

+impa7_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm720t impa7
+
 modnet50_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm720t modnet50

+evb4510_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm720t evb4510
+
 #########################################################################
 ## AT91RM9200 Systems
 #########################################################################
@ -1108,10 +1315,16 @@ modnet50_config :	unconfig
 at91rm9200dk_config	:	unconfig
 	@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk

+cmc_pu2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm at91rm9200 cmc_pu2
+
 #########################################################################
 ## XScale Systems
 #########################################################################

+cerf250_config :	unconfig
+	@./mkconfig $(@:_config=) arm pxa cerf250
+
 cradle_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa cradle

@ -1133,9 +1346,15 @@ logodl_config	:	unconfig
 wepep250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa wepep250

+xaeniax_config	:	unconfig
+	@./mkconfig $(@:_config=) arm pxa xaeniax
+
 xm250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa xm250

+xsengine_config :	unconfig
+	@./mkconfig $(@:_config=) arm pxa xsengine
+
 #========================================================================
 # i386
 #========================================================================
@ -1182,6 +1401,24 @@ incaip_config: unconfig
 tb0229_config: unconfig
 	@./mkconfig $(@:_config=) mips mips tb0229

+#########################################################################
+## MIPS32 AU1X00
+#########################################################################
+dbau1000_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1000 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
+dbau1100_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1100 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
+dbau1500_config		: 	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################
@ -1255,6 +1492,15 @@ ADNPESC1_config: unconfig
 		}
 	@./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv

+#########################################################################
+## Nios-II
+#########################################################################
+
+PK1C20_config : unconfig
+	@./mkconfig  PK1C20 nios2 nios2 pk1c20 psyent
+
+PCI5441_config : unconfig
+	@./mkconfig  PCI5441 nios2 nios2 pci5441 psyent

 #========================================================================
 # MicroBlaze
@ -1267,24 +1513,6 @@ suzaku_config:	unconfig
 	@echo "#define CONFIG_SUZAKU 1" >> include/config.h
 	@./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno

-#########################################################################
-## MIPS32 AU1X00
-#########################################################################
-dbau1000_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1000 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
-dbau1100_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1100 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
-dbau1500_config		: 	unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
-	@./mkconfig -a dbau1x00 mips mips dbau1x00
-
 #########################################################################
 #########################################################################

@ -1297,7 +1525,7 @@ clean:
 	      examples/eepro100_eeprom examples/sched \
 	      examples/mem_to_mem_idma2intr examples/82559_eeprom
 	rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
-	rm -f tools/mpc86x_clk
+	rm -f tools/mpc86x_clk tools/ncb
 	rm -f tools/easylogo/easylogo tools/bmp_logo
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
@ -1305,10 +1533,10 @@ clean:
 	rm -f board/trab/trab_fkt

 clobber:	clean
-	find . -type f \
-		\( -name .depend -o -name '*.srec' -o -name '*.bin' \) \
-		-print \
-		| xargs rm -f
+	find . -type f \( -name .depend \
+		-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
+		-print0 \
+		| xargs -0 rm -f
 	rm -f $(OBJS) *.bak tags TAGS
 	rm -fr *.*~
 	rm -f u-boot u-boot.map $(ALL)
--- a/2575
+++ b/2575
--- a/board/AtmarkTechno/suzaku/suzaku.c
+++ b/board/AtmarkTechno/suzaku/suzaku.c
@ -22,8 +22,11 @@
 * MA 02111-1307 USA
 */

-#include <common.h>
+/* This is a board specific file.  It's OK to include board specific
+ * header files */
+#include <asm/suzaku.h>

 void do_reset(void)
 {
+	*((unsigned long *)(MICROBLAZE_SYSREG_BASE_ADDR)) = MICROBLAZE_SYSREG_RECONFIGURE;
 }
--- a/board/Marvell/db64360/db64360.c
+++ b/board/Marvell/db64360/db64360.c
@ -549,18 +549,18 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 #if defined (CFG_DRAM_TEST_DATA)

 unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaa,
-	0xcccccccccccccccc,
-	0xf0f0f0f0f0f0f0f0,
-	0xff00ff00ff00ff00,
-	0xffff0000ffff0000,
-	0xffffffff00000000,
-	0x00000000ffffffff,
-	0x0000ffff0000ffff,
-	0x00ff00ff00ff00ff,
-	0x0f0f0f0f0f0f0f0f,
-	0x3333333333333333,
-	0x5555555555555555
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
 };

 /*********************************************************************/
--- a/board/Marvell/db64460/db64460.c
+++ b/board/Marvell/db64460/db64460.c
@ -549,18 +549,18 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 #if defined (CFG_DRAM_TEST_DATA)

 unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaa,
-	0xcccccccccccccccc,
-	0xf0f0f0f0f0f0f0f0,
-	0xff00ff00ff00ff00,
-	0xffff0000ffff0000,
-	0xffffffff00000000,
-	0x00000000ffffffff,
-	0x0000ffff0000ffff,
-	0x00ff00ff00ff00ff,
-	0x0f0f0f0f0f0f0f0f,
-	0x3333333333333333,
-	0x5555555555555555
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
 };

 /*********************************************************************/
--- a/board/RPXlite_dw/Makefile
+++ b/board/RPXlite_dw/Makefile
@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
--- a/board/RPXlite_dw/README
+++ b/board/RPXlite_dw/README
@ -0,0 +1,96 @@
+
+After following the step of Yoo. Jonghoon and Wolfgang Denk,
+I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW.
+
+There are three differences between the Yoo-ported RPXlite and the RPXlite_DW.
+
+Board(in U-BOOT)	version(in EmbeddedPlanet)	CPU	SDRAM	FLASH
+RPXlite				RPXlite CW		850	16MB	4MB
+RPXlite_DW			RPXlite DW		823e	64MB	16MB
+
+This fireware is specially coded for EmbeddedPlanet Co. Software Development
+Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel.
+
+It has the following three features:
+
+1. 64MHz/48MHz system frequence setting options.
+The default setting is 48MHz.To get a 64MHz u-boot,just add
+'64' in make command,like
+
+make RPXlite_DW_64_config
+make all
+
+2. CFG_ENV_IS_IN_FLASH/CFG_ENV_IS_IN_NVRAM
+
+The default environment parameter is stored in FLASH because it is a common choice for
+environment parameter.So I make NVRAM as backup parameter storeage.The reason why I
+didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter
+home.Because of the possibility of using two firewares on this board,I didn't
+'disturb' EEPROM.To get NVRAM support,you may use the following build command:
+
+make RPXlite_DW_NVRAM_config
+make all
+
+3. LCD panel support
+
+To support the Platform better,I added LCD panel(NL6448BC20-08) function.But bewear of
+the fact that once you build this support and program it to FLASH,you should make sure
+you put workable kernel and ramdisk at the right place in FLASH or through NFS.
+Otherwise, you must erase this fireware manually via BDI2000 or ICE tools.So this
+function is used for deployment and demo only.Pls look before you leap.
+
+To get a LCD support u-boot,you can do the following:
+
+make RPXlite_DW_LCD_config
+make all
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The basic make commands could be:
+
+make RPXlite_DW_config
+make RPXlite_DW_64_config
+make RPXlite_DW_LCD_config
+make RPXlite_DW_NVRAM_config
+
+BTW,you can combine the above features together and get a workable u-boot to meet your need.
+For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type:
+
+make RPXlite_DW_NVRAM_64_LCD_config
+make all
+
+So other combining make commands could be:
+
+make RPXlite_DW_NVRAM_64_config
+make RPXlite_DW_NVRAM_LCD_config
+make RPXlite_DW_64_LCD_config
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The boot process by "make RPXlite_DW_config" could be:
+
+U-Boot 1.1.1 (Jun  8 2004 - 11:16:30)
+
+CPU:   PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache
+Board: RPXlite_DW
+DRAM:  64 MB
+FLASH: 16 MB
+*** Warning - bad CRC, using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+u-boot>
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+I'd like to extend my heartfelt gratitute to kind people for helping me work it out.
+I would particually thank Wolfgang Denk for his nice help.
+
+Enjoy,
+
+Sam Song, samsongshu@yahoo.com.cn
+Institute of Electrical Machinery and Controls
+Shanghai University
+
+June 8,2004
--- a/board/RPXlite_dw/RPXlite_dw.c
+++ b/board/RPXlite_dw/RPXlite_dw.c
@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2004
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Sam Song
+ * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
+ * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
+ * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+static long int dram_size (long int, long int *, long int);
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
+	0x01FFCC20, 0x1FF74C20, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
+	_NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
+	_NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
+	0x01FFFC24, 0x1FF74C25, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
+	/* INIT sequence RAM WORDS
+	 * SDRAM Initialization (offset 0x36 in UPMA RAM)
+	 * The above definition uses the remaining space
+	 * to establish an initialization sequence,
+	 * which is executed by a RUN command.
+	 * The sequence is COMMAND INHIBIT(NOP),Precharge,
+	 * Load Mode Register,NOP,Auto Refresh.
+	 */
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
+};
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXlite_DW\n") ;
+	return (0) ;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CFG_MPTPR ;
+
+	memctl->memc_mar  = 0x00000088;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
+	/*Disable Periodic timer A. */
+
+ 	udelay(200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr  = 0x80002236; /* SDRAM bank 0 - refresh twice */
+
+	udelay(1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	/*Enable Periodic timer A */
+
+	udelay (1000);
+
+	 /* Check Bank 0 Memory Size
+	  * try 9 column mode
+	  */
+
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+
+	udelay (1000);
+
+	return (size9);
+}
+
+void rpxlite_init (void)
+{
+	/* Enable NVRAM */
+	*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
--- a/board/RPXlite_dw/config.mk
+++ b/board/RPXlite_dw/config.mk
@ -0,0 +1,29 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RPXlite dw boards : lite_dw
+#
+
+TEXT_BASE = 0xff000000
--- a/board/RPXlite_dw/flash.c
+++ b/board/RPXlite_dw/flash.c
@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * Some of flash control words are modified. (from 2x16bit device
+ * to 4x8bit device)
+ * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
+ * are not tested.
+ *
+ * (?) Does an RPXLite board which
+ * 	does not use AM29LV800 flash memory exist ?
+ *	I don't know...
+ */
+
+/* Yes,Yoo.They do use other FLASH for the board.
+ *
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ * U-Boot port on RPXlite DW version board
+ *
+ * By now,it uses 4 AM29DL323DB90VI devices(4x8bit).
+ * The total FLASH has 16MB(4x4MB).
+ * I just made some necessary changes on the basis of Wolfgang and Yoo's job.
+ *
+ * June 8, 2004 */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions   vu_long : volatile unsigned long IN include/common.h
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* If Monitor is in the cope of FLASH,then
+	 * protect this area by default in case for
+	 * other occupation. [SAM] */
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+	flash_info[0].size = size_b0;
+	return (size_b0);
+}
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000);
+		}
+	} else {
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AMDL323B:    printf ("AM29DL323B (32 Mbit, bottom boot sector)\n");
+				break;
+	/* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM]  */
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+	printf ("  Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0x00AA00AA ;
+	addr[0x555] = 0x00550055 ;
+	addr[0xAAA] = 0x00900090 ;
+
+	value = addr[0] ;
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:             		/* AMD_MANUFACT=0x00010001 in flash.h. */
+		info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;			/* device ID		*/
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_LV400T & 0x00FF00FF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (AMD_ID_LV400B & 0x00FF00FF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (AMD_ID_LV800T & 0x00FF00FF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (AMD_ID_LV800B & 0x00FF00FF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/* Size doubled by yooth */
+		break;				/* => 4 MB		 */
+	case (AMD_ID_LV160T & 0x00FF00FF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (AMD_ID_LV160B & 0x00FF00FF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (AMD_ID_DL323B & 0x00FF00FF):
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;                          /* => 16 MB(4x4MB)  */
+	/* AMD_ID_DL323B= 0x22532253  FLASH_AMDL323B= 0x0013
+	 * AMD_ID_DL323B could be found in <flash.h>.[SAM]
+	 * So we could get : flash_id = 0x00000013.
+	 * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+	/* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1,
+	 * it means bottom boot flash. GOOD IDEA! [SAM]
+	 */
+
+	/* set sector offsets for bottom boot block type        */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		/* info->protect[i] = addr[4] & 1 ; */
+		/* Mask it for disorder FLASH protection **[Sam]** */
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+	return (info->size);
+}
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
--- a/board/RPXlite_dw/u-boot.lds
+++ b/board/RPXlite_dw/u-boot.lds
@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+/* XXX ?
+    . = env_offset;
+*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/RPXlite_dw/u-boot.lds.debug
+++ b/board/RPXlite_dw/u-boot.lds.debug
@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/adder/Makefile
+++ b/board/adder/Makefile
@ -0,0 +1,46 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/adder/adder.c
+++ b/board/adder/adder.c
@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Adder boards family.
+ * Tested on AdderII and Adder87x.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*
+ * SDRAM is single Samsung K4S643232F-T70 chip.
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+	/* Single read	(offset 0x00 in UPM RAM) */
+	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
+	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
+
+	/* Burst read	(offset 0x08 in UPM RAM) */
+	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
+	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
+	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
+
+	/* Single write (offset 0x18 in UPM RAM) */
+	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
+	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Burst write	(offset 0x20 in UPM RAM) */
+	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Refresh	(offset 0x30 in UPM RAM) */
+	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Exception	(offset 0x3C in UPM RAM) */
+	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
+};
+
+long int initdram (int board_type)
+{
+	long int msize = CFG_SDRAM_SIZE;
+	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/* Configure SDRAM refresh */
+	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
+
+	memctl->memc_mamr = (94 << 24) | CFG_MAMR;
+	memctl->memc_mar  = 0x0;
+	udelay(200);
+
+	/* Run precharge from location 0x15 */
+	memctl->memc_mcr = 0x80002115;
+	udelay(200);
+
+	/* Run 8 refresh cycles */
+	memctl->memc_mcr = 0x80002830;
+	udelay(200);
+
+	memctl->memc_mar = 0x88;
+	udelay(200);
+
+	/* Run MRS pattern from location 0x16 */
+	memctl->memc_mcr = 0x80002116;
+	udelay(200);
+
+	return msize;
+}
+
+int checkboard( void )
+{
+	puts("Board: Adder");
+#if defined(CONFIG_MPC885_FAMILY)
+	puts("87x\n");
+#elif defined(CONFIG_MPC866_FAMILY)
+	puts("II\n");
+#endif
+
+	return 0;
+}
--- a/board/adder/config.mk
+++ b/board/adder/config.mk
@ -0,0 +1,27 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Analogue&Micro Adder boards family
+#
+TEXT_BASE = 0xFE000000
--- a/board/adder/u-boot.lds
+++ b/board/adder/u-boot.lds
@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)		}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text          :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
--- a/board/adderII/adderII.c
+++ b/board/adderII/adderII.c
@ -1,189 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-/*
- * Check Board Identity:
- */
-
-int checkboard( void )
-{
-	puts("Board: ");
-	puts("AdderII(MPC852T)\n" );
-
-  	return 0;
-}
-
-#if defined( CONFIG_SDRAM_50MHZ )
-
-/******************************************************************************
-** for chip Samsung K4S643232F - T70
-** this table is for 32-50MHz operation
-*******************************************************************************/
-
-#define SDRAM_MPTPRVALUE 	0x0200
-
-#define SDRAM_MAMRVALUE0 	0x00802114   /* refresh at 32MHz */
-#define SDRAM_MAMRVALUE1 	0x00802118
-
-#define SDRAM_OR1VALUE   	0xff800e00
-#define SDRAM_BR1VALUE   	0x00000081
-
-#define SDRAM_MARVALUE		94
-
-#define SDRAM_MCRVALUE0  	0x80808105
-#define SDRAM_MCRVALUE1  	0x80808130
-
-const uint sdram_table[] = {
-
-	/* single read   (offset 0x00 in upm ram) */
-       	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
-       	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
-
-	/* burst read    (offset 0x08 in upm ram) */
-       	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
-       	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
-       	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
-       	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
-
-	/* single write  (offset 0x18 in upm ram) */
-       	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
-       	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* burst write   (offset 0x20 in upm ram) */
-       	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
-       	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
-       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* refresh       (offset 0x30 in upm ram) */
-       	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-       	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
-       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* exception     (offset 0x3C in upm ram) */
-       	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-};
-
-#else
-#error SDRAM not correctly configured
-#endif
-
-int _initsdram (uint base, uint noMbytes)
-{
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	if (noMbytes != 8) {
-		return -1;
-	}
-
-	upmconfig (UPMA, (uint *) sdram_table,
-		   sizeof (sdram_table) / sizeof (uint));
-
-	memctl->memc_mptpr = SDRAM_MPTPRVALUE;
-
-	/* Configure the refresh (mostly).  This needs to be
-	 * based upon processor clock speed and optimized to provide
-	 * the highest level of performance.  For multiple banks,
-	 * this time has to be divided by the number of banks.
-	 * Although it is not clear anywhere, it appears the
-	 * refresh steps through the chip selects for this UPM
-	 * on each refresh cycle.
-	 * We have to be careful changing
-	 * UPM registers after we ask it to run these commands.
-	 */
-
-	memctl->memc_mamr = (SDRAM_MAMRVALUE0 | (SDRAM_MARVALUE << 24));
-	memctl->memc_mar = 0x0;
-	udelay (200);
-
-	/* Now run the precharge/nop/mrs commands.
-	 */
-	memctl->memc_mcr = 0x80002115;
-	udelay (200);
-
-	/* Run 8 refresh cycles */
-	memctl->memc_mcr = 0x80002380;
-	udelay (200);
-
-	memctl->memc_mar = 0x88;
-	udelay (200);
-
-	memctl->memc_mcr = 0x80002116;
-	udelay (200);
-
-	memctl->memc_or1 = SDRAM_OR1VALUE;
-	memctl->memc_br1 = SDRAM_BR1VALUE | base;
-
-	return 0;
-}
-
-void _sdramdisable( void )
-{
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_br1 = 0x00000000;
-
-	/* maybe we should turn off upma here or something */
-}
-
-int initsdram (uint base, uint * noMbytes)
-{
-	uint m = 8;
-
-	*noMbytes = m;
-
-	if (!_initsdram (base, m)) {
-		return 0;
-	} else {
-		_sdramdisable ();
-		return -1;
-	}
-}
-
-long int initdram (int board_type)
-{
-	/* AdderII: has 8MB SDRAM */
-	uint sdramsz;
-	uint m = 0;
-
-	if (!initsdram (0x00000000, &sdramsz)) {
-		m += sdramsz;
-	} else {
-		return -1;
-	}
-	return (m << 20);
-}
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX not an actual SDRAM test */
-	printf ("Test: 8MB SDRAM\n");
-
-	return (0);
-}
--- a/board/adderII/flash.c
+++ b/board/adderII/flash.c
@ -1,501 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/******************************************************************************
-** Notes: AM29LV320DB - 90EI ( 32 Mbit device )
-** Sectors - Eight 8 Kb sector
-** 	   - Sixty three 64 Kb sector
-** Bottom boot sector
-******************************************************************************/
-#include <common.h>
-#include <mpc8xx.h>
-
-
-/******************************************************************************
-**	Defines
-******************************************************************************/
-#ifdef CONFIG_ADDERII
-
-#define ADDR0	0x0555
-#define ADDR1	0x02AA
-#define FLASH_WORD_SIZE unsigned short
-
-#endif
-
-#if defined( CFG_ENV_IS_IN_FLASH )
-# ifndef  CFG_ENV_ADDR
-#  define CFG_ENV_ADDR  ( CFG_FLASH_BASE + CFG_ENV_OFFSET )
-# endif
-# ifndef  CFG_ENV_SIZE
-#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
-# endif
-# ifndef  CFG_ENV_SECT_SIZE
-#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
-# endif
-#endif
-
-/******************************************************************************
-**	Global Parameters
-******************************************************************************/
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-
-/******************************************************************************
-**	Function Prototypes
-******************************************************************************/
-static ulong flash_get_size( vu_long *addr, flash_info_t *info );
-
-static int write_word( flash_info_t *info, ulong dest, ulong data );
-
-static void flash_get_offsets( ulong base, flash_info_t *info );
-
-int wait_for_DQ7( flash_info_t *info, int sect );
-
-/******************************************************************************
-** Function :	flash_init
-** Param    :   void
-** Notes    :   Initializes the Flash Chip
-******************************************************************************/
-ulong flash_init (void)
-{
-	ulong size_b0 = -1;
-	int i;
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	/* Set Flash to unknown */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Get the Flash Bank Size */
-
-	size_b0 = flash_get_size ((vu_long *) (CFG_FLASH_BASE),
-				  &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## UNKNOWN Flash on Bank 0 - Size = 0x%08lx = %ldMB\n",
-			size_b0, size_b0 >> 20);
-	}
-
-	/* Remap Flash according to size detected  */
-	memctl->memc_or0 = 0xFF800774;
-	memctl->memc_br0 = CFG_BR0_PRELIM;
-
-	/* Setup Flash Sector Offsets */
-
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
-
-	/* Monitor Protection ON - default */
-
-#if ( CFG_MONITOR_BASE >= CFG_FLASH_BASE  )
-	flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-		       (CFG_MONITOR_BASE + monitor_flash_len - 1),
-		       &flash_info[0]);
-#endif
-
-	/* Protect Environment Variables */
-#ifdef CFG_ENV_IS_IN_FLASH
-	flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR,
-		       (CFG_ENV_ADDR + CFG_ENV_SIZE - 1), &flash_info[0]);
-#endif
-
-	return size_b0;
-}
-
-/******************************************************************************
-** Function : flash_get_offsets
-** Param    : ulong base, flash_into_t *info
-** Notes    :
-******************************************************************************/
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	return;
-}
-
-
-/******************************************************************************
-** Function : flash_print_info
-** Param    : flash_info_t
-** Notes    :
-******************************************************************************/
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Missing or unknown flash type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-		printf ("AMD ");
-		break;
-	case FLASH_MAN_FUJ:
-		printf ("FUJITSU ");
-		break;
-	case FLASH_MAN_BM:
-		printf ("BRIGHT MICRO ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM320B:
-		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM320T:
-		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20,
-		info->sector_count);
-	printf ("  Sector Start Addresses:");
-
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/******************************************************************************
-** Function : flash_get_size
-** Param    : vu_long *addr, flash_info_t *info
-** Notes    :
-******************************************************************************/
-static ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
-	short i;
-	FLASH_WORD_SIZE manu_id, dev_id;
-	ulong base = (ulong) addr;
-	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
-	/* Write Auto Select Command and read Manufacturer's ID and Dev ID */
-
-	addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
-	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
-	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
-
-	manu_id = addr2[0];
-
-	switch (manu_id) {
-	case (FLASH_WORD_SIZE) AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		break;
-	}
-
-	/* Read Device Id */
-	dev_id = addr2[1];
-
-	switch (dev_id) {
-	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 71;	/* 8 - boot sec + 63 normal */
-		info->size = 0x400000;	/* 4MByte */
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	/* Set up sector start Addresses */
-
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block
-		 ** Eight 8 Kb Boot sectors
-		 ** Sixty Three 64Kb sectors
-		 */
-		for (i = 0; i < 8; i++) {
-			info->start[i] = base + (i * 0x00002000);
-		}
-		for (i = 8; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00070000;
-		}
-	}
-
-	/* Reset To read mode */
-
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (ulong *) info->start[0];
-		*addr = 0xF0F0F0F0;
-	}
-	return (info->size);
-}
-
-/*******************************************************************************
-** Function : flash_erase
-** Param    : flash_info_t *info, int s_first, int s_last
-** Notes    :
-******************************************************************************/
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
-	volatile FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect, l_sect;
-	int i;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
-
-			if ((info->flash_id & FLASH_VENDMASK) ==
-			    FLASH_MAN_SST) {
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
-				for (i = 0; i < 50; i++)
-					udelay (1000);	/* wait 1 ms */
-			} else {
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-			}
-			l_sect = sect;
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7 (info, sect);
-		}
-	}
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/* reset to read mode */
-	addr = (FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-int wait_for_DQ7 (flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile FLASH_WORD_SIZE *addr =
-		(FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer (0);
-	last = start;
-	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
-	       (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {
-			putc ('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-
-/******************************************************************************
-** Function : write_buff
-** Param    : flash_info_t *info, uchar *src, ulong addr, ulong cnt
-** Notes    :
-******************************************************************************/
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	/* get lower word aligned address */
-	wp = (addr & ~3);
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_word (info, wp, data));
-}
-
-
-/******************************************************************************
-** Function : write_word
-** Param    : flash_info_t *info, ulong dest, ulong data
-** Notes    :
-******************************************************************************/
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
-	volatile FLASH_WORD_SIZE *addr2 =
-		(FLASH_WORD_SIZE *) (info->start[0]);
-	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
-	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
-	ulong start;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((volatile FLASH_WORD_SIZE *) dest) &
-	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
-		return (2);
-	}
-
-	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
-		int flag;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts ();
-
-		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts ();
-
-		/* data polling for D7 */
-		start = get_timer (0);
-		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
-		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-	}
-
-	return (0);
-}
--- a/board/altera/dk1c20/vectors.S
+++ b/board/altera/dk1c20/vectors.S
@ -38,6 +38,8 @@
 *	_cwp_lolimit	-Handles register window underflows.
 *	_cwp_hilimit	-Handles register window overflows.
 *	_timebase_int	-Increments the timebase.
+ *	_brkpt_hw_int	-Hardware breakpoint handler.
+ *	_brkpt_sw_int	-Software breakpoint handler.
 *	_def_xhandler	-Default exception handler.
 *
 * _timebase_int handles a Nios Timer interrupt and increments the
@ -58,9 +60,8 @@ _vectors:
 	.long	_def_xhandler@h		/* Vector 0  - NMI */
 	.long	_cwp_lolimit@h		/* Vector 1  -  underflow */
 	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
-
-	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
-	.long	_def_xhandler@h		/* Vector 4 - GNUPro debug */
+	.long	_brkpt_hw_int@h		/* Vector 3 - Breakpoint */
+	.long	_brkpt_sw_int@h		/* Vector 4 - Single step*/
 	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
 	.long	_def_xhandler@h		/* Vector 6 - future reserved */
 	.long	_def_xhandler@h		/* Vector 7 - future reserved */
--- a/board/assabet/assabet.c
+++ b/board/assabet/assabet.c
@ -101,7 +101,7 @@ board_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;

-	gd->bd->bi_arch_number = 25;	/* Intel Assabet Board */
+	gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
 	gd->bd->bi_boot_params = 0xc0000100;

 	neponset_init();
--- a/board/at91rm9200dk/Makefile
+++ b/board/at91rm9200dk/Makefile
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	:= at91rm9200dk.o flash.o
+OBJS	:= at91rm9200dk.o at45.o dm9161.o flash.o
 SOBJS	:=

 $(LIB):	$(OBJS) $(SOBJS)
--- a/board/at91rm9200dk/at45.c
+++ b/board/at91rm9200dk/at45.c
@ -25,7 +25,14 @@
 #ifdef CONFIG_HAS_DATAFLASH
 #include <dataflash.h>

-#define SPI_CLK 5000000
+#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
+the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS	(0xC << 16)
+#define DATAFLASH_TCHS	(0x1 << 24)
+
 #define AT91C_TIMEOUT_WRDY			200000
 #define AT91C_SPI_PCS0_SERIAL_DATAFLASH		0xE     /* Chip Select 0 : NPCS0 %1110 */
 #define AT91C_SPI_PCS3_DATAFLASH_CARD		0x7     /* Chip Select 3 : NPCS3 %0111 */
@ -50,9 +57,11 @@ void AT91F_SpiInit(void) {
 	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;

 	/* Configure CS0 and CS3 */
-	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & 0x100000) | ((AT91C_MASTER_CLOCK / (2*SPI_CLK)) << 8);
+	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);

-	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & 0x100000) | ((AT91C_MASTER_CLOCK / (2*SPI_CLK)) << 8);
+	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);

 }

--- a/board/at91rm9200dk/at91rm9200dk.c
+++ b/board/at91rm9200dk/at91rm9200dk.c
@ -45,7 +45,7 @@ int board_init (void)
 	/* so we do _nothing_ here */

 	/* arch number of AT91RM9200DK-Board */
-	gd->bd->bi_arch_number = 251;
+	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200;
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

@ -102,6 +102,10 @@ void nand_init (void)
 	*AT91C_PIOB_PER = AT91C_PIO_PB1;	/* enable direct output enable */
 	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */

+	/* PIOB and PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
 	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
 		printf ("  No SmartMedia card inserted\n");
 #ifdef DEBUG
--- a/board/at91rm9200dk/dm9161.c
+++ b/board/at91rm9200dk/dm9161.c
@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <dm9161.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ *	dm9161_IsPhyConnected
+ * Description:
+ *	Reads the 2 PHY ID registers
+ * Arguments:
+ *	p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ *	TRUE - if id read successfully
+ *	FALSE- if error
+ */
+static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+	unsigned short Id1, Id2;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
+		((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
+		return TRUE;
+
+	return FALSE;
+}
+
+/*
+ * Name:
+ *	dm9161_GetLinkSpeed
+ * Description:
+ *	Link parallel detection status of MAC is checked and set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to MAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+	unsigned short stat1, stat2;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
+		return FALSE;
+
+	if (!(stat1 & DM9161_LINK_STATUS))	/* link status up? */
+		return FALSE;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
+		return FALSE;
+
+	if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
+		/*set Emac for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
+		/*set MII for 100BaseTX and Half Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_SPD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
+		/*set MII for 10BaseT and Half Duplex  */
+		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+		return TRUE;
+	}
+	return FALSE;
+}
+
+
+/*
+ * Name:
+ *	dm9161_InitPhy
+ * Description:
+ *	MAC starts checking its link by using parallel detection and
+ *	Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
+{
+	UCHAR ret = TRUE;
+	unsigned short IntValue;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+
+	if (!dm9161_GetLinkSpeed (p_mac)) {
+		/* Try another time */
+		ret = dm9161_GetLinkSpeed (p_mac);
+	}
+
+	/* Disable PHY Interrupts */
+	at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
+	/* clear FDX, SPD, Link, INTR masks */
+	IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
+		      DM9161_LINK_MASK | DM9161_INTR_MASK);
+	at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	return (ret);
+}
+
+
+/*
+ * Name:
+ *	dm9161_AutoNegotiate
+ * Description:
+ *	MAC Autonegotiates with the partner status of same is set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	dev - pointer to struct net_device
+ * Return value:
+ *	TRUE - if link status set successfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+	unsigned short value;
+	unsigned short PhyAnar;
+	unsigned short PhyAnalpar;
+
+	/* Set dm9161 control register */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+	value &= ~DM9161_AUTONEG;	/* remove autonegotiation enable */
+	value |= DM9161_ISOLATE;	/* Electrically isolate PHY */
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	/* Set the Auto_negotiation Advertisement Register */
+	/* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
+	PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
+		  DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
+		return FALSE;
+
+	/* Read the Control Register     */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+	/* Restart Auto_negotiation  */
+	value |= DM9161_RESTART_AUTONEG;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	/*check AutoNegotiate complete */
+	udelay (10000);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
+	if (!(value & DM9161_AUTONEG_COMP))
+		return FALSE;
+
+	/* Get the AutoNeg Link partner base page */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
+		return FALSE;
+
+	if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
+		/*set MII for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+	return FALSE;
+}
+
+
+/*
+ * Name:
+ *	at91rm92000_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+
+#endif	/* CONFIG_DRIVER_ETHER */
--- a/board/at91rm9200dk/flash.c
+++ b/board/at91rm9200dk/flash.c
@ -42,20 +42,22 @@ typedef struct OrgDef
 /* Flash Organizations */
 OrgDef OrgAT49BV16x4[] =
 {
-	{ 8, 8*1024 }, /* 8 * 8kBytes sectors */
-	{ 2, 32*1024 }, /* 2 * 32kBytes sectors */
-	{ 30, 64*1024 } /* 30 * 64kBytes sectors */
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{  2, 32*1024 },	/*   2 * 32 kBytes sectors */
+	{ 30, 64*1024 },	/*  30 * 64 kBytes sectors */
 };

 OrgDef OrgAT49BV16x4A[] =
 {
-	{ 8, 8*1024 }, /* 8 * 8kBytes sectors */
-	{ 31, 64*1024 } /* 31 * 64kBytes sectors */
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 31, 64*1024 },	/*  31 * 64 kBytes sectors */
 };

-
-#define FLASH_BANK_SIZE 0x200000	/* 2 MB */
-#define MAIN_SECT_SIZE  0x10000		/* 64 KB */
+OrgDef OrgAT49BV6416[] =
+{
+	{   8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 127, 64*1024 },	/* 127 * 64 kBytes sectors */
+};

 flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];

@ -73,13 +75,11 @@ flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
 #define CMD_ERASE_CONFIRM	0x0030
 #define CMD_PROGRAM		0x00A0
 #define CMD_UNLOCK_BYPASS	0x0020
+#define CMD_SECTOR_UNLOCK	0x0070

 #define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1)))
 #define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1)))

-#define IDENT_FLASH_ADDR1	(*(volatile u16 *)(CFG_FLASH_BASE + (0x0000555<<1)))
-#define IDENT_FLASH_ADDR2	(*(volatile u16 *)(CFG_FLASH_BASE + (0x0000AAA<<1)))
-
 #define BIT_ERASE_DONE		0x0080
 #define BIT_RDY_MASK		0x0080
 #define BIT_PROGRAM_ERROR	0x0020
@ -95,17 +95,17 @@ void flash_identification (flash_info_t * info)
 {
 	volatile u16 manuf_code, device_code, add_device_code;

-	IDENT_FLASH_ADDR1 = FLASH_CODE1;
-	IDENT_FLASH_ADDR2 = FLASH_CODE2;
-	IDENT_FLASH_ADDR1 = ID_IN_CODE;
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_IN_CODE;

 	manuf_code = *(volatile u16 *) CFG_FLASH_BASE;
 	device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2);
 	add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1));

-	IDENT_FLASH_ADDR1 = FLASH_CODE1;
-	IDENT_FLASH_ADDR2 = FLASH_CODE2;
-	IDENT_FLASH_ADDR1 = ID_OUT_CODE;
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_OUT_CODE;

 	/* Vendor type */
 	info->flash_id = ATM_MANUFACT & FLASH_VENDMASK;
@ -117,14 +117,36 @@ void flash_identification (flash_info_t * info)
 			(ATM_ID_BV1614A & FLASH_TYPEMASK)) {
 			info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK;
 			printf ("AT49BV1614A (16Mbit)\n");
+		} else {				/* AT49BV1614 Flash */
+			info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
+			printf ("AT49BV1614 (16Mbit)\n");
 		}

-	} else {				/* AT49BV1614 Flash */
-		info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
-		printf ("AT49BV1614 (16Mbit)\n");
+	} else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) {
+		info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK;
+		printf ("AT49BV6416 (64Mbit)\n");
 	}
 }

+ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks)
+{
+	int i, nb_sectors = 0;
+
+	for (i=0; i<nb_blocks; i++){
+		nb_sectors += pOrgDef[i].sector_number;
+	}
+
+	return nb_sectors;
+}
+
+void flash_unlock_sector(flash_info_t * info, unsigned int sector)
+{
+	volatile u16 *addr = (volatile u16 *) (info->start[sector]);
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	*addr = CMD_SECTOR_UNLOCK;
+}
+

 ulong flash_init (void)
 {
@ -140,23 +162,29 @@ ulong flash_init (void)

 		flash_identification (&flash_info[i]);

-		flash_info[i].size = FLASH_BANK_SIZE;
-
 		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
 			(ATM_ID_BV1614 & FLASH_TYPEMASK)) {
-			flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);

 			pOrgDef = OrgAT49BV16x4;
 			flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef);
-		} else {			/* AT49BV1614A Flash */
-			flash_info[i].sector_count = CFG_MAX_FLASH_SECT - 1;
-			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT - 1);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614A & FLASH_TYPEMASK)){	/* AT49BV1614A Flash */

 			pOrgDef = OrgAT49BV16x4A;
 			flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			pOrgDef = OrgAT49BV6416;
+			flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef);
+		} else {
+			flash_nb_blocks = 0;
+			pOrgDef = OrgAT49BV16x4;
 		}

+		flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks);
+		memset (flash_info[i].protect, 0, flash_info[i].sector_count);
+
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@ -164,15 +192,26 @@ ulong flash_init (void)

 		sector = 0;
 		start_address = flashbase;
+		flash_info[i].size = 0;

 		for (j = 0; j < flash_nb_blocks; j++) {
 			for (k = 0; k < pOrgDef[j].sector_number; k++) {
 				flash_info[i].start[sector++] = start_address;
 				start_address += pOrgDef[j].sector_size;
+				flash_info[i].size += pOrgDef[j].sector_size;
 			}
 		}

 		size += flash_info[i].size;
+
+		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			/* Unlock all sectors at reset */
+			for (j=0; j<flash_info[i].sector_count; j++){
+				flash_unlock_sector(&flash_info[i], j);
+			}
+		}
 	}

 	/* Protect binary boot image */
@ -215,6 +254,9 @@ void flash_print_info (flash_info_t * info)
 	case (ATM_ID_BV1614A & FLASH_TYPEMASK):
 		printf ("AT49BV1614A (16Mbit)\n");
 		break;
+	case (ATM_ID_BV6416 & FLASH_TYPEMASK):
+		printf ("AT49BV6416 (64Mbit)\n");
+		break;
 	default:
 		printf ("Unknown Chip Type\n");
 		goto Done;
@ -234,7 +276,7 @@ void flash_print_info (flash_info_t * info)
 	}
 	printf ("\n");

-  Done:
+Done:	;
 }

 /*-----------------------------------------------------------------------
--- a/board/cds/common/cadmus.c
+++ b/board/cds/common/cadmus.c
@ -0,0 +1,95 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+
+
+/*
+ * CADMUS Board System Registers
+ */
+#ifndef CFG_CADMUS_BASE_REG
+#define CFG_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
+#endif
+
+typedef struct cadmus_reg {
+    u_char cm_ver;		/* Board version */
+    u_char cm_csr;		/* General control/status */
+    u_char cm_rst;		/* Reset control */
+    u_char cm_hsclk;		/* High speed clock */
+    u_char cm_hsxclk;		/* High speed clock extended */
+    u_char cm_led;		/* LED data */
+    u_char cm_pci;		/* PCI control/status */
+    u_char cm_dma;		/* DMA control */
+    u_char cm_reserved[248];	/* Total 256 bytes */
+} cadmus_reg_t;
+
+
+unsigned int
+get_board_version(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	return cadmus->cm_ver;
+}
+
+
+unsigned long
+get_clock_freq(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
+
+	if (pci1_speed == 0) {
+		return 33000000;
+	} else if (pci1_speed == 1) {
+		return 66000000;
+	} else {
+		/* Really, unknown. Be safe? */
+		return 33000000;
+	}
+}
+
+
+unsigned int
+get_pci_slot(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	/*
+	 * PCI slot in USER bits CSR[6:7] by convention.
+	 */
+	return ((cadmus->cm_csr >> 6) & 0x3) + 1;
+}
+
+
+unsigned int
+get_pci_dual(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	/*
+	 * PCI DUAL in CM_PCI[3]
+	 */
+	return cadmus->cm_pci & 0x10;
+}
--- a/board/cds/common/cadmus.h
+++ b/board/cds/common/cadmus.h
@ -0,0 +1,54 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CADMUS_H_
+#define __CADMUS_H_
+
+
+/*
+ * CADMUS Board System Register interface.
+ */
+
+/*
+ * Returns board version register.
+ */
+extern unsigned int get_board_version(void);
+
+/*
+ * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
+ */
+extern unsigned long get_clock_freq(void);
+
+
+/*
+ * Returns 1 - 4, as found in the USER CSR[6:7] bits.
+ */
+extern unsigned int get_pci_slot(void);
+
+
+/*
+ * Returns PCI DUAL as found in CM_PCI[3].
+ */
+extern unsigned int get_pci_dual(void);
+
+
+#endif	/* __CADMUS_H_ */
--- a/board/cds/common/eeprom.c
+++ b/board/cds/common/eeprom.c
@ -0,0 +1,60 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <i2c.h>
+
+#include "eeprom.h"
+
+
+typedef struct {
+	char idee_pcbid[4];		/* "CCID" for CDC v1.X */
+	u8 idee_major;
+	u8 idee_minor;
+	char idee_serial[10];
+	char idee_errata[2];
+	char idee_date[8];		/* yyyymmdd */
+	/* The rest of the EEPROM space is reserved */
+} id_eeprom_t;
+
+
+unsigned int
+get_cpu_board_revision(void)
+{
+	uint major = 0;
+	uint minor = 0;
+
+	id_eeprom_t id_eeprom;
+
+	i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2,
+		 (uchar *) &id_eeprom, sizeof(id_eeprom));
+
+	major = id_eeprom.idee_major;
+	minor = id_eeprom.idee_minor;
+
+	if (major == 0xff && minor == 0xff) {
+		major = minor = 0;
+	}
+
+	return MPC85XX_CPU_BOARD_REV(major,minor);
+}
--- a/board/cds/common/eeprom.h
+++ b/board/cds/common/eeprom.h
@ -0,0 +1,50 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EEPROM_H_
+#define __EEPROM_H_
+
+
+/*
+ * EEPROM Board System Register interface.
+ */
+
+
+/*
+ * CPU Board Revision
+ */
+#define MPC85XX_CPU_BOARD_REV(maj, min)	((((maj)&0xff) << 8) | ((min) & 0xff))
+#define MPC85XX_CPU_BOARD_MAJOR(rev)	(((rev) >> 8) & 0xff)
+#define MPC85XX_CPU_BOARD_MINOR(rev)	((rev) & 0xff)
+
+#define MPC85XX_CPU_BOARD_REV_UNKNOWN	MPC85XX_CPU_BOARD_REV(0,0)
+#define MPC85XX_CPU_BOARD_REV_1_0	MPC85XX_CPU_BOARD_REV(1,0)
+#define MPC85XX_CPU_BOARD_REV_1_1	MPC85XX_CPU_BOARD_REV(1,1)
+
+/*
+ * Returns CPU board revision register as a 16-bit value with
+ * the Major in the high byte, and Minor in the low byte.
+ */
+extern unsigned int get_cpu_board_revision(void);
+
+
+#endif	/* __CADMUS_H_ */
--- a/board/cds/mpc8541cds/Makefile
+++ b/board/cds/mpc8541cds/Makefile
@ -0,0 +1,51 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o \
+	   ../common/cadmus.o \
+	   ../common/eeprom.o
+
+SOBJS	:= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cds/mpc8541cds/config.mk
+++ b/board/cds/mpc8541cds/config.mk
@ -0,0 +1,30 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8541cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1
--- a/board/cds/mpc8541cds/init.S
+++ b/board/cds/mpc8541cds/init.S
@ -0,0 +1,255 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+
+law_entry:
+	entry_start
+	.long 6
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	entry_end
--- a/board/cds/mpc8541cds/mpc8541cds.c
+++ b/board/cds/mpc8541cds/mpc8541cds.c
@ -0,0 +1,349 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf ("    PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		(pci1_speed == 33000000) ? "33" :
+		(pci1_speed == 66000000) ? "66" : "unknown",
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf ("    PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		/*
+		 * Work around to stabilize DDR DLL MSYNC_IN.
+		 * Errata DDR9 seems to have been fixed.
+		 * This is now the workaround for Errata DDR11:
+		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+		 */
+
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay(200);
+	}
+#endif
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	/*
+	 * SDRAM Initialization
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+	uint temp_lbcdll;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+
+	} else {
+		lbc->lcrr &= (~0x8000000);	/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+	uint idx;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("    SDRAM: ");
+
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	asm("msync");
+
+	lbc->br2 = CFG_BR2_PRELIM;
+	asm("msync");
+
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * Determine which address lines to use baed on CPU board rev.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+	} else {
+		/*
+		 * Assume something unable to identify itself is
+		 * really old, and likely has lines 16/17 mapped.
+		 */
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	}
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxcds_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif
+}
--- a/board/cds/mpc8541cds/u-boot.lds
+++ b/board/cds/mpc8541cds/u-boot.lds
@ -0,0 +1,147 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/cds/mpc8541cds/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/cds/mpc8541cds/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/tsec.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/cds/mpc8555cds/Makefile
+++ b/board/cds/mpc8555cds/Makefile
@ -0,0 +1,51 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o \
+	   ../common/cadmus.o \
+	   ../common/eeprom.o
+
+SOBJS	:= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cds/mpc8555cds/config.mk
+++ b/board/cds/mpc8555cds/config.mk
@ -0,0 +1,30 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8555cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1
--- a/board/cds/mpc8555cds/init.S
+++ b/board/cds/mpc8555cds/init.S
@ -0,0 +1,255 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+
+law_entry:
+	entry_start
+	.long 6
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	entry_end
--- a/board/cds/mpc8555cds/mpc8555cds.c
+++ b/board/cds/mpc8555cds/mpc8555cds.c
@ -0,0 +1,346 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf ("    PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		(pci1_speed == 33000000) ? "33" :
+		(pci1_speed == 66000000) ? "66" : "unknown",
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf ("    PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		/*
+		 * Work around to stabilize DDR DLL MSYNC_IN.
+		 * Errata DDR9 seems to have been fixed.
+		 * This is now the workaround for Errata DDR11:
+		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+		 */
+
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay(200);
+	}
+#endif
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	/*
+	 * SDRAM Initialization
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+	uint temp_lbcdll;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+
+	} else {
+		lbc->lcrr &= (~0x8000000);	/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+	uint idx;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("    SDRAM: ");
+
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	asm("msync");
+
+	lbc->br2 = CFG_BR2_PRELIM;
+	asm("msync");
+
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * Determine which address lines to use baed on CPU board rev.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+	} else {
+		/*
+		 * Assume something unable to identify itself is
+		 * really old, and likely has lines 16/17 mapped.
+		 */
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	}
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxcds_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif
+}
--- a/board/cds/mpc8555cds/u-boot.lds
+++ b/board/cds/mpc8555cds/u-boot.lds
@ -0,0 +1,147 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/cds/mpc8555cds/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/cds/mpc8555cds/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/tsec.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/cerf250/Makefile
+++ b/board/cerf250/Makefile
@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cerf250.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cerf250/cerf250.c
+++ b/board/cerf250/cerf250.c
@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of cerf PXA Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
--- a/board/cerf250/config.mk
+++ b/board/cerf250/config.mk
@ -0,0 +1,5 @@
+#
+# Cerf board with PXA250 cpu
+#
+#
+TEXT_BASE = 0xa3080000
--- a/board/omap1510inn/flash.c
+++ b/board/omap1510inn/flash.c
@ -27,34 +27,34 @@
 #include <common.h>
 #include <linux/byteorder/swab.h>

-#define PHYS_FLASH_SECT_SIZE    0x00020000	/* 256 KB sectors (x2) */
+
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */

 /* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16

 #ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH	ushort
-#define FLASH_PORT_WIDTHV	vu_short
-#define SWAP(x)			__swab16(x)
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
 #else
-#define FLASH_PORT_WIDTH	ulong
-#define FLASH_PORT_WIDTHV	vu_long
-#define SWAP(x)			__swab32(x)
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
 #endif

-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV

 #define mb() __asm__ __volatile__ ("" : : : "memory")

 /*-----------------------------------------------------------------------
 * Functions
 */
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
 void inline spin_wheel (void);

 /*-----------------------------------------------------------------------
@ -71,6 +71,10 @@ unsigned long flash_init (void)
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
 			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
 			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
 		default:
 			panic ("configured too many flash banks!\n");
 			break;
@ -83,19 +87,18 @@ unsigned long flash_init (void)
 	flash_protect ( FLAG_PROTECT_SET,
 			CFG_FLASH_BASE,
 			CFG_FLASH_BASE + monitor_flash_len - 1,
-			&flash_info[0]);
+			&flash_info[0] );

 	flash_protect ( FLAG_PROTECT_SET,
 			CFG_ENV_ADDR,
-			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-			&flash_info[0]);
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );

 	return size;
 }

 /*-----------------------------------------------------------------------
 */
-static void flash_get_offsets (ulong base, flash_info_t * info)
+static void flash_get_offsets (ulong base, flash_info_t *info)
 {
 	int i;

@ -113,7 +116,7 @@ static void flash_get_offsets (ulong base, flash_info_t * info)

 /*-----------------------------------------------------------------------
 */
-void flash_print_info (flash_info_t * info)
+void flash_print_info (flash_info_t *info)
 {
 	int i;

@ -141,7 +144,7 @@ void flash_print_info (flash_info_t * info)
 	}

 	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
+			info->size >> 20, info->sector_count);

 	printf ("  Sector Start Addresses:");
 	for (i = 0; i < info->sector_count; ++i) {
@ -158,7 +161,7 @@ void flash_print_info (flash_info_t * info)
 /*
 * The following code cannot be run from FLASH!
 */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
 {
 	volatile FPW value;

@ -186,6 +189,7 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)

 	mb ();
 	value = addr[1];			/* device ID        */
+
 	switch (value) {

 	case (FPW) INTEL_ID_28F128J3A:
@ -205,7 +209,7 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 		info->sector_count = CFG_MAX_FLASH_SECT;
 	}

-	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */

 	return (info->size);
 }
@ -214,7 +218,7 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 /*-----------------------------------------------------------------------
 */

-int flash_erase (flash_info_t * info, int s_first, int s_last)
+int flash_erase (flash_info_t *info, int s_first, int s_last)
 {
 	int flag, prot, sect;
 	ulong type, start, last;
@ -250,7 +254,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		printf ("\n");
 	}

-	/*start = get_timer (0); */
+	start = get_timer (0);
 	last = start;

 	/* Disable interrupts which might cause a timeout here */
@ -281,8 +285,8 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 				}
 			}

-			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
-			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */

 			printf (" done\n");
 		}
@ -298,7 +302,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 * 4 - Flash not identified
 */

-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
 	ulong cp, wp;
 	FPW data;
@ -384,7 +388,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 * 1 - write timeout
 * 2 - Flash not erased
 */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
+static int write_data (flash_info_t *info, ulong dest, FPW data)
 {
 	FPWV *addr = (FPWV *) dest;
 	ulong status;
@ -392,7 +396,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)

 	/* Check if Flash is (sufficiently) erased */
 	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */
@ -406,7 +410,6 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)

 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-
 		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
--- a/board/cerf250/memsetup.S
+++ b/board/cerf250/memsetup.S
@ -0,0 +1,411 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/memsetup.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc  p15,0,\reg,c2,c0,0
+   mov  \reg,\reg
+   sub  pc,pc,#4
+   .endm
+
+
+/*
+ * 	Memory setup
+ */
+
+.globl memsetup
+memsetup:
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,  [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=PSSR				/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,	[r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr		r3,	=OSCR			/* reset the OS Timer Count to zero */
+	mov 	r2,	#0
+	str 	r2,	[r3]
+	ldr 	r4,	=0x300				/* really 0x2E1 is about 200usec,   */
+							/* so 0x300 should be plenty        */
+1:
+	ldr 	r2,	[r3]
+	cmp 	r4,	r2
+	bgt 	1b
+
+mem_init:
+
+	ldr  	r1,	=MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+	/* MSC0: nCS(0,1)                                                   */
+	ldr  	r2,	=CFG_MSC0_VAL
+	str  	r2,	[r1, #MSC0_OFFSET]
+	ldr  	r2,	[r1, #MSC0_OFFSET]	/* read back to ensure      */
+						/* that data latches        */
+	/* MSC1: nCS(2,3)                                                   */
+	ldr  	r2,	=CFG_MSC1_VAL
+	str  	r2,	[r1, #MSC1_OFFSET]
+	ldr  	r2,	[r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)                                                   */
+	ldr  	r2,	=CFG_MSC2_VAL
+	str  	r2,	[r1, #MSC2_OFFSET]
+	ldr  	r2,	[r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
+	ldr  	r2,	=CFG_MECR_VAL
+	str  	r2,	[r1, #MECR_OFFSET]
+	ldr	 	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing                             */
+	ldr  	r2,	=CFG_MCMEM0_VAL
+	str  	r2,	[r1, #MCMEM0_OFFSET]
+	ldr	 	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing                             */
+	ldr  	r2,	=CFG_MCMEM1_VAL
+	str  	r2,	[r1, #MCMEM1_OFFSET]
+	ldr	 	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+	ldr  	r2,	=CFG_MCATT0_VAL
+	str  	r2,	[r1, #MCATT0_OFFSET]
+	ldr	 	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+	ldr  	r2, =CFG_MCATT1_VAL
+	str  	r2, [r1, #MCATT1_OFFSET]
+	ldr	 	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+	ldr  	r2, =CFG_MCIO0_VAL
+	str  	r2, [r1, #MCIO0_OFFSET]
+	ldr	 	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+	ldr  	r2, =CFG_MCIO1_VAL
+	str  	r2, [r1, #MCIO1_OFFSET]
+	ldr	 	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+	/* ---------------------------------------------------------------- */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set     */
+	/* this to power on defaults + DRI field, set SDRAM clocks free running */
+
+	ldr  	r3, =CFG_MDREFR_VAL
+	ldr  	r2, =0xFFF
+	and  	r3, r3,  r2
+
+	ldr	 	r0,	[r1, #MDREFR_OFFSET]
+	bic	 	r0, r0, r2
+	bic	 	r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
+	orr	 	r0, r0, r3
+
+	str		r0,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits               */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
+
+	/* FIXME: we use async mode for now                                 */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM                                         */
+	/* ---------------------------------------------------------------- */
+
+	/* set MDREFR according to user define with exception of a few bits */
+
+	ldr     r4, =CFG_MDREFR_VAL
+	ldr		r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
+					MDREFR_K2RUN |MDREFR_K2DB2)
+	and		r4, r4, r2
+	bic		r0,	r0,	r2
+	orr		r0, r0, r4
+
+	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r0, [r1, #MDREFR_OFFSET]
+
+	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
+
+	bic		r0, r0,	#(MDREFR_SLFRSH)
+	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r0, [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE  */
+
+	ldr     r4, =CFG_MDREFR_VAL
+	ldr		r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
+					MDREFR_K1FREE | MDREFR_K2FREE)
+	and		r4, r4, r2
+	orr		r0, r0, r4
+	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r0, [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*          configure but not enable each SDRAM partition pair.     */
+
+	ldr		r4,	=CFG_MDCNFG_VAL
+	bic		r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+	bic		r4, r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+	str     r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
+	ldr     r4, [r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 <20>sec.                                          */
+
+	ldr 	r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov 	r2, #0
+	str 	r2, [r3]
+	ldr 	r4, =0x300			/* really 0x2E1 is about 200usec,   */
+						/* so 0x300 should be plenty        */
+1:
+	ldr 	r2, [r3]
+	cmp 	r4, r2
+	bgt 	1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
+
+	ldr		r3,	=CFG_DRAM_BASE
+.rept 8
+	str		r2,	[r3]
+.endr
+
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/*          (MDCNFG:DEx set to 1).                                  */
+
+	ldr     r3, [r1, #MDCNFG_OFFSET]
+	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
+	str     r3, [r1, #MDCNFG_OFFSET]
+
+	/* Step 4h: Write MDMRS.                                            */
+
+	ldr     r2, =CFG_MDMRS_VAL
+	str     r2, [r1, #MDMRS_OFFSET]
+
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr     r2, =ICLR
+	str     r1, [r2]
+
+	ldr     r2, =ICMR	/* mask all interrupts at the controller    */
+	str     r1, [r2]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
+	ldr     r1, =CKEN
+	mov     r2, #0
+	str     r2, [r1]
+
+
+	/* default value in case no valid rotary switch setting is found    */
+	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
+
+	/* ... and write the core clock config register                     */
+	ldr     r1, =CCCR
+	str     r2, [r1]
+
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+
+	ldr     r1, =OSCC
+	mov     r2, #OSCC_OON
+	str     r2, [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
+60:
+	ldr     r2, [r1]
+	ands    r2, r2, #1
+	beq     60b
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+	/* ---------------------------------------------------------------- */
+
+	/* Save SDRAM size */
+    ldr     r1, =DRAM_SIZE
+	str   	r8, [r1]
+
+	/* Interrupt init: Mask all interrupts                              */
+    ldr		r0,	=ICMR /* enable no sources */
+	mov 	r1,	#0
+    str 	r1,	[r0]
+
+	/* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov		r0,#0
+	mcr		p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr		p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr		p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov		r0,#0x80000000
+	mcr		p14,0,r0,c10,c0,0  /* dcsr */
+
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End memsetup                                                     */
+	/* ---------------------------------------------------------------- */
+
+endmemsetup:
+
+    mov     pc,	lr
--- a/board/cerf250/u-boot.lds
+++ b/board/cerf250/u-boot.lds
@ -21,23 +21,35 @@
 * MA 02111-1307 USA
 */

-/****************************************************************************
- * FLASH Memory Map as used by FADS Monitor:
- *
- *                          Start Address    Length
- * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
- * | MON8xx code           | 0xFE00_0100     Reset Vector
- * +-----------------------+ 0xFE0?_????
- * | (unused)              |
- * +-----------------------+
- * | 			   |
- * +-----------------------+
- * | 			   |
- * +-----------------------+
- * | 			   |
- * +-----------------------+
- * | 			   |
- * +=======================+
- * | 			   |
- * | ...                   |
- *****************************************************************************/
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/cmc_pu2/Makefile
+++ b/board/cmc_pu2/Makefile
@ -0,0 +1,47 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= at91rm9200dk.o at45.o dm9161.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cmc_pu2/at45.c
+++ b/board/cmc_pu2/at45.c
@ -0,0 +1,621 @@
+/* Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
+the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS	(0xC << 16)
+#define DATAFLASH_TCHS	(0x1 << 24)
+
+#define AT91C_TIMEOUT_WRDY			200000
+#define AT91C_SPI_PCS0_SERIAL_DATAFLASH		0xE     /* Chip Select 0 : NPCS0 %1110 */
+#define AT91C_SPI_PCS3_DATAFLASH_CARD		0x7     /* Chip Select 3 : NPCS3 %0111 */
+
+void AT91F_SpiInit(void) {
+
+/*-------------------------------------------------------------------*/
+/*	SPI DataFlash Init								*/
+/*-------------------------------------------------------------------*/
+	/* Configure PIOs */
+	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
+				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
+	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
+				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
+	/* Enable CLock */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
+
+	/* Reset the SPI */
+	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
+
+	/* Configure SPI in Master Mode with No CS selected !!! */
+	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
+
+	/* Configure CS0 and CS3 */
+	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+}
+
+void AT91F_SpiEnable(int cs) {
+	switch(cs) {
+	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
+		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
+		break;
+	case 3:	/* Configure SPI CS3 for Serial DataFlash Card */
+		/* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
+		AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7;	/* Set in PIO mode */
+		AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7;	/* Configure in output */
+		/* Clear Output */
+		AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
+		/* Configure PCS */
+		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+		break;
+	}
+
+	/* SPI_Enable */
+	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+/*----------------------------------------------------------------------------*/
+/* \fn    AT91F_SpiWrite						      */
+/* \brief Set the PDC registers for a transfert				      */
+/*----------------------------------------------------------------------------*/
+unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
+{
+	unsigned int timeout;
+
+	pDesc->state = BUSY;
+
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+
+	/* Initialize the Transmit and Receive Pointer */
+	AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
+	AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
+
+	/* Intialize the Transmit and Receive Counters */
+	AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
+	AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
+
+	if ( pDesc->tx_data_size != 0 ) {
+		/* Initialize the Next Transmit and Next Receive Pointer */
+		AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
+		AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
+
+		/* Intialize the Next Transmit and Next Receive Counters */
+		AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
+		AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
+	}
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+	timeout = 0;
+
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
+	while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+	pDesc->state = IDLE;
+
+	if (timeout >= CFG_SPI_WRITE_TOUT){
+		printf("Error Timeout\n\r");
+		return DATAFLASH_ERROR;
+	}
+
+	return DATAFLASH_OK;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashSendCommand					*/
+/* \brief Generic function to send a command to the dataflash		*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char OpCode,
+	unsigned int CmdSize,
+	unsigned int DataflashAddress)
+{
+    unsigned int adr;
+
+	if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* process the address to obtain page address and byte address */
+	adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
+
+	/* fill the  command  buffer */
+	pDataFlash->pDataFlashDesc->command[0] = OpCode;
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
+		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
+		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
+		pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
+	} else {
+		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
+		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
+		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
+		pDataFlash->pDataFlashDesc->command[4] = 0;
+	}
+	pDataFlash->pDataFlashDesc->command[5] = 0;
+	pDataFlash->pDataFlashDesc->command[6] = 0;
+	pDataFlash->pDataFlashDesc->command[7] = 0;
+
+	/* Initialize the SpiData structure for the spi write fuction */
+	pDataFlash->pDataFlashDesc->tx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->tx_cmd_size =  CmdSize ;
+	pDataFlash->pDataFlashDesc->rx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->rx_cmd_size =  CmdSize ;
+
+	/* send the command and read the data */
+	return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashGetStatus					*/
+/* \brief Read the status register of the dataflash			*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
+{
+	AT91S_DataFlashStatus status;
+
+	/* if a transfert is in progress ==> return 0 */
+	if( (pDesc->state) != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* first send the read status command (D7H) */
+	pDesc->command[0] = DB_STATUS;
+	pDesc->command[1] = 0;
+
+	pDesc->DataFlash_state  = GET_STATUS;
+	pDesc->tx_data_size 	= 0 ;	/* Transmit the command and receive response */
+	pDesc->tx_cmd_pt 		= pDesc->command ;
+	pDesc->rx_cmd_pt 		= pDesc->command ;
+	pDesc->rx_cmd_size 		= 2 ;
+	pDesc->tx_cmd_size 		= 2 ;
+	status = AT91F_SpiWrite (pDesc);
+
+	pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
+
+	return status;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashWaitReady					*/
+/* \brief wait for dataflash ready (bit7 of the status register == 1)	*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
+{
+	pDataFlashDesc->DataFlash_state = IDLE;
+
+	do {
+		AT91F_DataFlashGetStatus(pDataFlashDesc);
+		timeout--;
+	} while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
+
+	if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
+		return DATAFLASH_ERROR;
+
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashContinuousRead 				*/
+/* Object              : Continuous stream Read 				*/
+/* Input Parameters    : DataFlash Service					*/
+/*						: <src> = dataflash address	*/
+/*                     : <*dataBuffer> = data buffer pointer			*/
+/*                     : <sizeToRead> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
+	AT91PS_DataFlash pDataFlash,
+	int src,
+	unsigned char *dataBuffer,
+	int sizeToRead )
+{
+	AT91S_DataFlashStatus status;
+	/* Test the size to read in the device */
+	if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+		return DATAFLASH_MEMORY_OVERFLOW;
+
+	pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+	pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
+	pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+	pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
+
+	status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
+	/* Send the command to the dataflash */
+	return(status);
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashPagePgmBuf				*/
+/* Object              : Main memory page program through buffer 1 or buffer 2	*/
+/* Input Parameters    : DataFlash Service					*/
+/*						: <*src> = Source buffer	*/
+/*                     : <dest> = dataflash destination address			*/
+/*                     : <SizeToWrite> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	unsigned int dest,
+	unsigned int SizeToWrite)
+{
+	int cmdsize;
+	pDataFlash->pDataFlashDesc->tx_data_pt = src ;
+	pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
+	pDataFlash->pDataFlashDesc->rx_data_pt = src;
+	pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+
+	cmdsize = 4;
+	/* Send the command to the dataflash */
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_MainMemoryToBufferTransfert			*/
+/* Object              : Read a page in the SRAM Buffer 1 or 2			*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned int page)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
+		return DATAFLASH_BAD_COMMAND;
+
+	/* no data to transmit or receive */
+	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*----------------------------------------------------------------------------- */
+/* Function Name       : AT91F_DataFlashWriteBuffer				*/
+/* Object              : Write data to the internal sram buffer 1 or 2		*/
+/* Input Parameters    : DataFlash Service					*/
+/*			: <BufferCommand> = command to write buffer1 or buffer2	*/
+/*                     : <*dataBuffer> = data buffer to write			*/
+/*                     : <bufferAddress> = address in the internal buffer	*/
+/*                     : <SizeToWrite> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned char *dataBuffer,
+	unsigned int bufferAddress,
+	int SizeToWrite )
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
+		return DATAFLASH_BAD_COMMAND;
+
+	/* buffer address must be lower than page size */
+	if (bufferAddress > pDataFlash->pDevice->pages_size)
+		return DATAFLASH_BAD_ADDRESS;
+
+	if ( (pDataFlash->pDataFlashDesc->state)  != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* Send first Write Command */
+	pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
+	pDataFlash->pDataFlashDesc->command[1] = 0;
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+	    	pDataFlash->pDataFlashDesc->command[2] = 0;
+	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
+	    	pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
+		cmdsize = 5;
+	} else {
+	    	pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
+	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
+	    	pDataFlash->pDataFlashDesc->command[4] = 0;
+		cmdsize = 4;
+	}
+
+	pDataFlash->pDataFlashDesc->tx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
+	pDataFlash->pDataFlashDesc->rx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
+
+	pDataFlash->pDataFlashDesc->rx_data_pt 	= dataBuffer ;
+	pDataFlash->pDataFlashDesc->tx_data_pt 	= dataBuffer ;
+	pDataFlash->pDataFlashDesc->rx_data_size 	= SizeToWrite ;
+	pDataFlash->pDataFlashDesc->tx_data_size 	= SizeToWrite ;
+
+	return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+}
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_PageErase                                        */
+/* Object              : Erase a page 						*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PageErase(
+	AT91PS_DataFlash pDataFlash,
+	unsigned int page)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	/* no data to transmit or receive */
+    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_BlockErase                                       */
+/* Object              : Erase a Block 						*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_BlockErase(
+	AT91PS_DataFlash pDataFlash,
+	unsigned int block)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	/* no data to transmit or receive */
+    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
+}
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_WriteBufferToMain				*/
+/* Object              : Write buffer to the main memory			*/
+/* Input Parameters    : DataFlash Service					*/
+/*		: <BufferCommand> = command to send to buffer1 or buffer2	*/
+/*                     : <dest> = main memory address				*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_WriteBufferToMain (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned int dest )
+{
+	int cmdsize;
+	/* Test if the buffer command is correct */
+	if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
+	    (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
+	    (BufferCommand != DB_BUF2_PAGE_PGM) &&
+	    (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
+		return DATAFLASH_BAD_COMMAND;
+
+	/* no data to transmit or receive */
+	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	/* Send the command to the dataflash */
+	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_PartialPageWrite					*/
+/* Object              : Erase partielly a page					*/
+/* Input Parameters    : <page> = page number					*/
+/*			: <AdrInpage> = adr to begin the fading			*/
+/*                     : <length> = Number of bytes to erase			*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PartialPageWrite (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	unsigned int dest,
+	unsigned int size)
+{
+	unsigned int page;
+	unsigned int AdrInPage;
+
+	page = dest / (pDataFlash->pDevice->pages_size);
+	AdrInPage = dest % (pDataFlash->pDevice->pages_size);
+
+	/* Read the contents of the page in the Sram Buffer */
+	AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
+	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	/*Update the SRAM buffer */
+	AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
+
+	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+	/* Erase page if a 128 Mbits device */
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+		AT91F_PageErase(pDataFlash, page);
+		/* Rewrite the modified Sram Buffer in the main memory */
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	}
+
+	/* Rewrite the modified Sram Buffer in the main memory */
+	return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashWrite					*/
+/* Object              :							*/
+/* Input Parameters    : <*src> = Source buffer					*/
+/*                     : <dest> = dataflash adress				*/
+/*                     : <size> = data buffer size				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWrite(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	int dest,
+	int size )
+{
+	unsigned int length;
+	unsigned int page;
+	unsigned int status;
+
+	AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+	if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+		return DATAFLASH_MEMORY_OVERFLOW;
+
+	/* If destination does not fit a page start address */
+	if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size)))  != 0 ) {
+		length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
+
+		if (size < length)
+			length = size;
+
+		if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		/* Update size, source and destination pointers */
+		size -= length;
+		dest += length;
+		src += length;
+	}
+
+	while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+		/* program dataflash page */
+		page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
+
+		status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		status = AT91F_PageErase(pDataFlash, page);
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+		if (!status)
+			return DATAFLASH_ERROR;
+
+		status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
+		if(!status)
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		/* Update size, source and destination pointers */
+		size -= pDataFlash->pDevice->pages_size ;
+		dest += pDataFlash->pDevice->pages_size ;
+		src  += pDataFlash->pDevice->pages_size ;
+	}
+
+	/* If still some bytes to read */
+	if ( size > 0 ) {
+		/* program dataflash page */
+		if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	}
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashRead 					*/
+/* Object              : Read a block in dataflash				*/
+/* Input Parameters    : 							*/
+/* Return value		: 							*/
+/*------------------------------------------------------------------------------*/
+int AT91F_DataFlashRead(
+	AT91PS_DataFlash pDataFlash,
+	unsigned long addr,
+	unsigned long size,
+	char *buffer)
+{
+	unsigned long SizeToRead;
+
+	AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+	if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+		return -1;
+
+	while (size) {
+		SizeToRead = (size < 0x8000)? size:0x8000;
+
+		if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+			return -1;
+
+		if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
+			return -1;
+
+		size -= SizeToRead;
+		addr += SizeToRead;
+		buffer += SizeToRead;
+	}
+
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataflashProbe 					*/
+/* Object              : 							*/
+/* Input Parameters    : 							*/
+/* Return value	       : Dataflash status register				*/
+/*------------------------------------------------------------------------------*/
+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
+{
+	AT91F_SpiEnable(cs);
+	AT91F_DataFlashGetStatus(pDesc);
+	return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+}
+
+#endif
--- a/board/cmc_pu2/at91rm9200dk.c
+++ b/board/cmc_pu2/at91rm9200dk.c
@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* Correct IRDA resistor problem */
+	/* Set PA23_TXD in Output */
+	(AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of AT91RM9200DK-Board */
+	gd->bd->bi_arch_number = 251;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+/*
+ * Disk On Chip (NAND) Millenium initialization.
+ * The NAND lives in the CS2* space
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern ulong nand_probe (ulong physadr);
+
+#define AT91_SMARTMEDIA_BASE 0x40000000	/* physical address to access memory on NCS3 */
+void nand_init (void)
+{
+	/* Setup Smart Media, fitst enable the address range of CS3 */
+	*AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
+	/* set the bus interface characteristics based on
+	   tDS Data Set up Time 30 - ns
+	   tDH Data Hold Time 20 - ns
+	   tALS ALE Set up Time 20 - ns
+	   16ns at 60 MHz ~= 3  */
+/*memory mapping structures */
+#define SM_ID_RWH	(5 << 28)
+#define SM_RWH		(1 << 28)
+#define SM_RWS		(0 << 24)
+#define SM_TDF		(1 << 8)
+#define SM_NWS		(3)
+	AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
+		AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
+		SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
+
+	/* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
+	*AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
+		AT91C_PC3_BFBAA_SMWE;
+	*AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
+		AT91C_PC3_BFBAA_SMWE;
+
+	/* Configure PC2 as input (signal READY of the SmartMedia) */
+	*AT91C_PIOC_PER = AT91C_PC2_BFAVD;	/* enable direct output enable */
+	*AT91C_PIOC_ODR = AT91C_PC2_BFAVD;	/* disable output */
+
+	/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
+	*AT91C_PIOB_PER = AT91C_PIO_PB1;	/* enable direct output enable */
+	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */
+
+	/* PIOB and PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
+	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
+		printf ("  No SmartMedia card inserted\n");
+#ifdef DEBUG
+	printf ("  SmartMedia card inserted\n");
+
+	printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
+#endif
+	printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
+}
+#endif
--- a/board/cmc_pu2/config.mk
+++ b/board/cmc_pu2/config.mk
@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000
--- a/board/cmc_pu2/dm9161.c
+++ b/board/cmc_pu2/dm9161.c
@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <dm9161.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ *	dm9161_IsPhyConnected
+ * Description:
+ *	Reads the 2 PHY ID registers
+ * Arguments:
+ *	p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ *	TRUE - if id read successfully
+ *	FALSE- if error
+ */
+static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+	unsigned short Id1, Id2;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
+		((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
+		return TRUE;
+
+	return FALSE;
+}
+
+/*
+ * Name:
+ *	dm9161_GetLinkSpeed
+ * Description:
+ *	Link parallel detection status of MAC is checked and set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to MAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+	unsigned short stat1, stat2;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
+		return FALSE;
+
+	if (!(stat1 & DM9161_LINK_STATUS))	/* link status up? */
+		return FALSE;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
+		return FALSE;
+
+	if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
+		/*set Emac for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
+		/*set MII for 100BaseTX and Half Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_SPD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
+		/*set MII for 10BaseT and Half Duplex  */
+		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+		return TRUE;
+	}
+	return FALSE;
+}
+
+
+/*
+ * Name:
+ *	dm9161_InitPhy
+ * Description:
+ *	MAC starts checking its link by using parallel detection and
+ *	Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
+{
+	UCHAR ret = TRUE;
+	unsigned short IntValue;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+
+	if (!dm9161_GetLinkSpeed (p_mac)) {
+		/* Try another time */
+		ret = dm9161_GetLinkSpeed (p_mac);
+	}
+
+	/* Disable PHY Interrupts */
+	at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
+	/* clear FDX, SPD, Link, INTR masks */
+	IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
+		      DM9161_LINK_MASK | DM9161_INTR_MASK);
+	at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	return (ret);
+}
+
+
+/*
+ * Name:
+ *	dm9161_AutoNegotiate
+ * Description:
+ *	MAC Autonegotiates with the partner status of same is set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	dev - pointer to struct net_device
+ * Return value:
+ *	TRUE - if link status set successfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+	unsigned short value;
+	unsigned short PhyAnar;
+	unsigned short PhyAnalpar;
+
+	/* Set dm9161 control register */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+	value &= ~DM9161_AUTONEG;	/* remove autonegotiation enable */
+	value |= DM9161_ISOLATE;	/* Electrically isolate PHY */
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	/* Set the Auto_negotiation Advertisement Register */
+	/* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
+	PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
+		  DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
+		return FALSE;
+
+	/* Read the Control Register     */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+	/* Restart Auto_negotiation  */
+	value |= DM9161_RESTART_AUTONEG;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	/*check AutoNegotiate complete */
+	udelay (10000);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
+	if (!(value & DM9161_AUTONEG_COMP))
+		return FALSE;
+
+	/* Get the AutoNeg Link partner base page */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
+		return FALSE;
+
+	if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
+		/*set MII for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+	return FALSE;
+}
+
+
+/*
+ * Name:
+ *	at91rm92000_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+
+#endif	/* CONFIG_DRIVER_ETHER */
--- a/board/cmc_pu2/flash.c
+++ b/board/cmc_pu2/flash.c
@ -0,0 +1,507 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush(void);
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef
+{
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgAT49BV16x4[] =
+{
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{  2, 32*1024 },	/*   2 * 32 kBytes sectors */
+	{ 30, 64*1024 },	/*  30 * 64 kBytes sectors */
+};
+
+OrgDef OrgAT49BV16x4A[] =
+{
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 31, 64*1024 },	/*  31 * 64 kBytes sectors */
+};
+
+OrgDef OrgAT49BV6416[] =
+{
+	{   8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 127, 64*1024 },	/* 127 * 64 kBytes sectors */
+};
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+/* AT49BV1614A Codes */
+#define FLASH_CODE1		0xAA
+#define FLASH_CODE2		0x55
+#define ID_IN_CODE		0x90
+#define ID_OUT_CODE		0xF0
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+#define CMD_SECTOR_UNLOCK	0x0070
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000 /* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+void flash_identification (flash_info_t * info)
+{
+	volatile u16 manuf_code, device_code, add_device_code;
+
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_IN_CODE;
+
+	manuf_code = *(volatile u16 *) CFG_FLASH_BASE;
+	device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2);
+	add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1));
+
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_OUT_CODE;
+
+	/* Vendor type */
+	info->flash_id = ATM_MANUFACT & FLASH_VENDMASK;
+	printf ("Atmel: ");
+
+	if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) {
+
+		if ((add_device_code & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614A & FLASH_TYPEMASK)) {
+			info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK;
+			printf ("AT49BV1614A (16Mbit)\n");
+		} else {				/* AT49BV1614 Flash */
+			info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
+			printf ("AT49BV1614 (16Mbit)\n");
+		}
+
+	} else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) {
+		info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK;
+		printf ("AT49BV6416 (64Mbit)\n");
+	}
+}
+
+ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks)
+{
+	int i, nb_sectors = 0;
+
+	for (i=0; i<nb_blocks; i++){
+		nb_sectors += pOrgDef[i].sector_number;
+	}
+
+	return nb_sectors;
+}
+
+void flash_unlock_sector(flash_info_t * info, unsigned int sector)
+{
+	volatile u16 *addr = (volatile u16 *) (info->start[sector]);
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	*addr = CMD_SECTOR_UNLOCK;
+}
+
+
+ulong flash_init (void)
+{
+	int i, j, k;
+	unsigned int flash_nb_blocks, sector;
+	unsigned int start_address;
+	OrgDef *pOrgDef;
+
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_identification (&flash_info[i]);
+
+		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614 & FLASH_TYPEMASK)) {
+
+			pOrgDef = OrgAT49BV16x4;
+			flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614A & FLASH_TYPEMASK)){	/* AT49BV1614A Flash */
+
+			pOrgDef = OrgAT49BV16x4A;
+			flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			pOrgDef = OrgAT49BV6416;
+			flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef);
+		} else {
+			flash_nb_blocks = 0;
+			pOrgDef = OrgAT49BV16x4;
+		}
+
+		flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks);
+		memset (flash_info[i].protect, 0, flash_info[i].sector_count);
+
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+
+		sector = 0;
+		start_address = flashbase;
+		flash_info[i].size = 0;
+
+		for (j = 0; j < flash_nb_blocks; j++) {
+			for (k = 0; k < pOrgDef[j].sector_number; k++) {
+				flash_info[i].start[sector++] = start_address;
+				start_address += pOrgDef[j].sector_size;
+				flash_info[i].size += pOrgDef[j].sector_size;
+			}
+		}
+
+		size += flash_info[i].size;
+
+		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			/* Unlock all sectors at reset */
+			for (j=0; j<flash_info[i].sector_count; j++){
+				flash_unlock_sector(&flash_info[i], j);
+			}
+		}
+	}
+
+	/* Protect binary boot image */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + CFG_BOOT_SIZE - 1, &flash_info[0]);
+
+	/* Protect environment variables */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	/* Protect U-Boot gzipped image */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_U_BOOT_BASE,
+		       CFG_U_BOOT_BASE + CFG_U_BOOT_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (ATM_MANUFACT & FLASH_VENDMASK):
+		printf ("Atmel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (ATM_ID_BV1614 & FLASH_TYPEMASK):
+		printf ("AT49BV1614 (16Mbit)\n");
+		break;
+	case (ATM_ID_BV1614A & FLASH_TYPEMASK):
+		printf ("AT49BV1614A (16Mbit)\n");
+		break;
+	case (ATM_ID_BV6416 & FLASH_TYPEMASK):
+		printf ("AT49BV6416 (64Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(ATM_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr = (volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {			/* it was protected */
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word (flash_info_t * info, ulong dest,
+								ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	};
+
+	if ((int) src & 1) {
+		printf ("unaligned source not supported\n");
+		return ERR_ALIGN;
+	};
+
+	wp = addr;
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) <<
+										   8);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	};
+
+	return ERR_OK;
+}
--- a/board/cmc_pu2/memsetup.S
+++ b/board/cmc_pu2/memsetup.S
@ -0,0 +1,200 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifdef CONFIG_BOOTBINFUNC
+/*
+ * some parameters for the board
+ *
+ * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
+ * turn is based on the boot.bin code from ATMMEL
+ *
+ */
+
+/* flash */
+#define MC_PUIA 0xFFFFFF10
+#define MC_PUIA_VAL 0x00000000
+#define MC_PUP 0xFFFFFF50
+#define MC_PUP_VAL 0x00000000
+#define MC_PUER 0xFFFFFF54
+#define MC_PUER_VAL 0x00000000
+#define MC_ASR 0xFFFFFF04
+#define MC_ASR_VAL 0x00000000
+#define MC_AASR 0xFFFFFF08
+#define MC_AASR_VAL 0x00000000
+#define EBI_CFGR 0xFFFFFF64
+#define EBI_CFGR_VAL 0x00000000
+#define SMC2_CSR 0xFFFFFF70
+#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR 0xFFFFFC28
+#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
+#define PLLBR 0xFFFFFC2C
+#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR 0xFFFFFC30
+#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR 0xFFFFF870
+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR 0xFFFFF804
+#define PIOC_BSR_VAL 0x00000000
+#define PIOC_PDR 0xFFFFF804
+#define PIOC_PDR_VAL 0xFFFF0000
+#define EBI_CSA 0xFFFFFF60
+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define SDRC_CR 0xFFFFFF98
+#define SDRC_CR_VAL 0x2188c155
+#define SDRAM 0x20000000 /* address of the SDRAM */
+#define SDRAM1 0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define SDRC_MR 0xFFFFFF90
+#define SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1 0x00000004 /* refresh */
+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define SDRC_TR 0xFFFFFF94
+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl memsetup
+memsetup:
+	/* memory control configuration */
+	/* this isn't very elegant, but	 what the heck */
+	ldr	r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #80
+0:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	0b
+	/* delay - this is all done by guess */
+	ldr	r0, =0x00001000
+1:
+	subs	r0, r0, #1
+	bhi	1b
+	ldr	r0, =SMRDATA1
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #176
+2:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	2b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word MC_PUIA
+	.word MC_PUIA_VAL
+	.word MC_PUP
+	.word MC_PUP_VAL
+	.word MC_PUER
+	.word MC_PUER_VAL
+	.word MC_ASR
+	.word MC_ASR_VAL
+	.word MC_AASR
+	.word MC_AASR_VAL
+	.word EBI_CFGR
+	.word EBI_CFGR_VAL
+	.word SMC2_CSR
+	.word SMC2_CSR_VAL
+	.word PLLAR
+	.word PLLAR_VAL
+	.word PLLBR
+	.word PLLBR_VAL
+	.word MCKR
+	.word MCKR_VAL
+	/* SMRDATA is 80 bytes long */
+	/* here there's a delay of 100 */
+SMRDATA1:
+	.word PIOC_ASR
+	.word PIOC_ASR_VAL
+	.word PIOC_BSR
+	.word PIOC_BSR_VAL
+	.word PIOC_PDR
+	.word PIOC_PDR_VAL
+	.word EBI_CSA
+	.word EBI_CSA_VAL
+	.word SDRC_CR
+	.word SDRC_CR_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL1
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL2
+	.word SDRAM1
+	.word SDRAM_VAL
+	.word SDRC_TR
+	.word SDRC_TR_VAL
+	.word SDRAM
+	.word SDRAM_VAL
+	.word SDRC_MR
+	.word SDRC_MR_VAL3
+	.word SDRAM
+	.word SDRAM_VAL
+	/* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_BOOTBINFUNC */
--- a/board/cmc_pu2/u-boot.lds
+++ b/board/cmc_pu2/u-boot.lds
@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/at91rm9200/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/cogent/mb.h
+++ b/board/cogent/mb.h
@ -54,7 +54,7 @@
 * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
 * will be at byte 7 (the address + 7). For little endian addressing, the
 * register will be at byte 0 (the address + 0). To learn the endianess
- * we must include <asm/byteorder.h>
+ * we must include <endian.h>
 *
 * Take the CMA102 and CMA111 motherboards as examples...
 *
@ -230,16 +230,20 @@

 #ifndef __ASSEMBLY__

-#include <asm/byteorder.h>
+#ifdef USE_HOSTCC
+#include <endian.h>		/* avoid using private kernel header files */
+#else
+#include <asm/byteorder.h>	/* use U-Boot provided headers */
+#endif

 /* a single CMA10x motherboard i/o register */
 typedef
    struct {
-#if defined(__LITTLE_ENDIAN)
+#if __BYTE_ORDER == __LITTLE_ENDIAN
 	unsigned char value;
 #endif
 	unsigned char filler[7];
-#if defined(__BIG_ENDIAN)
+#if __BYTE_ORDER == __BIG_ENDIAN
 	unsigned char value;
 #endif
    }
@ -357,7 +361,7 @@ cma_mb_dipsw;
 /* V360EPC PCI Bridge */
 typedef
    struct {
-#if defined(__LITTLE_ENDIAN)
+#if __BYTE_ORDER == __LITTLE_ENDIAN
 	unsigned short v3_pci_vendor;		/* 0x00 */
 	unsigned short v3_pci_device;
 	unsigned short v3_pci_cmd;		/* 0x04 */
@ -436,7 +440,7 @@ typedef
 	unsigned long  reserved8:24;
 	unsigned long  reserved9[7];		/* 0xe4 */
 #endif
-#if defined(__BIG_ENDIAN)
+#if __BYTE_ORDER == __BIG_ENDIAN
 	unsigned short v3_pci_device;		/* 0x00 */
 	unsigned short v3_pci_vendor;
 	unsigned short v3_pci_stat;		/* 0x04 */
--- a/board/cpc45/cpc45.c
+++ b/board/cpc45/cpc45.c
@ -25,6 +25,7 @@
 #include <mpc824x.h>
 #include <asm/processor.h>
 #include <pci.h>
+#include <i2c.h>

 int sysControlDisplay(int digit, uchar ascii_code);
 extern void Plx9030Init(void);
@ -49,7 +50,7 @@ int checkboard(void)
 	ulong busfreq  = get_bus_freq(0);
 	char  buf[32];

-	printf("CPC45 ");
+	puts ("CPC45  ");
 /*
 	printf("Revision %d ", revision);
 */
@ -58,46 +59,134 @@ int checkboard(void)
 	return 0;
 }

-long int initdram(int board_type)
+long int initdram (int board_type)
 {
-	long size;
-	long new_bank0_end;
-	long mear1;
-	long emear1;
+	int m, row, col, bank, i, ref;
+	unsigned long start, end;
+	uint32_t mccr1, mccr2;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
+	unsigned int tmp;

-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);

-	new_bank0_end = size - 1;
-	mear1 = mpc824x_mpc107_getreg(MEAR1);
-	emear1 = mpc824x_mpc107_getreg(EMEAR1);
-	mear1 = (mear1  & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
-	emear1 = (emear1 & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-	mpc824x_mpc107_setreg(MEAR1, mear1);
-	mpc824x_mpc107_setreg(EMEAR1, emear1);
+	if (i2c_reg_read (0x50, 2) != 0x04)
+		return 0;	/* Memory type */

-	return (size);
+	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
+	row = i2c_reg_read (0x50, 3);	/* # of rows */
+	col = i2c_reg_read (0x50, 4);	/* # of columns */
+	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
+	ref  = i2c_reg_read (0x50, 12);	/* refresh rate / type */
+
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	CONFIG_READ_WORD(MCCR2, mccr2);
+	mccr2 &= 0xffff0000;
+
+	start = CFG_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	switch(ref) {
+		case 0x00:
+		case 0x80:
+			tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
+			break;
+		case 0x01:
+		case 0x81:
+			tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
+			break;
+		case 0x02:
+		case 0x82:
+			tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
+			break;
+		case 0x03:
+		case 0x83:
+			tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
+			break;
+		case 0x04:
+		case 0x84:
+			tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
+			break;
+		case 0x05:
+		case 0x85:
+			tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
+			break;
+		default:
+			tmp = 0x512;
+			break;
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
 }

+
 /*
 * Initialize PCI Devices, report devices found.
 */
-#ifndef CONFIG_PCI_PNP

-static struct pci_config_table pci_sandpoint_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+static struct pci_config_table pci_cpc45_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
 	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 				       PCI_ENET0_MEMADDR,
 				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
+				       PCI_PLX9030_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+#endif /*CONFIG_PCI_PNP*/
 	{ }
 };
-#endif
-

 struct pci_controller hose = {
 #ifndef CONFIG_PCI_PNP
-	config_table: pci_sandpoint_config_table,
+	config_table: pci_cpc45_config_table,
 #endif
 };

@ -108,6 +197,9 @@ void pci_init_board(void)
 	/* init PCI_to_LOCAL Bus BRIDGE */
 	Plx9030Init();

+	/* Clear Display */
+	DISP_CWORD = 0x0;
+
 	sysControlDisplay(0,' ');
 	sysControlDisplay(1,'C');
 	sysControlDisplay(2,'P');
@ -130,16 +222,14 @@ void pci_init_board(void)
 * RETURNS: NA
 */

-int sysControlDisplay
-    (
-    int digit, 			/* number of digit 0..7 */
-    uchar ascii_code		/* ASCII code */
-    )
+int sysControlDisplay (int digit,	/* number of digit 0..7 */
+		       uchar ascii_code	/* ASCII code */
+		      )
 {
 	if ((digit < 0) || (digit > 7))
 		return (-1);

-	*((volatile uchar*)(DISP_CHR_RAM + digit)) = ascii_code;
+	*((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;

 	return (0);
 }
--- a/board/cpc45/flash.c
+++ b/board/cpc45/flash.c
@ -41,12 +41,12 @@
 #define MAIN_SECT_SIZE  0x40000
 #define PARAM_SECT_SIZE 0x8000

-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];

-static int write_data (flash_info_t *info, ulong dest, ulong *data);
-static void write_via_fpu(vu_long *addr, ulong *data);
-static __inline__ unsigned long get_msr(void);
-static __inline__ void set_msr(unsigned long msr);
+static int write_data (flash_info_t * info, ulong dest, ulong * data);
+static void write_via_fpu (vu_long * addr, ulong * data);
+static __inline__ unsigned long get_msr (void);
+static __inline__ void set_msr (unsigned long msr);

 /*---------------------------------------------------------------------*/
 #undef	DEBUG_FLASH
@ -62,102 +62,132 @@ static __inline__ void set_msr(unsigned long msr);
 /*-----------------------------------------------------------------------
 */

-unsigned long flash_init(void)
+unsigned long flash_init (void)
 {
-    int i, j;
-    ulong size = 0;
-    uchar tempChar;
+	int i, j;
+	ulong size = 0;
+	uchar tempChar;
+	vu_long *tmpaddr;

-   /* Enable flash writes on CPC45 */
+	/* Enable flash writes on CPC45 */

-    tempChar = BOARD_CTRL;
+	tempChar = BOARD_CTRL;

-    tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
+	tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);

-    tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
+	tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);

-    BOARD_CTRL = tempChar;
+	BOARD_CTRL = tempChar;
+
+	__asm__ volatile ("sync\n eieio");
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+		addr[0] = 0x00900090;
+
+		__asm__ volatile ("sync\n eieio");
+
+		udelay (100);
+
+		DEBUGF ("Flash bank # %d:\n"
+			"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+			"\tDevice ID @ 0x%08lX: 0x%08lX\n",
+			i,
+			(ulong) (&addr[0]), addr[0],
+			(ulong) (&addr[2]), addr[2]);


-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-	vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+		if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
+		    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {

-	addr[0] = 0x00900090;
+			flash_info[i].flash_id =
+				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				(INTEL_ID_28F160F3T & FLASH_TYPEMASK);

-	DEBUGF ("Flash bank # %d:\n"
-		"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
-		"\tDevice ID @ 0x%08lX: 0x%08lX\n",
-		i,
-		(ulong)(&addr[0]), addr[0],
-		(ulong)(&addr[2]), addr[2]);
+		} else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
+			 && (addr[2] == addr[3])
+			 && (addr[2] == INTEL_ID_28F160C3T)) {

+			flash_info[i].flash_id =
+				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				(INTEL_ID_28F160C3T & FLASH_TYPEMASK);

-	if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
-	    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T))
-	{
-
-	    flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
-				     (INTEL_ID_28F160F3T & FLASH_TYPEMASK);
-
-	} else {
-	    flash_info[i].flash_id = FLASH_UNKNOWN;
-	    addr[0] = 0xFFFFFFFF;
-	    goto Done;
-	}
-
-	DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
-
-	addr[0] = 0xFFFFFFFF;
-
-	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
-	for (j = 0; j < flash_info[i].sector_count; j++) {
-		if (j > 30) {
-			flash_info[i].start[j] = CFG_FLASH_BASE +
-						 i * FLASH_BANK_SIZE +
-						 (MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE;
 		} else {
-			flash_info[i].start[j] = CFG_FLASH_BASE +
-						 i * FLASH_BANK_SIZE +
-						 j * MAIN_SECT_SIZE;
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			addr[0] = 0xFFFFFFFF;
+			goto Done;
 		}
-	}
-	size += flash_info[i].size;
-    }

-    /* Protect monitor and environment sectors
-     */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+		addr[0] = 0xFFFFFFFF;
+
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j > 30) {
+				flash_info[i].start[j] = CFG_FLASH_BASE +
+					i * FLASH_BANK_SIZE +
+					(MAIN_SECT_SIZE * 31) + (j -
+								 31) *
+					PARAM_SECT_SIZE;
+			} else {
+				flash_info[i].start[j] = CFG_FLASH_BASE +
+					i * FLASH_BANK_SIZE +
+					j * MAIN_SECT_SIZE;
+			}
+		}
+
+		/* unlock sectors, if 160C3T */
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			tmpaddr = (vu_long *) flash_info[i].start[j];
+
+			if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			    (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
+				tmpaddr[0] = 0x00600060;
+				tmpaddr[0] = 0x00D000D0;
+				tmpaddr[1] = 0x00600060;
+				tmpaddr[1] = 0x00D000D0;
+			}
+		}
+
+		size += flash_info[i].size;
+
+		addr[0] = 0x00FF00FF;
+		addr[1] = 0x00FF00FF;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_MONITOR_BASE,
-	      CFG_MONITOR_BASE + monitor_flash_len - 1,
-	      &flash_info[1]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[1]);
 #else
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_MONITOR_BASE,
-	      CFG_MONITOR_BASE + monitor_flash_len - 1,
-	      &flash_info[0]);
-#endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
 #endif

 #if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
 #if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_ENV_ADDR,
-	      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-	      &flash_info[1]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
 #else
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_ENV_ADDR,
-	      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-	      &flash_info[0]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
 #endif
 #endif

 Done:
-    return size;
+	return size;
 }

 /*-----------------------------------------------------------------------
@ -179,6 +209,11 @@ void flash_print_info (flash_info_t * info)
 	case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
 		printf ("28F160F3T (16Mbit)\n");
 		break;
+
+	case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
+		printf ("28F160C3T (16Mbit)\n");
+		break;
+
 	default:
 		printf ("Unknown Chip Type 0x%04x\n", i);
 		goto Done;
@ -186,7 +221,7 @@ void flash_print_info (flash_info_t * info)
 	}

 	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
+		info->size >> 20, info->sector_count);

 	printf ("  Sector Start Addresses:");
 	for (i = 0; i < info->sector_count; i++) {
@ -194,7 +229,7 @@ void flash_print_info (flash_info_t * info)
 			printf ("\n   ");
 		}
 		printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
+			info->protect[i] ? " (RO)" : "     ");
 	}
 	printf ("\n");

@ -205,7 +240,7 @@ Done:
 /*-----------------------------------------------------------------------
 */

-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
 	int flag, prot, sect;
 	ulong start, now, last;
@ -229,33 +264,32 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	}

 	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
+	for (sect = s_first; sect <= s_last; ++sect) {
 		if (info->protect[sect]) {
 			prot++;
 		}
 	}

 	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
 	} else {
 		printf ("\n");
 	}

 	start = get_timer (0);
-	last  = start;
+	last = start;
 	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
+	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			vu_long *addr = (vu_long *)(info->start[sect]);
+			vu_long *addr = (vu_long *) (info->start[sect]);

 			DEBUGF ("Erase sect %d @ 0x%08lX\n",
-				sect, (ulong)addr);
+				sect, (ulong) addr);

 			/* Disable interrupts which might cause a timeout
 			 * here.
 			 */
-			flag = disable_interrupts();
+			flag = disable_interrupts ();

 			addr[0] = 0x00500050;	/* clear status register */
 			addr[0] = 0x00200020;	/* erase setup */
@ -267,23 +301,23 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)

 			/* re-enable interrupts if necessary */
 			if (flag)
-				enable_interrupts();
+				enable_interrupts ();

 			/* wait at least 80us - let's wait 1 ms */
 			udelay (1000);

 			while (((addr[0] & 0x00800080) != 0x00800080) ||
-			       ((addr[1] & 0x00800080) != 0x00800080) ) {
-				if ((now=get_timer(start)) >
-					   CFG_FLASH_ERASE_TOUT) {
+			       ((addr[1] & 0x00800080) != 0x00800080)) {
+				if ((now = get_timer (start)) >
+				    CFG_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
-					addr[0] = 0x00B000B0; /* suspend erase */
-					addr[0] = 0x00FF00FF; /* to read mode  */
+					addr[0] = 0x00B000B0;	/* suspend erase */
+					addr[0] = 0x00FF00FF;	/* to read mode  */
 					return 1;
 				}

 				/* show that we're waiting */
-				if ((now - last) > 1000) {  /* every second  */
+				if ((now - last) > 1000) {	/* every second  */
 					putc ('.');
 					last = now;
 				}
@ -306,7 +340,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)

 #define	FLASH_WIDTH	8	/* flash bus width in bytes */

-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	ulong wp, cp, msr;
 	int l, rc, i;
@ -315,16 +349,16 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	ulong *datal = &data[1];

 	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
-		addr, (ulong)src, cnt);
+		addr, (ulong) src, cnt);

 	if (info->flash_id == FLASH_UNKNOWN) {
 		return 4;
 	}

-	msr = get_msr();
-	set_msr(msr | MSR_FP);
+	msr = get_msr ();
+	set_msr (msr | MSR_FP);

-	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower aligned address */
+	wp = (addr & ~(FLASH_WIDTH - 1));	/* get lower aligned address */

 	/*
 	 * handle unaligned start bytes
@ -335,39 +369,35 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 		for (i = 0, cp = wp; i < l; i++, cp++) {
 			if (i >= 4) {
 				*datah = (*datah << 8) |
-						((*datal & 0xFF000000) >> 24);
+					((*datal & 0xFF000000) >> 24);
 			}

-			*datal = (*datal << 8) | (*(uchar *)cp);
+			*datal = (*datal << 8) | (*(uchar *) cp);
 		}
 		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
-			char tmp;
-
-			tmp = *src;
-
-			src++;
+			char tmp = *src++;

 			if (i >= 4) {
 				*datah = (*datah << 8) |
-						((*datal & 0xFF000000) >> 24);
+					((*datal & 0xFF000000) >> 24);
 			}

 			*datal = (*datal << 8) | tmp;
-
-			--cnt; ++cp;
+			--cnt;
+			++cp;
 		}

 		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
 			if (i >= 4) {
 				*datah = (*datah << 8) |
-						((*datal & 0xFF000000) >> 24);
+					((*datal & 0xFF000000) >> 24);
 			}

-			*datal = (*datah << 8) | (*(uchar *)cp);
+			*datal = (*datah << 8) | (*(uchar *) cp);
 		}

-		if ((rc = write_data(info, wp, data)) != 0) {
-			set_msr(msr);
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
 			return (rc);
 		}

@ -378,19 +408,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle FLASH_WIDTH aligned part
 	 */
 	while (cnt >= FLASH_WIDTH) {
-		*datah = *(ulong *)src;
-		*datal = *(ulong *)(src + 4);
-		if ((rc = write_data(info, wp, data)) != 0) {
-			set_msr(msr);
+		*datah = *(ulong *) src;
+		*datal = *(ulong *) (src + 4);
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
 			return (rc);
 		}
-		wp  += FLASH_WIDTH;
+		wp += FLASH_WIDTH;
 		cnt -= FLASH_WIDTH;
 		src += FLASH_WIDTH;
 	}

 	if (cnt == 0) {
-		set_msr(msr);
+		set_msr (msr);
 		return (0);
 	}

@ -399,31 +429,28 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	*datah = *datal = 0;
 	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
-		char tmp;
-
-		tmp = *src;
-
-		src++;
+		char tmp = *src++;

 		if (i >= 4) {
-			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+						  24);
 		}

 		*datal = (*datal << 8) | tmp;
-
 		--cnt;
 	}

 	for (; i < FLASH_WIDTH; ++i, ++cp) {
 		if (i >= 4) {
-			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+						  24);
 		}

-		*datal = (*datal << 8) | (*(uchar *)cp);
+		*datal = (*datal << 8) | (*(uchar *) cp);
 	}

-	rc = write_data(info, wp, data);
-	set_msr(msr);
+	rc = write_data (info, wp, data);
+	set_msr (msr);

 	return (rc);
 }
@ -434,32 +461,32 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 * 1 - write timeout
 * 2 - Flash not erased
 */
-static int write_data (flash_info_t *info, ulong dest, ulong *data)
+static int write_data (flash_info_t * info, ulong dest, ulong * data)
 {
-	vu_long *addr = (vu_long *)dest;
+	vu_long *addr = (vu_long *) dest;
 	ulong start;
 	int flag;

 	/* Check if Flash is (sufficiently) erased */
 	if (((addr[0] & data[0]) != data[0]) ||
-	    ((addr[1] & data[1]) != data[1]) ) {
+	    ((addr[1] & data[1]) != data[1])) {
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();

-	addr[0] = 0x00400040;		/* write setup */
-	write_via_fpu(addr, data);
+	addr[0] = 0x00400040;	/* write setup */
+	write_via_fpu (addr, data);

 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();

 	start = get_timer (0);

 	while (((addr[0] & 0x00800080) != 0x00800080) ||
-	       ((addr[1] & 0x00800080) != 0x00800080) ) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	       ((addr[1] & 0x00800080) != 0x00800080)) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
 			addr[0] = 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
@ -472,22 +499,24 @@ static int write_data (flash_info_t *info, ulong dest, ulong *data)

 /*-----------------------------------------------------------------------
 */
-static void write_via_fpu(vu_long *addr, ulong *data)
+static void write_via_fpu (vu_long * addr, ulong * data)
 {
-	__asm__ __volatile__ ("lfd  1, 0(%0)" : : "r" (data));
-	__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
+	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
 }
+
 /*-----------------------------------------------------------------------
 */
-static __inline__ unsigned long get_msr(void)
+static __inline__ unsigned long get_msr (void)
 {
-    unsigned long msr;
+	unsigned long msr;

-    __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
-    return msr;
+	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+	return msr;
 }

-static __inline__ void set_msr(unsigned long msr)
+static __inline__ void set_msr (unsigned long msr)
 {
-    __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
 }
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@ -186,7 +186,7 @@ board_init (void)
 	led_code (0xf, YELLOW);

 	/* arch number of HHP Cradle */
-	gd->bd->bi_arch_number = 174;
+	gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;

 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0xa0000100;
--- a/board/cradle/flash.c
+++ b/board/cradle/flash.c
@ -30,338 +30,330 @@
 #define FLASH_BANK_SIZE 0x400000
 #define MAIN_SECT_SIZE  0x20000

-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];


 /*-----------------------------------------------------------------------
 */

-ulong flash_init(void)
+ulong flash_init (void)
 {
-   int i, j;
-   ulong size = 0;
+	int i, j;
+	ulong size = 0;

-   for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
-   {
-      ulong flashbase = 0;
-      flash_info[i].flash_id =
-	  (INTEL_MANUFACT & FLASH_VENDMASK) |
-	  (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
-      flash_info[i].size = FLASH_BANK_SIZE;
-      flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-      memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
-      switch (i)
-      {
-	 case 0:
-		flashbase = PHYS_FLASH_1;
-		break;
-	 case 1:
-		flashbase = PHYS_FLASH_2;
-		break;
-	 default:
-		panic("configured too many flash banks!\n");
-		break;
-      }
-      for (j = 0; j < flash_info[i].sector_count; j++)
-      {
-	 flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
-      }
-      size += flash_info[i].size;
-   }
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;

-   /* Protect monitor and environment sectors
-    */
-   flash_protect(FLAG_PROTECT_SET,
-		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + monitor_flash_len - 1,
-		  &flash_info[0]);
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = PHYS_FLASH_1;
+			break;
+		case 1:
+			flashbase = PHYS_FLASH_2;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] =
+				flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}

-   flash_protect(FLAG_PROTECT_SET,
-		  CFG_ENV_ADDR,
-		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-		  &flash_info[0]);
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);

-   return size;
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
 }

 /*-----------------------------------------------------------------------
 */
-void flash_print_info  (flash_info_t *info)
+void flash_print_info (flash_info_t * info)
 {
-   int i, j;
+	int i, j;

-   for (j=0; j<CFG_MAX_FLASH_BANKS; j++)
-   {
-      switch (info->flash_id & FLASH_VENDMASK)
-      {
-	 case (INTEL_MANUFACT & FLASH_VENDMASK):
-		printf("Intel: ");
-		break;
-	 default:
-		printf("Unknown Vendor ");
-		break;
-      }
+	for (j = 0; j < CFG_MAX_FLASH_BANKS; j++) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf ("Intel: ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
+		}

-      switch (info->flash_id & FLASH_TYPEMASK)
-      {
-	 case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
-		printf("28F320J3A (32Mbit)\n");
-		break;
-	 case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
-		printf("28F128J3 (128Mbit)\n");
-		break;
-	 default:
-		printf("Unknown Chip Type\n");
-		goto Done;
-		break;
-      }
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
+			printf ("28F320J3A (32Mbit)\n");
+			break;
+		case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+			printf ("28F128J3 (128Mbit)\n");
+			break;
+		default:
+			printf ("Unknown Chip Type\n");
+			goto Done;
+			break;
+		}

-      printf("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);

-      printf("  Sector Start Addresses:");
-      for (i = 0; i < info->sector_count; i++)
-      {
-	 if ((i % 5) == 0)
-	 {
-	    printf ("\n   ");
-	 }
-	 printf (" %08lX%s", info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-      }
-      printf ("\n");
-      info++;
-   }
+		printf ("  Sector Start Addresses:");
+		for (i = 0; i < info->sector_count; i++) {
+			if ((i % 5) == 0) {
+				printf ("\n   ");
+			}
+			printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+		}
+		printf ("\n");
+		info++;
+	}

-Done:
+Done:	;
 }

 /*-----------------------------------------------------------------------
 */

-int        flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
-   int flag, prot, sect;
-   int rc = ERR_OK;
+	int flag, prot, sect;
+	int rc = ERR_OK;

-   if (info->flash_id == FLASH_UNKNOWN)
-	return ERR_UNKNOWN_FLASH_TYPE;
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;

-   if ((s_first < 0) || (s_first > s_last)) {
-	return ERR_INVAL;
-   }
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}

-   if ((info->flash_id & FLASH_VENDMASK) !=
-	(INTEL_MANUFACT & FLASH_VENDMASK)) {
-	return ERR_UNKNOWN_FLASH_VENDOR;
-   }
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}

-   prot = 0;
-   for (sect=s_first; sect<=s_last; ++sect) {
-      if (info->protect[sect]) {
-	    prot++;
-      }
-   }
-   if (prot)
-	return ERR_PROTECTED;
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;

-   /*
-    * Disable interrupts which might cause a timeout
-    * here. Remember that our exception vectors are
-    * at address 0 in the flash, and we don't want a
-    * (ticker) exception to happen while the flash
-    * chip is in programming mode.
-    */
-   flag = disable_interrupts();
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();

-   /* Start erase on unprotected sectors */
-   for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {

-      printf("Erasing sector %2d ... ", sect);
+		printf ("Erasing sector %2d ... ", sect);

-      /* arm simple, non interrupt dependent timer */
-      reset_timer_masked();
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();

-      if (info->protect[sect] == 0) {        /* not protected */
-	  vu_short *addr = (vu_short *)(info->start[sect]);
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);

-	  *addr = 0x20;        /* erase setup */
-	  *addr = 0xD0;        /* erase confirm */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */

-	  while ((*addr & 0x80) != 0x80) {
-	     if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
-		*addr = 0xB0; /* suspend erase */
-		*addr = 0xFF;        /* reset to read mode */
-		rc = ERR_TIMOUT;
-		goto outahere;
-	     }
-	  }
+			while ((*addr & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}

-	  /* clear status register command */
-	  *addr = 0x50;
-	  /* reset to read mode */
-	  *addr = 0xFF;
-      }
-      printf("ok.\n");
-   }
-   if (ctrlc())
-      printf("User Interrupt!\n");
+			/* clear status register command */
+			*addr = 0x50;
+			/* reset to read mode */
+			*addr = 0xFF;
+		}
+		printf ("ok.\n");
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");

 outahere:

-   /* allow flash to settle - wait 10 ms */
-   udelay_masked(10000);
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);

-   if (flag)
-      enable_interrupts();
+	if (flag)
+		enable_interrupts ();

-   return rc;
+	return rc;
 }

 /*-----------------------------------------------------------------------
 * Copy memory to flash
 */

-static int write_word (flash_info_t *info, ulong dest, ushort data)
+static int write_word (flash_info_t * info, ulong dest, ushort data)
 {
-   vu_short *addr = (vu_short *)dest, val;
-   int rc = ERR_OK;
-   int flag;
+	vu_short *addr = (vu_short *) dest, val;
+	int rc = ERR_OK;
+	int flag;

-   /* Check if Flash is (sufficiently) erased
-    */
-   if ((*addr & data) != data)
-      return ERR_NOT_ERASED;
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return ERR_NOT_ERASED;

-   /*
-    * Disable interrupts which might cause a timeout
-    * here. Remember that our exception vectors are
-    * at address 0 in the flash, and we don't want a
-    * (ticker) exception to happen while the flash
-    * chip is in programming mode.
-    */
-   flag = disable_interrupts();
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();

-   /* clear status register command */
-   *addr = 0x50;
+	/* clear status register command */
+	*addr = 0x50;

-   /* program set-up command */
-   *addr = 0x40;
+	/* program set-up command */
+	*addr = 0x40;

-   /* latch address/data */
-   *addr = data;
+	/* latch address/data */
+	*addr = data;

-   /* arm simple, non interrupt dependent timer */
-   reset_timer_masked();
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();

-   /* wait while polling the status register */
-   while(((val = *addr) & 0x80) != 0x80)
-   {
-      if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
-	  rc = ERR_TIMOUT;
-	  /* suspend program command */
-	  *addr = 0xB0;
-	  goto outahere;
-      }
-   }
+	/* wait while polling the status register */
+	while (((val = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			/* suspend program command */
+			*addr = 0xB0;
+			goto outahere;
+		}
+	}

-   if(val & 0x1A) {        /* check for error */
-      printf("\nFlash write error %02x at address %08lx\n",
-	       (int)val, (unsigned long)dest);
-      if(val & (1<<3)) {
-	 printf("Voltage range error.\n");
-	 rc = ERR_PROG_ERROR;
-	 goto outahere;
-      }
-      if(val & (1<<1)) {
-	 printf("Device protect error.\n");
-	 rc = ERR_PROTECTED;
-	 goto outahere;
-      }
-      if(val & (1<<4)) {
-	 printf("Programming error.\n");
-	 rc = ERR_PROG_ERROR;
-	 goto outahere;
-      }
-      rc = ERR_PROG_ERROR;
-      goto outahere;
-   }
+	if (val & 0x1A) {	/* check for error */
+		printf ("\nFlash write error %02x at address %08lx\n",
+			(int) val, (unsigned long) dest);
+		if (val & (1 << 3)) {
+			printf ("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if (val & (1 << 1)) {
+			printf ("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if (val & (1 << 4)) {
+			printf ("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}

 outahere:
-   /* read array command */
-   *addr = 0xFF;
+	/* read array command */
+	*addr = 0xFF;

-   if (flag)
-      enable_interrupts();
+	if (flag)
+		enable_interrupts ();

-   return rc;
+	return rc;
 }

 /*-----------------------------------------------------------------------
 * Copy memory to flash.
 */

-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
-   ulong cp, wp;
-   ushort data;
-   int l;
-   int i, rc;
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;

-   wp = (addr & ~1);        /* get lower word aligned address */
+	wp = (addr & ~1);	/* get lower word aligned address */

-   /*
-    * handle unaligned start bytes
-    */
-   if ((l = addr - wp) != 0)
-   {
-      data = 0;
-      for (i=0, cp=wp; i<l; ++i, ++cp) {
-	   data = (data >> 8) | (*(uchar *)cp << 8);
-      }
-      for (; i<2 && cnt>0; ++i) {
-	 data = (data >> 8) | (*src++ << 8);
-	 --cnt;
-	 ++cp;
-      }
-      for (; cnt==0 && i<2; ++i, ++cp) {
-	 data = (data >> 8) | (*(uchar *)cp << 8);
-      }
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}

-      if ((rc = write_word(info, wp, data)) != 0) {
-	 return (rc);
-      }
-      wp += 2;
-   }
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}

-   /*
-    * handle word aligned part
-    */
-   while (cnt >= 2) {
-      data = *((vu_short*)src);
-      if ((rc = write_word(info, wp, data)) != 0) {
-	  return (rc);
-      }
-      src += 2;
-      wp  += 2;
-      cnt -= 2;
-   }
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}

-   if (cnt == 0) {
-      return ERR_OK;
-   }
+	if (cnt == 0) {
+		return ERR_OK;
+	}

-   /*
-    * handle unaligned tail bytes
-    */
-   data = 0;
-   for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
-      data = (data >> 8) | (*src++ << 8);
-      --cnt;
-   }
-   for (; i<2; ++i, ++cp) {
-      data = (data >> 8) | (*(uchar *)cp << 8);
-   }
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}

-   return write_word(info, wp, data);
+	return write_word (info, wp, data);
 }
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@ -71,7 +71,7 @@ int board_init (void)
 	/* so we do _nothing_ here */

 	/* arch number of CSB226 board */
-	gd->bd->bi_arch_number = 216;
+	gd->bd->bi_arch_number = MACH_TYPE_CSB226;

 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0xa0000100;
--- a/board/csb472/Makefile
+++ b/board/csb472/Makefile
@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+#OBJS	= $(BOARD).o flash.o
+#OBJS	= $(BOARD).o strataflash.o
+OBJS	= $(BOARD).o
+
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/csb472/config.mk
+++ b/board/csb472/config.mk
@ -0,0 +1,36 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Cogent CSB472 board
+#
+
+LDFLAGS += $(LINKER_UNDEFS)
+
+TEXT_BASE := 0xFFFC0000
+#TEXT_BASE := 0x00100000
+
+PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
--- a/board/csb472/csb472.c
+++ b/board/csb472/csb472.c
@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <405gp_enet.h>
+
+/*
+ * board_early_init_f: do early board initialization
+ *
+ */
+int board_early_init_f(void)
+{
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the Walnut board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+   |       IRQ 27 (EXT IRQ 2) Not Used
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for Walnut board:
+   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+   |       interrupt. The FPGA must be read to determine which device
+   |       caused the interrupt. The default setting of the FPGA clears
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (uicer, 0x00000000);   /* disable all ints */
+	mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (uictr, 0x10000000);   /* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+
+	mtebc (epcr, 0xa8400000);   /* EBC always driven */
+
+	return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+	printf("BOARD: Cogent CSB472\n");
+
+	return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+long initdram (int board_type)
+{
+	ulong tot_size;
+	ulong bank_size;
+	ulong tmp;
+
+	tot_size = 0;
+
+	mtdcr (memcfga, mem_mb0cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb1cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb2cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb3cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+	/* initialize the PHY */
+	miiphy_reset(CONFIG_PHY_ADDR);
+	miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);	/* AUTO neg */
+	miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);	/* LEDs     */
+
+	return 0; /* success */
+}
--- a/board/csb472/init.S
+++ b/board/csb472/init.S
@ -0,0 +1,212 @@
+/******************************************************************************
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+	addis   reg,0,val@h;\
+	ori     reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   ebccfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   ebccfgd,r4
+
+#define WDCR_SDRAM(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   memcfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   memcfgd,r4
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * SETUP CPC0_CR0
+	 *******************************************************************/
+	LI32(r4, 0x00c01030)
+	mtdcr	cntrl0, r4
+
+	/********************************************************************
+	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, cntrl1
+	ori	r4, r4, 0x4000
+	mtdcr	cntrl1, r4
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	WDCR_EBC(epcr, 0xd84c0000)
+	/********************************************************************
+	 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb0ap, 0x03055200)*/
+	/*WDCR_EBC(pb0ap, 0x04055200)*/
+	WDCR_EBC(pb0ap, 0x08055200)
+	WDCR_EBC(pb0cr, 0xff87a000)
+	/********************************************************************
+	 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb3ap, 0x07869200)*/
+	WDCR_EBC(pb3ap, 0x04055200)
+	WDCR_EBC(pb3cr, 0xff01c000)
+	/********************************************************************
+	 * Memory Bank 1,2,4-7 (Unused) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb1ap, 0)
+	WDCR_EBC(pb1cr, 0)
+	WDCR_EBC(pb2ap, 0)
+	WDCR_EBC(pb2cr, 0)
+	WDCR_EBC(pb4ap, 0)
+	WDCR_EBC(pb4cr, 0)
+	WDCR_EBC(pb5ap, 0)
+	WDCR_EBC(pb5cr, 0)
+	WDCR_EBC(pb6ap, 0)
+	WDCR_EBC(pb6cr, 0)
+	WDCR_EBC(pb7ap, 0)
+	WDCR_EBC(pb7cr, 0)
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	WDCR_SDRAM(mem_mcopt1, 0x00000000)
+
+	/*
+	 * Configure Memory Banks
+	 */
+	WDCR_SDRAM(mem_mb0cf, 0x00062001)
+	WDCR_SDRAM(mem_mb1cf, 0x00000000)
+	WDCR_SDRAM(mem_mb2cf, 0x00000000)
+	WDCR_SDRAM(mem_mb3cf, 0x00000000)
+
+	/*
+	 * Set up SDTR1 (SDRAM Timing Register)
+	 */
+	WDCR_SDRAM(mem_sdtr1, 0x00854009)
+
+	/*
+	 * Set RTR (Refresh Timing Register)
+	 */
+	WDCR_SDRAM(mem_rtr,   0x10000000)
+	/* WDCR_SDRAM(mem_rtr,   0x05f00000) */
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait >200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	WDCR_SDRAM(mem_mcopt1,0x80800000)
+
+..sdri_done:
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
--- a/board/csb472/u-boot.lds
+++ b/board/csb472/u-boot.lds
@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/csb472/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    lib_ppc/extable.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_generic/zlib.o	(.text)
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/dave/B2/B2.c
+++ b/board/dave/B2/B2.c
@ -109,7 +109,7 @@ int board_init (void)
    PDATF = temp;

 	/* arch number MACH_TYPE_MBA44B0 */
-	gd->bd->bi_arch_number = 178;
+	gd->bd->bi_arch_number = MACH_TYPE_S3C44B0;

 	/* location of boot parameters */
 	gd->bd->bi_boot_params = 0x0c000100;
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@ -31,25 +31,8 @@

 /* ------------------------------------------------------------------------- */

-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
 /* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
-
+int gunzip(void *, int, unsigned char *, unsigned long *);

 int board_early_init_f (void)
 {
@ -60,13 +43,13 @@ int board_early_init_f (void)
 	 * IRQ 0-15  405GP internally generated; active high; level sensitive
 	 * IRQ 16    405GP internally generated; active low; level sensitive
 	 * IRQ 17-24 RESERVED
-	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
-	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
-	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
-	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
-	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
-	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 * IRQ 25 (EXT IRQ 0)
+	 * IRQ 26 (EXT IRQ 1)
+	 * IRQ 27 (EXT IRQ 2)
+	 * IRQ 28 (EXT IRQ 3)
+	 * IRQ 29 (EXT IRQ 4)
+	 * IRQ 30 (EXT IRQ 5)
+	 * IRQ 31 (EXT IRQ 6)
 	 */
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 	mtdcr(uicer, 0x00000000);       /* disable all ints */
@ -84,11 +67,9 @@ int board_early_init_f (void)
 #else
 	mtebc (epcr, 0x28400000); /* ebc in high-z */
 #endif
-
 	return 0;
 }

-
 /* ------------------------------------------------------------------------- */

 int misc_init_f (void)
@ -96,11 +77,15 @@ int misc_init_f (void)
 	return 0;  /* dummy implementation */
 }

+extern flash_info_t flash_info[];	/* info for FLASH chips */

 int misc_init_r (void)
 {
-#if 0 /* test-only */
 	DECLARE_GLOBAL_DATA_PTR;
+
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart = 0 - flash_info[0].size;
+	gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
 #if 0
 	volatile unsigned short *fpga_mode =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
@ -119,7 +104,7 @@ int misc_init_r (void)
 	unsigned long cntrl0Reg;

 	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
@ -177,7 +162,6 @@ int misc_init_r (void)
 	udelay(1000); /* wait 1ms */
 	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 	udelay(1000); /* wait 1ms */
-
 #endif

 #if 0
@ -192,12 +176,9 @@ int misc_init_r (void)
 	*duart0_mcr = 0x08;
 	*duart1_mcr = 0x08;
 #endif
-#endif
-
 	return (0);
 }

-
 /*
 * Check Board Identity:
 */
@ -266,8 +247,13 @@ nand_init(void)
 {
 	ulong totlen = 0;

-#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) || \
+/*
+	The HI model is equipped with a large block NAND chip not supported yet
+	by U-Boot
    (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
+*/
+
+#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
 	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
 	totlen += nand_probe (CFG_NAND0_BASE);
 #endif	/* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
@ -278,3 +264,39 @@ nand_init(void)
 	printf ("%4lu MB\n", totlen >>20);
 }
 #endif
+
+#ifdef CONFIG_CFB_CONSOLE
+# ifdef CONFIG_CONSOLE_EXTRA_INFO
+# include <video_fb.h>
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+	uint pvr = get_pvr ();
+
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		switch (pvr) {
+		case PVR_405EP_RB:
+			sprintf (info, " IBM PowerPC 405EP Rev. B");
+			break;
+		default:
+			sprintf (info, " IBM PowerPC 405EP Rev. <unknown>");
+			break;
+		}
+		return;
+	case 2:
+		sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}
+
+	/* no more info lines */
+	*info = 0;
+	return;
+}
+# endif	/* CONFIG_CONSOLE_EXTRA_INFO */
+#endif	/* CONFIG_CFB_CONSOLE */
--- a/board/dave/PPChameleonEVB/flash.c
+++ b/board/dave/PPChameleonEVB/flash.c
@ -44,12 +44,15 @@ unsigned long flash_init (void)
 #ifdef __DEBUG_START_FROM_SRAM__
 	return CFG_DUMMY_FLASH_SIZE;
 #else
-	unsigned long size_b0;
+	unsigned long size;
 	int i;
 	uint pbcr;
-	unsigned long base_b0;
+	unsigned long base;
 	int size_val = 0;

+	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
+	debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info);
+
 	/* Init: no FLASHes known */
 	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
@ -57,22 +60,26 @@ unsigned long flash_init (void)

 	/* Static FLASH Bank configuration here - FIXME XXX */

-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+	debug("[%s, %d] Calling flash_get_size ...\n", __FUNCTION__, __LINE__);
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);

 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
+			size, size<<20);
 	}

+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
 	/* Setup offsets */
-	flash_get_offsets (-size_b0, &flash_info[0]);
+	flash_get_offsets (-size, &flash_info[0]);
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);

 	/* Re-do sizing to get full correct info */
 	mtdcr(ebccfga, pb0cr);
 	pbcr = mfdcr(ebccfgd);
 	mtdcr(ebccfga, pb0cr);
-	base_b0 = -size_b0;
-	switch (size_b0) {
+	base = -size;
+	switch (size) {
 	case 1 << 20:
 		size_val = 0;
 		break;
@ -89,8 +96,9 @@ unsigned long flash_init (void)
 		size_val = 4;
 		break;
 	}
-	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
 	mtdcr(ebccfgd, pbcr);
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);

 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
@ -98,8 +106,9 @@ unsigned long flash_init (void)
 			    0xffffffff,
 			    &flash_info[0]);

-	flash_info[0].size = size_b0;
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+	flash_info[0].size  = size;

-	return (size_b0);
+	return (size);
 #endif
 }
--- a/board/dave/common/flash.c
+++ b/board/dave/common/flash.c
@ -220,6 +220,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	ulong base = (ulong)addr;
 	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;

+	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
+
 	/* Write auto select command: read Manufacturer ID */
 	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
 	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
--- a/board/dbau1x00/README
+++ b/board/dbau1x00/README
@ -1,30 +1,40 @@
-By Thomas.Lange@corelatus.se 2003-10-06
+By Thomas.Lange@corelatus.se 2004-Oct-05
 ----------------------------------------
-DbAu1000 is a development board from AMD containing
-an Alchemy AU1000 with mips32 core.
+DbAu1xx0 are development boards from AMD containing
+an Alchemy AU1xx0 series cpu with mips32 core.
+Existing cpu:s are Au1000, Au1100, Au1500 and Au1550

 Limitations & comments
 ----------------------
-I assume that you set board to BIG endian!
-Little endian not tested, most probably broken.
+Support was originally big endian only.
+I have not tested, but several u-boot users report working
+configurations in little endian mode.

 I named the board dbau1x00, to allow
 support for all three development boards
-some day ( dbau1000, dbau1100 and dbau1500 ).
+( dbau1000, dbau1100 and dbau1500 ).
+Now there is a new board called dbau1550 also, which
+should be supported RSN.

-I only have a dbau1000, so all testing is limited
-to this board!
+I only have a dbau1000, so my testing is limited
+to this board.

 The board has two different flash banks, that can
 be selected via dip switch. This makes it possible
 to test new bootloaders without thrashing the YAMON
-boot loader deliviered with board.
+boot loader delivered with board.
+
+NOTE! When you switch between the two boot flashes, the
+base addresses will be swapped.
+Have this in mind when you compile u-boot. TEXT_BASE has
+to match the address where u-boot is located when you
+actually launch.

 Ethernet only supported for mac0.

-Pcmcia only supported for slot 0, only 3.3V.
+PCMCIA only supported for slot 0, only 3.3V.

-Pcmcia IDE tested with Sandisk Compact Flash and
+PCMCIA IDE tested with Sandisk Compact Flash and
 IBM microdrive.

 ###################################
@ -32,7 +42,7 @@ IBM microdrive.
 ###################################
 If you partition a disk on another system (e.g. laptop),
 all bytes will be swapped on 16bit level when using
-PCMCIA!!!!
+PCMCIA and running cpu in big endian mode!!!!

 This is probably due to an error in Au1000 chip.

--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@ -104,17 +104,17 @@ int checkboard (void)
 		      CFG_PCMCIA_ATTR_BASE, /* Hi */
 		      0x3D000017,           /* Lo0 */
 		      0x3D200017);          /* Lo1 */
-#endif
+#endif	/* 0 */
 	write_one_tlb(22,                   /* index */
 		      0x01ffe000,           /* Pagemask, 16 MB pages */
 		      CFG_PCMCIA_MEM_ADDR,  /* Hi */
 		      0x3E000017,           /* Lo0 */
 		      0x3E200017);          /* Lo1 */
+#endif	/* CONFIG_IDE_PCMCIA */

 	/* Release reset of ethernet PHY chips */
 	/* Always do this, because linux does not know about it */
 	*phy = 3;

 	return 0;
-#endif
 }
--- a/board/dnp1110/dnp1110.c
+++ b/board/dnp1110/dnp1110.c
@ -39,7 +39,7 @@ int board_init (void)
 	/* so we do _nothing_ here */

 	/* arch number of DNP1110-Board */
-	gd->bd->bi_arch_number = 255;
+	gd->bd->bi_arch_number = MACH_TYPE_DNP1110;

    /* flash vpp on */
    PPDR |= 0x80;	/* assumes LCD controller is off */
--- a/board/eltec/elppc/misc.c
+++ b/board/eltec/elppc/misc.c
@ -250,10 +250,6 @@ int misc_init_r (void)
 		 eerev.etheraddr[4], eerev.etheraddr[5]);
 	setenv ("ethaddr", buf);

-	/* set serial console as default */
-	if ((ptr = getenv ("console")) == NULL)
-		setenv ("console", "serial");
-
 	/* print actual board identification */
 	printf ("Ident: %s  Ser %s  Rev %c%c\n",
 		eerev.board, (char *) &eerev.serial,
--- a/board/ep7312/ep7312.c
+++ b/board/ep7312/ep7312.c
@ -40,7 +40,7 @@ int board_init (void)
 	IO_LEDFLSH = 0x40;

 	/* arch number MACH_TYPE_EDB7312 */
-	gd->bd->bi_arch_number = 131;
+	gd->bd->bi_arch_number = MACH_TYPE_EDB7312;

 	/* location of boot parameters */
 	gd->bd->bi_boot_params = 0xc0020100;
--- a/board/esd/ar405/Makefile
+++ b/board/esd/ar405/Makefile
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o flash.o ../common/misc.o

 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/esd/ar405/ar405.c
+++ b/board/esd/ar405/ar405.c
@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
@ -28,6 +28,7 @@

 /*cmd_boot.c*/
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);

 /* ------------------------------------------------------------------------- */

@ -40,6 +41,10 @@ const unsigned char fpgadata[] = {
 #include "fpgadata.c"
 };

+const unsigned char fpgadata_xl30[] = {
+#include "fpgadata_xl30.c"
+};
+
 /*
 * include common fpga code (for esd boards)
 */
@ -64,45 +69,52 @@ int board_early_init_f (void)
 	/*
 	 * Boot onboard FPGA
 	 */
+	/* first try 40er image */
+	gd->board_type = 40;
 	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
 	if (status != 0) {
-		/* booting FPGA failed */
+		/* try xl30er image */
+		gd->board_type = 30;
+		status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
+		if (status != 0) {
+			/* booting FPGA failed */
 #ifndef FPGA_DEBUG
-		/* set up serial port with default baudrate */
-		(void) get_clocks ();
-		gd->baudrate = CONFIG_BAUDRATE;
-		serial_init ();
-		console_init_f ();
+			/* set up serial port with default baudrate */
+			(void) get_clocks ();
+			gd->baudrate = CONFIG_BAUDRATE;
+			serial_init ();
+			console_init_f ();
 #endif
-		printf ("\nFPGA: Booting failed ");
-		switch (status) {
-		case ERROR_FPGA_PRG_INIT_LOW:
-			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_INIT_HIGH:
-			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_DONE:
-			printf ("(Timeout: DONE not high after programming FPGA)\n ");
-			break;
-		}
+			printf ("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf ("(Timeout: DONE not high after programming FPGA)\n ");
+				break;
+			}

-		/* display infos on fpgaimage */
-		index = 15;
-		for (i = 0; i < 4; i++) {
-			len = fpgadata[index];
-			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
-			index += len + 3;
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i = 0; i < 4; i++) {
+				len = fpgadata[index];
+				printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+				index += len + 3;
+			}
+			putc ('\n');
+			/* delayed reboot */
+			for (i = 20; i > 0; i--) {
+				printf ("Rebooting in %2d seconds \r", i);
+				for (index = 0; index < 1000; index++)
+					udelay (1000);
+			}
+			putc ('\n');
+			do_reset (NULL, 0, 0, NULL);
 		}
-		putc ('\n');
-		/* delayed reboot */
-		for (i = 20; i > 0; i--) {
-			printf ("Rebooting in %2d seconds \r", i);
-			for (index = 0; index < 1000; index++)
-				udelay (1000);
-		}
-		putc ('\n');
-		do_reset (NULL, 0, 0, NULL);
 	}

 	/*
@ -139,32 +151,44 @@ int board_early_init_f (void)

 int checkboard (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	int index;
 	int len;
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof (str));
+	const unsigned char *fpga;

 	puts ("Board: ");

-	if (!i || strncmp (str, "AR405", 5)) {
-		puts ("### No HW ID - assuming AR405\n");
-		return (0);
+	if (i == -1) {
+		puts ("### No HW ID - assuming AR405");
+	} else {
+		puts(str);
 	}

-	puts (str);
-
 	puts ("\nFPGA:  ");

 	/* display infos on fpgaimage */
+	if (gd->board_type == 30) {
+		fpga = fpgadata_xl30;
+	} else {
+		fpga = fpgadata;
+	}
 	index = 15;
 	for (i = 0; i < 4; i++) {
-		len = fpgadata[index];
-		printf ("%s ", &(fpgadata[index + 1]));
+		len = fpga[index];
+		printf ("%s ", &(fpga[index + 1]));
 		index += len + 3;
 	}

 	putc ('\n');

+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
 	return 0;
 }

--- a/board/esd/ar405/config.mk
+++ b/board/esd/ar405/config.mk
@ -26,4 +26,5 @@
 #

 #TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFFD0000
+#TEXT_BASE = 0xFFFD0000
+TEXT_BASE = 0xFFFC0000
--- a/board/esd/ar405/flash.c
+++ b/board/esd/ar405/flash.c
@ -33,18 +33,19 @@
 /*-----------------------------------------------------------------------
 * Functions
 */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static void flash_get_offsets (ulong base, flash_info_t *info);
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);

 /*-----------------------------------------------------------------------
 */

 unsigned long flash_init (void)
 {
-	unsigned long size_b0, size_b1;
+	unsigned long size_b0;
 	int i;
 	uint pbcr;
-	unsigned long base_b0, base_b1;
+	unsigned long base_b0;
+	int size_val = 0;

 	/* Init: no FLASHes known */
 	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
@ -53,74 +54,48 @@ unsigned long flash_init (void)

 	/* Static FLASH Bank configuration here - FIXME XXX */

-	base_b0 = FLASH_BASE0_PRELIM;
-	size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);

 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 			size_b0, size_b0<<20);
 	}

-	base_b1 = FLASH_BASE1_PRELIM;
-	size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);

 	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);

-	if (size_b1)
-	  {
-	    mtdcr(ebccfga, pb0cr);
-	    pbcr = mfdcr(ebccfgd);
-	    mtdcr(ebccfga, pb0cr);
-	    base_b1 = -size_b1;
-	    pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
-	    mtdcr(ebccfgd, pbcr);
-	    /*          printf("pb1cr = %x\n", pbcr); */
-	  }
-
-	if (size_b0)
-	  {
-	    mtdcr(ebccfga, pb1cr);
-	    pbcr = mfdcr(ebccfgd);
-	    mtdcr(ebccfga, pb1cr);
-	    base_b0 = base_b1 - size_b0;
-	    pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
-	    mtdcr(ebccfgd, pbcr);
-	    /*            printf("pb0cr = %x\n", pbcr); */
-	  }
-
-	size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
-
-	flash_get_offsets (base_b0, &flash_info[0]);
-
-	/* monitor protection ON by default */
+	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    base_b0+size_b0-monitor_flash_len,
-			    base_b0+size_b0-1,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
 			    &flash_info[0]);

-	if (size_b1) {
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
-
-		flash_get_offsets (base_b1, &flash_info[1]);
-
-		/* monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET,
-				    base_b1+size_b1-monitor_flash_len,
-				    base_b1+size_b1-1,
-				    &flash_info[1]);
-		/* monitor protection OFF by default (one is enough) */
-		(void)flash_protect(FLAG_PROTECT_CLEAR,
-				    base_b0+size_b0-monitor_flash_len,
-				    base_b0+size_b0-1,
-				    &flash_info[0]);
-	} else {
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-	}
-
 	flash_info[0].size = size_b0;
-	flash_info[1].size = size_b1;

-	return (size_b0 + size_b1);
+	return (size_b0);
 }
--- a/board/esd/ar405/fpgadata_xl30.c
+++ b/board/esd/ar405/fpgadata_xl30.c
--- a/board/esd/ash405/ash405.c
+++ b/board/esd/ash405/ash405.c
@ -47,7 +47,7 @@ const unsigned char fpgadata[] =


 /* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);


 int board_early_init_f (void)
@ -102,7 +102,7 @@ int misc_init_r (void)
 	int i;

 	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
--- a/board/esd/common/misc.c
+++ b/board/esd/common/misc.c
@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+#include <miiphy.h>
+#endif
+
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+void lxt971_no_sleep(void)
+{
+	unsigned short reg;
+
+	miiphy_read(CONFIG_PHY_ADDR, 0x10, &reg);
+	reg &= ~0x0040;                  /* disable sleep mode */
+	miiphy_write(CONFIG_PHY_ADDR, 0x10, reg);
+}
+#endif /* CONFIG_LXT971_NO_SLEEP */
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@ -54,7 +54,7 @@ const unsigned char fpgadata[] =

 /* Prototypes */
 int cpci405_version(void);
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);


 int board_early_init_f (void)
@ -259,7 +259,7 @@ int misc_init_r (void)
 		mtdcr(cntrl0, cntrl0Reg | 0x00300000);

 		dst = malloc(CFG_FPGA_MAX_SIZE);
-		if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+		if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 			printf ("GUNZIP ERROR - must RESET board to recover\n");
 			do_reset (NULL, 0, 0, NULL);
 		}
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@ -50,7 +50,7 @@ const unsigned char fpgadata[] =


 /* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);


 int board_early_init_f (void)
@ -116,7 +116,7 @@ int misc_init_r (void)
 	 */

 	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@ -47,7 +47,7 @@ const unsigned char fpgadata[] =


 /* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);


 int board_early_init_f (void)
@ -101,7 +101,7 @@ int misc_init_r (void)

 #if 1 /* test-only */
 	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@ -47,7 +47,7 @@ const unsigned char fpgadata[] =


 /* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);


 int board_early_init_f (void)
@ -102,7 +102,7 @@ int misc_init_r (void)
 	int i;

 	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
--- a/board/evb4510/Makefile
+++ b/board/evb4510/Makefile
@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= evb4510.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/evb4510/config.mk
+++ b/board/evb4510/config.mk
@ -0,0 +1,27 @@
+#
+# Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+# Curt Brune <curt@cucy.com>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x007d0000
--- a/board/evb4510/evb4510.c
+++ b/board/evb4510/evb4510.c
@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <command.h>
+
+#ifdef CONFIG_EVB4510
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	icache_enable();
+
+	/* address for the kernel command line */
+	gd->bd->bi_boot_params = 0x800;
+
+	/* enable board LEDs for output */
+	PUT_REG( REG_IOPDATA, 0x0);
+	PUT_REG( REG_IOPMODE, 0xFFFF);
+	PUT_REG( REG_IOPDATA, 0xFF);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+#if CONFIG_NR_DRAM_BANKS == 2
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
+#endif
+	return 0;
+}
+
+#endif
--- a/board/evb4510/flash.c
+++ b/board/evb4510/flash.c
@ -0,0 +1,540 @@
+/*
+ *
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <flash.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+typedef enum {
+	FLASH_DEV_U9_512KB = 0,
+	FLASH_DEV_U7_2MB = 1
+} FLASH_DEV;
+
+#define FLASH_DQ7		(0x80)
+#define FLASH_DQ5		(0x20)
+
+#define PROG_ADDR		(0xAAA)
+#define SETUP_ADDR		(0xAAA)
+#define ID_ADDR			(0xAAA)
+#define UNLOCK_ADDR1		(0xAAA)
+#define UNLOCK_ADDR2		(0x555)
+
+#define UNLOCK_CMD1		(0xAA)
+#define UNLOCK_CMD2		(0x55)
+#define ERASE_SUSPEND_CMD	(0xB0)
+#define ERASE_RESUME_CMD	(0x30)
+#define RESET_CMD		(0xF0)
+#define ID_CMD			(0x90)
+#define SELECT_CMD		(0x90)
+#define CHIPERASE_CMD		(0x10)
+#define BYPASS_CMD		(0x20)
+#define SECERASE_CMD		(0x30)
+#define PROG_CMD		(0xa0)
+#define SETUP_CMD		(0x80)
+
+#if 0
+#define WRITE_UNLOCK(addr) { \
+	PUT__U8( addr + UNLOCK_ADDR1, UNLOCK_CMD1); \
+	PUT__U8( addr + UNLOCK_ADDR2, UNLOCK_CMD2); \
+}
+
+/* auto select command */
+#define CMD_ID(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, ID_CMD); \
+}
+
+#define CMD_RESET(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, RESET_CMD); \
+}
+
+#define CMD_ERASE_SEC(base, addr) WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, SETUP_CMD); \
+	WRITE_UNLOCK(base); \
+	PUT__U8( addr, SECERASE_CMD);
+
+#define CMD_ERASE_CHIP(base) WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, SETUP_CMD); \
+	WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, CHIPERASE_CMD);
+
+/* prepare for bypass programming */
+#define CMD_UNLOCK_BYPASS(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, 0x20); \
+}
+
+/* terminate bypass programming */
+#define CMD_BYPASS_RESET(addr) { \
+	PUT__U8(addr, 0x90); \
+	PUT__U8(addr, 0x00); \
+}
+#endif
+
+inline static void FLASH_CMD_UNLOCK (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		PUT__U8 (base + 0xAAA, 0xAA);
+		PUT__U8 (base + 0x555, 0x55);
+		break;
+	case FLASH_DEV_U9_512KB:
+		PUT__U8 (base + 0x555, 0xAA);
+		PUT__U8 (base + 0x2AA, 0x55);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_SELECT (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SELECT_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SELECT_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_RESET (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, RESET_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, RESET_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_ERASE_SEC (FLASH_DEV dev, u32 base, u32 addr)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (addr, SECERASE_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (addr, SECERASE_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_ERASE_CHIP (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base, CHIPERASE_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base, CHIPERASE_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_UNLOCK_BYPASS (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, BYPASS_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, BYPASS_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_BYPASS_RESET (FLASH_DEV dev, u32 base)
+{
+	PUT__U8 (base, SELECT_CMD);
+	PUT__U8 (base, 0x0);
+}
+
+/* poll for flash command completion */
+static u16 _flash_poll (FLASH_DEV dev, u32 addr, u16 data, ulong timeOut)
+{
+	u32 done = 0;
+	ulong t0;
+
+	u16 error = 0;
+	volatile u16 flashData;
+
+	data = data & 0xFF;
+	t0 = get_timer (0);
+	while (get_timer (t0) < timeOut) {
+		/*	for( i = 0; i < POLL_LOOPS; i++) { */
+		/*  Read the Data */
+		flashData = GET__U8 (addr);
+
+		/*  FLASH_DQ7 = Data? */
+		if ((flashData & FLASH_DQ7) == (data & FLASH_DQ7)) {
+			done = 1;
+			break;
+		}
+
+		/*  Check Timeout (FLASH_DQ5==1) */
+		if (flashData & FLASH_DQ5) {
+			/*  Read the Data */
+			flashData = GET__U8 (addr);
+
+			/*  FLASH_DQ7 = Data? */
+			if (!((flashData & FLASH_DQ7) == (data & FLASH_DQ7))) {
+				printf ("_flash_poll(): FLASH_DQ7 & flashData not equal to write value\n");
+				error = ERR_PROG_ERROR;
+			}
+			FLASH_CMD_RESET (dev, addr);
+			done = 1;
+			break;
+		}
+		/*  spin delay */
+		udelay (10);
+	}
+
+
+	/*  error update */
+	if (!done) {
+		printf ("_flash_poll(): Timeout\n");
+		error = ERR_TIMOUT;
+	}
+
+	/*  Check the data */
+	if (!error) {
+		/*  Read the Data */
+		flashData = GET__U8 (addr);
+		if (flashData != data) {
+			error = ERR_PROG_ERROR;
+			printf ("_flash_poll(): flashData(0x%04x) not equal to data(0x%04x)\n",
+				flashData, data);
+		}
+	}
+
+	return error;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int _flash_check_protection (flash_info_t * info, int s_first, int s_last)
+{
+	int sect, prot = 0;
+
+	for (sect = s_first; sect <= s_last; sect++)
+		if (info->protect[sect]) {
+			printf ("  Flash sector %d protected.\n", sect);
+			prot++;
+		}
+	return prot;
+}
+
+static int _detectFlash (FLASH_DEV dev, u32 base, u8 venId, u8 devId)
+{
+
+	u32 baseAddr = base | CACHE_DISABLE_MASK;
+	u8 vendorId, deviceId;
+
+	/*	printf(__FUNCTION__"(): detecting flash @ 0x%08x\n", base); */
+
+	/* Send auto select command and read manufacturer info */
+	FLASH_CMD_SELECT (dev, baseAddr);
+	vendorId = GET__U8 (baseAddr);
+	FLASH_CMD_RESET (dev, baseAddr);
+
+	/* Send auto select command and read device info */
+	FLASH_CMD_SELECT (dev, baseAddr);
+
+	if (dev == FLASH_DEV_U7_2MB) {
+		deviceId = GET__U8 (baseAddr + 2);
+	} else if (dev == FLASH_DEV_U9_512KB) {
+		deviceId = GET__U8 (baseAddr + 1);
+	} else {
+		return 0;
+	}
+
+	FLASH_CMD_RESET (dev, baseAddr);
+
+	/* printf (__FUNCTION__"(): found vendorId 0x%04x, deviceId 0x%04x\n",
+		vendorId, deviceId);
+	 */
+
+	return (vendorId == venId) && (deviceId == devId);
+
+}
+
+/******************************************************************************
+ *
+ * Public u-boot interface functions below
+ *
+ *****************************************************************************/
+
+/***************************************************************************
+ *
+ * Flash initialization
+ *
+ * This board has two banks of flash, but the base addresses depend on
+ * how the board is jumpered.
+ *
+ * The two flash types are:
+ *
+ *   AMD Am29LV160DB (2MB) sectors layout 16KB, 2x8KB, 32KB, 31x64KB
+ *
+ *   AMD Am29LV040B  (512KB)  sectors: 8x64KB
+ *****************************************************************************/
+
+unsigned long flash_init (void)
+{
+	flash_info_t *info;
+	u16 i;
+	u32 flashtest;
+	s16 amd160 = -1;
+	u32 amd160base = 0;
+
+#if CFG_MAX_FLASH_BANKS == 2
+	s16 amd040 = -1;
+	u32 amd040base = 0;
+#endif
+
+	/* configure PHYS_FLASH_1 */
+	if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_1, 0x1, 0x49)) {
+		amd160 = 0;
+		amd160base = PHYS_FLASH_1;
+#if CFG_MAX_FLASH_BANKS == 1
+	}
+#else
+		if (_detectFlash
+		    (FLASH_DEV_U9_512KB, PHYS_FLASH_2, 0x1, 0x4F)) {
+			amd040 = 1;
+			amd040base = PHYS_FLASH_2;
+		} else {
+			printf (__FUNCTION__
+				"(): Unable to detect PHYS_FLASH_2: 0x%08x\n",
+				PHYS_FLASH_2);
+		}
+	} else if (_detectFlash (FLASH_DEV_U9_512KB, PHYS_FLASH_1, 0x1, 0x4F)) {
+		amd040 = 0;
+		amd040base = PHYS_FLASH_1;
+		if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_2, 0x1, 0x49)) {
+			amd160 = 1;
+			amd160base = PHYS_FLASH_2;
+		} else {
+			printf (__FUNCTION__
+				"(): Unable to detect PHYS_FLASH_2: 0x%08x\n",
+				PHYS_FLASH_2);
+		}
+	}
+#endif
+	else {
+		printf (__FUNCTION__
+			"(): Unable to detect PHYS_FLASH_1: 0x%08x\n",
+			PHYS_FLASH_1);
+	}
+
+	/* Configure AMD Am29LV160DB (2MB) */
+	info = &flash_info[amd160];
+	info->flash_id = FLASH_DEV_U7_2MB;
+	info->sector_count = 35;
+	info->size = 2 * 1024 * 1024;	/* 2MB */
+	/* 1*16K Boot Block
+	   2*8K Parameter Block
+	   1*32K Small Main Block */
+	info->start[0] = amd160base;
+	info->start[1] = amd160base + 0x4000;
+	info->start[2] = amd160base + 0x6000;
+	info->start[3] = amd160base + 0x8000;
+	for (i = 1; i < info->sector_count; i++)
+		info->start[3 + i] = amd160base + i * (64 * 1024);
+
+	for (i = 0; i < info->sector_count; i++) {
+		/* Write auto select command sequence and query sector protection */
+		FLASH_CMD_SELECT (info->flash_id,
+				  info->start[i] | CACHE_DISABLE_MASK);
+		flashtest =
+			GET__U8 (((info->start[i] + 4) | CACHE_DISABLE_MASK));
+		FLASH_CMD_RESET (info->flash_id,
+				 amd160base | CACHE_DISABLE_MASK);
+		info->protect[i] = (flashtest & 0x0001);
+	}
+
+	/*
+	 * protect monitor and environment sectors in 2MB flash
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       amd160base, amd160base + monitor_flash_len - 1, info);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SIZE - 1, info);
+
+#if CFG_MAX_FLASH_BANKS == 2
+	/* Configure AMD Am29LV040B (512KB) */
+	info = &flash_info[amd040];
+	info->flash_id = FLASH_DEV_U9_512KB;
+	info->sector_count = 8;
+	info->size = 512 * 1024;	/* 512KB, 8 x 64KB */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = amd040base + i * (64 * 1024);
+		/* Write auto select command sequence and query sector protection */
+		FLASH_CMD_SELECT (info->flash_id,
+				  info->start[i] | CACHE_DISABLE_MASK);
+		flashtest =
+			GET__U8 (((info->start[i] + 2) | CACHE_DISABLE_MASK));
+		FLASH_CMD_RESET (info->flash_id,
+				 amd040base | CACHE_DISABLE_MASK);
+		info->protect[i] = (flashtest & 0x0001);
+	}
+#endif
+
+	return flash_info[0].size
+#if CFG_MAX_FLASH_BANKS == 2
+		+ flash_info[1].size
+#endif
+		;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_DEV_U7_2MB) {
+		printf ("AMD Am29LV160DB (2MB) 16KB,2x8KB,32KB,31x64KB\n");
+	} else if (info->flash_id == FLASH_DEV_U9_512KB) {
+		printf ("AMD Am29LV040B	 (512KB) 8x64KB\n");
+	} else {
+		printf ("Unknown flash_id ...\n");
+		return;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 4) == 0)
+			printf ("\n   ");
+		printf (" S%02d @ 0x%08lX%s", i,
+			info->start[i], info->protect[i] ? " !" : "  ");
+	}
+	printf ("\n");
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	u16 i, error = 0;
+
+	printf ("\n");
+
+	/* check flash protection bits */
+	if (_flash_check_protection (info, s_first, s_last)) {
+		printf ("  Flash erase aborted due to protected sectors\n");
+		return ERR_PROTECTED;
+	}
+
+	if ((s_first < info->sector_count) && (s_first <= s_last)) {
+		for (i = s_first; i <= s_last && !error; i++) {
+			printf ("  Erasing Sector %d @ 0x%08lx ... ", i,
+				info->start[i]);
+			/* bypass the cache to access the flash memory */
+			FLASH_CMD_ERASE_SEC (info->flash_id,
+					     (info->
+					      start[0] | CACHE_DISABLE_MASK),
+					     (info->
+					      start[i] | CACHE_DISABLE_MASK));
+			/* look for sector to become 0xFF after erase */
+			error = _flash_poll (info->flash_id,
+					     info->
+					     start[i] | CACHE_DISABLE_MASK,
+					     0xFF, CFG_FLASH_ERASE_TOUT);
+			FLASH_CMD_RESET (info->flash_id,
+					 (info->
+					  start[0] | CACHE_DISABLE_MASK));
+			printf ("done\n");
+			if (error) {
+				break;
+			}
+		}
+	} else
+		error = ERR_INVAL;
+
+	return error;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	u16 error = 0, i;
+	u32 n;
+	u8 *bp, *bps;
+
+	/*  Write Setup */
+	/* bypass the cache to access the flash memory */
+	FLASH_CMD_UNLOCK_BYPASS (info->flash_id,
+				 (info->start[0] | CACHE_DISABLE_MASK));
+
+	/*  Write the Data to Flash */
+
+	bp = (u8 *) (addr | CACHE_DISABLE_MASK);
+	bps = (u8 *) src;
+
+	for (n = 0; n < cnt && !error; n++, bp++, bps++) {
+
+		if (!(n % (cnt / 15))) {
+			printf (".");
+		}
+
+		/*  write the flash command for flash memory */
+		*bp = 0xA0;
+
+		/*  Write the data */
+		*bp = *bps;
+
+		/*  Check if the write is done */
+		for (i = 0; i < 0xff; i++);
+		error = _flash_poll (info->flash_id, (u32) bp, *bps,
+				     CFG_FLASH_WRITE_TOUT);
+		if (error) {
+			return error;
+		}
+	}
+
+	/*  Reset the Flash Mode to read */
+	FLASH_CMD_BYPASS_RESET (info->flash_id, info->start[0]);
+
+	printf (" ");
+
+	return error;
+}
--- a/board/evb4510/memsetup.S
+++ b/board/evb4510/memsetup.S
@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/hardware.h>
+
+/***********************************************************************
+ * Configure Memory Map
+ *
+ * This memory map allows us to relocate from FLASH to SRAM.  After
+ * power-on reset the CPU only knows about the FLASH memory at address
+ * 0x00000000.	After memsetup completes the memory map will be:
+ *
+ * Memory Addr
+ * 0x00000000
+ *     to	8MB SRAM (U5) -- 8MB Map
+ * 0x00800000
+ *
+ * 0x01000000
+ *     to	2MB Flash @ 0x00000000 (U7) -- 2MB Map
+ * 0x01200000
+ *
+ * 0x02000000
+ *     to	512KB Flash @ 0x02000000 (U9) -- 2MB Map
+ * 0x02080000
+ *
+ * Load all 12 memory registers with the STMIA instruction since
+ * memory access is disabled once these registers are written.	The
+ * last register written re-enables memory access.  For more info see
+ * the user's manual for the S3C4510B, available from Samsung's web
+ * site.  Search for part number "S3C4510B".
+ *
+ ***********************************************************************/
+
+.globl memsetup
+memsetup:
+
+	/* preserve the temp register (r12 AKA ip) and remap it. */
+	ldr r1, =SRAM_BASE+0xC
+	add r0, r12, #0x01000000
+	str r0, [r1]
+
+	/* remap the link register for when we return */
+	add lr, lr, #0x01000000
+
+	/* store a short program in the on chip SRAM, which is
+	 * unaffected when remapping memory.  Note the cache must be
+	 * disabled for the on chip SRAM to be available.
+	 */
+	ldr r1, =SRAM_BASE
+	ldr r0, =0xe8801ffe  /* stmia r0, {r1-r12} */
+	str r0, [r1]
+	add r1, r1, #4
+	ldr r0, =0xe59fc000  /* ldr r12, [pc, #0]  */
+	str r0, [r1]
+	add r1, r1, #4
+	ldr r0, =0xe1a0f00e  /* mov pc, lr	   */
+	str r0, [r1]
+
+	adr   r0, memory_map_data
+	ldmia r0, {r1-r12}
+	ldr   r0, =REG_EXTDBWTH
+
+	ldr pc, =SRAM_BASE
+
+.globl reset_cpu
+reset_cpu:
+	/*
+	 * reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to
+	 * address 0x0.	 We accomplish this by storing a few
+	 * instructions into the on chip SRAM (8KB) and run from
+	 * there.  Note the cache must be disabled for the on chip
+	 * SRAM to be available.
+	 *
+	 * load r2 with REG_ROMCON0
+	 * load r3 with 0x12040060	   configure FLASH bank 0 @ 0x00000000
+	 * load r4 with REG_DRAMCON0
+	 * load r5 with 0x08000380	   configure   RAM bank 0 @ 0x01000000
+	 * load r6 with REG_REFEXTCON
+	 * load r7 with 0x9c218360
+	 * load r8 with 0x0
+	 * store str r3,[r2] @ SRAM_BASE
+	 * store str r5,[r4] @ SRAM_BASE + 0x4
+	 * store str r7,[r6] @ SRAM_BASE + 0x8
+	 * store mov pc,r8   @ SRAM_BASE + 0xC
+	 * mov pc, SRAM_BASE
+	 *
+	 */
+
+	/* disable cache */
+	ldr r0, =REG_SYSCFG
+	ldr r1, =0x83ffffa0	/* cache-disabled  */
+	str r1, [r0]
+
+	ldr r2, =REG_ROMCON0
+	ldr r3, =0x02000060	/* Bank0 2MB FLASH   @ 0x00000000 */
+	ldr r4, =REG_DRAMCON0
+	ldr r5, =0x18040380	/* DRAM0 8MB SRAM    @ 0x01000000 */
+	ldr r6, =REG_REFEXTCON
+	ldr r7, =0xce278360
+	ldr r8, =0x00000000
+	ldr r1, =SRAM_BASE
+	ldr r0, =0xe5823000	/* str	r3, [r2] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+4
+	ldr r0, =0xe5845000	/* str	r5, [r4] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+8
+	ldr r0, =0xe5867000	/* str	r7, [r6] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+0xC
+	ldr r0, =0xe1a0f008	/* mov	pc, r8	 */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE
+	mov pc, r1
+
+	/* never return */
+
+/************************************************************************
+ * Below are twelve 32-bit values for the twelve memory registers of
+ * the system manager, starting with register REG_EXTDBWTH.
+ ***********************************************************************/
+memory_map_data:
+	.long 0x00f03005     /* memory widths */
+	.long 0x12040060     /* Bank0 2MB FLASH	  @ 0x01000000 */
+	.long 0x22080060     /* Bank1 512KB FLASH @ 0x02000000 */
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x08000380     /* DRAM0 8MB SRAM	  @ 0x00000000 */
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x9c218360     /* enable memory */
--- a/board/evb4510/u-boot.lds
+++ b/board/evb4510/u-boot.lds
@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  cpu/arm720t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+				  /* Stabs debugging sections.	  */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
--- a/board/fads/config.mk
+++ b/board/fads/config.mk
@ -24,8 +24,8 @@
 #

 #
-# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and DUET
-# (MPC87x/88x) ADS boards
+# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and
+# MPC885ADS boards
 #

 TEXT_BASE = 0xFE000000
--- a/board/fads/fads.c
+++ b/board/fads/fads.c
@ -26,12 +26,13 @@
 #include <config.h>
 #include <common.h>
 #include <mpc8xx.h>
+#include <pcmcia.h>

 #define	_NOT_USED_	0xFFFFFFFF

 /* ========================================================================= */

-#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */
+#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */

 #if defined(CONFIG_DRAM_50MHZ)
 /* 50MHz tables */
@ -290,7 +291,7 @@ static void _dramdisable(void)

 	/* maybe we should turn off upma here or something */
 }
-#endif /* !CONFIG_DUET_ADS */
+#endif /* !CONFIG_MPC885ADS */

 /* ========================================================================= */

@ -604,7 +605,7 @@ long int initdram (int board_type)
 	uint sdramsz = 0;	/* size of sdram in Mbytes */
 	uint base = 0;		/* base of dram in bytes */
 	uint m = 0;		/* size of dram in Mbytes */
-#ifndef CONFIG_DUET_ADS
+#ifndef CONFIG_MPC885ADS
 	uint k, s;
 #endif

@ -614,7 +615,7 @@ long int initdram (int board_type)
 		printf ("(%u MB SDRAM) ", sdramsz);
 	}
 #endif
-#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */
+#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
 	k = (*((uint *) BCSR2) >> 23) & 0x0f;

 	switch (k & 0x3) {
@ -665,7 +666,7 @@ long int initdram (int board_type)
 		_dramdisable ();
 		m = 0;
 	}
-#endif /* !CONFIG_DUET_ADS */
+#endif /* !CONFIG_MPC885ADS */
 	m += sdramsz;				/* add sdram size to total */

 	return (m << 20);
@ -734,8 +735,8 @@ int checkboard (void)

 #if defined(CONFIG_MPC86xADS)
 	puts ("MPC86xADS");
-#elif defined(CONFIG_DUET_ADS)
-	puts ("DUET ADS");
+#elif defined(CONFIG_MPC885ADS)
+	puts ("MPC885ADS");
 	r = 0; /* I've got NR (No Revision) board */
 #elif defined(CONFIG_FADS)
 	puts ("FADS");
@ -759,7 +760,7 @@ int checkboard (void)
 	case 0x03:
 		puts ("B \n");
 		break;
-#elif defined(CONFIG_DUET_ADS)
+#elif defined(CONFIG_MPC885ADS)
 	case 0x00:
 		puts ("NR\n");
 		break;
@ -790,7 +791,7 @@ volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
 int pcmcia_init(void)
 {
 	volatile pcmconf8xx_t	*pcmp;
-	uint v, slota, slotb;
+	uint v, slota = 0, slotb = 0;

 	/*
 	** Enable the PCMCIA for a Flash card.
@ -805,10 +806,10 @@ int pcmcia_init(void)
 	/* Set all slots to zero by default. */
 	pcmp->pcmc_pgcra = 0;
 	pcmp->pcmc_pgcrb = 0;
-#ifdef PCMCIA_SLOT_A
+#ifdef CONFIG_PCMCIA_SLOT_A
 	pcmp->pcmc_pgcra = 0x40;
 #endif
-#ifdef PCMCIA_SLOT_B
+#ifdef CONFIG_PCMCIA_SLOT_B
 	pcmp->pcmc_pgcrb = 0x40;
 #endif

@ -817,17 +818,17 @@ int pcmcia_init(void)

 	/* Check if any PCMCIA card is plugged in. */

+#ifdef CONFIG_PCMCIA_SLOT_A
 	slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
 	slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
+#endif

 	if (!(slota || slotb)) {
 		printf("No card present\n");
-#ifdef PCMCIA_SLOT_A
 		pcmp->pcmc_pgcra = 0;
-#endif
-#ifdef PCMCIA_SLOT_B
 		pcmp->pcmc_pgcrb = 0;
-#endif
 		return -1;
 	}
 	else
@ -908,9 +909,10 @@ int pcmcia_init(void)

 	udelay(20);

-#ifdef PCMCIA_SLOT_A
+#ifdef CONFIG_PCMCIA_SLOT_A
 	pcmp->pcmc_pgcra = 0;
-#elif PCMCIA_SLOT_B
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
 	pcmp->pcmc_pgcrb = 0;
 #endif

--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@ -48,9 +48,6 @@
 * | ...                   |                                 v
 *
 *****************************************************************************/
-/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
-/* in general, we always know this for FADS+new ADS anyway */
-#define CONFIG_8xx_GCLK_FREQ     ((CFG_8XX_XIN) * (CFG_8XX_FACT))

 #if 0
 #define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
@ -66,6 +63,7 @@
    "bootm"

 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_BZIP2	 /* include support for bzip2 compressed images */

 /*
 * New MPC86xADS and Duet provide two Ethernet connectivity options:
@ -90,11 +88,13 @@
 #endif

 #ifndef CONFIG_COMMANDS
-#define CONFIG_COMMANDS	(CONFIG_CMD_DFL  \
-			 | CFG_CMD_DHCP  \
-			 | CFG_CMD_IMMAP \
-			 | CFG_CMD_MII   \
-			 | CFG_CMD_PING  \
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL   \
+			 | CFG_CMD_DHCP   \
+			 | CFG_CMD_IMMAP  \
+			 | CFG_CMD_JFFS2  \
+			 | CFG_CMD_MII    \
+			 | CFG_CMD_PCMCIA \
+			 | CFG_CMD_PING   \
 			)
 #endif /* !CONFIG_COMMANDS */

@ -146,7 +146,7 @@
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
 #define	CFG_SDRAM_BASE		0x00000000
-#if defined(CONFIG_MPC86xADS) || defined(CONFIG_DUET_ADS) /* New ADS or Duet */
+#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
 #define	CFG_SDRAM_SIZE		0x00800000      	/* 8 Mbyte */
 #elif defined(CONFIG_FADS)				/* Old/new FADS */
 #define	CFG_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
@ -167,14 +167,24 @@
 * the maximum mapped by the Linux kernel during initialization.
 */
 #define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
+
+#ifdef CONFIG_BZIP2
+#define	CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
+#else
+#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#endif /* CONFIG_BZIP2 */
+
 /*-----------------------------------------------------------------------
 * Flash organization
 */
-#define CFG_FLASH_BASE		TEXT_BASE
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define CFG_FLASH_BASE		CFG_MONITOR_BASE
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte	*/

-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	16      /* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
@ -184,9 +194,14 @@
 #define CFG_ENV_OFFSET		CFG_ENV_SECT_SIZE
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment		*/

-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
-#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#define	CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR  4
+#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */

 /*-----------------------------------------------------------------------
 * Cache Configuration
@ -248,7 +263,16 @@
 #define SCCR_MASK	SCCR_EBDF11
 #define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)

- /*-----------------------------------------------------------------------
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		14-22
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control
+ */
+#ifndef CFG_PLPRCR
+#define CFG_PLPRCR	PLPRCR_TEXPS
+#endif
+
+/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
@ -339,6 +363,7 @@
 #define BCSR1_PCCVCCON		 BCSR1_PCCVCC0

 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_FLASH_PD_SHIFT     28
 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 #define BCSR2_DRAM_PD_SHIFT      23
 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
@ -407,6 +432,20 @@
 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 #endif /* CONFIG_MPC850 */

+/* BSCR5 exists on MPC86xADS and Duet ADS only */
+
+#define CFG_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)
+
+#define BCSR5			(CFG_PHYDEV_ADDR + 0x300)
+
+#define BCSR5_MII2_EN		0x40
+#define BCSR5_MII2_RST		0x20
+#define BCSR5_T1_RST		0x10
+#define BCSR5_ATM155_RST	0x08
+#define BCSR5_ATM25_RST		0x04
+#define BCSR5_MII1_EN		0x02
+#define BCSR5_MII1_RST		0x01
+
 /* We don't use the 8259.
 */
 #define NR_8259_INTS	0
@ -419,10 +458,6 @@
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 */
-#if !defined(CONFIG_MPC823) && !defined(CONFIG_MPC850)
-#define PCMCIA_SLOT_A 1
-#endif
-
 #define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
 #define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
--- a/board/fads/flash.c
+++ b/board/fads/flash.c
@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>

-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */

 #if defined(CFG_ENV_IS_IN_FLASH)
 # ifndef  CFG_ENV_ADDR
@ -38,124 +38,103 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 # endif
 #endif

+#define QUAD_ID(id)	((((ulong)(id) & 0xFF) << 24) | \
+			 (((ulong)(id) & 0xFF) << 16) | \
+			 (((ulong)(id) & 0xFF) << 8)  | \
+			 (((ulong)(id) & 0xFF) << 0)    \
+			)
+
 /*-----------------------------------------------------------------------
 * Functions
 */
 static ulong flash_get_size (vu_long * addr, flash_info_t * info);
 static int write_word (flash_info_t * info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t * info);

 /*-----------------------------------------------------------------------
 */
-
 unsigned long flash_init (void)
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long total_size;
-	unsigned long size_b0, size_b1;
+	vu_long *bcsr = (vu_long *)BCSR_ADDR;
+	unsigned long pd_size, total_size, bsize, or_am;
 	int i;

 	/* Init: no FLASHes known */
 	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].size = 0;
+		flash_info[i].sector_count = 0;
+		flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */
+	}
+
+	switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) {
+	case 2:
+	case 4:
+	case 6:
+		pd_size = 0x800000;
+		or_am = 0xFF800000;
+		break;
+
+	case 5:
+	case 7:
+		pd_size = 0x400000;
+		or_am = 0xFFC00000;
+		break;
+
+	case 8:
+		pd_size = 0x200000;
+		or_am = 0xFFE00000;
+		break;
+
+	default:
+		pd_size = 0;
+		or_am = 0xFFE00000;
+		printf("## Unsupported flash detected by BCSR: 0x%08X\n", bcsr[2]);
 	}

 	total_size = 0;
-	size_b0 = 0xffffffff;
-
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
-		size_b1 =
-			flash_get_size ((vu_long *) (CFG_FLASH_BASE +
-						     total_size),
-					&flash_info[i]);
+	for (i = 0; i < CFG_MAX_FLASH_BANKS && total_size < pd_size; ++i) {
+		bsize = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size),
+				       &flash_info[i]);

 		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", i, size_b1, size_b1 >> 20);
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, bsize, bsize >> 20);
 		}

-		/* Is this really needed ? - LP */
-		if (size_b1 > size_b0) {
-			printf ("## ERROR: Bank %d (0x%08lx = %ld MB) > Bank %d (0x%08lx = %ld MB)\n", i, size_b1, size_b1 >> 20, i - 1, size_b0, size_b0 >> 20);
-			goto out_error;
-		}
-		size_b0 = size_b1;
-		total_size += size_b1;
+		total_size += bsize;
 	}

-	/* Compute the Address Mask */
-	for (i = 0; (total_size >> i) != 0; ++i) {
-	}
-	i--;
-
-	if (total_size != (1 << i)) {
-		printf ("## WARNING: Total FLASH size (0x%08lx = %ld MB) is not a power of 2\n", total_size, total_size >> 20);
+	if (total_size != pd_size) {
+		printf("## Detected flash size %lu conflicts with PD data %lu\n",
+		       total_size, pd_size);
 	}

 	/* Remap FLASH according to real size */
-	memctl->memc_or0 =
-		((((unsigned long) ~1) << i) & OR_AM_MSK) |
-		CFG_OR_TIMING_FLASH;
-	memctl->memc_br0 = CFG_BR0_PRELIM;
-
-	total_size = 0;
+	memctl->memc_or0 = or_am | CFG_OR_TIMING_FLASH;

 	for (i = 0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) {
-		/* Re-do sizing to get full correct info */
-		/* Why ? - LP */
-		size_b1 =
-			flash_get_size ((vu_long *) (CFG_FLASH_BASE +
-						     total_size),
-					&flash_info[i]);
-
-		/* This is done by flash_get_size - LP */
-		/* flash_get_offsets (CFG_FLASH_BASE + total_size, &flash_info[i]); */
-
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 		/* monitor protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-			       CFG_MONITOR_BASE,
-			       CFG_MONITOR_BASE + monitor_flash_len - 1,
-			       &flash_info[i]);
+		if (CFG_MONITOR_BASE >= flash_info[i].start[0])
+			flash_protect (FLAG_PROTECT_SET,
+				       CFG_MONITOR_BASE,
+				       CFG_MONITOR_BASE + monitor_flash_len - 1,
+				       &flash_info[i]);
 #endif

 #ifdef	CFG_ENV_IS_IN_FLASH
 		/* ENV protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-			       CFG_ENV_ADDR,
-			       CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-			       &flash_info[i]);
+		if (CFG_ENV_ADDR >= flash_info[i].start[0])
+			flash_protect (FLAG_PROTECT_SET,
+				       CFG_ENV_ADDR,
+				       CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+				       &flash_info[i]);
 #endif
-
-		total_size += size_b1;
 	}

-	return (total_size);
-
-      out_error:
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].sector_count = -1;
-		flash_info[i].size = 0;
-	}
-
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040
-	    || (info->flash_id & FLASH_TYPEMASK) == FLASH_AM080) {
-		/* set sector offsets for uniform sector type   */
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00040000);
-		}
-	}
+	return total_size;
 }

 /*-----------------------------------------------------------------------
@ -235,48 +214,26 @@ void flash_print_info (flash_info_t * info)
 	}

 	printf ("\n");
-	return;
 }

 /*-----------------------------------------------------------------------
+ * The following code can not run from flash!
 */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
 static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 {
 	short i;

-#if 0
-	ulong base = (ulong) addr;
-#endif
-	uchar value;
-
 	/* Write auto select command: read Manufacturer ID */
-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-#else
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
 	addr[0x0555] = 0x90909090;
-#endif

-	value = addr[0];
-
-	switch (value + (value << 16)) {
-	case AMD_MANUFACT:
+	switch (addr[0]) {
+	case QUAD_ID(AMD_MANUFACT):
 		info->flash_id = FLASH_MAN_AMD;
 		break;

-	case FUJ_MANUFACT:
+	case QUAD_ID(FUJ_MANUFACT):
 		info->flash_id = FLASH_MAN_FUJ;
 		break;

@ -287,21 +244,20 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		break;
 	}

-	value = addr[1];	/* device ID            */
-
-	switch (value) {
-	case AMD_ID_F040B:
+	switch (addr[1]) {	/* device ID            */
+	case QUAD_ID(AMD_ID_F040B):
+	case QUAD_ID(AMD_ID_LV040B):
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x00200000;
 		break;		/* => 2 MB              */

-	case AMD_ID_F080B:
+	case QUAD_ID(AMD_ID_F080B):
 		info->flash_id += FLASH_AM080;
 		info->sector_count = 16;
 		info->size = 0x00400000;
 		break;		/* => 4 MB              */
-
+#if 0
 	case AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
@ -337,7 +293,7 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		info->sector_count = 35;
 		info->size = 0x00400000;
 		break;		/* => 4 MB              */
-#if 0				/* enable when device IDs are available */
+
 	case AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 67;
@ -349,11 +305,10 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		info->sector_count = 67;
 		info->size = 0x00800000;
 		break;		/* => 8 MB              */
-#endif
+#endif /* 0 */
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);	/* => no or unknown flash */
-
 	}

 #if 0
@ -378,7 +333,9 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		}
 	}
 #else
-	flash_get_offsets ((ulong) addr, info);
+	/* set sector offsets for uniform sector type */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = (ulong)addr + (i * 0x00040000);
 #endif

 	/* check for protected sectors */
@ -389,25 +346,16 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		info->protect[i] = addr[2] & 1;
 	}

-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
 	if (info->flash_id != FLASH_UNKNOWN) {
 		addr = (volatile unsigned long *) info->start[0];
-#if 0
-		*addr = 0x00F000F0;	/* reset bank */
-#else
 		*addr = 0xF0F0F0F0;	/* reset bank */
-#endif
 	}

 	return (info->size);
 }

-
 /*-----------------------------------------------------------------------
 */
-
 int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
 	vu_long *addr = (vu_long *) (info->start[0]);
@ -420,13 +368,13 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		} else {
 			printf ("- no sectors to erase\n");
 		}
-		return 1;
+		return ERR_INVAL;
 	}

 	if ((info->flash_id == FLASH_UNKNOWN) ||
 	    (info->flash_id > FLASH_AMD_COMP)) {
 		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
+		return ERR_UNKNOWN_FLASH_TYPE;
 	}

 	prot = 0;
@ -447,29 +395,17 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();

-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-#else
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
 	addr[0x0555] = 0x80808080;
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
-#endif

 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
 			addr = (vu_long *) (info->start[sect]);
-#if 0
-			addr[0] = 0x00300030;
-#else
 			addr[0] = 0x30303030;
-#endif
 			l_sect = sect;
 		}
 	}
@ -490,15 +426,11 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	start = get_timer (0);
 	last = start;
 	addr = (vu_long *) (info->start[l_sect]);
-#if 0
-	while ((addr[0] & 0x00800080) != 0x00800080)
-#else
 	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
-#endif
 	{
 		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
-			return 1;
+			return ERR_TIMOUT;
 		}
 		/* show that we're waiting */
 		if ((now - last) > 1000) {	/* every second */
@ -510,13 +442,10 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
      DONE:
 	/* reset to read mode */
 	addr = (volatile unsigned long *) info->start[0];
-#if 0
-	addr[0] = 0x00F000F0;	/* reset bank */
-#else
 	addr[0] = 0xF0F0F0F0;	/* reset bank */
-#endif

 	printf (" done\n");
+
 	return 0;
 }

@ -526,7 +455,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 * 1 - write timeout
 * 2 - Flash not erased
 */
-
 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	ulong cp, wp, data;
@ -605,20 +533,14 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)

 	/* Check if Flash is (sufficiently) erased */
 	if ((*((vu_long *) dest) & data) != data) {
-		return (2);
+		return ERR_NOT_ERASED;
 	}
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();

-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-#else
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
 	addr[0x0555] = 0xA0A0A0A0;
-#endif

 	*((vu_long *) dest) = data;

@ -628,18 +550,11 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)

 	/* data polling for D7 */
 	start = get_timer (0);
-#if 0
-	while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080))
-#else
 	while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080))
-#endif
 	{
 		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
-			return (1);
+			return ERR_TIMOUT;
 		}
 	}
 	return (0);
 }
-
-/*-----------------------------------------------------------------------
- */
--- a/board/fads/u-boot.lds
+++ b/board/fads/u-boot.lds
@ -52,7 +52,7 @@ SECTIONS
  {
    cpu/mpc8xx/start.o		(.text)

-    . = DEFINED(env_offset) ? env_offset : .;
+    /*. = DEFINED(env_offset) ? env_offset : .;*/
    common/environment.o	(.ppcenv)

    *(.text)
--- a/Show More
+++ b/Show More