* Patch by Detlev Zundel, 08 Sep 2004:

Update etags build target

* Improve NetConsole support: add support for broadcast destination
  address and buffered input.

* Cleanup compiler warnings for GCC 3.3.x and later

* Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch

CHANGELOG

@@ -2,6 +2,18 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Patch by Detlev Zundel, 08 Sep 2004:
+  Update etags build target
+
+* Improve NetConsole support: add support for broadcast destination
+  address and buffered input.
+
+* Cleanup compiler warnings for GCC 3.3.x and later
+
+* Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch
+
+* Add support for IDS "NC650" board
+
 * Add automatic update support for LWMON board
 
 * Clear Block Lock-Bits when erasing flash on LWMON board.
@@ -16,7 +28,7 @@ Changes since U-Boot 1.1.1:
 * Patch by Mark Jonas, 13 July 2004:
   - Total5200 LCD now run in little endian mode. Endianess conversion
     is done in hardware.
-  - Removed last reference to "console" environment variable. 
+  - Removed last reference to "console" environment variable.
 
 * Patches by Lars Munch, 12 Jul 2004:
   - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk

MAINTAINERS

@@ -58,13 +58,14 @@ Torsten Demke <torsten.demke@fci.com>
 
 Wolfgang Denk <wd@denx.de>
 
+	IceCube_5100		MGT5100
+	IceCube_5200		MPC5200
+
 	AMX860			MPC860
 	ETX094			MPC850
 	FPS850L			MPC850
 	FPS860L			MPC860
 	ICU862			MPC862
-	IceCube_5100		MGT5100
-	IceCube_5200		MPC5200
 	IP860			MPC860
 	IVML24			MPC860
 	IVML24_128		MPC860
@@ -74,6 +75,7 @@ Wolfgang Denk <wd@denx.de>
 	IVMS8_256		MPC860
 	LANTEC			MPC850
 	LWMON			MPC823
+	NC650			MPC852
 	R360MPI			MPC823
 	RMU			MPC850
 	RRvision		MPC823

Makefile

@@ -176,6 +176,9 @@ tags:
 
 etags:
 		etags -a `find $(SUBDIRS) include \
+				lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
+				fs/cramfs fs/fat fs/fdos fs/jffs2 \
+				net disk rtc dtt drivers drivers/sk98lin common \
 			\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
 
 System.map:	u-boot
@@ -532,6 +535,9 @@ NETTA2_config:		unconfig
 		 }
 	@./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
 
+NC650_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx nc650
+
 NX823_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx nx823
 
@@ -1467,7 +1473,7 @@ clean:
 	      examples/eepro100_eeprom examples/sched \
 	      examples/mem_to_mem_idma2intr examples/82559_eeprom
 	rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
-	rm -f tools/mpc86x_clk
+	rm -f tools/mpc86x_clk tools/ncb
 	rm -f tools/easylogo/easylogo tools/bmp_logo
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv

board/Marvell/db64360/db64360.c

@@ -549,18 +549,18 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 #if defined (CFG_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaa,
-	0xcccccccccccccccc,
-	0xf0f0f0f0f0f0f0f0,
-	0xff00ff00ff00ff00,
-	0xffff0000ffff0000,
-	0xffffffff00000000,
-	0x00000000ffffffff,
-	0x0000ffff0000ffff,
-	0x00ff00ff00ff00ff,
-	0x0f0f0f0f0f0f0f0f,
-	0x3333333333333333,
-	0x5555555555555555
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
 };
 
 /*********************************************************************/

board/Marvell/db64460/db64460.c

@@ -549,18 +549,18 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 #if defined (CFG_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaa,
-	0xcccccccccccccccc,
-	0xf0f0f0f0f0f0f0f0,
-	0xff00ff00ff00ff00,
-	0xffff0000ffff0000,
-	0xffffffff00000000,
-	0x00000000ffffffff,
-	0x0000ffff0000ffff,
-	0x00ff00ff00ff00ff,
-	0x0f0f0f0f0f0f0f0f,
-	0x3333333333333333,
-	0x5555555555555555
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
 };
 
 /*********************************************************************/

board/dave/PPChameleonEVB/PPChameleonEVB.c

@@ -32,7 +32,7 @@
 /* ------------------------------------------------------------------------- */
 
 /* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);
 
 int board_early_init_f (void)
 {
@@ -104,7 +104,7 @@ int misc_init_r (void)
 	unsigned long cntrl0Reg;
 
 	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}

board/esd/ash405/ash405.c

@@ -47,7 +47,7 @@ const unsigned char fpgadata[] =
 
 
 /* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);
 
 
 int board_early_init_f (void)
@@ -102,7 +102,7 @@ int misc_init_r (void)
 	int i;
 
 	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}

board/esd/cpci405/cpci405.c

@@ -54,7 +54,7 @@ const unsigned char fpgadata[] =
 
 /* Prototypes */
 int cpci405_version(void);
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);
 
 
 int board_early_init_f (void)
@@ -259,7 +259,7 @@ int misc_init_r (void)
 		mtdcr(cntrl0, cntrl0Reg | 0x00300000);
 
 		dst = malloc(CFG_FPGA_MAX_SIZE);
-		if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+		if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 			printf ("GUNZIP ERROR - must RESET board to recover\n");
 			do_reset (NULL, 0, 0, NULL);
 		}

board/esd/pci405/pci405.c

@@ -50,7 +50,7 @@ const unsigned char fpgadata[] =
 
 
 /* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);
 
 
 int board_early_init_f (void)
@@ -116,7 +116,7 @@ int misc_init_r (void)
 	 */
 
 	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}

board/esd/plu405/plu405.c

@@ -47,7 +47,7 @@ const unsigned char fpgadata[] =
 
 
 /* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);
 
 
 int board_early_init_f (void)
@@ -101,7 +101,7 @@ int misc_init_r (void)
 
 #if 1 /* test-only */
 	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}

board/esd/voh405/voh405.c

@@ -47,7 +47,7 @@ const unsigned char fpgadata[] =
 
 
 /* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);
 
 
 int board_early_init_f (void)
@@ -102,7 +102,7 @@ int misc_init_r (void)
 	int i;
 
 	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}

board/gw8260/gw8260.c

@@ -259,18 +259,18 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 #if defined (CFG_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaa,
-	0xcccccccccccccccc,
-	0xf0f0f0f0f0f0f0f0,
-	0xff00ff00ff00ff00,
-	0xffff0000ffff0000,
-	0xffffffff00000000,
-	0x00000000ffffffff,
-	0x0000ffff0000ffff,
-	0x00ff00ff00ff00ff,
-	0x0f0f0f0f0f0f0f0f,
-	0x3333333333333333,
-	0x5555555555555555
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
 };
 
 /*********************************************************************/

board/lwmon/lwmon.c

@@ -643,7 +643,7 @@ static uchar kbd_command_prefix[] = "key_cmd";
 static int compare_magic (uchar *kbd_data, uchar *str)
 {
 	uchar compare[KEYBD_DATALEN-1];
-	uchar *nxt;
+	char *nxt;
 	int i;
 
 	/* Don't include modifier byte */
@@ -655,7 +655,7 @@ static int compare_magic (uchar *kbd_data, uchar *str)
 
 		c = (uchar) simple_strtoul (str, (char **) (&nxt), 16);
 
-		if (str == nxt) {	/* invalid character */
+		if (str == (uchar *)nxt) {	/* invalid character */
 			break;
 		}
 

board/mpl/common/common_util.c

@@ -46,7 +46,7 @@
 #define FIRM_START 0xFFF00000
 #endif
 
-extern int gunzip(void *, int, uchar *, int *);
+extern int gunzip(void *, int, uchar *, unsigned long *);
 extern int mem_test(ulong start, ulong ramsize, int quiet);
 
 #define I2C_BACKUP_ADDR 0x7C00		/* 0x200 bytes for backup */
@@ -224,7 +224,7 @@ mpl_prg_image(uchar *ld_addr)
 		switch (hdr->ih_comp) {
 		case IH_COMP_GZIP:
 			puts("Uncompressing (GZIP) ... ");
-			rc = gunzip ((void *)(buf), IMAGE_SIZE, data, (int *)&len);
+			rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len);
 			if (rc != 0) {
 				puts("GUNZIP ERROR\n");
 				free(buf);

board/nc650/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/nc650/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# NC650 board
+#
+
+TEXT_BASE = 0x40700000

board/nc650/flash.c

@@ -0,0 +1,542 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef DEBUG
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
+#define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				      OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH8
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#elif FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#else /* FLASH_PORT_WIDTH8 */
+#define FLASH_PORT_WIDTH	uchar
+#define FLASH_PORT_WIDTHV	vu_char
+#endif
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPWV * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
+	int scy, trlx, flash_or_timing, clk_diff;
+
+	DECLARE_GLOBAL_DATA_PTR;
+
+	scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+		trlx = OR_TRLX;
+		scy *= 2;
+	} else
+		trlx = 0;
+
+		/* We assume that each 10MHz of bus clock require 1-clk SCY
+		 * adjustment.
+		 */
+	clk_diff = (gd->bus_clk / 1000000) - 50;
+
+		/* We need proper rounding here. This is what the "+5" and "-5"
+		 * are here for.
+		 */
+	if (clk_diff >= 0)
+		scy += (clk_diff + 5) / 10;
+	else
+		scy += (clk_diff - 5) / 10;
+
+		/* For bus frequencies above 50MHz, we want to use relaxed
+		 * timing (OR_TRLX).
+		 */
+	if (gd->bus_clk >= 50000000)
+		trlx = OR_TRLX;
+	else
+		trlx = 0;
+
+	if (trlx)
+		scy /= 2;
+
+	if (scy > 0xf)
+		scy = 0xf;
+	if (scy < 1)
+		scy = 1;
+
+	flash_or_timing = (scy << 4) | trlx |
+			  (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+#endif
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	/* Remap FLASH according to real size */
+#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+#else
+	memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
+#endif
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				&flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPWV * addr, flash_info_t * info)
+{
+	FPW value;
+
+	addr[0] = (FPW) 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+#ifdef FLASH_PORT_WIDTH8
+	value = addr[2];			/* device ID        */
+#else
+	value = addr[1];			/* device ID        */
+#endif
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 4 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+				rcode = 1;
+				break;
+			    }
+
+			    /* show that we're waiting */
+			    if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			    }
+			}
+
+			*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+
+	int i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#elif defined(FLASH_PORT_WIDTH32)
+	wp = (addr & ~3);
+	port_width = 4;
+#else
+	wp = addr;
+	port_width = 1;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}

board/nc650/nc650.c

@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/*
+ *  Memory Controller Using
+ *
+ *  CS0 - Flash memory            (0x40000000)
+ *  CS3 - SDRAM                   (0x00000000}
+ */
+
+/* ------------------------------------------------------------------------- */
+
+#define _not_used_	0xffffffff
+
+const uint sdram_table[] = {
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* MRS initialization (offset 5) */
+
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: NC650\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
+	unsigned long reg;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 1 to the SDRAM bank at
+	 * preliminary address - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 0 */
+	udelay (200);
+	memctl->memc_mcr = 0x80006230;	/* SDRAM bank 0 - execute twice */
+	udelay (200);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
+					  SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	if (size8 < size9) {
+		size_b0 = size9;
+	} else {
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+	}
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks.
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+
+	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;					/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}

board/nc650/u-boot.lds

@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/nc650/u-boot.lds.debug

@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/trab/memory.c

@@ -206,19 +206,20 @@ static void move64(unsigned long long *src, unsigned long long *dest)
  *
  */
 const static unsigned long long pattern[] = {
-    0xaaaaaaaaaaaaaaaa,
-    0xcccccccccccccccc,
-    0xf0f0f0f0f0f0f0f0,
-    0xff00ff00ff00ff00,
-    0xffff0000ffff0000,
-    0xffffffff00000000,
-    0x00000000ffffffff,
-    0x0000ffff0000ffff,
-    0x00ff00ff00ff00ff,
-    0x0f0f0f0f0f0f0f0f,
-    0x3333333333333333,
-    0x5555555555555555};
-const unsigned long long otherpattern = 0x0123456789abcdef;
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
+};
+const unsigned long long otherpattern = 0x0123456789abcdefULL;
 
 
 static int memory_post_dataline(unsigned long long * pmem)

common/cmd_bootm.c

@@ -73,7 +73,7 @@
 # define CHUNKSZ (64 * 1024)
 #endif
 
-int  gunzip (void *, int, unsigned char *, int *);
+int  gunzip (void *, int, unsigned char *, unsigned long *);
 
 static void *zalloc(void *, unsigned, unsigned);
 static void zfree(void *, void *, unsigned);
@@ -326,7 +326,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	case IH_COMP_GZIP:
 		printf ("   Uncompressing %s ... ", name);
 		if (gunzip ((void *)ntohl(hdr->ih_load), unc_len,
-			    (uchar *)data, (int *)&len) != 0) {
+			    (uchar *)data, &len) != 0) {
 			puts ("GUNZIP ERROR - must RESET board to recover\n");
 			SHOW_BOOT_PROGRESS (-6);
 			do_reset (cmdtp, flag, argc, argv);
@@ -1239,7 +1239,7 @@ static void zfree(void *x, void *addr, unsigned nb)
 
 #define DEFLATED	8
 
-int gunzip(void *dst, int dstlen, unsigned char *src, int *lenp)
+int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp)
 {
 	z_stream s;
 	int r, i, flags;

common/cmd_jffs2.c

@@ -257,6 +257,12 @@ do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 
 }
+
+U_BOOT_CMD(
+	chpart,	2,	0,	do_jffs2_chpart,
+	"chpart\t- change active partition\n",
+	"    - change active partition\n"
+);
 #endif	/* CFG_JFFS_SINGLE_PART */
 
 /***************************************************/
@@ -282,10 +288,4 @@ U_BOOT_CMD(
 	"    - list files in a directory.\n"
 );
 
-U_BOOT_CMD(
-	chpart,	2,	0,	do_jffs2_chpart,
-	"chpart\t- change active partition\n",
-	"    - change active partition\n"
-);
-
 #endif /* CFG_CMD_JFFS2 */

cpu/mpc8xx/speed.c

@@ -172,7 +172,7 @@ unsigned long measure_gclk(void)
 
 #endif
 
-#if !defined(CONFIG_TQM866M)
+#if !defined(CONFIG_TQM866M) && !defined(CONFIG_NC650)
 
 /*
  * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ

doc/README.NetConsole

@@ -6,6 +6,12 @@ serial and network input/output devices by adjusting the 'stdin' and
 set either of these variables to "nc". Input and output can be
 switched independently.
 
+We use an environment variable 'ncip' to set the IP address and the
+port of the destination. The format is <ip_addr>:<port>. If <port> is
+omitted, the value of 6666 is used. If the env var doesn't exist, the
+broadcast address and port 6666 are used. If it is set to an IP
+address of 0 (or 0.0.0.0) then no messages are sent to the network.
+
 On the host side, please use this script to access the console:
 
 +++++++++++++++++++++++++++++++++++++++++++
@@ -19,6 +25,21 @@ nc -u ${TARGET_IP} 6666
 stty icanon echo intr ^C
 +++++++++++++++++++++++++++++++++++++++++++
 
+It turned out that 'netcat' couldn't be used to listen to broadcast
+packets. We developed our own tool 'ncb' (see tools directory) that
+listens to broadcast packets on a given port and dumps them to the
+standard output. use it as follows:
+
++++++++++++++++++++++++++++++++++++++++++++
+#! /bin/bash
+
+stty icanon echo intr ^T
+./ncb &
+nc -u mpc5200 6666
+stty icanon echo intr ^C
+kill 0
++++++++++++++++++++++++++++++++++++++++++++
+
 For Linux, the network-based console needs special configuration.
 Minimally, the host IP address needs to be specified. This can be
 done either via the kernel command line, or by passing parameters

drivers/i82365.c

@@ -429,7 +429,8 @@ static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
 	u_char map, ioctl;
 
 	map = io->map;
-	if ((map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) ||
+	/* comment out: comparison is always false due to limited range of data type */
+	if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
 		(io->stop < io->start))
 		return -1;
 	/* Turn off the window before changing anything */

drivers/netconsole.c

@@ -33,10 +33,17 @@
 #error define CONFIG_NET_MULTI to use netconsole
 #endif
 
-static uchar nc_buf = 0;	/* input buffer */
+static char input_buffer[512];
+static int input_size = 0;		/* char count in input buffer */
+static int input_offset = 0;		/* offset to valid chars in input buffer */
 static int input_recursion = 0;
 static int output_recursion = 0;
 static int net_timeout;
+static uchar nc_ether[6];		/* server enet address */
+static IPaddr_t nc_ip;			/* server ip */
+static short nc_port;			/* source/target port */
+static const char *output_packet;	/* used by first send udp */
+static int output_packet_len = 0;
 
 static void nc_wait_arp_handler (uchar * pkt, unsigned dest, unsigned src,
 				 unsigned len)
@@ -47,7 +54,7 @@ static void nc_wait_arp_handler (uchar * pkt, unsigned dest, unsigned src,
 static void nc_handler (uchar * pkt, unsigned dest, unsigned src,
 			unsigned len)
 {
-	if (nc_buf)
+	if (input_size)
 		NetState = NETLOOP_SUCCESS;	/* got input - quit net loop */
 }
 
@@ -58,23 +65,45 @@ static void nc_timeout (void)
 
 void NcStart (void)
 {
-	if (memcmp (NetServerEther, NetEtherNullAddr, 6)) {
+	if (!output_packet_len || memcmp (nc_ether, NetEtherNullAddr, 6)) {
 		/* going to check for input packet */
 		NetSetHandler (nc_handler);
 		NetSetTimeout (net_timeout, nc_timeout);
 	} else {
 		/* send arp request */
+		uchar *pkt;
 		NetSetHandler (nc_wait_arp_handler);
-		NetSendUDPPacket (NetServerEther, NetServerIP, 6665, 6666, 0);
+		pkt = (uchar *) NetTxPacket + NetEthHdrSize () + IP_HDR_SIZE;
+		memcpy (pkt, output_packet, output_packet_len);
+		NetSendUDPPacket (nc_ether, nc_ip, nc_port, nc_port, output_packet_len);
 	}
 }
 
 int nc_input_packet (uchar * pkt, unsigned dest, unsigned src, unsigned len)
 {
-	if (dest != 6666 || !len)
+	int end, chunk;
+
+	if (dest != nc_port || !len)
 		return 0;		/* not for us */
 
-	nc_buf = *pkt;
+	if (input_size == sizeof input_buffer)
+		return 1;		/* no space */
+	if (len > sizeof input_buffer - input_size)
+		len = sizeof input_buffer - input_size;
+
+	end = input_offset + input_size;
+	if (end > sizeof input_buffer)
+		end -= sizeof input_buffer;
+
+	chunk = len;
+	if (end + len > sizeof input_buffer) {
+		chunk = sizeof input_buffer - end;
+		memcpy(input_buffer, pkt + chunk, len - chunk);
+	}
+	memcpy (input_buffer + end, pkt, chunk);
+
+	input_size += len;
+
 	return 1;
 }
 
@@ -85,14 +114,23 @@ static void nc_send_packet (const char *buf, int len)
 	struct eth_device *eth;
 	int inited = 0;
 	uchar *pkt;
-
-	if (!memcmp (NetServerEther, NetEtherNullAddr, 6))
-		return;
+	uchar *ether;
+	IPaddr_t ip;
 
 	if ((eth = eth_get_dev ()) == NULL) {
 		return;
 	}
 
+	if (!memcmp (nc_ether, NetEtherNullAddr, 6)) {
+		if (eth->state == ETH_STATE_ACTIVE)
+			return;	/* inside net loop */
+		output_packet = buf;
+		output_packet_len = len;
+		NetLoop (NETCONS);	/* wait for arp reply and send packet */
+		output_packet_len = 0;
+		return;
+	}
+
 	if (eth->state != ETH_STATE_ACTIVE) {
 		if (eth_init (gd->bd) < 0)
 			return;
@@ -100,7 +138,9 @@ static void nc_send_packet (const char *buf, int len)
 	}
 	pkt = (uchar *) NetTxPacket + NetEthHdrSize () + IP_HDR_SIZE;
 	memcpy (pkt, buf, len);
-	NetSendUDPPacket (NetServerEther, NetServerIP, 6666, 6665, len);
+	ether = nc_ether;
+	ip = nc_ip;
+	NetSendUDPPacket (ether, ip, nc_port, nc_port, len);
 
 	if (inited)
 		eth_halt ();
@@ -108,10 +148,31 @@ static void nc_send_packet (const char *buf, int len)
 
 int nc_start (void)
 {
-	if (memcmp (NetServerEther, NetEtherNullAddr, 6))
-		return 0;
+	int netmask, our_ip;
 
-	return NetLoop (NETCONS);	/* wait for arp reply */
+	nc_port = 6666;		/* default port */
+
+	if (getenv ("ncip")) {
+		nc_ip = getenv_IPaddr ("ncip");
+		if (!nc_ip)
+			return -1;	/* ncip is 0.0.0.0 */
+		char *p = strchr (getenv ("ncip"), ':');
+		if (p)
+			nc_port = simple_strtoul (p + 1, NULL, 10);
+	} else
+		nc_ip = ~0;		/* ncip is not set */
+
+	our_ip = getenv_IPaddr ("ipaddr");
+	netmask = getenv_IPaddr ("netmask");
+
+	if (nc_ip == ~0 ||				/* 255.255.255.255 */
+	    ((netmask & our_ip) == (netmask & nc_ip) &&	/* on the same net */
+	    (netmask | nc_ip) == ~0))			/* broadcast to our net */
+		memset (nc_ether, 0xff, sizeof nc_ether);
+	else
+		memset (nc_ether, 0, sizeof nc_ether);	/* force arp request */
+
+	return 0;
 }
 
 void nc_putc (char c)
@@ -146,15 +207,18 @@ int nc_getc (void)
 	input_recursion = 1;
 
 	net_timeout = 0;	/* no timeout */
-	while (!nc_buf)
+	while (!input_size)
 		NetLoop (NETCONS);
 
 	input_recursion = 0;
 
-	uchar tmp = nc_buf;
+	uchar c = input_buffer[input_offset];
+	input_offset++;
+	if (input_offset >= sizeof input_buffer)
+		input_offset -= sizeof input_buffer;
+	input_size--;
 
-	nc_buf = 0;
-	return tmp;
+	return c;
 }
 
 int nc_tstc (void)
@@ -164,7 +228,7 @@ int nc_tstc (void)
 	if (input_recursion)
 		return 0;
 
-	if (nc_buf)
+	if (input_size)
 		return 1;
 
 	eth = eth_get_dev ();
@@ -174,11 +238,11 @@ int nc_tstc (void)
 	input_recursion = 1;
 
 	net_timeout = 1;
-	NetLoop (NETCONS);		/* kind of poll */
+	NetLoop (NETCONS);	/* kind of poll */
 
 	input_recursion = 0;
 
-	return nc_buf != 0;
+	return input_size != 0;
 }
 
 int drv_nc_init (void)

drivers/smiLynxEM.c

@@ -550,7 +550,7 @@ static void smiLoadCcr (struct ctfb_res_modes *var, unsigned short device_id)
 	smiWrite (SMI_INDX_C4, 0x6b, 0x15);
 
 	/* VCLK */
-	freq = 1000000000000L / var -> pixclock;
+	freq = 1000000000000LL / var -> pixclock;
 
 	FindPQ ((unsigned int)freq, &p, &q);
 

include/configs/ML2.h

@@ -76,12 +76,17 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
-#define CONFIG_COMMANDS	       ( (CONFIG_CMD_DFL & (~CFG_CMD_NET)	 &  \
-				(~CFG_CMD_RTC) & ~(CFG_CMD_PCI)  & ~(CFG_CMD_I2C)) | \
+#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL & \
+				     ~( CFG_CMD_NET | \
+					CFG_CMD_RTC | \
+					CFG_CMD_PCI | \
+					CFG_CMD_I2C   \
+				      ) ) | \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_KGDB	| \
 				CFG_CMD_BEDBUG	| \
-				CFG_CMD_ELF	 | CFG_CMD_JFFS2 )
+				CFG_CMD_ELF	| \
+				CFG_CMD_JFFS2	  )
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>

include/configs/NC650.h

@@ -0,0 +1,347 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC852T		1
+#define CONFIG_NC650		1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+/*
+ * 10 MHz - PLL input clock
+ */
+#define CFG_866_OSCCLK		10000000
+
+/*
+ * 50 MHz - default CPU clock
+ */
+#define CFG_866_CPUCLK_DEFAULT	50000000
+
+/*
+ * 15 MHz - CPU minimum clock
+ */
+#define CFG_866_CPUCLK_MIN	15000000
+
+/*
+ * 133 MHz - CPU maximum clock
+ */
+#define CFG_866_CPUCLK_MAX	133000000
+
+#define CFG_MEASURE_CPUCLK
+#define CFG_8XX_XIN		CFG_866_OSCCLK
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp;" 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" 	\
+	"bootm"
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
+#define FEC_ENET
+#define CONFIG_MII
+#define CFG_DISCOVER_PHY	1
+
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		100000	/* 100 kHz			*/
+#define CFG_I2C_SLAVE		0x7f
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define SCL		0x10000000	/* PA 3 */
+#define SDA		0x40000000	/* PA 1 */
+
+#define PAR		immr->im_ioport.iop_papar
+#define DIR		immr->im_ioport.iop_padir
+#define DAT		immr->im_ioport.iop_padat
+
+#define I2C_INIT	{PAR &= ~(SCL | SDA); DIR |=  SCL;}
+#define I2C_ACTIVE	(DIR |=  SDA)
+#define I2C_TRISTATE	(DIR &= ~SDA)
+#define I2C_READ	((DAT & SDA) != 0)
+#define I2C_SDA(bit)	if (bit) DAT |=  SDA; \
+			else DAT &= ~SDA
+#define I2C_SCL(bit)	if (bit) DAT |=  SCL; \
+			else DAT &= ~SCL
+#define I2C_DELAY	udelay(50)	/* 1/4 I2C clock duration */
+
+#define CFG_I2C_EEPROM_ADDR		0x50
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS  	4	/* 16 bytes page write mode */
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR	 	0x00100000
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00740000
+
+#define CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration					11-6
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00	| SCCR_DFSYNC00	| \
+			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
+			 SCCR_DFLCD000	| SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: Default value of OR0 after reset */
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_MSK | OR_BI | \
+				 OR_SCY_15_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+/*
+ * BR3 and OR3 (SDRAM)
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank		*/
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+ /*
+  * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+  */
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR3_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+
+/*
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4    Number of refresh cycles per period
+ * 64   Refresh cycle in ms per number of rows
+ */
+#define CFG_866_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA		39
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+#endif	/* __CONFIG_H */

include/configs/ep8260.h

@@ -269,31 +269,31 @@
 /* What U-Boot subsytems do you want enabled? */
 /*
 */
-#define CONFIG_COMMANDS		(	CFG_CMD_ALL     & \
-					~CFG_CMD_BMP	& \
-					~CFG_CMD_BSP    & \
-					~CFG_CMD_DCR    & \
-					~CFG_CMD_DHCP   & \
-					~CFG_CMD_DOC    & \
-					~CFG_CMD_DTT	& \
-					~CFG_CMD_EEPROM & \
-					~CFG_CMD_FDC    & \
-					~CFG_CMD_FDOS	& \
-					~CFG_CMD_HWFLOW	& \
-					~CFG_CMD_IDE    & \
-					~CFG_CMD_JFFS2	& \
-					~CFG_CMD_KGDB   & \
-					~CFG_CMD_MII    & \
-					~CFG_CMD_MMC	& \
-					~CFG_CMD_NAND	& \
-					~CFG_CMD_PCI    & \
-					~CFG_CMD_PCMCIA & \
-					~CFG_CMD_REISER	& \
-					~CFG_CMD_SCSI   & \
-					~CFG_CMD_SPI	& \
-					~CFG_CMD_USB	& \
-					~CFG_CMD_VFD	& \
-					~CFG_CMD_XIMG	)
+#define CONFIG_COMMANDS		( CFG_CMD_ALL     & \
+				  ~(	CFG_CMD_BMP	| \
+					CFG_CMD_BSP	| \
+					CFG_CMD_DCR	| \
+					CFG_CMD_DHCP	| \
+					CFG_CMD_DOC	| \
+					CFG_CMD_DTT	| \
+					CFG_CMD_EEPROM	| \
+					CFG_CMD_FDC	| \
+					CFG_CMD_FDOS	| \
+					CFG_CMD_HWFLOW	| \
+					CFG_CMD_IDE	| \
+					CFG_CMD_JFFS2	| \
+					CFG_CMD_KGDB	| \
+					CFG_CMD_MII	| \
+					CFG_CMD_MMC	| \
+					CFG_CMD_NAND	| \
+					CFG_CMD_PCI	| \
+					CFG_CMD_PCMCIA	| \
+					CFG_CMD_REISER	| \
+					CFG_CMD_SCSI	| \
+					CFG_CMD_SPI	| \
+					CFG_CMD_USB	| \
+					CFG_CMD_VFD	| \
+					CFG_CMD_XIMG	) )
 
 /* Where do the internal registers live? */
 #define CFG_IMMR               0xF0000000

lib_ppc/board.c

@@ -264,7 +264,7 @@ init_fnc_t *init_sequence[] = {
 	board_early_init_f,
 #endif
 
-#if !defined(CONFIG_TQM866M)
+#if !defined(CONFIG_TQM866M) && !defined(CONFIG_NC650)
 	get_clocks,		/* get CPU and bus clocks (etc.) */
 #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
 	adjust_sdram_tbs_8xx,
@@ -280,7 +280,7 @@ init_fnc_t *init_sequence[] = {
 	board_postclk_init,
 #endif
 	env_init,
-#if defined(CONFIG_TQM866M)
+#if defined(CONFIG_TQM866M) || defined(CONFIG_NC650)
 	get_clocks_866,		/* get CPU and bus clocks according to the environment variable */
 	sdram_adjust_866,	/* adjust sdram refresh rate according to the new clock */
 	init_timebase,

post/memory.c

@@ -206,19 +206,20 @@ static void move64(unsigned long long *src, unsigned long long *dest)
  *
  */
 const static unsigned long long pattern[] = {
-    0xaaaaaaaaaaaaaaaa,
-    0xcccccccccccccccc,
-    0xf0f0f0f0f0f0f0f0,
-    0xff00ff00ff00ff00,
-    0xffff0000ffff0000,
-    0xffffffff00000000,
-    0x00000000ffffffff,
-    0x0000ffff0000ffff,
-    0x00ff00ff00ff00ff,
-    0x0f0f0f0f0f0f0f0f,
-    0x3333333333333333,
-    0x5555555555555555};
-const unsigned long long otherpattern = 0x0123456789abcdef;
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL
+};
+const unsigned long long otherpattern = 0x0123456789abcdefULL;
 
 
 static int memory_post_dataline(unsigned long long * pmem)

tools/Makefile

@@ -131,6 +131,10 @@ mkimage$(SFX):	mkimage.o crc32.o
 		$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
 		$(STRIP) $@
 
+ncb$(SFX):	ncb.o
+		$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
+		$(STRIP) $@
+
 gen_eth_addr$(SFX):	gen_eth_addr.o
 		$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
 		$(STRIP) $@
@@ -156,6 +160,9 @@ crc32.o:	crc32.c
 mkimage.o:	mkimage.c
 		$(CC) -g $(CFLAGS) -c $<
 
+ncb.o:		ncb.c
+		$(CC) -g $(CFLAGS) -c $<
+
 gen_eth_addr.o:	gen_eth_addr.c
 		$(CC) -g $(CFLAGS) -c $<
 

tools/ncb.c

@@ -0,0 +1,36 @@
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/socket.h>
+#include <linux/in.h>
+
+int main (int argc, char *argv[])
+{
+	int s, len, o, port = 6666;
+	char buf[512];
+	struct sockaddr_in addr;
+	int addr_len = sizeof addr;
+
+	if (argc > 1)
+		port = atoi (argv[1]);
+
+	s = socket (PF_INET, SOCK_DGRAM, IPPROTO_UDP);
+
+	o = 1;
+	len = 4;
+	setsockopt (3, SOL_SOCKET, SO_REUSEADDR, &o, len);
+
+	addr.sin_family = AF_INET;
+	addr.sin_port = htons (port);
+	addr.sin_addr.s_addr = INADDR_ANY;	/* receive broadcasts */
+
+	bind (s, (struct sockaddr *) &addr, sizeof addr);
+
+	for (;;) {
+		len = recvfrom (s, buf, sizeof buf, 0, (struct sockaddr *) &addr, &addr_len);
+		if (len < 0)
+			break;
+		write (1, buf, len);
+	}
+
+	return 0;
+}