Prepare v2008.10 release: update CHANGELOG & Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

@@ -1,3 +1,119 @@
+commit f7a35a60cf45491871a5c28e9ad24db005487857
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 18:24:06 2008 +0200
+
+    mgcoge: add redundant environment sector
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit c2537ee85954af9d036b18b644f3e18d837bf4a5
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 18:23:27 2008 +0200
+
+    mgsuvd: update size of environment
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit fa7b1c07e9371aea8f87ee6d3c2ea5564bd8cc8d
+Author: Lepcha Suchit <Suchit.Lepcha@freescale.com>
+Date:	Thu Oct 16 13:38:00 2008 -0500
+
+    83xx NAND boot: wait for LTESR[CC]
+
+    At least some revisions of the 8313, and possibly other chips, do not
+    wait for all pages of the initial 4K NAND region to be loaded before
+    beginning execution; thus, we wait for it before branching out of the
+    first NAND page.
+
+    This fixes warm reset problems when booting from NAND on 8313erdb.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+    Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit bf29e0ea0af03d593c64614136acc723a7a022a2
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date:	Fri Oct 17 12:54:18 2008 +0200
+
+    ppc4xx: PPC44x MQ initialization
+
+    Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
+    values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
+    dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
+
+    Previously the appropriate initialization had been made in Linux, by the
+    ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
+    registers after normal operation has begun is not supported and could
+    have unpredictable results.
+
+    Comment from Stefan: This patch doesn't change the resulting value of the
+    MQ registers. It explicitly sets/clears all bits to the desired state which
+    better documents the resulting register value instead of relying on pre-set
+    default values.
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f7d190b1c0b3ab7fc53074ad2862f7de99de37ff
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Oct 16 21:58:50 2008 -0500
+
+    85xx: Using proper I2C source clock divider for MPC8544
+
+    The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being
+    bit 26, instead it should be bit 28.  This caused in incorrect
+    interpretation of the i2c_clk which is the same as the SEC clk on
+    MPC8544.  The SEC clk is controlled by cfg_sec_freq that is reported
+    in PORDEVSR2.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 42653b826adb319a1df06e24ef26096b2a5d9d2a
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Oct 16 21:58:49 2008 -0500
+
+    Revert "85xx: Using proper I2C source clock divider for MPC8544"
+
+    This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159.
+
+    The fix introduced by this patch is not correct.  The problem is
+    that the documentation is not correct for the MPC8544 with regards
+    to which bit in PORDEVSR2 is for the SEC_CFG.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 2179c4766bffeece98e5e92040629a96c97e230c
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Oct 15 10:19:41 2008 -0500
+
+    85xx: Fix compile warning
+
+    mpc8536ds.c: In function 'is_sata_supported':
+    mpc8536ds.c:614: warning: unused variable 'devdisr'
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9029b68f3f81b3013044f167ea025e836e6c8c0e
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:	Wed Oct 15 10:40:24 2008 +0800
+
+    Fix the function conflict in x86emu when DEBUG is on
+
+    The function parse_line() in common/main.c was exposed globally by commit
+    6636b62a6efc7f14e6e788788631ae7a7fca4537, Result in conflict with the same
+    name funciton in drivers/bios_emulator/x86emu/debug.c when define the DEBUG.
+    This patch fix this by renaming the function in the debug.c file.
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit b4dbacf69a669a17487054552fc2761149dd6767
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Oct 15 15:50:45 2008 +0200
+
+    Coding Style cleanup, update CHANGELOG, prepare 2008.10-rc3
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 374b9038293d01d8744a46af9b7854a6fd99b228
 Author: Heiko Schocher <hs@denx.de>
 Date:	Wed Oct 15 09:51:19 2008 +0200

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2008
 PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else

board/freescale/mpc8536ds/mpc8536ds.c

@@ -611,7 +611,6 @@ get_board_ddr_clk(ulong dummy)
 int is_sata_supported(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	uint devdisr = gur->devdisr;
 	uint sdrs2_io_sel =
 		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
 	if (sdrs2_io_sel & 0x04)

cpu/mpc83xx/start.S

@@ -167,6 +167,18 @@ boot_warm: /* time t 5 */
 	/* Initialise the E300 processor core		*/
 	/*------------------------------------------*/
 
+#ifdef CONFIG_NAND_SPL
+	/* The FCM begins execution after only the first page
+	 * is loaded.  Wait for the rest before branching
+	 * to another flash page.
+	 */
+	addi	r7, r3, 0x50b0
+1:	dcbi	0, r7
+	lwz	r6, 0(r7)
+	andi.	r6, r6, 1
+	beq	1b
+#endif
+
 	bl	init_e300_core
 
 #ifdef CFG_FLASHBOOT

cpu/mpc85xx/speed.c

@@ -102,9 +102,9 @@ int get_clocks (void)
 	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
 	 */
 	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
-		gd->i2c1_clk = sys_info.freqSystemBus / 2;
-	else
 		gd->i2c1_clk = sys_info.freqSystemBus / 3;
+	else
+		gd->i2c1_clk = sys_info.freqSystemBus / 2;
 #else
 	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
 	gd->i2c1_clk = sys_info.freqSystemBus / 2;

cpu/ppc4xx/44x_spd_ddr2.c

@@ -2261,10 +2261,12 @@ static void program_memory_queue(unsigned long *dimm_populated,
 	/*
 	 * Set optimal value for Memory Queue HB/LL Configuration registers
 	 */
-	mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
-	      SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
-	mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
-	      SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+	mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
+	      SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
+	      SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
+	mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
+	      SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
+	      SDRAM_CONF1LL_RPLM);
 	mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
 #endif
 }

drivers/bios_emulator/x86emu/debug.c

@@ -50,7 +50,7 @@
 
 static void print_encoded_bytes(u16 s, u16 o);
 static void print_decoded_instruction(void);
-static int parse_line(char *s, int *ps, int *n);
+static int x86emu_parse_line(char *s, int *ps, int *n);
 
 /* should look something like debug's output. */
 void X86EMU_trace_regs(void)
@@ -257,7 +257,7 @@ void x86emu_single_step(void)
 	offset = M.x86.saved_ip;
 	while (!done) {
 		printk("-");
-		cmd = parse_line(s, ps, &ntok);
+		cmd = x86emu_parse_line(s, ps, &ntok);
 		switch (cmd) {
 		case 'u':
 			disassemble_forward(M.x86.saved_cs, (u16) offset, 10);
@@ -331,7 +331,7 @@ int X86EMU_trace_off(void)
 	return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F);
 }
 
-static int parse_line(char *s, int *ps, int *n)
+static int x86emu_parse_line(char *s, int *ps, int *n)
 {
 	int cmd;
 

include/asm-ppc/immap_85xx.h

@@ -1579,7 +1579,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
 	uint	pordevsr2;	/* 0xe0014 - POR I/O device status regsiter 2 */
-#define MPC85xx_PORDEVSR2_SEC_CFG	0x00000020
+#define MPC85xx_PORDEVSR2_SEC_CFG	0x00000080
 	char	res1[8];
 	uint	gpporcr;	/* 0xe0020 - General-purpose POR configuration register */
 	char	res2[12];

include/asm-ppc/ppc4xx-sdram.h

@@ -272,8 +272,11 @@
 #define SDRAM_CONF1HB_PRPD	0x00080000	/* PLB Read pipeline Disable - Bit 12 */
 #define SDRAM_CONF1HB_PWPD	0x00040000	/* PLB Write pipeline Disable - Bit 13 */
 #define SDRAM_CONF1HB_PRW	0x00020000	/* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1HB_RPLM	0x00001000	/* Read Passing Limit 1 - Bits 16..19 */
 #define SDRAM_CONF1HB_RPEN	0x00000800	/* Read Passing Enable - Bit 20 */
 #define SDRAM_CONF1HB_RFTE	0x00000400	/* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1HB_WRCL	0x00000080	/* MCIF Cycle Limit 1 - Bits 22..24 */
+#define SDRAM_CONF1HB_MASK	0x0000F380	/* RPLM & WRCL mask */
 
 #define SDRAM_ERRSTATHB		(SDRAMQ_DCR_BASE+0x7)	/* error status HB             */
 #define SDRAM_ERRADDUHB		(SDRAMQ_DCR_BASE+0x8)	/* error address upper 32 HB   */
@@ -284,8 +287,10 @@
 #define SDRAM_CONF1LL_PRPD	0x00080000		/* PLB Read pipeline Disable - Bit 12 */
 #define SDRAM_CONF1LL_PWPD	0x00040000		/* PLB Write pipeline Disable - Bit 13 */
 #define SDRAM_CONF1LL_PRW	0x00020000		/* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1LL_RPLM	0x00001000		/* Read Passing Limit 1 - Bits 16..19 */
 #define SDRAM_CONF1LL_RPEN	0x00000800		/* Read Passing Enable - Bit 20 */
 #define SDRAM_CONF1LL_RFTE	0x00000400		/* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1LL_MASK	0x0000F000		/* RPLM mask */
 
 #define SDRAM_ERRSTATLL		(SDRAMQ_DCR_BASE+0xC)	/* error status LL             */
 #define SDRAM_ERRADDULL		(SDRAMQ_DCR_BASE+0xD)	/* error address upper 32 LL   */

include/configs/mgcoge.h

@@ -174,6 +174,11 @@
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	CFG_MONITOR_LEN
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
 #define CFG_IMMR		0xF0000000

include/configs/mgsuvd.h

@@ -199,14 +199,12 @@
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
 #define CONFIG_ENV_SIZE		0x08000 /* Total Size of Environment Sector	*/
-#define CONFIG_ENV_SECT_SIZE	0x40000 /* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */