Prepare v2009.01

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

@@ -1,3 +1,138 @@
+commit 635e5f8fc82365e6e9734b3132bc95135a6de679
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Jan 18 21:37:48 2009 +0100
+
+    Prepare 2009.01-rc3
+
+    Update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4cda437898f7873752f0201757cd33f12196ce87
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sat Jan 17 13:32:42 2009 -0500
+
+    build system: treat all Darwin's alike
+
+    The x86 based version of Darwin behaves the same quirky way as the powerpc
+    Darwin, so only check HOSTOS when setting up Darwin workarounds.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit c088a108c75db565e07292fd668dfa5491e85bc2
+Author: Peter Korsgaard <jacmet@sunsite.dk>
+Date:	Wed Jan 14 13:52:24 2009 +0100
+
+    fdt_resize(): fix actualsize calculations with unaligned blobs
+
+    The code in fdt_resize() to extend the fdt size to end on a page boundary
+    is wrong for fdt's not located at an address aligned on a page boundary.
+    What's even worse, the code would make actualsize shrink rather than grow
+    if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(),
+    causing fdt_add_mem_rsv to fail.
+
+    Fix it by aligning end address (blob + size) to a page boundary instead.
+    For aligned fdt's this is equivalent to what we had before.
+
+    Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
+
+commit fadad1573fb16c90025f08a2861d6047d093cba7
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Fri Jan 9 04:38:17 2009 -0500
+
+    ncb: use socklen_t
+
+    The recvfrom() function takes a socklen_t, not an int.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit fc83c9273cec6e6e542f4a0ea3b653b7d0513ffa
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Jan 11 16:35:16 2009 +0100
+
+    sh: serial: use readx/writex accessors
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 9e1fa628bdb64745811cdd26c4f953846c076180
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Jan 11 16:35:15 2009 +0100
+
+    sh: serial: coding style cleanup
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit c9935c992575922b7ef13eec0656ed8665d324e3
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Jan 11 17:48:56 2009 +0900
+
+    sh: Fix compile error on lowlevel_init file
+
+    lowlevel_init of SH was corrected to use the write/readXX macro.
+    However, there was a problem that was not able to be compiled partially.
+    This patch corrected this.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit a5b04d00bfeb940c62232972ce644d50b45797f9
+Author: Kieran Bingham <kieranbingham@gmail.com>
+Date:	Tue Dec 30 01:16:03 2008 +0000
+
+    sh: Fix up rsk7203 target for out of tree build
+
+    Fix up rsk7203 target to build successfully using out-of-tree build.
+
+    Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit f7e78f3b74aae9caca2997bad865a72338326c0a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Dec 20 19:29:49 2008 +0100
+
+    sh: use write{8,16,32} in all lowlevel_init
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit e4430779623af500de1cee7892c379f07ef59813
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Dec 20 19:29:48 2008 +0100
+
+    sh: lowlevel_init coding style cleanup
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 85cb052ee41675ca361e6a4c69455dc715c8f2d9
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Dec 20 15:27:45 2008 +0100
+
+    sh: update sh2/sh2a timer coding style
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 1e15ff999322e81af4c0c0c548908f38944ba39c
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Dec 20 15:25:22 2008 +0100
+
+    sh: update sh timer coding style
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 0e3ece33801e377be67ffa29f083421ad820f28b
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jan 14 23:26:05 2009 +0100
+
+    Prepare 2009.01-rc2
+
+    Update CHANGELOG.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit e92c9a860e44c14513c8909ce4299e253a775eeb
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Wed Jan 14 22:35:30 2009 +0100
@@ -12,6 +147,57 @@ Date:	Wed Jan 14 22:35:30 2009 +0100
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit 3ba605d4beec649438539e7df97b5fedb26592fb
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Jan 2 12:18:49 2009 +0100
+
+    ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boards
+
+    This patch adds esd's loadpci BSP command to CPCI4052 and
+    CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 600fe46fb3dab7f07604f9009904f31584415114
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Jan 2 12:18:12 2009 +0100
+
+    ppc4xx: Disable pci node in device tree on CPCI405 pci adapters
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f6a1f490d224c600a09137e58d1026d150b8e679
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Jan 2 12:17:36 2009 +0100
+
+    ppc4xx: Cleanup CPCI405 board code
+
+    This patch cleans up CPCI405 board support:
+    - wrap long lines
+    - unification of spaces in function calls
+    - remove dead code
+
+    Use correct io accessors on peripherals.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit fceebb45a0b97e92f9889861f8c3b9cb885e706f
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Jan 2 12:16:35 2009 +0100
+
+    ppc4xx: Enable auto RS485 mode on PLU405 boards
+
+    This patch turns on the auto RS485 mode in the 2nd external
+    uart on PLU405 boards. This is a special mode of the used
+    Exar XR16C2850 uart. Because these boards only have a 485 physical
+    layer connected it's a good idea to turn it on by default.
+
+    Signed-off-by: Matthias Fuchs <mf@esd.eu>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6
 Author: Haiying Wang <Haiying.Wang@freescale.com>
 Date:	Tue Jan 13 16:29:28 2009 -0500

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2009
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -3230,8 +3230,8 @@ mimc200_config		:	unconfig
 ## sh2 (Renesas SuperH)
 #########################################################################
 rsk7203_config: unconfig
-	@ >include/config.h
-	@echo "#define CONFIG_RSK7203 1" >> include/config.h
+	@mkdir -p $(obj)include
+	@echo "#define CONFIG_RSK7203 1" > $(obj)/include/config.h
 	@$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas
 
 #########################################################################

board/esd/cpci405/Makefile

@@ -29,6 +29,7 @@ endif
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS	+= ../common/cmd_loadpci.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/cpci405/cpci405.c

@@ -20,8 +20,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-
 #include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <command.h>
@@ -31,16 +32,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);	/*cmd_boot.c*/
-#if 0
-#define FPGA_DEBUG
-#endif
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+#undef FPGA_DEBUG
 
 /* fpga configuration data - generated by bin2cc */
 const unsigned char fpgadata[] =
 {
-#ifdef CONFIG_CPCI405_VER2
-# ifdef CONFIG_CPCI405AB
+#if defined(CONFIG_CPCI405_VER2)
+# if defined(CONFIG_CPCI405AB)
 #  include "fpgadata_cpci405ab.c"
 # else
 #  include "fpgadata_cpci4052.c"
@@ -56,7 +57,7 @@ const unsigned char fpgadata[] =
 #include "../common/fpga.c"
 #include "../common/auto_update.h"
 
-#ifdef CONFIG_CPCI405AB
+#if defined(CONFIG_CPCI405AB)
 au_image_t au_image[] = {
 	{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
 	{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
@@ -65,7 +66,7 @@ au_image_t au_image[] = {
 	{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
 };
 #else
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
 au_image_t au_image[] = {
 	{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
 	{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
@@ -91,7 +92,7 @@ int cpci405_version(void);
 int gunzip(void *, int, unsigned char *, unsigned long *);
 void lxt971_no_sleep(void);
 
-int board_early_init_f (void)
+int board_early_init_f(void)
 {
 #ifndef CONFIG_CPCI405_VER2
 	int index, len, i;
@@ -100,18 +101,19 @@ int board_early_init_f (void)
 
 #ifdef FPGA_DEBUG
 	/* set up serial port with default baudrate */
-	(void) get_clocks ();
+	(void)get_clocks();
 	gd->baudrate = CONFIG_BAUDRATE;
-	serial_init ();
+	serial_init();
 	console_init_f();
 #endif
 
 	/*
-	 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
+	 * First pull fpga-prg pin low,
+	 * to disable fpga logic (on version 2 board)
 	 */
 	out32(GPIO0_ODR, 0x00000000);	     /* no open drain pins	*/
-	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output	*/
-	out32(GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
+	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output	*/
+	out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
 	out32(GPIO0_OR, 0);		     /* pull prg low		*/
 
 	/*
@@ -124,39 +126,42 @@ int board_early_init_f (void)
 			/* booting FPGA failed */
 #ifndef FPGA_DEBUG
 			/* set up serial port with default baudrate */
-			(void) get_clocks ();
+			(void)get_clocks();
 			gd->baudrate = CONFIG_BAUDRATE;
-			serial_init ();
+			serial_init();
 			console_init_f();
 #endif
 			printf("\nFPGA: Booting failed ");
 			switch (status) {
 			case ERROR_FPGA_PRG_INIT_LOW:
-				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not low after "
+				       "asserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_INIT_HIGH:
-				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not high after "
+				       "deasserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_DONE:
-				printf("(Timeout: DONE not high after programming FPGA)\n ");
+				printf("(Timeout: DONE not high after "
+				       "programming FPGA)\n ");
 				break;
 			}
 
 			/* display infos on fpgaimage */
 			index = 15;
-			for (i=0; i<4; i++) {
+			for (i = 0; i < 4; i++) {
 				len = fpgadata[index];
-				printf("FPGA: %s\n", &(fpgadata[index+1]));
-				index += len+3;
+				printf("FPGA: %s\n", &(fpgadata[index + 1]));
+				index += len + 3;
 			}
-			putc ('\n');
+			putc('\n');
 			/* delayed reboot */
-			for (i=20; i>0; i--) {
+			for (i = 20; i > 0; i--) {
 				printf("Rebooting in %2d seconds \r",i);
-				for (index=0;index<1000;index++)
+				for (index = 0; index < 1000; index++)
 					udelay(1000);
 			}
-			putc ('\n');
+			putc('\n');
 			do_reset(NULL, 0, 0, NULL);
 		}
 	}
@@ -167,7 +172,7 @@ int board_early_init_f (void)
 	 * IRQ 16    405GP internally generated; active low; level sensitive
 	 * IRQ 17-24 RESERVED
 	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
 	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
 	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
 	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
@@ -177,7 +182,7 @@ int board_early_init_f (void)
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(uicer, 0x00000000);	/* disable all ints */
 	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical*/
-#ifdef CONFIG_CPCI405_6U
+#if defined(CONFIG_CPCI405_6U)
 	if (cpci405_version() == 3) {
 		mtdcr(uicpr, 0xFFFFFF99);	/* set int polarities */
 	} else {
@@ -187,21 +192,20 @@ int board_early_init_f (void)
 	mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */
 #endif
 	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority*/
+	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,
+					 * INT0 highest priority */
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
-
 int ctermm2(void)
 {
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
 	return 0;			/* no, board is cpci405 */
 #else
-	if ((*(unsigned char *)0xf0000400 == 0x00) &&
-	    (*(unsigned char *)0xf0000401 == 0x01))
+	if ((in_8((void*)0xf0000400) == 0x00) &&
+	    (in_8((void*)0xf0000401) == 0x01))
 		return 0;		/* no, board is cpci405 */
 	else
 		return -1;		/* yes, board is cterm-m2 */
@@ -228,8 +232,8 @@ int cpci405_version(void)
 	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
 	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
 	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
-	udelay(1000);			/* wait some time before reading input */
-	value = in_be32((void*)GPIO0_IR) & 0x00180000;	     /* get config bits */
+	udelay(1000); /* wait some time before reading input */
+	value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
 
 	/*
 	 * Restore GPIO settings
@@ -263,7 +267,7 @@ int misc_init_r (void)
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
 	{
 	unsigned char *dst;
 	ulong len = sizeof(fpgadata);
@@ -283,9 +287,10 @@ int misc_init_r (void)
 		mtdcr(cntrl0, cntrl0Reg | 0x00300000);
 
 		dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
-		if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
-			printf ("GUNZIP ERROR - must RESET board to recover\n");
-			do_reset (NULL, 0, 0, NULL);
+		if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+			   (uchar *)fpgadata, &len) != 0) {
+			printf("GUNZIP ERROR - must RESET board to recover\n");
+			do_reset(NULL, 0, 0, NULL);
 		}
 
 		status = fpga_boot(dst, len);
@@ -293,31 +298,34 @@ int misc_init_r (void)
 			printf("\nFPGA: Booting failed ");
 			switch (status) {
 			case ERROR_FPGA_PRG_INIT_LOW:
-				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not low after "
+				       "asserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_INIT_HIGH:
-				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not high after "
+				       "deasserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_DONE:
-				printf("(Timeout: DONE not high after programming FPGA)\n ");
+				printf("(Timeout: DONE not high after "
+				       "programming FPGA)\n ");
 				break;
 			}
 
 			/* display infos on fpgaimage */
 			index = 15;
-			for (i=0; i<4; i++) {
+			for (i = 0; i < 4; i++) {
 				len = dst[index];
-				printf("FPGA: %s\n", &(dst[index+1]));
-				index += len+3;
+				printf("FPGA: %s\n", &(dst[index + 1]));
+				index += len + 3;
 			}
-			putc ('\n');
+			putc('\n');
 			/* delayed reboot */
-			for (i=20; i>0; i--) {
-				printf("Rebooting in %2d seconds \r",i);
-				for (index=0;index<1000;index++)
+			for (i = 20; i > 0; i--) {
+				printf("Rebooting in %2d seconds \r", i);
+				for (index = 0; index < 1000; index++)
 					udelay(1000);
 			}
-			putc ('\n');
+			putc('\n');
 			do_reset(NULL, 0, 0, NULL);
 		}
 
@@ -328,12 +336,12 @@ int misc_init_r (void)
 
 		/* display infos on fpgaimage */
 		index = 15;
-		for (i=0; i<4; i++) {
+		for (i = 0; i < 4; i++) {
 			len = dst[index];
-			printf("%s ", &(dst[index+1]));
-			index += len+3;
+			printf("%s ", &(dst[index + 1]));
+			index += len + 3;
 		}
-		putc ('\n');
+		putc('\n');
 
 		free(dst);
 
@@ -345,68 +353,48 @@ int misc_init_r (void)
 		SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 		udelay(1000); /* wait 1ms */
 
-#ifdef CONFIG_CPCI405_6U
+#if defined(CONFIG_CPCI405_6U)
+#error HIER GETH ES WEITER MIT IO ACCESSORS
 		if (cpci405_version() == 3) {
-			volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
-			volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR;
-
 			/*
 			 * Enable outputs in fpga on version 3 board
 			 */
-			*fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT;
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+				 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
 
 			/*
 			 * Set outputs to 0
 			 */
-			*leds = 0x00;
+			out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
 
 			/*
 			 * Reset external DUART
 			 */
-			*fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET;
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+				 CONFIG_SYS_FPGA_MODE_DUART_RESET);
 			udelay(100);
-			*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET);
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+				 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
 		}
 #endif
 	}
 	else {
 		puts("\n*** U-Boot Version does not match Board Version!\n");
 		puts("*** CPCI-405 Version 1.x detected!\n");
-		puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
+		puts("*** Please use correct U-Boot version "
+		     "(CPCI405 instead of CPCI4052)!\n\n");
 	}
 	}
-
 #else /* CONFIG_CPCI405_VER2 */
-
-#if 0 /* test-only: code-plug now not relavant for ip-address any more */
-	/*
-	 * Generate last byte of ip-addr from code-plug @ 0xf0000400
-	 */
-	if (ctermm2()) {
-		char str[32];
-		unsigned char ipbyte = *(unsigned char *)0xf0000400;
-
-		/*
-		 * Only overwrite ip-addr with allowed values
-		 */
-		if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
-			bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
-			sprintf(str, "%ld.%ld.%ld.%ld",
-				(bd->bi_ip_addr & 0xff000000) >> 24,
-				(bd->bi_ip_addr & 0x00ff0000) >> 16,
-				(bd->bi_ip_addr & 0x0000ff00) >> 8,
-				(bd->bi_ip_addr & 0x000000ff));
-			setenv("ipaddr", str);
-		}
-	}
-#endif
-
 	if (cpci405_version() >= 2) {
 		puts("\n*** U-Boot Version does not match Board Version!\n");
 		puts("*** CPCI-405 Board Version 2.x detected!\n");
-		puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
+		puts("*** Please use correct U-Boot version "
+		     "(CPCI4052 instead of CPCI405)!\n\n");
 	}
-
 #endif /* CONFIG_CPCI405_VER2 */
 
 	/*
@@ -415,46 +403,33 @@ int misc_init_r (void)
 	cntrl0Reg = mfdcr(cntrl0);
 	mtdcr(cntrl0, cntrl0Reg | 0x00001000);
 
-	return (0);
+	return 0;
 }
 
 /*
  * Check Board Identity:
  */
 
-int checkboard (void)
+int checkboard(void)
 {
 #ifndef CONFIG_CPCI405_VER2
 	int index;
 	int len;
 #endif
 	char str[64];
-	int i = getenv_r ("serial#", str, sizeof(str));
+	int i = getenv_r("serial#", str, sizeof(str));
 	unsigned short ver;
 
-	puts ("Board: ");
+	puts("Board: ");
 
-	if (i == -1) {
-		puts ("### No HW ID - assuming CPCI405");
-	} else {
+	if (i == -1)
+		puts("### No HW ID - assuming CPCI405");
+	else
 		puts(str);
-	}
 
 	ver = cpci405_version();
 	printf(" (Ver %d.x, ", ver);
 
-#if 0 /* test-only */
-	if (ver >= 2) {
-		volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1;
-
-		if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) {
-			puts ("FLASH Bank B, ");
-		} else {
-			puts ("FLASH Bank A, ");
-		}
-	}
-#endif
-
 	if (ctermm2()) {
 		char str[4];
 
@@ -465,32 +440,31 @@ int checkboard (void)
 		setenv("boardid", str);
 		printf("CTERM-M2 - Id=%s)", str);
 	} else {
-		if (cpci405_host()) {
-			puts ("PCI Host Version)");
-		} else {
-			puts ("PCI Adapter Version)");
-		}
+		if (cpci405_host())
+			puts("PCI Host Version)");
+		else
+			puts("PCI Adapter Version)");
 	}
 
 #ifndef CONFIG_CPCI405_VER2
-	puts ("\nFPGA:	");
+	puts("\nFPGA:	");
 
 	/* display infos on fpgaimage */
 	index = 15;
-	for (i=0; i<4; i++) {
+	for (i = 0; i < 4; i++) {
 		len = fpgadata[index];
-		printf("%s ", &(fpgadata[index+1]));
-		index += len+3;
+		printf("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
 	}
 #endif
 
-	putc ('\n');
+	putc('\n');
 	return 0;
 }
 
 void reset_phy(void)
 {
-#ifdef CONFIG_LXT971_NO_SLEEP
+#if defined(CONFIG_LXT971_NO_SLEEP)
 
 	/*
 	 * Disable sleep mode in LXT971
@@ -499,25 +473,24 @@ void reset_phy(void)
 #endif
 }
 
-#ifdef CONFIG_CPCI405_VER2
-#ifdef CONFIG_IDE_RESET
-
+#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
 void ide_set_reset(int on)
 {
-	volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
-
 	/*
 	 * Assert or deassert CompactFlash Reset Pin
 	 */
-	if (on) {		/* assert RESET */
-		*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET);
-	} else {		/* release RESET */
-		*fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET;
+	if (on) {	/* assert RESET */
+		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+			 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
+	} else {	/* release RESET */
+		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+			 CONFIG_SYS_FPGA_MODE_CF_RESET);
 	}
 }
 
-#endif /* CONFIG_IDE_RESET */
-#endif /* CONFIG_CPCI405_VER2 */
+#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
 
 #if defined(CONFIG_PCI)
 void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
@@ -552,15 +525,44 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
 
-#ifdef CONFIG_CPCI405AB
+	__ft_board_setup(blob, bd);
 
-#define ONE_WIRE_CLEAR	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
-			  |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_SET	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
-			  &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_GET	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \
-			  & CONFIG_SYS_FPGA_MODE_1WIRE)
+	/*
+	 * Disable PCI in adapter mode.
+	 */
+	if (!cpci405_host()) {
+		rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCI node, "
+			       "err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CPCI405AB)
+#define ONE_WIRE_CLEAR	 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +	\
+					  CONFIG_SYS_FPGA_MODE),	\
+				  in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+						  CONFIG_SYS_FPGA_MODE)) | \
+					  CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+
+#define ONE_WIRE_SET	 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +	\
+					  CONFIG_SYS_FPGA_MODE),	\
+				  in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+						  CONFIG_SYS_FPGA_MODE)) & \
+					  ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+
+#define ONE_WIRE_GET	 (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+					  CONFIG_SYS_FPGA_STATUS)) &  \
+			  CONFIG_SYS_FPGA_MODE_1WIRE)
 
 /*
  * Generate a 1-wire reset, return 1 if no presence detect was found,
@@ -630,7 +632,7 @@ void OWWriteByte(int data)
 {
 	int loop;
 
-	for (loop=0; loop<8; loop++) {
+	for (loop = 0; loop < 8; loop++) {
 		OWWriteBit(data & 0x01);
 		data >>= 1;
 	}
@@ -640,11 +642,10 @@ int OWReadByte(void)
 {
 	int loop, result = 0;
 
-	for (loop=0; loop<8; loop++) {
+	for (loop = 0; loop < 8; loop++) {
 		result >>= 1;
-		if (OWReadBit()) {
+		if (OWReadBit())
 			result |= 0x80;
-		}
 	}
 
 	return result;
@@ -652,7 +653,7 @@ int OWReadByte(void)
 
 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	volatile unsigned short val;
+	unsigned short val;
 	int result;
 	int i;
 	unsigned char ow_id[6];
@@ -662,23 +663,25 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	/*
 	 * Clear 1-wire bit (open drain with pull-up)
 	 */
-	val = *(volatile unsigned short *)0xf0400000;
-	val &= ~0x1000; /* clear 1-wire bit */
-	*(volatile unsigned short *)0xf0400000 = val;
+	val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+			      CONFIG_SYS_FPGA_MODE));
+	val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
+	out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+			 CONFIG_SYS_FPGA_MODE), val);
 
 	result = OWTouchReset();
-	if (result != 0) {
+	if (result != 0)
 		puts("No 1-wire device detected!\n");
-	}
 
 	OWWriteByte(0x33); /* send read rom command */
 	OWReadByte(); /* skip family code ( == 0x01) */
-	for (i=0; i<6; i++) {
+	for (i = 0; i < 6; i++)
 		ow_id[i] = OWReadByte();
-	}
 	ow_crc = OWReadByte(); /* read crc */
 
-	sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
+	sprintf(str, "%08X%04X",
+		*(unsigned int *)&ow_id[0],
+		*(unsigned short *)&ow_id[4]);
 	printf("Setting environment variable 'ow_id' to %s\n", str);
 	setenv("ow_id", str);
 
@@ -690,8 +693,8 @@ U_BOOT_CMD(
 	NULL
 	);
 
-#define CONFIG_SYS_I2C_EEPROM_ADDR_2	0x51	/* EEPROM CAT28WC32		*/
-#define CONFIG_ENV_SIZE_2	0x800	/* 2048 bytes may be used for env vars*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
+#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
 
 /*
  * Write backplane ip-address...
@@ -706,12 +709,14 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	IPaddr_t ipaddr;
 
 	buf = malloc(CONFIG_ENV_SIZE_2);
-	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
+			(uchar *)buf, CONFIG_ENV_SIZE_2))
 		puts("\nError reading backplane EEPROM!\n");
-	} else {
-		crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
+	else {
+		crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 		if (crc != *(ulong *)buf) {
-			printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
+			printf("ERROR: crc mismatch %08lx %08lx\n",
+			       crc, *(ulong *)buf);
 			return -1;
 		}
 
@@ -768,12 +773,12 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	memset(buf, 0, CONFIG_ENV_SIZE_2);
 	sprintf(str, "bp_ip=%s", argv[1]);
 	strcpy(buf+4, str);
-	crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
+	crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 	*(ulong *)buf = crc;
 
-	if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+	if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
+			 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
 		puts("\nError writing backplane EEPROM!\n");
-	}
 
 	free(buf);
 

board/esd/plu405/plu405.c

@@ -104,6 +104,7 @@ int misc_init_r (void)
 	unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
 	unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
 	unsigned char *dst;
+	unsigned char fctr;
 	ulong len = sizeof(fpgadata);
 	int status;
 	int index;
@@ -203,6 +204,15 @@ int misc_init_r (void)
 	out_8(duart0_mcr, 0x08);
 	out_8(duart1_mcr, 0x08);
 
+	/*
+	 * Enable auto RS485 mode in 2nd external uart
+	 */
+	out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
+	fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
+	fctr |= 0x08;                       /* enable RS485 mode */
+	out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
+	out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
+
 	return (0);
 }
 

board/mpr2/lowlevel_init.S

@@ -22,6 +22,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#include <asm/macro.h>
 
 	.global	lowlevel_init
 
@@ -33,59 +34,35 @@ lowlevel_init:
 /*
  * Set frequency multipliers and dividers in FRQCR.
  */
-	mov.l	WTCSR_A,r1
-	mov.l	WTCSR_D,r0
-	mov.w	r0,@r1
+	write16	WTCSR_A, WTCSR_D
 
-	mov.l	WTCNT_A,r1
-	mov.l	WTCNT_D,r0
-	mov.w	r0,@r1
+	write16	WTCNT_A, WTCNT_D
 
-	mov.l	FRQCR_A,r1
-	mov.l	FRQCR_D,r0
-	mov.w	r0,@r1
+	write16	FRQCR_A, FRQCR_D
 
 /*
  * Setup CS0 (Flash).
  */
-	mov.l	CS0BCR_A, r1
-	mov.l	CS0BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS0BCR_A, CS0BCR_D
 
-	mov.l	CS0WCR_A, r1
-	mov.l	CS0WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS0WCR_A, CS0WCR_D
 
 /*
  * Setup CS3 (SDRAM).
  */
-	mov.l	CS3BCR_A, r1
-	mov.l	CS3BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS3BCR_A, CS3BCR_D
 
-	mov.l	CS3WCR_A, r1
-	mov.l	CS3WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS3WCR_A, CS3WCR_D
 
-	mov.l	SDCR_A, r1
-	mov.l	SDCR_D1, r0
-	mov.l	r0, @r1
+	write32	SDCR_A, SDCR_D1
 
-	mov.l	RTCSR_A, r1
-	mov.l	RTCSR_D, r0
-	mov.l	r0, @r1
+	write32	RTCSR_A, RTCSR_D
 
-	mov.l	RTCNT_A, r1
-	mov.l	RTCNT_D, r0
-	mov.l	r0, @r1
+	write32	RTCNT_A, RTCNT_D
 
-	mov.l	RTCOR_A, r1
-	mov.l	RTCOR_D, r0
-	mov.l	r0, @r1
+	write32	RTCOR_A, RTCOR_D
 
-	mov.l	SDCR_A, r1
-	mov.l	SDCR_D2, r0
-	mov.l	r0, @r1
+	write32	SDCR_A, SDCR_D2
 
 	mov.l	SDMR3_A, r1
 	mov.l	SDMR3_D, r0
@@ -112,21 +89,27 @@ WTCSR_D:	.long	0xA507		/* divide by 4096 */
 /*
  * Spansion S29GL256N11 @ 48 MHz
  */
-CS0BCR_D:	.long	0x12490400  /* 1 idle cycle inserted, normal space, 16 bit */
-CS0WCR_D:	.long	0x00000340  /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+/* 1 idle cycle inserted, normal space, 16 bit */
+CS0BCR_D:	.long	0x12490400
+/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+CS0WCR_D:	.long	0x00000340
 
 /*
  * Samsung K4S511632B-UL75 @ 48 MHz
  * Micron MT48LC32M16A2-75 @ 48 MHz
  */
-CS3BCR_D:	.long	0x10004400  /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
-CS3WCR_D:	.long	0x00000091  /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
-SDCR_D1:	.long	0x00000012  /* no refresh, 13 rows, 10 cols, NO bank active mode */
-SDCR_D2:	.long	0x00000812  /* refresh */
-RTCSR_D:	.long	0xA55A0008  /* 1/4, once */
-RTCNT_D:	.long	0xA55A005D  /* count 93 */
-RTCOR_D:	.long	0xa55a005d  /* count 93 */
-SDMR3_D:	.long	0x440       /* mode register CL2, burst read and SINGLE WRITE */
+/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
+CS3BCR_D:	.long	0x10004400
+/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
+CS3WCR_D:	.long	0x00000091
+/* no refresh, 13 rows, 10 cols, NO bank active mode */
+SDCR_D1:	.long	0x00000012
+SDCR_D2:	.long	0x00000812	/* refresh */
+RTCSR_D:	.long	0xA55A0008	/* 1/4, once */
+RTCNT_D:	.long	0xA55A005D	/* count 93 */
+RTCOR_D:	.long	0xa55a005d	/* count 93 */
+/* mode register CL2, burst read and SINGLE WRITE */
+SDMR3_D:	.long	0x440
 
 /*
  * Registers

board/ms7722se/lowlevel_init.S

@@ -27,13 +27,14 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 /*
- *  Board specific low level init code, called _very_ early in the
- *  startup sequence. Relocation to SDRAM has not happened yet, no
- *  stack is available, bss section has not been initialised, etc.
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
  *
- *  (Note: As no stack is available, no subroutines can be called...).
+ * (Note: As no stack is available, no subroutines can be called...).
  */
 
 	.global	lowlevel_init
@@ -43,167 +44,96 @@
 
 lowlevel_init:
 
-	/* Address of Cache Control Register */
-	mov.l	CCR_A, r1
-	/*Instruction Cache Invalidate */
-	mov.l	CCR_D, r0
-	mov.l	r0, @r1
+	/*
+	 * Cache Control Register
+	 * Instruction Cache Invalidate
+	 */
+	write32	CCR_A, CCR_D
 
-	/* Address of MMU Control Register */
-	mov.l	MMUCR_A, r1
-	/* TI == TLB Invalidate bit */
-	mov.l	MMUCR_D, r0
-	mov.l	r0, @r1
+	/*
+	 * Address of MMU Control Register
+	 * TI == TLB Invalidate bit
+	 */
+	write32	MMUCR_A, MMUCR_D
 
 	/* Address of Power Control Register 0 */
-	mov.l	MSTPCR0_A, r1
-	mov.l	MSTPCR0_D, r0
-	mov.l	r0, @r1
+	write32	MSTPCR0_A, MSTPCR0_D
 
 	/* Address of Power Control Register 2 */
-	mov.l	MSTPCR2_A, r1
-	mov.l	MSTPCR2_D, r0
-	mov.l	r0, @r1
+	write32	MSTPCR2_A, MSTPCR2_D
 
-	mov.l	SBSCR_A, r1
-	mov.w	SBSCR_D, r0
-	mov.w	r0, @r1
+	write16	SBSCR_A, SBSCR_D
 
-	mov.l	PSCR_A, r1
-	mov.w	PSCR_D, r0
-	mov.w	r0, @r1
+	write16	PSCR_A, PSCR_D
 
 	/* 0xA4520004 (Watchdog Control / Status Register) */
-!	mov.l	RWTCSR_A, r1
-	/* 0xA507 -> timer_STOP/WDT_CLK=max */
-!	mov.w	RWTCSR_D_1, r0
-!	mov.w	r0, @r1
+!	write16	RWTCSR_A, RWTCSR_D_1	/* 0xA507 -> timer_STOP/WDT_CLK=max */
 
 	/* 0xA4520000 (Watchdog Count Register) */
-	mov.l	RWTCNT_A, r1
-	/*0x5A00 -> Clear */
-	mov.w	RWTCNT_D, r0
-	mov.w	r0, @r1
+	write16	RWTCNT_A, RWTCNT_D	/*0x5A00 -> Clear */
 
 	/* 0xA4520004 (Watchdog Control / Status Register) */
-	mov.l	RWTCSR_A, r1
-	/* 0xA504 -> timer_STOP/CLK=500ms */
-	mov.w	RWTCSR_D_2, r0
-	mov.w	r0, @r1
+	write16	RWTCSR_A, RWTCSR_D_2	/* 0xA504 -> timer_STOP/CLK=500ms */
 
 	/* 0xA4150000 Frequency control register */
-	mov.l	FRQCR_A, r1
-	mov.l	FRQCR_D, r0	!
-	mov.l	r0, @r1
+	write32	FRQCR_A, FRQCR_D
 
-	mov.l	CCR_A, r1
-	mov.l	CCR_D_2, r0
-	mov.l	r0, @r1
+	write32	CCR_A, CCR_D_2
 
 bsc_init:
 
-	mov.l	PSELA_A, r1
-	mov.w	PSELA_D, r0
-	mov.w	r0, @r1
+	write16	PSELA_A, PSELA_D
 
-	mov.l	DRVCR_A, r1
-	mov.w	DRVCR_D, r0
-	mov.w	r0, @r1
+	write16	DRVCR_A, DRVCR_D
 
-	mov.l	PCCR_A, r1
-	mov.w	PCCR_D, r0
-	mov.w	r0, @r1
+	write16	PCCR_A, PCCR_D
 
-	mov.l	PECR_A, r1
-	mov.w	PECR_D, r0
-	mov.w	r0, @r1
+	write16	PECR_A, PECR_D
 
-	mov.l	PJCR_A, r1
-	mov.w	PJCR_D, r0
-	mov.w	r0, @r1
+	write16	PJCR_A, PJCR_D
 
-	mov.l	PXCR_A, r1
-	mov.w	PXCR_D, r0
-	mov.w	r0, @r1
+	write16	PXCR_A, PXCR_D
 
-	mov.l	CMNCR_A, r1	! CMNCR address -> R1
-	mov.l	CMNCR_D, r0	! CMNCR data    -> R0
-	mov.l	r0, @r1		! CMNCR set
+	write32	CMNCR_A, CMNCR_D
 
-	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
-	mov.l	CS0BCR_D, r0	! CS0BCR data    -> R0
-	mov.l	r0, @r1		! CS0BCR set
+	write32	CS0BCR_A, CS0BCR_D
 
-	mov.l	CS2BCR_A, r1	! CS2BCR address -> R1
-	mov.l	CS2BCR_D, r0	! CS2BCR data    -> R0
-	mov.l	r0, @r1		! CS2BCR set
+	write32	CS2BCR_A, CS2BCR_D
 
-	mov.l	CS4BCR_A, r1	! CS4BCR address -> R1
-	mov.l	CS4BCR_D, r0	! CS4BCR data    -> R0
-	mov.l	r0, @r1		! CS4BCR set
+	write32	CS4BCR_A, CS4BCR_D
 
-	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
-	mov.l	CS5ABCR_D, r0	! CS5ABCR data    -> R0
-	mov.l	r0, @r1		! CS5ABCR set
+	write32	CS5ABCR_A, CS5ABCR_D
 
-	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
-	mov.l	CS5BBCR_D, r0	! CS5BBCR data    -> R0
-	mov.l	r0, @r1		! CS5BBCR set
+	write32	CS5BBCR_A, CS5BBCR_D
 
-	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
-	mov.l	CS6ABCR_D, r0	! CS6ABCR data    -> R0
-	mov.l	r0, @r1		! CS6ABCR set
+	write32	CS6ABCR_A, CS6ABCR_D
 
-	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
-	mov.l	CS0WCR_D, r0	! CS0WCR data    -> R0
-	mov.l	r0, @r1		! CS0WCR set
+	write32	CS0WCR_A, CS0WCR_D
 
-	mov.l	CS2WCR_A, r1	! CS2WCR address -> R1
-	mov.l	CS2WCR_D, r0	! CS2WCR data    -> R0
-	mov.l	r0, @r1		! CS2WCR set
+	write32	CS2WCR_A, CS2WCR_D
 
-	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
-	mov.l	CS4WCR_D, r0	! CS4WCR data    -> R0
-	mov.l	r0, @r1		! CS4WCR set
+	write32	CS4WCR_A, CS4WCR_D
 
-	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
-	mov.l	CS5AWCR_D, r0	! CS5AWCR data    -> R0
-	mov.l	r0, @r1		! CS5AWCR set
+	write32	CS5AWCR_A, CS5AWCR_D
 
-	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
-	mov.l	CS5BWCR_D, r0	! CS5BWCR data    -> R0
-	mov.l	r0, @r1		! CS5BWCR set
+	write32	CS5BWCR_A, CS5BWCR_D
 
-	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
-	mov.l	CS6AWCR_D, r0	! CS6AWCR data    -> R0
-	mov.l	r0, @r1		! CS6AWCR set
+	write32	CS6AWCR_A, CS6AWCR_D
 
 	! SDRAM initialization
-	mov.l	SDCR_A, r1	! SB_SDCR address -> R1
-	mov.l	SDCR_D, r0	! SB_SDCR data    -> R0
-	mov.l	r0, @r1		! SB_SDCR set
+	write32	SDCR_A, SDCR_D
 
-	mov.l	SDWCR_A, r1	! SB_SDWCR address -> R1
-	mov.l	SDWCR_D, r0	! SB_SDWCR data    -> R0
-	mov.l	r0, @r1		! SB_SDWCR set
+	write32	SDWCR_A, SDWCR_D
 
-	mov.l	SDPCR_A, r1	! SB_SDPCR address -> R1
-	mov.l	SDPCR_D, r0	! SB_SDPCR data    -> R0
-	mov.l	r0, @r1		! SB_SDPCR set
+	write32	SDPCR_A, SDPCR_D
 
-	mov.l	RTCOR_A, r1	! SB_RTCOR address -> R1
-	mov.l	RTCOR_D, r0	! SB_RTCOR data    -> R0
-	mov.l	r0, @r1		! SB_RTCOR set
+	write32	RTCOR_A, RTCOR_D
 
-	mov.l	RTCSR_A, r1	! SB_RTCSR address -> R1
-	mov.l	RTCSR_D, r0	! SB_RTCSR data    -> R0
-	mov.l	r0, @r1		! SB_RTCSR set
+	write32	RTCSR_A, RTCSR_D
 
-	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
-	mov	#0x00, r0	! SDMR3 data    -> R0
-	mov.b	r0, @r1		! SDMR3 set
+	write8	SDMR3_A, SDMR3_D
 
-	! BL bit off (init = ON)  (?!?)
+	! BL bit off (init = ON) (?!?)
 
 	stc	sr, r0				! BL bit off(init=ON)
 	mov.l	SR_MASK_D, r1
@@ -232,28 +162,28 @@ MSTPCR0_D:	.long	0x00001001
 MSTPCR2_D:	.long	0xffffffff
 FRQCR_D:	.long	0x07022538
 
-PSELA_A:	.long   0xa405014E
-PSELA_D:	.word   0x0A10
+PSELA_A:	.long	0xa405014E
+PSELA_D:	.word	0x0A10
 	.align 2
 
-DRVCR_A:	.long   0xa405018A
-DRVCR_D:	.word   0x0554
+DRVCR_A:	.long	0xa405018A
+DRVCR_D:	.word	0x0554
 	.align 2
 
-PCCR_A:		.long   0xa4050104
-PCCR_D:		.word   0x8800
+PCCR_A:		.long	0xa4050104
+PCCR_D:		.word	0x8800
 	.align 2
 
-PECR_A:		.long   0xa4050108
-PECR_D:		.word   0x0000
+PECR_A:		.long	0xa4050108
+PECR_D:		.word	0x0000
 	.align 2
 
-PJCR_A:		.long   0xa4050110
-PJCR_D:		.word   0x1000
+PJCR_A:		.long	0xa4050110
+PJCR_D:		.word	0x1000
 	.align 2
 
-PXCR_A:		.long   0xa4050148
-PXCR_D:		.word   0x0AAA
+PXCR_A:		.long	0xa4050148
+PXCR_D:		.word	0x0AAA
 	.align 2
 
 CMNCR_A:	.long	CMNCR
@@ -295,6 +225,7 @@ RTCOR_D:	.long	0xA55A0034
 RTCSR_A:	.long	SBSC_RTCSR
 RTCSR_D:	.long	0xA55A0010
 SDMR3_A:	.long	0xFE500180
+SDMR3_D:	.long	0x0
 
 	.align	1
 

board/ms7750se/lowlevel_init.S

@@ -29,120 +29,94 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 #ifdef CONFIG_CPU_SH7751
-#define BCR2_D_VALUE	0x2FFC	   /* Area 1-6 width: 32/32/32/32/32/16 */
-#define WCR1_D_VALUE    0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
+#define BCR2_D_VALUE	0x2FFC		/* Area 1-6 width: 32/32/32/32/32/16 */
+#define WCR1_D_VALUE	0x02770771	/* DMA:0 A6:2 A3:0 A0:1 Others:15 */
 #ifdef CONFIG_MARUBUN_PCCARD
-#define WCR2_D_VALUE    0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
-				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#define WCR2_D_VALUE	0xFFFE4FE7	/* A6:15 A6B:7 A5:15 A5B:7 A4:15
+					   A3:2  A2:15 A1:15 A0:6  A0B:7  */
 #else /* CONFIG_MARUBUN_PCCARD */
-#define WCR2_D_VALUE    0x7FFE4FE7 /* A6:3  A6B:7 A5:15 A5B:7 A4:15
-				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#define WCR2_D_VALUE	0x7FFE4FE7	/* A6:3  A6B:7 A5:15 A5B:7 A4:15
+					   A3:2  A2:15 A1:15 A0:6  A0B:7  */
 #endif /* CONFIG_MARUBUN_PCCARD */
-#define WCR3_D_VALUE	0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
-				      A2: 1-3 A1: 1-3 A0: 0-1 */
-#define RTCOR_D_VALUE	0xA50D	   /* Write code A5, data 0D (~15us?) */
-#define SDMR3_ADDRESS	0xFF940088 /* SDMR3 address on 32-bit bus */
-#define MCR_D1_VALUE	0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
-#define MCR_D2_VALUE	0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
+#define WCR3_D_VALUE	0x01777771	/* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
+					   A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE	0xA50D		/* Write code A5, data 0D (~15us?) */
+#define SDMR3_ADDRESS	0xFF940088	/* SDMR3 address on 32-bit bus */
+#define MCR_D1_VALUE	0x100901B4	/* SDRAM 32-bit, CAS/RAS Refresh, .. */
+#define MCR_D2_VALUE	0x500901B4	/* Same w/MRSET now 1 (mode reg cmd) */
 #else /* CONFIG_CPU_SH7751 */
-#define BCR2_D_VALUE	0x2E3C	   /* Area 1-6 width: 32/32/64/16/32/16 */
-#define WCR1_D_VALUE	0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
-#define WCR2_D_VALUE	0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
-				      A3:2  A2:15 A1:15 A0:15 A0B:7  */
-#define WCR3_D_VALUE	0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
-				      A2: 1-3 A1: 1-3 A0: 0-1 */
-#define RTCOR_D_VALUE	0xA510	   /* Write code A5, data 10 (~15us?) */
-#define SDMR3_ADDRESS	0xFF940110 /* SDMR3 address on 64-bit bus */
-#define MCR_D1_VALUE	0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
-#define MCR_D2_VALUE	0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
+#define BCR2_D_VALUE	0x2E3C		/* Area 1-6 width: 32/32/64/16/32/16 */
+#define WCR1_D_VALUE	0x02720777	/* DMA:0 A6:2 A4:2 A3:0 Others:15 */
+#define WCR2_D_VALUE	0xFFFE4FFF	/* A6:15 A6B:7 A5:15 A5B:7 A4:15
+					   A3:2  A2:15 A1:15 A0:15 A0B:7  */
+#define WCR3_D_VALUE	0x01717771	/* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
+					   A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE	0xA510		/* Write code A5, data 10 (~15us?) */
+#define SDMR3_ADDRESS	0xFF940110	/* SDMR3 address on 64-bit bus */
+#define MCR_D1_VALUE	0x8801001C	/* SDRAM 64-bit, CAS/RAS Refresh, .. */
+#define MCR_D2_VALUE	0xC801001C	/* Same w/MRSET now 1 (mode reg cmd) */
 #endif /* CONFIG_CPU_SH7751 */
 
 	.global lowlevel_init
 	.text
-	.align  2
+	.align	2
 
 lowlevel_init:
 
-	mov.l   CCR_A, r1               ! CCR Address
-	mov.l   CCR_D_DISABLE, r0       ! CCR Data
-	mov.l   r0, @r1
+	write32	CCR_A, CCR_D_DISABLE
 
 init_bsc:
-	mov.l	FRQCR_A,r1	/* FRQCR Address */
-	mov.l	FRQCR_D,r0	/* FRQCR Data */
-	mov.w	r0,@r1
+	write16	FRQCR_A, FRQCR_D
 
-	mov.l	BCR1_A,r1	/* BCR1 Address */
-	mov.l	BCR1_D,r0	/* BCR1 Data */
-	mov.l	r0,@r1
+	write32	BCR1_A, BCR1_D
 
-	mov.l	BCR2_A,r1	/* BCR2 Address */
-	mov.l	BCR2_D,r0	/* BCR2 Data */
-	mov.w	r0,@r1
+	write16	BCR2_A, BCR2_D
 
-	mov.l	WCR1_A,r1	/* WCR1 Address */
-	mov.l	WCR1_D,r0	/* WCR1 Data */
-	mov.l	r0,@r1
+	write32	WCR1_A, WCR1_D
 
-	mov.l	WCR2_A,r1	/* WCR2 Address */
-	mov.l	WCR2_D,r0	/* WCR2 Data */
-	mov.l	r0,@r1
+	write32	WCR2_A, WCR2_D
 
-	mov.l	WCR3_A,r1	/* WCR3 Address */
-	mov.l	WCR3_D,r0	/* WCR3 Data */
-	mov.l	r0,@r1
+	write32	WCR3_A, WCR3_D
 
-	mov.l	MCR_A,r1	/* MCR Address */
-	mov.l	MCR_D1,r0	/* MCR Data1 */
-	mov.l	r0,@r1
+	write32	MCR_A, MCR_D1
 
-	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
-	mov	#0,r0
-	mov.b	r0,@r1
+	/* Set SDRAM mode */
+	write8	SDMR3_A, SDMR3_D
 
 	! Do you need PCMCIA setting?
 	! If so, please add the lines here...
 
-	mov.l	RTCNT_A,r1	/* RTCNT Address */
-	mov.l	RTCNT_D,r0	/* RTCNT Data */
-	mov.w	r0,@r1
+	write16	RTCNT_A, RTCNT_D
 
-	mov.l	RTCOR_A,r1	/* RTCOR Address */
-	mov.l	RTCOR_D,r0	/* RTCOR Data */
-	mov.w	r0,@r1
+	write16	RTCOR_A, RTCOR_D
 
-	mov.l	RTCSR_A,r1	/* RTCSR Address */
-	mov.l	RTCSR_D,r0	/* RTCSR Data */
-	mov.w	r0,@r1
+	write16	RTCSR_A, RTCSR_D
+
+	write16	RFCR_A, RFCR_D
 
-	mov.l	RFCR_A,r1	/* RFCR Address */
-	mov.l	RFCR_D,r0	/* RFCR Data */
-	mov.w	r0,@r1		/* Clear reflesh counter */
 	/* Wait DRAM refresh 30 times */
-	mov	#30,r3
+	mov	#30, r3
 1:
-	mov.w	@r1,r0
-	extu.w	r0,r2
-	cmp/hi	r3,r2
+	mov.w	@r1, r0
+	extu.w	r0, r2
+	cmp/hi	r3, r2
 	bf	1b
 
-	mov.l	MCR_A,r1	/* MCR Address */
-	mov.l	MCR_D2,r0	/* MCR Data2 */
-	mov.l	r0,@r1
+	write32	MCR_A, MCR_D2
 
-	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
-	mov	#0,r0
-	mov.b	r0,@r1
+	/* Set SDRAM mode */
+	write8	SDMR3_A, SDMR3_D
 
 	rts
-	 nop
+	nop
 
 	.align	2
 
-CCR_A:          .long   CCR
-CCR_D_DISABLE:  .long   0x0808
+CCR_A:		 .long	CCR
+CCR_D_DISABLE:	.long	0x0808
 FRQCR_A:	.long	FRQCR
 FRQCR_D:
 #ifdef CONFIG_CPU_TYPE_R
@@ -172,6 +146,7 @@ RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
 RTCOR_A:	.long	RTCOR
 RTCOR_D:	.long	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
 SDMR3_A:	.long	SDMR3_ADDRESS
+SDMR3_D:	.long	0x00
 MCR_A:		.long	MCR
 MCR_D1:		.long	MCR_D1_VALUE
 MCR_D2:		.long	MCR_D2_VALUE

board/renesas/MigoR/lowlevel_init.S

@@ -27,13 +27,14 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 /*
- *  Board specific low level init code, called _very_ early in the
- *  startup sequence. Relocation to SDRAM has not happened yet, no
- *  stack is available, bss section has not been initialised, etc.
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
  *
- *  (Note: As no stack is available, no subroutines can be called...).
+ * (Note: As no stack is available, no subroutines can be called...).
  */
 
 	.global	lowlevel_init
@@ -42,141 +43,83 @@
 	.align	2
 
 lowlevel_init:
-	mov.l	CCR_A, r1	! Address of Cache Control Register
-	mov.l	CCR_D, r0	! Instruction Cache Invalidate
-	mov.l	r0, @r1
+	write32	CCR_A, CCR_D		! Address of Cache Control Register
+					! Instruction Cache Invalidate
 
-	mov.l	MMUCR_A, r1	! Address of MMU Control Register
-	mov.l	MMUCR_D, r0	! TI == TLB Invalidate bit
-	mov.l	r0, @r1
+	write32	MMUCR_A, MMUCR_D	! Address of MMU Control Register
+					! TI == TLB Invalidate bit
 
-	mov.l	MSTPCR0_A, r1	! Address of Power Control Register 0
-	mov.l	MSTPCR0_D, r0	!
-	mov.l	r0, @r1
+	write32	MSTPCR0_A, MSTPCR0_D	! Address of Power Control Register 0
 
-	mov.l	MSTPCR2_A, r1	! Address of Power Control Register 2
-	mov.l	MSTPCR2_D, r0	!
-	mov.l	r0, @r1
+	write32	MSTPCR2_A, MSTPCR2_D	! Address of Power Control Register 2
 
-	mov.l	PFC_PULCR_A, r1
-	mov.w	PFC_PULCR_D, r0
-	mov.w	r0,@r1
+	write16	PFC_PULCR_A, PFC_PULCR_D
 
-	mov.l	PFC_DRVCR_A, r1
-	mov.w	PFC_DRVCR_D, r0
-	mov.w	r0, @r1
+	write16	PFC_DRVCR_A, PFC_DRVCR_D
 
-	mov.l	SBSCR_A, r1	!
-	mov.w	SBSCR_D, r0	!
-	mov.w	r0, @r1
+	write16	SBSCR_A, SBSCR_D
 
-	mov.l	PSCR_A, r1	!
-	mov.w	PSCR_D, r0	!
-	mov.w	r0, @r1
+	write16	PSCR_A, PSCR_D
 
-	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
-	mov.w	RWTCSR_D_1, r0	! 0xA507 -> timer_STOP/WDT_CLK=max
-	mov.w	r0, @r1
+	write16	RWTCSR_A, RWTCSR_D_1	! 0xA4520004 (Watchdog Control / Status Register)
+					! 0xA507 -> timer_STOP / WDT_CLK = max
 
-	mov.l	RWTCNT_A, r1	! 0xA4520000 (Watchdog Count Register)
-	mov.w	RWTCNT_D, r0	! 0x5A00 -> Clear
-	mov.w	r0, @r1
+	write16	RWTCNT_A, RWTCNT_D	! 0xA4520000 (Watchdog Count Register)
+					! 0x5A00 -> Clear
 
-	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
-	mov.w	RWTCSR_D_2, r0	! 0xA504 -> timer_STOP/CLK=500ms
-	mov.w	r0, @r1
+	write16	RWTCSR_A, RWTCSR_D_2	! 0xA4520004 (Watchdog Control / Status Register)
+					! 0xA504 -> timer_STOP / CLK = 500ms
 
-	mov.l	DLLFRQ_A, r1	! 20080115
-	mov.l	DLLFRQ_D, r0	! 20080115
-	mov.l	r0, @r1
+	write32	DLLFRQ_A, DLLFRQ_D	! 20080115
+					! 20080115
 
-	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
-	mov.l	FRQCR_D, r0	! 20080115
-	mov.l	r0, @r1
+	write32	FRQCR_A, FRQCR_D	! 0xA4150000 Frequency control register
+					! 20080115
 
-	mov.l	CCR_A, r1		! Address of Cache Control Register
-	mov.l	CCR_D_2, r0	! ??
-	mov.l	r0, @r1
+	write32	CCR_A, CCR_D_2		! Address of Cache Control Register
+					! ??
 
 bsc_init:
-	mov.l	CMNCR_A, r1	! CMNCR address -> R1
-	mov.l	CMNCR_D, r0	! CMNCR data    -> R0
-	mov.l	r0, @r1		! CMNCR set
+	write32	CMNCR_A, CMNCR_D
 
-	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
-	mov.l	CS0BCR_D, r0	! CS0BCR data    -> R0
-	mov.l	r0, @r1		! CS0BCR set
+	write32	CS0BCR_A, CS0BCR_D
 
-	mov.l	CS4BCR_A, r1	! CS4BCR address -> R1
-	mov.l	CS4BCR_D, r0	! CS4BCR data    -> R0
-	mov.l	r0, @r1		! CS4BCR set
+	write32	CS4BCR_A, CS4BCR_D
 
-	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
-	mov.l	CS5ABCR_D, r0	! CS5ABCR data    -> R0
-	mov.l	r0, @r1		! CS5ABCR set
+	write32	CS5ABCR_A, CS5ABCR_D
 
-	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
-	mov.l	CS5BBCR_D, r0	! CS5BBCR data    -> R0
-	mov.l	r0, @r1		! CS5BBCR set
+	write32	CS5BBCR_A, CS5BBCR_D
 
-	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
-	mov.l	CS6ABCR_D, r0	! CS6ABCR data    -> R0
-	mov.l	r0, @r1		! CS6ABCR set
+	write32	CS6ABCR_A, CS6ABCR_D
 
-	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
-	mov.l	CS0WCR_D, r0	! CS0WCR data    -> R0
-	mov.l	r0, @r1		! CS0WCR set
+	write32	CS0WCR_A, CS0WCR_D
 
-	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
-	mov.l	CS4WCR_D, r0	! CS4WCR data    -> R0
-	mov.l	r0, @r1		! CS4WCR set
+	write32	CS4WCR_A, CS4WCR_D
 
-	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
-	mov.l	CS5AWCR_D, r0	! CS5AWCR data    -> R0
-	mov.l	r0, @r1		! CS5AWCR set
+	write32	CS5AWCR_A, CS5AWCR_D
 
-	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
-	mov.l	CS5BWCR_D, r0	! CS5BWCR data    -> R0
-	mov.l	r0, @r1		! CS5BWCR set
+	write32	CS5BWCR_A, CS5BWCR_D
 
-	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
-	mov.l	CS6AWCR_D, r0	! CS6AWCR data    -> R0
-	mov.l	r0, @r1		! CS6AWCR set
+	write32	CS6AWCR_A, CS6AWCR_D
 
 	! SDRAM initialization
-	mov.l	SDCR_A, r1	! SB_SDCR address -> R1
-	mov.l	SDCR_D, r0	! SB_SDCR data    -> R0
-	mov.l	r0, @r1		! SB_SDCR set
+	write32	SDCR_A, SDCR_D
 
-	mov.l	SDWCR_A, r1	! SB_SDWCR address -> R1
-	mov.l	SDWCR_D, r0	! SB_SDWCR data    -> R0
-	mov.l	r0, @r1		! SB_SDWCR set
+	write32	SDWCR_A, SDWCR_D
 
-	mov.l	SDPCR_A, r1	! SB_SDPCR address -> R1
-	mov.l	SDPCR_D, r0	! SB_SDPCR data    -> R0
-	mov.l	r0, @r1		! SB_SDPCR set
+	write32	SDPCR_A, SDPCR_D
 
-	mov.l	RTCOR_A, r1	! SB_RTCOR address -> R1
-	mov.l	RTCOR_D, r0	! SB_RTCOR data    -> R0
-	mov.l	r0, @r1		! SB_RTCOR set
+	write32	RTCOR_A, RTCOR_D
 
-	mov.l	RTCNT_A, r1	! SB_RTCNT address -> R1
-	mov.l	RTCNT_D, r0	! SB_RTCNT data    -> R0
-	mov.l	r0, @r1
+	write32	RTCNT_A, RTCNT_D
 
-	mov.l	RTCSR_A, r1	! SB_RTCSR address -> R1
-	mov.l	RTCSR_D, r0	! SB_RTCSR data    -> R0
-	mov.l	r0, @r1		! SB_RTCSR set
+	write32	RTCSR_A, RTCSR_D
 
-	mov.l	RFCR_A, r1	! SB_RFCR address -> R1
-	mov.l	RFCR_D, r0	! SB_RFCR data    -> R0
-	mov.l	r0, @r1
+	write32	RFCR_A, RFCR_D
 
-	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
-	mov	#0x00, r0	! SDMR3 data    -> R0
-	mov.b	r0, @r1		! SDMR3 set
+	write8	SDMR3_A, SDMR3_D
 
-	! BL bit off (init = ON)  (?!?)
+	! BL bit off (init = ON) (?!?)
 
 	stc	sr, r0				! BL bit off(init=ON)
 	mov.l	SR_MASK_D, r1
@@ -252,6 +195,7 @@ RFCR_A:		.long	SBSC_RFCR
 RFCR_D:		.long	0xA55A0221
 RTCSR_D:	.long	0xA55A009a
 SDMR3_A:	.long	0xFE581180
+SDMR3_D:	.long	0x0
 
 SR_MASK_D:	.long	0xEFFFFF0F
 

board/renesas/ap325rxa/lowlevel_init.S

@@ -23,6 +23,7 @@
 #include <config.h>
 #include <version.h>
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 /*
  * Board specific low level init code, called _very_ early in the
@@ -38,113 +39,59 @@
 	.align	2
 
 lowlevel_init:
-	mov.l	DRVCRA_A, r1
-	mov.l 	DRVCRA_D, r0
-	mov.w	r0, @r1
+	write16	DRVCRA_A, DRVCRA_D
 
-	mov.l	DRVCRB_A, r1
-	mov.l 	DRVCRB_D, r0
-	mov.w	r0, @r1
+	write16	DRVCRB_A, DRVCRB_D
 
-	mov.l	RWTCSR_A, r1
-	mov.l 	RWTCSR_D1, r0
-	mov.w	r0, @r1
+	write16	RWTCSR_A, RWTCSR_D1
 
-	mov.l	RWTCNT_A, r1
-	mov.l 	RWTCNT_D, r0
-	mov.w	r0, @r1
+	write16	RWTCNT_A, RWTCNT_D
 
-	mov.l	RWTCSR_A, r1
-	mov.l 	RWTCSR_D2, r0
-	mov.w	r0, @r1
+	write16	RWTCSR_A, RWTCSR_D2
 
-	mov.l	FRQCR_A, r1
-	mov.l 	FRQCR_D, r0
-	mov.l	r0, @r1
+	write32	FRQCR_A, FRQCR_D
 
-	mov.l	CMNCR_A, r1
-	mov.l	CMNCR_D, r0
-	mov.l	r0, @r1
+	write32	CMNCR_A, CMNCR_D
 
-	mov.l	CS0BCR_A ,r1
-	mov.l	CS0BCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS0BCR_A, CS0BCR_D
 
-	mov.l	CS4BCR_A ,r1
-	mov.l	CS4BCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS4BCR_A, CS4BCR_D
 
-	mov.l	CS5ABCR_A ,r1
-	mov.l	CS5ABCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS5ABCR_A, CS5ABCR_D
 
-	mov.l	CS5BBCR_A ,r1
-	mov.l	CS5BBCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS5BBCR_A, CS5BBCR_D
 
-	mov.l	CS6ABCR_A ,r1
-	mov.l	CS6ABCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS6ABCR_A, CS6ABCR_D
 
-	mov.l	CS6BBCR_A ,r1
-	mov.l	CS6BBCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS6BBCR_A, CS6BBCR_D
 
-	mov.l	CS0WCR_A ,r1
-	mov.l	CS0WCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS0WCR_A, CS0WCR_D
 
-	mov.l	CS4WCR_A ,r1
-	mov.l	CS4WCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS4WCR_A, CS4WCR_D
 
-	mov.l	CS5AWCR_A ,r1
-	mov.l	CS5AWCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS5AWCR_A, CS5AWCR_D
 
-	mov.l	CS5BWCR_A ,r1
-	mov.l	CS5BWCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS5BWCR_A, CS5BWCR_D
 
-	mov.l	CS6AWCR_A ,r1
-	mov.l	CS6AWCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS6AWCR_A, CS6AWCR_D
 
-	mov.l	CS6BWCR_A ,r1
-	mov.l	CS6BWCR_D ,r0
-	mov.l	r0, @r1
+	write32	CS6BWCR_A, CS6BWCR_D
 
-	mov.l	SBSC_SDCR_A, r1
-	mov.l 	SBSC_SDCR_D1, r0
-	mov.l	r0, @r1
+	write32	SBSC_SDCR_A, SBSC_SDCR_D1
 
-	mov.l	SBSC_SDWCR_A, r1
-	mov.l 	SBSC_SDWCR_D, r0
-	mov.l	r0, @r1
+	write32	SBSC_SDWCR_A, SBSC_SDWCR_D
 
-	mov.l	SBSC_SDPCR_A, r1
-	mov.l 	SBSC_SDPCR_D, r0
-	mov.l	r0, @r1
+	write32	SBSC_SDPCR_A, SBSC_SDPCR_D
 
-	mov.l	SBSC_RTCSR_A, r1
-	mov.l 	SBSC_RTCSR_D, r0
-	mov.l	r0, @r1
+	write32	SBSC_RTCSR_A, SBSC_RTCSR_D
 
-	mov.l	SBSC_RTCNT_A, r1
-	mov.l 	SBSC_RTCNT_D, r0
-	mov.l	r0, @r1
+	write32	SBSC_RTCNT_A, SBSC_RTCNT_D
 
-	mov.l	SBSC_RTCOR_A, r1
-	mov.l 	SBSC_RTCOR_D, r0
-	mov.l	r0, @r1
+	write32	SBSC_RTCOR_A, SBSC_RTCOR_D
 
-	mov.l	SBSC_SDMR3_A1, r1
-	mov.l 	SBSC_SDMR3_D, r0
-	mov.b	r0, @r1
+	write8	SBSC_SDMR3_A1, SBSC_SDMR3_D
 
-	mov.l	SBSC_SDMR3_A2, r1
-	mov.l 	SBSC_SDMR3_D, r0
-	mov.b	r0, @r1
+	write8	SBSC_SDMR3_A2, SBSC_SDMR3_D
 
 	mov.l	SLEEP_CNT, r1
 2:	tst	r1, r1
@@ -152,19 +99,13 @@ lowlevel_init:
 	bf/s	2b
 	dt	r1
 
-	mov.l	SBSC_SDMR3_A3, r1
-	mov.l 	SBSC_SDMR3_D, r0
-	mov.b	r0, @r1
+	write8	SBSC_SDMR3_A3, SBSC_SDMR3_D
 
-	mov.l	SBSC_SDCR_A, r1
-	mov.l 	SBSC_SDCR_D2, r0
-	mov.l	r0, @r1
+	write32	SBSC_SDCR_A, SBSC_SDCR_D2
 
-	mov.l	CCR_A, r1
-	mov.l 	CCR_D, r0
-	mov.l	r0, @r1
+	write32	CCR_A, CCR_D
 
-	! BL bit off (init = ON)  (?!?)
+	! BL bit off (init = ON) (?!?)
 
 	stc	sr, r0				! BL bit off(init=ON)
 	mov.l	SR_MASK_D, r1
@@ -211,7 +152,7 @@ SBSC_SDMR3_D:	.long	0x00
 CMNCR_A:	.long	CMNCR
 CS0BCR_A:	.long	CS0BCR
 CS4BCR_A:	.long	CS4BCR
-CS5ABCR_A:	.long 	CS5ABCR
+CS5ABCR_A:	.long	CS5ABCR
 CS5BBCR_A:	.long	CS5BBCR
 CS6ABCR_A:	.long	CS6ABCR
 CS6BBCR_A:	.long	CS6BBCR

board/renesas/r2dplus/lowlevel_init.S

@@ -8,6 +8,7 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 	.global lowlevel_init
 	.text
@@ -15,98 +16,56 @@
 
 lowlevel_init:
 
-	mov.l	CCR_A, r1
-	mov.l	CCR_D_D, r0
-	mov.l	r0,@r1
+	write32	CCR_A, CCR_D_D
 
-	mov.l	MMUCR_A,r1
-	mov.l	MMUCR_D,r0
-	mov.l	r0,@r1
+	write32	MMUCR_A, MMUCR_D
 
-	mov.l	BCR1_A,r1
-	mov.l	BCR1_D,r0
-	mov.l	r0,@r1
+	write32	BCR1_A, BCR1_D
 
-	mov.l	BCR2_A,r1
-	mov.l	BCR2_D,r0
-	mov.w	r0,@r1
+	write16	BCR2_A, BCR2_D
 
-	mov.l	BCR3_A,r1
-	mov.l	BCR3_D,r0
-	mov.w	r0,@r1
+	write16	BCR3_A, BCR3_D
 
-	mov.l	BCR4_A,r1
-	mov.l	BCR4_D,r0
-	mov.l	r0,@r1
+	write32	BCR4_A, BCR4_D
 
-	mov.l	WCR1_A,r1
-	mov.l	WCR1_D,r0
-	mov.l	r0,@r1
+	write32	WCR1_A, WCR1_D
 
-	mov.l	WCR2_A,r1
-	mov.l	WCR2_D,r0
-	mov.l	r0,@r1
+	write32	WCR2_A, WCR2_D
 
-	mov.l	WCR3_A,r1
-	mov.l	WCR3_D,r0
-	mov.l	r0,@r1
+	write32	WCR3_A, WCR3_D
 
-	mov.l	PCR_A,r1
-	mov.l	PCR_D,r0
-	mov.w	r0,@r1
+	write16	PCR_A, PCR_D
 
-	mov.l	LED_A,r1
-	mov	#0xff,r0
-	mov.w	r0,@r1
+	write16	LED_A, LED_D
 
-	mov.l	MCR_A,r1
-	mov.l	MCR_D1,r0
-	mov.l	r0,@r1
+	write32	MCR_A, MCR_D1
 
-	mov.l	RTCNT_A,r1
-	mov.l	RTCNT_D,r0
-	mov.w	r0,@r1
+	write16	RTCNT_A, RTCNT_D
 
-	mov.l	RTCOR_A,r1
-	mov.l	RTCOR_D,r0
-	mov.w	r0,@r1
+	write16	RTCOR_A, RTCOR_D
 
-	mov.l	RFCR_A,r1
-	mov.l	RFCR_D,r0
-	mov.w	r0,@r1
+	write16	RFCR_A, RFCR_D
 
-	mov.l	RTCSR_A,r1
-	mov.l	RTCSR_D,r0
-	mov.w	r0,@r1
+	write16	RTCSR_A, RTCSR_D
 
-	mov.l	SDMR3_A,r1
-	mov	#0x55,r0
-	mov.b	r0,@r1
+	write8	SDMR3_A, SDMR3_D0
 
 	/* Wait DRAM refresh 30 times */
-	mov.l	RFCR_A,r1
-	mov	#30,r3
+	mov.l	RFCR_A, r1
+	mov	#30, r3
 1:
-	mov.w	@r1,r0
-	extu.w	r0,r2
-	cmp/hi	r3,r2
+	mov.w	@r1, r0
+	extu.w	r0, r2
+	cmp/hi	r3, r2
 	bf	1b
 
-	mov.l	MCR_A,r1
-	mov.l	MCR_D2,r0
-	mov.l	r0,@r1
+	write32	MCR_A, MCR_D2
 
-	mov.l	SDMR3_A,r1
-	mov	#0,r0
-	mov.b	r0,@r1
+	write8	SDMR3_A, SDMR3_D1
 
-	mov.l	IRLMASK_A,r1
-	mov.l	IRLMASK_D,r0
-	mov.l	r0,@r1
+	write32	IRLMASK_A, IRLMASK_D
 
-	mov.l	CCR_A, r1
-	mov.l	CCR_D_E, r0
-	mov.l	r0, @r1
+	write32	CCR_A, CCR_D_E
 
 	rts
 	nop
@@ -133,6 +92,7 @@ WCR2_D:		.long	0xcff86fbf
 WCR3_A:		.long	WCR3		/* WCR3 Address */
 WCR3_D:		.long	0x07777707
 LED_A:		.long	0x04000036	/* LED Address */
+LED_D:		.long	0xFF		/* LED Data */
 RTCNT_A:	.long	RTCNT		/* RTCNT Address */
 RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
 RTCOR_A:	.long	RTCOR		/* RTCOR Address */
@@ -140,7 +100,8 @@ RTCOR_D:	.long	0xA534		/* RTCOR Write Code */
 RTCSR_A:	.long	RTCSR		/* RTCSR Address */
 RTCSR_D:	.long	0xA510		/* RTCSR Write Code */
 SDMR3_A:	.long	0xFF9400CC	/* SDMR3 Address */
-SDMR3_D:	.long	0x55
+SDMR3_D0:	.long	0x55
+SDMR3_D1:	.long	0x00
 MCR_A:		.long	MCR		/* MCR Address */
 MCR_D1:		.long	0x081901F4	/* MRSET:'0' */
 MCR_D2:		.long	0x481901F4	/* MRSET:'1' */

board/renesas/r7780mp/lowlevel_init.S

@@ -22,13 +22,14 @@
 #include <config.h>
 #include <version.h>
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 /*
- *  Board specific low level init code, called _very_ early in the
- *  startup sequence. Relocation to SDRAM has not happened yet, no
- *  stack is available, bss section has not been initialised, etc.
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
  *
- *  (Note: As no stack is available, no subroutines can be called...).
+ * (Note: As no stack is available, no subroutines can be called...).
  */
 
 	.global	lowlevel_init
@@ -38,63 +39,36 @@
 
 lowlevel_init:
 
-	mov.l	CCR_A, r1	/* Address of Cache Control Register */
-	mov.l	CCR_D, r0	/* Instruction Cache Invalidate */
-	mov.l	r0, @r1
+	write32	CCR_A, CCR_D		/* Address of Cache Control Register */
+					/* Instruction Cache Invalidate */
 
-	mov.l	FRQCR_A, r1	/* Frequency control register */
-	mov.l	FRQCR_D, r0
-	mov.l	r0, @r1
+	write32	FRQCR_A, FRQCR_D	/* Frequency control register */
 
 	/* pin_multi_setting */
-	mov.l   BBG_PMMR_A,r1
-	mov.l   BBG_PMMR_D_PMSR1,r0
-	mov.l   r0,@r1
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR1
 
-	mov.l   BBG_PMSR1_A,r1
-	mov.l   BBG_PMSR1_D,r0
-	mov.l   r0,@r1
+	write32	BBG_PMSR1_A, BBG_PMSR1_D
 
-	mov.l   BBG_PMMR_A,r1
-	mov.l   BBG_PMMR_D_PMSR2,r0
-	mov.l   r0,@r1
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR2
 
-	mov.l   BBG_PMSR2_A,r1
-	mov.l   BBG_PMSR2_D,r0
-	mov.l   r0,@r1
+	write32	BBG_PMSR2_A, BBG_PMSR2_D
 
-	mov.l   BBG_PMMR_A,r1
-	mov.l   BBG_PMMR_D_PMSR3,r0
-	mov.l   r0,@r1
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR3
 
-	mov.l   BBG_PMSR3_A,r1
-	mov.l   BBG_PMSR3_D,r0
-	mov.l   r0,@r1
+	write32	BBG_PMSR3_A, BBG_PMSR3_D
 
-	mov.l   BBG_PMMR_A,r1
-	mov.l   BBG_PMMR_D_PMSR4,r0
-	mov.l   r0,@r1
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR4
 
-	mov.l   BBG_PMSR4_A,r1
-	mov.l   BBG_PMSR4_D,r0
-	mov.l   r0,@r1
+	write32	BBG_PMSR4_A, BBG_PMSR4_D
 
-	mov.l   BBG_PMMR_A,r1
-	mov.l   BBG_PMMR_D_PMSRG,r0
-	mov.l   r0,@r1
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSRG
 
-	mov.l   BBG_PMSRG_A,r1
-	mov.l   BBG_PMSRG_D,r0
-	mov.l   r0,@r1
+	write32	BBG_PMSRG_A, BBG_PMSRG_D
 
 	/* cpg_setting */
-	mov.l   FRQCR_A,r1
-	mov.l   FRQCR_D,r0
-	mov.l   r0,@r1
+	write32	FRQCR_A, FRQCR_D
 
-	mov.l   DLLCSR_A,r1
-	mov.l   DLLCSR_D,r0
-	mov.l   r0,@r1
+	write32	DLLCSR_A, DLLCSR_D
 
 	nop
 	nop
@@ -108,111 +82,79 @@ lowlevel_init:
 	nop
 
 	/* wait 200us */
-	mov.l   REPEAT0_R3,r3
-	mov     #0,r2
+	mov.l	REPEAT0_R3, r3
+	mov	#0, r2
 repeat0:
-	add     #1,r2
-	cmp/hs  r3,r2
-	bf      repeat0
+	add	#1, r2
+	cmp/hs	r3, r2
+	bf	repeat0
 	nop
 
 	/* bsc_setting */
-	mov.l	MMSELR_A,r1
-	mov.l	MMSELR_D,r0
-	mov.l	r0,@r1
+	write32	MMSELR_A, MMSELR_D
 
-	mov.l	BCR_A,r1
-	mov.l	BCR_D,r0
-	mov.l	r0,@r1
+	write32	BCR_A, BCR_D
 
-	mov.l	CS0BCR_A,r1
-	mov.l	CS0BCR_D,r0
-	mov.l	r0,@r1
+	write32	CS0BCR_A, CS0BCR_D
 
-	mov.l	CS1BCR_A,r1
-	mov.l	CS1BCR_D,r0
-	mov.l	r0,@r1
+	write32	CS1BCR_A, CS1BCR_D
 
-	mov.l	CS2BCR_A,r1
-	mov.l	CS2BCR_D,r0
-	mov.l	r0,@r1
+	write32	CS2BCR_A, CS2BCR_D
 
-	mov.l	CS4BCR_A,r1
-	mov.l	CS4BCR_D,r0
-	mov.l	r0,@r1
+	write32	CS4BCR_A, CS4BCR_D
 
-	mov.l	CS5BCR_A,r1
-	mov.l	CS5BCR_D,r0
-	mov.l	r0,@r1
+	write32	CS5BCR_A, CS5BCR_D
 
-	mov.l	CS6BCR_A,r1
-	mov.l	CS6BCR_D,r0
-	mov.l	r0,@r1
+	write32	CS6BCR_A, CS6BCR_D
 
-	mov.l	CS0WCR_A,r1
-	mov.l	CS0WCR_D,r0
-	mov.l	r0,@r1
+	write32	CS0WCR_A, CS0WCR_D
 
-	mov.l	CS1WCR_A,r1
-	mov.l	CS1WCR_D,r0
-	mov.l	r0,@r1
+	write32	CS1WCR_A, CS1WCR_D
 
-	mov.l	CS2WCR_A,r1
-	mov.l	CS2WCR_D,r0
-	mov.l	r0,@r1
+	write32	CS2WCR_A, CS2WCR_D
 
-	mov.l	CS4WCR_A,r1
-	mov.l	CS4WCR_D,r0
-	mov.l	r0,@r1
+	write32	CS4WCR_A, CS4WCR_D
 
-	mov.l	CS5WCR_A,r1
-	mov.l	CS5WCR_D,r0
-	mov.l	r0,@r1
+	write32	CS5WCR_A, CS5WCR_D
 
-	mov.l	CS6WCR_A,r1
-	mov.l	CS6WCR_D,r0
-	mov.l	r0,@r1
+	write32	CS6WCR_A, CS6WCR_D
 
-	mov.l	CS5PCR_A,r1
-	mov.l	CS5PCR_D,r0
-	mov.l	r0,@r1
+	write32	CS5PCR_A, CS5PCR_D
 
-	mov.l	CS6PCR_A,r1
-	mov.l	CS6PCR_D,r0
-	mov.l	r0,@r1
+	write32	CS6PCR_A, CS6PCR_D
 
 	/* ddr_setting */
 	/* wait 200us */
-	mov.l   REPEAT0_R3,r3
-	mov     #0,r2
+	mov.l	REPEAT0_R3, r3
+	mov	#0, r2
 repeat1:
-	add     #1,r2
-	cmp/hs  r3,r2
-	bf      repeat1
+	add	#1, r2
+	cmp/hs	r3, r2
+	bf	repeat1
 	nop
 
-	mov.l   MIM_U_A,r0
-	mov.l   MIM_U_D,r1
+	mov.l	MIM_U_A, r0
+	mov.l	MIM_U_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
-	mov.l	MIM_L_A,r0
-	mov.l	MIM_L_D0,r1
+	mov.l	MIM_L_A, r0
+	mov.l	MIM_L_D0, r1
 	synco
-	mov.l	r1,@r0
+	mov.l	r1, @r0
 	synco
 
-	mov.l   STR_L_A,r0
-	mov.l   STR_L_D,r1
+	mov.l	STR_L_A, r0
+	mov.l	STR_L_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
-	mov.l   SDR_L_A,r0
-	mov.l   SDR_L_D,r1
+	mov.l	SDR_L_A, r0
+	mov.l	SDR_L_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
@@ -220,193 +162,193 @@ repeat1:
 	nop
 	nop
 
-	mov.l   SCR_L_A,r0
-	mov.l   SCR_L_D0,r1
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D0, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
-	mov.l   SCR_L_A,r0
-	mov.l   SCR_L_D1,r1
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D1, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   EMRS_A,r0
-	mov.l   EMRS_D,r1
+	mov.l	EMRS_A, r0
+	mov.l	EMRS_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   MRS1_A,r0
-	mov.l   MRS1_D,r1
+	mov.l	MRS1_A, r0
+	mov.l	MRS1_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   SCR_L_A,r0
-	mov.l   SCR_L_D2,r1
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D2, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   SCR_L_A,r0
-	mov.l   SCR_L_D3,r1
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D3, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   SCR_L_A,r0
-	mov.l   SCR_L_D4,r1
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D4, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   MRS2_A,r0
-	mov.l   MRS2_D,r1
+	mov.l	MRS2_A, r0
+	mov.l	MRS2_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   SCR_L_A,r0
-	mov.l   SCR_L_D5,r1
+	mov.l	SCR_L_A, r0
+	mov.l	SCR_L_D5, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	/* wait 200us */
-	mov.l   REPEAT0_R1,r3
-	mov     #0,r2
+	mov.l	REPEAT0_R1, r3
+	mov	#0, r2
 repeat2:
-	add     #1,r2
-	cmp/hs  r3,r2
-	bf      repeat2
+	add	#1, r2
+	cmp/hs	r3, r2
+	bf	repeat2
 
 	synco
 
-	mov.l   MIM_L_A,r0
-	mov.l   MIM_L_D1,r1
+	mov.l	MIM_L_A, r0
+	mov.l	MIM_L_D1, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	rts
 	nop
 	.align	4
 
-RWTCSR_D_1:				.word	0xA507
-RWTCSR_D_2:				.word	0xA507
-RWTCNT_D:				.word	0x5A00
+RWTCSR_D_1:		.word	0xA507
+RWTCSR_D_2:		.word	0xA507
+RWTCNT_D:		.word	0x5A00
 	.align	2
 
-BBG_PMMR_A:				.long	0xFF800010
-BBG_PMSR1_A:			.long	0xFF800014
-BBG_PMSR2_A:			.long	0xFF800018
-BBG_PMSR3_A:			.long	0xFF80001C
-BBG_PMSR4_A:			.long	0xFF800020
-BBG_PMSRG_A:			.long	0xFF800024
+BBG_PMMR_A:		.long	0xFF800010
+BBG_PMSR1_A:		.long	0xFF800014
+BBG_PMSR2_A:		.long	0xFF800018
+BBG_PMSR3_A:		.long	0xFF80001C
+BBG_PMSR4_A:		.long	0xFF800020
+BBG_PMSRG_A:		.long	0xFF800024
 
-BBG_PMMR_D_PMSR1:       .long	0xffffbffd
-BBG_PMSR1_D:            .long	0x00004002
-BBG_PMMR_D_PMSR2:       .long	0xfc21a7ff
-BBG_PMSR2_D:            .long	0x03de5800
-BBG_PMMR_D_PMSR3:       .long	0xfffffff8
-BBG_PMSR3_D:            .long	0x00000007
-BBG_PMMR_D_PMSR4:       .long	0xdffdfff9
-BBG_PMSR4_D:            .long	0x20020006
-BBG_PMMR_D_PMSRG:       .long	0xffffffff
-BBG_PMSRG_D:            .long	0x00000000
+BBG_PMMR_D_PMSR1:	.long	0xffffbffd
+BBG_PMSR1_D:		.long	0x00004002
+BBG_PMMR_D_PMSR2:	.long	0xfc21a7ff
+BBG_PMSR2_D:		.long	0x03de5800
+BBG_PMMR_D_PMSR3:	.long	0xfffffff8
+BBG_PMSR3_D:		.long	0x00000007
+BBG_PMMR_D_PMSR4:	.long	0xdffdfff9
+BBG_PMSR4_D:		.long	0x20020006
+BBG_PMMR_D_PMSRG:	.long	0xffffffff
+BBG_PMSRG_D:		.long	0x00000000
 
-FRQCR_A:				.long	FRQCR
-DLLCSR_A:				.long	0xffc40010
-FRQCR_D:				.long	0x40233035
-DLLCSR_D:				.long	0x00000000
+FRQCR_A:		.long	FRQCR
+DLLCSR_A:		.long	0xffc40010
+FRQCR_D:		.long	0x40233035
+DLLCSR_D:		.long	0x00000000
 
 /* for DDR-SDRAM */
-MIM_U_A:				.long	MIM_1
-MIM_L_A:				.long	MIM_2
-SCR_U_A:				.long	SCR_1
-SCR_L_A:				.long	SCR_2
-STR_U_A:				.long	STR_1
-STR_L_A:				.long	STR_2
-SDR_U_A:				.long	SDR_1
-SDR_L_A:				.long	SDR_2
+MIM_U_A:		.long	MIM_1
+MIM_L_A:		.long	MIM_2
+SCR_U_A:		.long	SCR_1
+SCR_L_A:		.long	SCR_2
+STR_U_A:		.long	STR_1
+STR_L_A:		.long	STR_2
+SDR_U_A:		.long	SDR_1
+SDR_L_A:		.long	SDR_2
 
-EMRS_A:					.long	0xFEC02000
-MRS1_A:					.long	0xFEC00B08
-MRS2_A:					.long	0xFEC00308
+EMRS_A:			.long	0xFEC02000
+MRS1_A:			.long	0xFEC00B08
+MRS2_A:			.long	0xFEC00308
 
-MIM_U_D:				.long	0x00004000
-MIM_L_D0:				.long	0x03e80009
-MIM_L_D1:				.long	0x03e80209
-SCR_L_D0:				.long	0x3
-SCR_L_D1:				.long	0x2
-SCR_L_D2:				.long	0x2
-SCR_L_D3:				.long	0x4
-SCR_L_D4:				.long	0x4
-SCR_L_D5:				.long	0x0
-STR_L_D:				.long	0x000f0000
-SDR_L_D:				.long	0x00000400
-EMRS_D:					.long	0x0
-MRS1_D:					.long	0x0
-MRS2_D:					.long	0x0
+MIM_U_D:		.long	0x00004000
+MIM_L_D0:		.long	0x03e80009
+MIM_L_D1:		.long	0x03e80209
+SCR_L_D0:		.long	0x3
+SCR_L_D1:		.long	0x2
+SCR_L_D2:		.long	0x2
+SCR_L_D3:		.long	0x4
+SCR_L_D4:		.long	0x4
+SCR_L_D5:		.long	0x0
+STR_L_D:		.long	0x000f0000
+SDR_L_D:		.long	0x00000400
+EMRS_D:			.long	0x0
+MRS1_D:			.long	0x0
+MRS2_D:			.long	0x0
 
 /* Cache Controller */
-CCR_A:		.long	CCR
-MMUCR_A:	.long	MMUCR
-RWTCNT_A:	.long	WTCNT
+CCR_A:			.long	CCR
+MMUCR_A:		.long	MMUCR
+RWTCNT_A:		.long	WTCNT
 
-CCR_D:		.long	0x0000090b
-CCR_D_2:	.long	0x00000103
-MMUCR_D:	.long	0x00000004
-MSTPCR0_D:	.long	0x00001001
-MSTPCR2_D:	.long	0xffffffff
+CCR_D:			.long	0x0000090b
+CCR_D_2:		.long	0x00000103
+MMUCR_D:		.long	0x00000004
+MSTPCR0_D:		.long	0x00001001
+MSTPCR2_D:		.long	0xffffffff
 
 /* local Bus State Controller */
-MMSELR_A:   .long   MMSELR
-BCR_A:      .long   BCR
-CS0BCR_A:   .long   CS0BCR
-CS1BCR_A:   .long   CS1BCR
-CS2BCR_A:   .long   CS2BCR
-CS4BCR_A:   .long   CS4BCR
-CS5BCR_A:   .long   CS5BCR
-CS6BCR_A:   .long   CS6BCR
-CS0WCR_A:   .long   CS0WCR
-CS1WCR_A:   .long   CS1WCR
-CS2WCR_A:   .long   CS2WCR
-CS4WCR_A:   .long   CS4WCR
-CS5WCR_A:   .long   CS5WCR
-CS6WCR_A:   .long   CS6WCR
-CS5PCR_A:   .long   CS5PCR
-CS6PCR_A:   .long   CS6PCR
+MMSELR_A:		.long	MMSELR
+BCR_A:			.long	BCR
+CS0BCR_A:		.long	CS0BCR
+CS1BCR_A:		.long	CS1BCR
+CS2BCR_A:		.long	CS2BCR
+CS4BCR_A:		.long	CS4BCR
+CS5BCR_A:		.long	CS5BCR
+CS6BCR_A:		.long	CS6BCR
+CS0WCR_A:		.long	CS0WCR
+CS1WCR_A:		.long	CS1WCR
+CS2WCR_A:		.long	CS2WCR
+CS4WCR_A:		.long	CS4WCR
+CS5WCR_A:		.long	CS5WCR
+CS6WCR_A:		.long	CS6WCR
+CS5PCR_A:		.long	CS5PCR
+CS6PCR_A:		.long	CS6PCR
 
 MMSELR_D:		.long	0xA5A50003
 BCR_D:			.long	0x00000000
@@ -425,5 +367,5 @@ CS6WCR_D:		.long	0x77777703
 CS5PCR_D:		.long	0x77000000
 CS6PCR_D:		.long	0x77000000
 
-REPEAT0_R3:	.long   0x00002000
-REPEAT0_R1:	.long   0x0000200
+REPEAT0_R3:		.long	0x00002000
+REPEAT0_R1:		.long	0x0000200

board/renesas/rsk7203/Makefile

@@ -26,6 +26,10 @@ LIB	= lib$(BOARD).a
 OBJS	:= rsk7203.o
 SOBJS	:= lowlevel_init.o
 
+LIB	:= $(addprefix $(obj),$(LIB))
+OBJS	:= $(addprefix $(obj),$(OBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 

board/renesas/rsk7203/lowlevel_init.S

@@ -21,6 +21,7 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 	.global	lowlevel_init
 
@@ -29,153 +30,89 @@
 
 lowlevel_init:
 	/* Cache setting */
-	mov.l CCR1_A ,r1
-	mov.l CCR1_D ,r0
-	mov.l r0,@r1
+	write32	CCR1_A ,CCR1_D
 
 	/* ConfigurePortPins */
-	mov.l PECRL3_A, r1
-	mov.l PECRL3_D, r0
-	mov.w r0,@r1
+	write16	PECRL3_A, PECRL3_D
 
-	mov.l PCCRL4_A, r1
-	mov.l PCCRL4_D0, r0
-	mov.w r0,@r1
+	write16	PCCRL4_A, PCCRL4_D0
 
-	mov.l PECRL4_A, r1
-	mov.l PECRL4_D0, r0
-	mov.w r0,@r1
+	write16	PECRL4_A, PECRL4_D0
 
-	mov.l PEIORL_A, r1
-	mov.l PEIORL_D0, r0
-	mov.w r0,@r1
+	write16	PEIORL_A, PEIORL_D0
 
-	mov.l PCIORL_A, r1
-	mov.l PCIORL_D, r0
-	mov.w r0,@r1
+	write16	PCIORL_A, PCIORL_D
 
-	mov.l PFCRH2_A, r1
-	mov.l PFCRH2_D, r0
-	mov.w r0,@r1
+	write16	PFCRH2_A, PFCRH2_D
 
-	mov.l PFCRH3_A, r1
-	mov.l PFCRH3_D, r0
-	mov.w r0,@r1
+	write16	PFCRH3_A, PFCRH3_D
 
-	mov.l PFCRH1_A, r1
-	mov.l PFCRH1_D, r0
-	mov.w r0,@r1
+	write16	PFCRH1_A, PFCRH1_D
 
-	mov.l PFIORH_A, r1
-	mov.l PFIORH_D, r0
-	mov.w r0,@r1
+	write16	PFIORH_A, PFIORH_D
 
-	mov.l PECRL1_A, r1
-	mov.l PECRL1_D0, r0
-	mov.w r0,@r1
+	write16	PECRL1_A, PECRL1_D0
 
-	mov.l PEIORL_A, r1
-	mov.l PEIORL_D1, r0
-	mov.w r0,@r1
+	write16	PEIORL_A, PEIORL_D1
 
 	/* Configure Operating Frequency */
-	mov.l WTCSR_A ,r1
-	mov.l WTCSR_D0 ,r0
-	mov.w r0,@r1
+	write16	WTCSR_A, WTCSR_D0
 
-	mov.l WTCSR_A ,r1
-	mov.l WTCSR_D1 ,r0
-	mov.w r0,@r1
+	write16	WTCSR_A, WTCSR_D1
 
-	mov.l WTCNT_A ,r1
-	mov.l WTCNT_D ,r0
-	mov.w r0,@r1
+	write16	WTCNT_A, WTCNT_D
 
 	/* Set clock mode*/
-	mov.l FRQCR_A,r1
-	mov.l FRQCR_D,r0
-	mov.w r0,@r1
+	write16	FRQCR_A, FRQCR_D
 
 	/* Configure Bus And Memory */
 init_bsc_cs0:
-	mov.l   PCCRL4_A,r1
-	mov.l   PCCRL4_D1,r0
-	mov.w   r0,@r1
+	write16	PCCRL4_A, PCCRL4_D1
 
-	mov.l   PECRL1_A,r1
-	mov.l   PECRL1_D1,r0
-	mov.w   r0,@r1
+	write16	PECRL1_A, PECRL1_D1
 
-	mov.l CMNCR_A,r1
-	mov.l CMNCR_D,r0
-	mov.l r0,@r1
+	write32	CMNCR_A, CMNCR_D
 
-	mov.l SC0BCR_A,r1
-	mov.l SC0BCR_D,r0
-	mov.l r0,@r1
+	write32	SC0BCR_A, SC0BCR_D
 
-	mov.l CS0WCR_A,r1
-	mov.l CS0WCR_D,r0
-	mov.l r0,@r1
+	write32	CS0WCR_A, CS0WCR_D
 
 init_bsc_cs1:
-	mov.l   PECRL4_A,r1
-	mov.l   PECRL4_D1,r0
-	mov.w   r0,@r1
+	write16	PECRL4_A, PECRL4_D1
 
-	mov.l CS1WCR_A,r1
-	mov.l CS1WCR_D,r0
-	mov.l r0,@r1
+	write32	CS1WCR_A, CS1WCR_D
 
 init_sdram:
-	mov.l	PCCRL2_A,r1
-	mov.l	PCCRL2_D,r0
-	mov.w	r0,@r1
+	write16	PCCRL2_A, PCCRL2_D
 
-	mov.l	PCCRL4_A,r1
-	mov.l	PCCRL4_D2,r0
-	mov.w   r0,@r1
+	write16	PCCRL4_A, PCCRL4_D2
 
-	mov.l   PCCRL1_A,r1
-	mov.l	PCCRL1_D,r0
-	mov.w   r0,@r1
+	write16	PCCRL1_A, PCCRL1_D
 
-	mov.l   PCCRL3_A,r1
-	mov.l	PCCRL3_D,r0
-	mov.w   r0,@r1
+	write16	PCCRL3_A, PCCRL3_D
 
-	mov.l CS3BCR_A,r1
-	mov.l CS3BCR_D,r0
-	mov.l r0,@r1
+	write32	CS3BCR_A, CS3BCR_D
 
-	mov.l CS3WCR_A,r1
-	mov.l CS3WCR_D,r0
-	mov.l r0,@r1
+	write32	CS3WCR_A, CS3WCR_D
 
-	mov.l SDCR_A,r1
-	mov.l SDCR_D,r0
-	mov.l r0,@r1
+	write32	SDCR_A, SDCR_D
 
-	mov.l RTCOR_A,r1
-	mov.l RTCOR_D,r0
-	mov.l r0,@r1
+	write32	RTCOR_A, RTCOR_D
 
-	mov.l RTCSR_A,r1
-	mov.l RTCSR_D,r0
-	mov.l r0,@r1
+	write32	RTCSR_A, RTCSR_D
 
 	/* wait 200us */
-	mov.l   REPEAT_D,r3
-	mov     #0,r2
+	mov.l	REPEAT_D, r3
+	mov	#0, r2
 repeat0:
-	add     #1,r2
-	cmp/hs  r3,r2
-	bf      repeat0
+	add	#1, r2
+	cmp/hs	r3, r2
+	bf	repeat0
 	nop
 
-	mov.l SDRAM_MODE, r1
-	mov   #0,r0
-	mov.l r0, @r1
+	mov.l	SDRAM_MODE, r1
+	mov	#0, r0
+	mov.l	r0, @r1
 
 	nop
 	rts
@@ -208,8 +145,8 @@ PECRL1_D0:	.long 0x00000033
 
 
 WTCSR_A:	.long 0xFFFE0000
-WTCSR_D0: 	.long 0x0000A518
-WTCSR_D1: 	.long 0x0000A51D
+WTCSR_D0:	.long 0x0000A518
+WTCSR_D1:	.long 0x0000A51D
 WTCNT_A:	.long 0xFFFE0002
 WTCNT_D:	.long 0x00005A84
 FRQCR_A:	.long 0xFFFE0010
@@ -259,7 +196,7 @@ STBCR4_A:	.long 0xFFFE040C
 STBCR4_D:	.long 0x00000008
 STBCR5_A:	.long 0xFFFE0410
 STBCR5_D:	.long 0x00000000
-STBCR6_A: 	.long 0xFFFE0414
+STBCR6_A:	.long 0xFFFE0414
 STBCR6_D:	.long 0x00000002
 SDRAM_MODE:	.long 0xFFFC5040
 REPEAT_D:	.long 0x00009C40

board/renesas/sh7763rdp/lowlevel_init.S

@@ -25,6 +25,7 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 	.global	lowlevel_init
 
@@ -33,218 +34,141 @@
 
 lowlevel_init:
 
-	mov.l   WDTCSR_A, r1	/* Watchdog Control / Status Register */
-	mov.l   WDTCSR_D, r0
-	mov.l   r0, @r1
+	write32	WDTCSR_A, WDTCSR_D	/* Watchdog Control / Status Register */
 
-	mov.l   WDTST_A, r1		/* Watchdog Stop Time Register */
-	mov.l   WDTST_D, r0
-	mov.l   r0, @r1
+	write32	WDTST_A, WDTST_D	/* Watchdog Stop Time Register */
 
-	mov.l   WDTBST_A, r1	/* 0xFFCC0008 (Watchdog Base Stop Time Register */
-	mov.l   WDTBST_D, r0
-	mov.l   r0, @r1
+	write32	WDTBST_A, WDTBST_D	/*
+					 * 0xFFCC0008
+					 * Watchdog Base Stop Time Register
+					 */
 
-	mov.l	CCR_A, r1		/* Address of Cache Control Register */
-	mov.l	CCR_CACHE_ICI_D, r0	/* Instruction Cache Invalidate */
-	mov.l	r0, @r1
+	write32	CCR_A, CCR_CACHE_ICI_D	/* Address of Cache Control Register */
+					/* Instruction Cache Invalidate */
 
-	mov.l	MMUCR_A, r1		/* Address of MMU Control Register */
-	mov.l	MMU_CONTROL_TI_D, r0	/* TI == TLB Invalidate bit */
-	mov.l	r0, @r1
+	write32	MMUCR_A, MMU_CONTROL_TI_D	/* MMU Control Register */
+						/* TI == TLB Invalidate bit */
 
-	mov.l	MSTPCR0_A, r1	/* Address of Power Control Register 0 */
-	mov.l	MSTPCR0_D, r0
-	mov.l	r0, @r1
+	write32	MSTPCR0_A, MSTPCR0_D	/* Address of Power Control Register 0 */
 
-	mov.l	MSTPCR1_A, r1	/*i Address of Power Control Register 1 */
-	mov.l	MSTPCR1_D, r0
-	mov.l	r0, @r1
+	write32	MSTPCR1_A, MSTPCR1_D	/* Address of Power Control Register 1 */
 
-	mov.l	RAMCR_A,r1
-	mov.l	RAMCR_D,r0
-	mov.l	r0, @r1
+	write32	RAMCR_A, RAMCR_D
 
-	mov.l	MMSELR_A,r1
-	mov.l	MMSELR_D,r0
+	mov.l	MMSELR_A, r1
+	mov.l	MMSELR_D, r0
 	synco
 	mov.l	r0, @r1
 
-	mov.l	@r1,r2		/* execute two reads after setting MMSELR*/
-	mov.l	@r1,r2
+	mov.l	@r1, r2		/* execute two reads after setting MMSELR */
+	mov.l	@r1, r2
 	synco
 
 	/* issue memory read */
-	mov.l   DDRSD_START_A,r1	/* memory address to read*/
-	mov.l   @r1,r0
+	mov.l	DDRSD_START_A, r1	/* memory address to read*/
+	mov.l	@r1, r0
 	synco
 
-	mov.l	MIM8_A,r1
-	mov.l	MIM8_D,r0
-	mov.l	r0,@r1
+	write32	MIM8_A, MIM8_D
 
-	mov.l	MIMC_A,r1
-	mov.l	MIMC_D1,r0
-	mov.l	r0,@r1
+	write32	MIMC_A, MIMC_D1
 
-	mov.l	STRC_A,r1
-	mov.l	STRC_D,r0
-	mov.l	r0,@r1
+	write32	STRC_A, STRC_D
 
-	mov.l	SDR4_A,r1
-	mov.l	SDR4_D,r0
-	mov.l	r0,@r1
+	write32	SDR4_A, SDR4_D
 
-	mov.l	MIMC_A,r1
-	mov.l	MIMC_D2,r0
-	mov.l	r0,@r1
+	write32	MIMC_A, MIMC_D2
 
 	nop
 	nop
 	nop
 
-	mov.l	SCR4_A,r1
-	mov.l	SCR4_D3,r0
-	mov.l	r0,@r1
+	write32	SCR4_A, SCR4_D3
 
-	mov.l	SCR4_A,r1
-	mov.l	SCR4_D2,r0
-	mov.l	r0,@r1
+	write32	SCR4_A, SCR4_D2
 
-	mov.l	SDMR02000_A,r1
-	mov.l	SDMR02000_D,r0
-	mov.l	r0,@r1
+	write32	SDMR02000_A, SDMR02000_D
 
-	mov.l	SDMR00B08_A,r1
-	mov.l	SDMR00B08_D,r0
-	mov.l	r0,@r1
+	write32	SDMR00B08_A, SDMR00B08_D
 
-	mov.l	SCR4_A,r1
-	mov.l	SCR4_D2,r0
-	mov.l	r0,@r1
+	write32	SCR4_A, SCR4_D2
 
-	mov.l	SCR4_A,r1
-	mov.l	SCR4_D4,r0
-	mov.l	r0,@r1
+	write32	SCR4_A, SCR4_D4
 
 	nop
 	nop
 	nop
 	nop
 
-	mov.l	SCR4_A,r1
-	mov.l	SCR4_D4,r0
-	mov.l	r0,@r1
+	write32	SCR4_A, SCR4_D4
 
 	nop
 	nop
 	nop
 	nop
 
-	mov.l	SDMR00308_A,r1
-	mov.l	SDMR00308_D,r0
-	mov.l	r0,@r1
+	write32	SDMR00308_A, SDMR00308_D
 
-	mov.l	MIMC_A,r1
-	mov.l	MIMC_D3,r0
-	mov.l	r0,@r1
+	write32	MIMC_A, MIMC_D3
 
-	mov.l	SCR4_A,r1
-	mov.l	SCR4_D1,r0
-	mov.l	DELAY60_D,r3
+	mov.l	SCR4_A, r1
+	mov.l	SCR4_D1, r0
+	mov.l	DELAY60_D, r3
 
 delay_loop_60:
-	mov.l	r0,@r1
+	mov.l	r0, @r1
 	dt	r3
 	bf	delay_loop_60
 	nop
 
-	mov.l   CCR_A, r1	/* Address of Cache Control Register */
-	mov.l   CCR_CACHE_D_2, r0
-	mov.l   r0, @r1
+	write32	CCR_A, CCR_CACHE_D_2	/* Address of Cache Control Register */
 
 bsc_init:
-	mov.l	BCR_A, r1
-	mov.l	BCR_D, r0
-	mov.l	r0, @r1
+	write32	BCR_A, BCR_D
 
-	mov.l	CS0BCR_A, r1
-	mov.l	CS0BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS0BCR_A, CS0BCR_D
 
-	mov.l	CS1BCR_A,r1
-	mov.l	CS1BCR_D,r0
-	mov.l	r0,@r1
+	write32	CS1BCR_A, CS1BCR_D
 
-	mov.l	CS2BCR_A, r1
-	mov.l	CS2BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS2BCR_A, CS2BCR_D
 
-	mov.l	CS4BCR_A, r1
-	mov.l	CS4BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS4BCR_A, CS4BCR_D
 
-	mov.l	CS5BCR_A, r1
-	mov.l	CS5BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS5BCR_A, CS5BCR_D
 
-	mov.l	CS6BCR_A, r1
-	mov.l	CS6BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS6BCR_A, CS6BCR_D
 
-	mov.l	CS0WCR_A, r1
-	mov.l	CS0WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS0WCR_A, CS0WCR_D
 
-	mov.l	CS1WCR_A, r1
-	mov.l	CS1WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS1WCR_A, CS1WCR_D
 
-	mov.l	CS2WCR_A, r1
-	mov.l	CS2WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS2WCR_A, CS2WCR_D
 
-	mov.l	CS4WCR_A, r1
-	mov.l	CS4WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS4WCR_A, CS4WCR_D
 
-	mov.l	CS5WCR_A, r1
-	mov.l	CS5WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS5WCR_A, CS5WCR_D
 
-	mov.l	CS6WCR_A, r1
-	mov.l	CS6WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS6WCR_A, CS6WCR_D
 
-	mov.l	CS5PCR_A, r1
-	mov.l	CS5PCR_D, r0
-	mov.l	r0, @r1
+	write32	CS5PCR_A, CS5PCR_D
 
-	mov.l	CS6PCR_A, r1
-	mov.l	CS6PCR_D, r0
-	mov.l	r0, @r1
+	write32	CS6PCR_A, CS6PCR_D
 
-	mov.l	DELAY200_D,r3
+	mov.l	DELAY200_D, r3
 
 delay_loop_200:
 	dt	r3
 	bf	delay_loop_200
 	nop
 
-	mov.l	PSEL0_A,r1
-	mov.l	PSEL0_D,r0
-	mov.w	r0,@r1
+	write16	PSEL0_A, PSEL0_D
 
-	mov.l	PSEL1_A,r1
-	mov.l	PSEL1_D,r0
-	mov.w	r0,@r1
+	write16	PSEL1_A, PSEL1_D
 
-	mov.l	ICR0_A,r1
-	mov.l	ICR0_D,r0
-	mov.l	r0,@r1
+	write32	ICR0_A, ICR0_D
 
 	stc sr, r0	/* BL bit off(init=ON) */
-	mov.l   SR_MASK_D, r1
+	mov.l	SR_MASK_D, r1
 	and r1, r0
 	ldc r0, sr
 
@@ -321,7 +245,7 @@ CS4BCR_D:	.long	0x77777670
 CS5BCR_D:	.long	0x77777670
 CS6BCR_D:	.long	0x77777670
 CS0WCR_D:	.long	0x7777770F
-CS1WCR_D:	.long   0x22000002
+CS1WCR_D:	.long	0x22000002
 CS2WCR_D:	.long	0x7777770F
 CS4WCR_D:	.long	0x7777770F
 CS5WCR_D:	.long	0x7777770F

board/renesas/sh7785lcr/lowlevel_init.S

@@ -19,33 +19,7 @@
 #include <config.h>
 #include <version.h>
 #include <asm/processor.h>
-
-.macro	write32, addr, data
-	mov.l \addr ,r1
-	mov.l \data ,r0
-	mov.l r0, @r1
-.endm
-
-.macro	write16, addr, data
-	mov.l \addr ,r1
-	mov.l \data ,r0
-	mov.w r0, @r1
-.endm
-
-.macro	write8, addr, data
-	mov.l \addr ,r1
-	mov.l \data ,r0
-	mov.b r0, @r1
-.endm
-
-.macro	wait_timer, time
-	mov.l	\time ,r3
-1:
-	nop
-	tst	r3, r3
-	bf/s	1b
-	dt	r3
-.endm
+#include <asm/macro.h>
 
 #include <asm/processor.h>
 
@@ -305,7 +279,7 @@ CS4WCR_D:	.long	0x00101012
 CS_USB_BCR_D:	.long	0x11111200
 CS_USB_WCR_D:	.long	0x00020004
 
-/* SD setting  : 32bit mode = CS3, 29bit mode = CS6 */
+/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
 CS_SD_BCR_D:	.long	0x00000300
 CS_SD_WCR_D:	.long	0x00030108
 

common/fdt_support.c

@@ -610,7 +610,7 @@ int fdt_resize(void *blob)
 		fdt_size_dt_strings(blob) + sizeof(struct fdt_reserve_entry);
 
 	/* Make it so the fdt ends on a page boundary */
-	actualsize = ALIGN(actualsize, 0x1000);
+	actualsize = ALIGN(actualsize + ((uint)blob & 0xfff), 0x1000);
 	actualsize = actualsize - ((uint)blob & 0xfff);
 
 	/* Change the fdt header to reflect the correct size */

config.mk

@@ -46,7 +46,7 @@ PLATFORM_LDFLAGS =
 
 #########################################################################
 
-ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
+ifeq ($(HOSTOS),darwin)
 HOSTCC		= cc
 else
 HOSTCC		= gcc
@@ -181,7 +181,7 @@ endif
 #
 # So far, this is used only by tools/gdb/Makefile.
 
-ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
+ifeq ($(HOSTOS),darwin)
 BFD_ROOT_DIR =		/usr/local/tools
 else
 ifeq ($(HOSTARCH),$(ARCH))

cpu/sh2/Makefile

@@ -28,19 +28,24 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).a
 
-START	= start.o
-OBJS	= cpu.o interrupts.o watchdog.o
+SOBJS	= start.o
+COBJS	= cpu.o interrupts.o watchdog.o
 
-all:	.depend $(START) $(LIB)
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
 
 #########################################################################
 
-.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
-
 # defines $(obj).depend target
 include $(SRCTREE)/rules.mk
 

drivers/serial/serial_sh.c

@@ -18,6 +18,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/processor.h>
 
 #if defined(CONFIG_CONS_SCIF0)
@@ -49,7 +50,7 @@
 # define SCFRDR	(vu_char  *)(SCIF_BASE + 0x24)
 #else
 # define SCFTDR (vu_char  *)(SCIF_BASE + 0xC)
-# define SCFSR 	(vu_short *)(SCIF_BASE + 0x10)
+# define SCFSR	(vu_short *)(SCIF_BASE + 0x10)
 # define SCFRDR (vu_char  *)(SCIF_BASE + 0x14)
 #endif
 
@@ -64,7 +65,7 @@
 #elif defined(CONFIG_CPU_SH7763)
 # if defined(CONFIG_CONS_SCIF2)
 # define SCSPTR	(vu_short *)(SCIF_BASE + 0x20)
-# define SCLSR 	(vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR	(vu_short *)(SCIF_BASE + 0x24)
 # define LSR_ORER	1
 # define FIFOLEVEL_MASK	0x1F
 # else
@@ -90,7 +91,7 @@
 	defined(CONFIG_CPU_SH7722) || \
 	defined(CONFIG_CPU_SH7203)
 # define SCSPTR	(vu_short *)(SCIF_BASE + 0x20)
-# define SCLSR 	(vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR	(vu_short *)(SCIF_BASE + 0x24)
 # define LSR_ORER	1
 # define FIFOLEVEL_MASK	0x1F
 #elif defined(CONFIG_CPU_SH7720)
@@ -106,42 +107,43 @@
 
 /* SCBRR register value setting */
 #if defined(CONFIG_CPU_SH7720)
-# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) (((clk * 2) + 16 * bps) / (32 * bps) - 1)
 #elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
 /* SH7723 SCIFA use bus clock. So clock *2 */
-# define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) (((clk * 2 * 2) + 16 * bps) / (32 * bps) - 1)
 #else /* Generic SuperH */
-# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) ((clk + 16 * bps) / (32 * bps) - 1)
 #endif
 
-#define SCR_RE 		(1 << 4)
-#define SCR_TE 		(1 << 5)
+#define SCR_RE		(1 << 4)
+#define SCR_TE		(1 << 5)
 #define FCR_RFRST	(1 << 1)	/* RFCL */
 #define FCR_TFRST	(1 << 2)	/* TFCL */
-#define FSR_DR   	(1 << 0)
-#define FSR_RDF  	(1 << 1)
-#define FSR_FER  	(1 << 3)
-#define FSR_BRK  	(1 << 4)
-#define FSR_FER  	(1 << 3)
-#define FSR_TEND 	(1 << 6)
-#define FSR_ER   	(1 << 7)
+#define FSR_DR		(1 << 0)
+#define FSR_RDF		(1 << 1)
+#define FSR_FER		(1 << 3)
+#define FSR_BRK		(1 << 4)
+#define FSR_FER		(1 << 3)
+#define FSR_TEND	(1 << 6)
+#define FSR_ER		(1 << 7)
 
 /*----------------------------------------------------------------------*/
 
 void serial_setbrg(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	*SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
+
+	writeb(SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ), SCBRR);
 }
 
 int serial_init(void)
 {
-	*SCSCR = (SCR_RE | SCR_TE);
-	*SCSMR = 0;
-	*SCSMR = 0;
-	*SCFCR = (FCR_RFRST | FCR_TFRST);
-	*SCFCR;
-	*SCFCR = 0;
+	writew((SCR_RE | SCR_TE), SCSCR);
+	writew(0, SCSMR);
+	writew(0, SCSMR);
+	writew((FCR_RFRST | FCR_TFRST), SCFCR);
+	readw(SCFCR);
+	writew(0, SCFCR);
 
 	serial_setbrg();
 	return 0;
@@ -150,9 +152,9 @@ int serial_init(void)
 static int serial_rx_fifo_level(void)
 {
 #if defined(SCRFDR)
-	return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
+	return (readw(SCRFDR) >> 0) & FIFOLEVEL_MASK;
 #else
-	return (*SCFDR >> 0) & FIFOLEVEL_MASK;
+	return (readw(SCFDR) >> 0) & FIFOLEVEL_MASK;
 #endif
 }
 
@@ -161,15 +163,15 @@ void serial_raw_putc(const char c)
 	unsigned int fsr_bits_to_clear;
 
 	while (1) {
-		if (*SCFSR & FSR_TEND) {	/* Tx fifo is empty */
+		if (readw(SCFSR) & FSR_TEND) { /* Tx fifo is empty */
 			fsr_bits_to_clear = FSR_TEND;
 			break;
 		}
 	}
 
-	*SCFTDR = c;
+	writeb(c, SCFTDR);
 	if (fsr_bits_to_clear != 0)
-		*SCFSR &= ~fsr_bits_to_clear;
+		writew(readw(SCFSR) & ~fsr_bits_to_clear, SCFSR);
 }
 
 void serial_putc(const char c)
@@ -191,26 +193,25 @@ int serial_tstc(void)
 	return serial_rx_fifo_level() ? 1 : 0;
 }
 
-#define FSR_ERR_CLEAR   0x0063
-#define RDRF_CLEAR      0x00fc
+#define FSR_ERR_CLEAR	0x0063
+#define RDRF_CLEAR		0x00fc
 void handle_error(void)
 {
-
-	(void)*SCFSR;
-	*SCFSR = FSR_ERR_CLEAR;
-	(void)*SCLSR;
-	*SCLSR = 0x00;
+	readw(SCFSR);
+	writew(FSR_ERR_CLEAR, SCFSR);
+	readw(SCLSR);
+	writew(0x00, SCLSR);
 }
 
 int serial_getc_check(void)
 {
 	unsigned short status;
 
-	status = *SCFSR;
+	status = readw(SCFSR);
 
 	if (status & (FSR_FER | FSR_ER | FSR_BRK))
 		handle_error();
-	if (*SCLSR & LSR_ORER)
+	if (readw(SCLSR) & LSR_ORER)
 		handle_error();
 	return status & (FSR_DR | FSR_RDF);
 }
@@ -223,15 +224,15 @@ int serial_getc(void)
 	while (!serial_getc_check())
 		;
 
-	ch = *SCFRDR;
-	status = *SCFSR;
+	ch = readb(SCFRDR);
+	status = readw(SCFSR);
 
-	*SCFSR = RDRF_CLEAR;
+	writew(RDRF_CLEAR, SCFSR);
 
 	if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
 		handle_error();
 
-	if (*SCLSR & LSR_ORER)
+	if (readw(SCLSR) & LSR_ORER)
 		handle_error();
 
 	return ch;

include/asm-sh/macro.h

@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACRO_H__
+#define __MACRO_H__
+#ifdef __ASSEMBLY__
+
+.macro	write32, addr, data
+	mov.l \addr ,r1
+	mov.l \data ,r0
+	mov.l r0, @r1
+.endm
+
+.macro	write16, addr, data
+	mov.l \addr ,r1
+	mov.l \data ,r0
+	mov.w r0, @r1
+.endm
+
+.macro	write8, addr, data
+	mov.l \addr ,r1
+	mov.l \data ,r0
+	mov.b r0, @r1
+.endm
+
+.macro	wait_timer, time
+	mov.l	\time ,r3
+1:
+	nop
+	tst	r3, r3
+	bf/s	1b
+	dt	r3
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __MACRO_H__ */

include/configs/CPCI4052.h

@@ -216,6 +216,8 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is

include/configs/CPCI405AB.h

@@ -92,6 +92,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
 
@@ -212,6 +213,8 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is

lib_sh/time.c

@@ -49,21 +49,21 @@ int timer_init (void)
 {
 	/* Divide clock by TMU_CLK_DIVIDER */
 	u16 bit = 0;
-	switch( TMU_CLK_DIVIDER ){
-	case 4:
-		bit = 0;
-		break;
-	case 16:
-		bit = 1;
-		break;
-	case 64: bit = 2;
+
+	switch (TMU_CLK_DIVIDER) {
+	case 1024:
+		bit = 4;
 		break;
 	case 256:
 		bit = 3;
 		break;
-	case 1024:
-		bit = 4;
+	case 64:
+		bit = 2;
 		break;
+	case 16:
+		bit = 1;
+		break;
+	case 4:
 	default:
 		bit = 0;
 		break;
@@ -71,7 +71,7 @@ int timer_init (void)
 	writew(readw(TCR0) | bit, TCR0);
 
 	/* Clock adjustment calc */
-	clk_adj = (int)(1.0/((1.0/CONFIG_SYS_HZ)*1000000));
+	clk_adj = (int)(1.0 / ((1.0 / CONFIG_SYS_HZ) * 1000000));
 	if (clk_adj < 1)
 		clk_adj = 1;
 
@@ -102,8 +102,8 @@ void udelay (unsigned long usec)
 
 unsigned long get_timer (unsigned long base)
 {
-	/*  return msec */
-	return ((get_usec()/clk_adj)/1000) - base;
+	/* return msec */
+	return ((get_usec() / clk_adj) / 1000) - base;
 }
 
 void set_timer (unsigned long t)

lib_sh/time_sh2.c

@@ -28,7 +28,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-#define CMT_CMCSR_INIT  0x0001	/* PCLK/32 */
+#define CMT_CMCSR_INIT	0x0001	/* PCLK/32 */
 #define CMT_CMCSR_CALIB 0x0000
 #define CMT_MAX_COUNTER (0xFFFFFFFF)
 #define CMT_TIMER_RESET (0xFFFF)
@@ -87,7 +87,7 @@ static unsigned long get_usec (void)
 /* return msec */
 ulong get_timer(ulong base)
 {
-	return (get_usec()/1000) - base;
+	return (get_usec() / 1000) - base;
 }
 
 void set_timer(ulong t)

tools/ncb.c

@@ -8,7 +8,7 @@ int main (int argc, char *argv[])
 	int s, len, o, port = 6666;
 	char buf[512];
 	struct sockaddr_in addr;
-	int addr_len = sizeof addr;
+	socklen_t addr_len = sizeof addr;
 
 	if (argc > 1)
 		port = atoi (argv[1]);