Prepare v2010.03

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

@@ -1,3 +1,155 @@
+commit 8e64d6efd8d778a5f83d8bff9cd273a86dcc182f
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Mar 31 08:34:51 2010 +0200
+
+    net, doc: How to setup MAC address correctly
+
+    As this seems unclear, document how the flow of setting up
+    the MAC address is correct.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+    Text changed slightly, adding input from Mike Frysinger.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit b78b48c6a0c34b2991e31fc4548aaf773d34f2b3
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Mar 31 08:34:46 2010 +0200
+
+    net, fec_mxc: only setup the device enetaddr with eeprom value
+
+    Only fill the device enetaddr with the contents of the eeprom,
+    do not program it in MAC address registers
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit d5a64237d58ded31c2eed455c7a346e1c85f5565
+Author: Felix Radensky <felix@embedded-sol.com>
+Date:	Tue Mar 30 15:02:13 2010 +0300
+
+    doc: Fix ramdisk examples in doc/uImage.FIT/multi.its
+
+    The ramdisk sections in doc/uImage.FIT/multi.its lack
+    load address and entry point properties. Using examples
+    from this file will result in unbootable image, u-boot
+    will issue the following error messages:
+
+    Can't get ramdisk subimage load address!
+    Ramdisk image is corrupt or invalid
+
+    This patch adds missing properties to ramdisk sections.
+
+    Signed-off-by: Felix Radensky <felix@embedded-sol.com>
+
+commit 2d2018f3db5ed834bc1ee208a2c6212fdf00bca1
+Author: Heiko Schocher <heiko.schocher@invitel.hu>
+Date:	Wed Mar 24 13:22:50 2010 +0100
+
+    jffs2, suen3: Fix compiler warning
+
+    $ ./MAKEALL suen3
+    jffs2_1pass.c: In function 'get_fl_mem':
+    jffs2_1pass.c:399: warning: unused variable 'id'
+    jffs2_1pass.c: In function 'get_node_mem':
+    jffs2_1pass.c:423: warning: unused variable 'id'
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Tested-by: Tom <Tom.Rix@windriver.com>
+
+commit 9ff32d8ccf0e23b5577c25610f001af8d761b4a2
+Author: Timur Tabi <timur@freescale.com>
+Date:	Mon Mar 29 12:51:07 2010 -0500
+
+    mpc86xx: set the DDR BATs after calculating true DDR size
+
+    After determining how much DDR is actually in the system, set DBAT0 and
+    IBAT0 accordingly.	This ensures that the CPU won't attempt to access
+    (via speculation) addresses outside of actual memory.
+
+    On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
+    and kept that way.	If the system has less than 2GB of memory (typical for
+    an MPC8610 HPCD), the CPU may attempt to access this memory during
+    speculation.  The zlib code is notorious for generating such memory reads,
+    and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
+    check (without this patch).
+
+    Currently we are limited to power of two sized DDR since we only use a
+    single bat.  If a non-power of two size is used that is less than
+    CONFIG_MAX_MEM_MAPPED u-boot will crash.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 33f57bd553edf29dffef5a6c7d76e169c79a6049
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Fri Mar 26 15:14:43 2010 -0500
+
+    85xx: Fix enabling of L1 cache parity on secondary cores
+
+    Use the same code between primary and secondary cores to init the
+    L1 cache.  We were not enabling cache parity on the secondary cores.
+
+    Also, reworked the L1 cache init code to match the e500mc L2 init code
+    that first invalidates the cache and locks.  Than enables the cache and
+    makes sure its enabled before continuing.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 1a332da61df9c38b567359af114daeaaaefaead8
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Mar 29 15:30:46 2010 +0200
+
+    ppc4xx: Fix problem with I2C bus >= 1 initialization
+
+    This patch fixes a problem introduced with patch eb5eb2b0
+    [ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C
+    base address to the "i2c" pointer inside of the controller loop.
+    Otherwise controller 0 is initialized multiple times instead of
+    initializing each I2C controller sequentially.
+
+    Tested on Katmai.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Acked-by: Heiko Schocher <hs@denx.de>
+
+commit 24de2f4be00f81c58270d0df47296bf3a3601cef
+Author: Heiko Schocher <hs@denx.de>
+Date:	Mon Mar 29 13:15:48 2010 +0200
+
+    bootm, linux: fix booting Multi-File Image with "kernel+ramdisk+fdt"
+
+    Booting a "Multi-File Image" including a linux kernel, ramdisk and
+    fdt, generated with
+
+    mkimage -A ppc \
+	-O linux \
+	-T multi \
+	-C gzip \
+	-a 00000000 \
+	-e 00000000 \
+	-n "kernel-2.6+initrd+dtb" \
+	-d "vmlinux.bin.gz:ramdisk_image.gz:board.dtb" \
+	multi.bin
+
+    actually fails, because ramdisk start and end addresses
+    didn;t get initialized. This patch fixes this issue.
+
+    Tested on the KUP4K board.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 2883cc2d48e99fd1873ef8af03fee7966611b735
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Mar 28 00:25:14 2010 +0100
+
+    Prepare 2010.03-rc3
+
+    Update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 060f28532b09dd3d2c78423bdd809ac768a27629
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Thu Mar 25 14:07:23 2010 +0100

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2010
 PATCHLEVEL = 03
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else

board/freescale/mpc8610hpcd/mpc8610hpcd.c

@@ -127,6 +127,8 @@ initdram(int board_type)
 	dram_size = fixed_sdram();
 #endif
 
+	setup_ddr_bat(dram_size);
+
 	puts(" DDR: ");
 	return dram_size;
 }

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -74,6 +74,8 @@ initdram(int board_type)
 	dram_size = fixed_sdram();
 #endif
 
+	setup_ddr_bat(dram_size);
+
 	puts("    DDR: ");
 	return dram_size;
 }

common/cmd_bootm.c

@@ -291,7 +291,8 @@ static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	if ((images.os.type == IH_TYPE_KERNEL) &&
+	if (((images.os.type == IH_TYPE_KERNEL) ||
+	     (images.os.type == IH_TYPE_MULTI)) &&
 	    (images.os.os == IH_OS_LINUX)) {
 		/* find ramdisk */
 		ret = boot_get_ramdisk (argc, argv, &images, IH_INITRD_ARCH,

cpu/mpc85xx/release.S

@@ -70,18 +70,40 @@ __secondary_start_page:
 	mttbu	r3
 
 	/* Enable/invalidate the I-Cache */
-	mfspr	r0,SPRN_L1CSR1
-	ori	r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
-	mtspr	SPRN_L1CSR1,r0
+	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+	mtspr	SPRN_L1CSR1,r2
+1:
+	mfspr	r3,SPRN_L1CSR1
+	and.	r1,r3,r2
+	bne	1b
+
+	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+	mtspr	SPRN_L1CSR1,r3
 	isync
+2:
+	mfspr	r3,SPRN_L1CSR1
+	andi.	r1,r3,L1CSR1_ICE@l
+	beq	2b
 
 	/* Enable/invalidate the D-Cache */
-	mfspr	r0,SPRN_L1CSR0
-	ori	r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
-	msync
-	isync
-	mtspr	SPRN_L1CSR0,r0
+	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+	mtspr	SPRN_L1CSR0,r2
+1:
+	mfspr	r3,SPRN_L1CSR0
+	and.	r1,r3,r2
+	bne	1b
+
+	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+	mtspr	SPRN_L1CSR0,r3
 	isync
+2:
+	mfspr	r3,SPRN_L1CSR0
+	andi.	r1,r3,L1CSR0_DCE@l
+	beq	2b
 
 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
 

cpu/mpc85xx/start.S

@@ -108,13 +108,41 @@ _start_e500:
 	mtspr	L1CSR2,r2
 #endif
 
-	lis	r2,L1CSR0_CPE@H	/* enable parity */
-	ori	r2,r2,L1CSR0_DCE
-	mtspr	L1CSR0,r2	/* enable L1 Dcache */
+	/* Enable/invalidate the I-Cache */
+	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+	mtspr	SPRN_L1CSR1,r2
+1:
+	mfspr	r3,SPRN_L1CSR1
+	and.	r1,r3,r2
+	bne	1b
+
+	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+	mtspr	SPRN_L1CSR1,r3
 	isync
-	mtspr	L1CSR1,r2	/* enable L1 Icache */
+2:
+	mfspr	r3,SPRN_L1CSR1
+	andi.	r1,r3,L1CSR1_ICE@l
+	beq	2b
+
+	/* Enable/invalidate the D-Cache */
+	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+	mtspr	SPRN_L1CSR0,r2
+1:
+	mfspr	r3,SPRN_L1CSR0
+	and.	r1,r3,r2
+	bne	1b
+
+	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+	mtspr	SPRN_L1CSR0,r3
 	isync
-	msync
+2:
+	mfspr	r3,SPRN_L1CSR0
+	andi.	r1,r3,L1CSR0_DCE@l
+	beq	2b
 
 	/* Setup interrupt vectors */
 	lis	r1,TEXT_BASE@h

cpu/mpc86xx/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2006,2009 Freescale Semiconductor, Inc.
+ * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
  * Jeff Brown
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
@@ -197,3 +197,37 @@ void mpc86xx_reginfo(void)
 	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
 
 }
+
+/*
+ * Set the DDR BATs to reflect the actual size of DDR.
+ *
+ * dram_size is the actual size of DDR, in bytes
+ *
+ * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
+ * are using a single BAT to cover DDR.
+ *
+ * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
+ * is not defined) then we might have a situation where U-Boot will attempt
+ * to relocated itself outside of the region mapped by DBAT0.
+ * This will cause a machine check.
+ *
+ * Currently we are limited to power of two sized DDR since we only use a
+ * single bat.  If a non-power of two size is used that is less than
+ * CONFIG_MAX_MEM_MAPPED u-boot will crash.
+ *
+ */
+void setup_ddr_bat(phys_addr_t dram_size)
+{
+	unsigned long batu, bl;
+
+	bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
+
+	if (BATU_SIZE(bl) != dram_size) {
+		u64 sz = (u64)dram_size - BATU_SIZE(bl);
+		print_size(sz, " left unmapped\n");
+	}
+
+	batu = bl | BATU_VS | BATU_VP;
+	write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
+	write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
+}

cpu/mpc86xx/cpu_init.c

@@ -138,8 +138,12 @@ int cpu_init_r(void)
 /* Set up BAT registers */
 void setup_bats(void)
 {
+#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L)
 	write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
+#endif
+#if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
 	write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
+#endif
 	write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
 	write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
 	write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);

cpu/ppc4xx/i2c.c

@@ -93,7 +93,7 @@ static void _i2c_bus_reset(void)
 
 void i2c_init(int speed, int slaveaddr)
 {
-	struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
+	struct ppc4xx_i2c *i2c;
 	int val, divisor;
 	int bus;
 
@@ -109,6 +109,9 @@ void i2c_init(int speed, int slaveaddr)
 	for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
 		I2C_SET_BUS(bus);
 
+		/* Set i2c pointer after calling I2C_SET_BUS() */
+		i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
+
 		/* Handle possible failed I2C state */
 		/* FIXME: put this into i2c_init_board()? */
 		_i2c_bus_reset();

doc/README.enetaddr

@@ -28,6 +28,17 @@ Here are the places where MAC addresses might be stored:
 	      purpose of passing this information to an OS kernel we are about
 	      to boot
 
+Correct flow of setting up the MAC address (summarized):
+
+1. Read from hardware in initialize() function
+2. Read from environment in net/eth.c after initialize()
+3. Give priority to the value in the environment if a conflict
+4. Program hardware in the device's init() function.
+
+If somebody wants to subvert the design philosophy, this can be done
+in the board-specific board_eth_init() function by calling eth_init()
+after all the NICs have been registered.
+
 -------
  Usage
 -------

doc/uImage.FIT/multi.its

@@ -61,6 +61,8 @@
 			arch = "ppc";
 			os = "linux";
 			compression = "gzip";
+			load = <00000000>;
+			entry = <00000000>;
 			hash@1 {
 				algo = "sha1";
 			};
@@ -73,6 +75,8 @@
 			arch = "ppc";
 			os = "linux";
 			compression = "gzip";
+			load = <00000000>;
+			entry = <00000000>;
 			hash@1 {
 				algo = "crc32";
 			};

drivers/net/fec_mxc.c

@@ -752,7 +752,6 @@ static int fec_probe(bd_t *bd)
 	if (fec_get_hwaddr(edev, ethaddr) == 0) {
 		printf("got MAC address from EEPROM: %pM\n", ethaddr);
 		memcpy(edev->enetaddr, ethaddr, 6);
-		fec_set_hwaddr(edev);
 	}
 
 	return 0;

fs/jffs2/jffs2_1pass.c

@@ -398,23 +398,26 @@ static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf)
 {
 	struct mtdids *id = current_part->dev->id;
 
+	switch(id->type) {
 #if defined(CONFIG_CMD_FLASH)
-	if (id->type == MTD_DEV_TYPE_NOR) {
+	case MTD_DEV_TYPE_NOR:
 		return get_fl_mem_nor(off, size, ext_buf);
-	}
+		break;
 #endif
-
 #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
-	if (id->type == MTD_DEV_TYPE_NAND)
+	case MTD_DEV_TYPE_NAND:
 		return get_fl_mem_nand(off, size, ext_buf);
+		break;
 #endif
-
 #if defined(CONFIG_CMD_ONENAND)
-	if (id->type == MTD_DEV_TYPE_ONENAND)
+	case MTD_DEV_TYPE_ONENAND:
 		return get_fl_mem_onenand(off, size, ext_buf);
+		break;
 #endif
-
-	printf("get_fl_mem: unknown device type, using raw offset!\n");
+	default:
+		printf("get_fl_mem: unknown device type, " \
+			"using raw offset!\n");
+	}
 	return (void*)off;
 }
 
@@ -422,23 +425,27 @@ static inline void *get_node_mem(u32 off, void *ext_buf)
 {
 	struct mtdids *id = current_part->dev->id;
 
+	switch(id->type) {
 #if defined(CONFIG_CMD_FLASH)
-	if (id->type == MTD_DEV_TYPE_NOR)
+	case MTD_DEV_TYPE_NOR:
 		return get_node_mem_nor(off, ext_buf);
+		break;
 #endif
-
 #if defined(CONFIG_JFFS2_NAND) && \
     defined(CONFIG_CMD_NAND)
-	if (id->type == MTD_DEV_TYPE_NAND)
+	case MTD_DEV_TYPE_NAND:
 		return get_node_mem_nand(off, ext_buf);
+		break;
 #endif
-
 #if defined(CONFIG_CMD_ONENAND)
-	if (id->type == MTD_DEV_TYPE_ONENAND)
+	case MTD_DEV_TYPE_ONENAND:
 		return get_node_mem_onenand(off, ext_buf);
+		break;
 #endif
-
-	printf("get_node_mem: unknown device type, using raw offset!\n");
+	default:
+		printf("get_fl_mem: unknown device type, " \
+			"using raw offset!\n");
+	}
 	return (void*)off;
 }
 

include/asm-ppc/mmu.h

@@ -213,7 +213,11 @@ extern void print_bats(void);
 #define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000)		\
 				     | ((x & 0x0e00ULL) << 24)	\
 				     | ((x & 0x04ULL) << 30)))
-#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17))
+#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17))
+
+/* bytes into BATU_BL */
+#define TO_BATU_BL(x) \
+	(u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4)
 
 /* Used to set up SDR1 register */
 #define HASH_TABLE_SIZE_64K	0x00010000

include/asm-ppc/processor.h

@@ -485,10 +485,12 @@
 #define SPRN_L2CFG0	0x207	/* L2 Cache Configuration Register 0 */
 #define SPRN_L1CSR0	0x3f2	/* L1 Data Cache Control and Status Register 0 */
 #define   L1CSR0_CPE		0x00010000	/* Data Cache Parity Enable */
+#define   L1CSR0_DCLFR		0x00000100	/* D-Cache Lock Flash Reset */
 #define   L1CSR0_DCFI		0x00000002	/* Data Cache Flash Invalidate */
 #define   L1CSR0_DCE		0x00000001	/* Data Cache Enable */
 #define SPRN_L1CSR1	0x3f3	/* L1 Instruction Cache Control and Status Register 1 */
 #define   L1CSR1_CPE		0x00010000	/* Instruction Cache Parity Enable */
+#define   L1CSR1_ICLFR		0x00000100	/* I-Cache Lock Flash Reset */
 #define   L1CSR1_ICFI		0x00000002	/* Instruction Cache Flash Invalidate */
 #define   L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
 #define SPRN_L1CSR2	0x25e	/* L1 Data Cache Control and Status Register 2 */

include/configs/MPC8610HPCD.h

@@ -341,10 +341,8 @@
  * BAT0		2G	Cacheable, non-guarded
  * 0x0000_0000	2G	DDR
  */
-#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW)
 
 /*
  * BAT1		1G	Cache-inhibited, guarded

include/configs/MPC8641HPCN.h

@@ -482,9 +482,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * BAT0		DDR
  */
 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
 
 /*
  * BAT1		LBC (PIXIS/CF)

include/mpc86xx.h

@@ -83,5 +83,7 @@ static __inline__ unsigned long get_l2cr (void)
    return l2cr_val;
 }
 
+void setup_ddr_bat(phys_addr_t dram_size);
+
 #endif  /* _ASMLANGUAGE */
 #endif	/* __MPC86xx_H__ */