Prepare v

Signed-off-by: Wolfgang Denk <wd@denx.de>

MAINTAINERS

@@ -146,6 +146,7 @@ Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX
 	dlvision        PPC405EP
+	dlvision-10g	PPC405EP
 	gdppc440etx	PPC440EP/GR
 	intip		PPC460EX
 	io		PPC405EP
@@ -857,6 +858,15 @@ Prafulla Wadaskar <prafulla@marvell.com>
 	rd6281a		ARM926EJS (Kirkwood SoC)
 	sheevaplug	ARM926EJS (Kirkwood SoC)
 
+Tom Warren <twarren@nvidia.com>
+
+	harmony		Tegra2 (ARM7 & A9 Dual Core)
+	seaboard	Tegra2 (ARM7 & A9 Dual Core)
+
+Lei Wen <leiwen@marvell.com>
+
+	dkb		ARM926EJS (PANTHEON 88AP920 SOC)
+
 Matthias Weisser <weisserm@arcor.de>
 
 	jadecpu		ARM926EJS (MB86R01 SoC)
@@ -1036,6 +1046,7 @@ Mark Jonas <mark.jonas@de.bosch.com>
 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
 
 	MS7720SE	SH7720
+	R0P77570030RL	SH7757
 	R0P77850011RL	SH7785
 
 #########################################################################

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2011
 PATCHLEVEL = 03
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -235,6 +235,7 @@ endif
 LIBS += drivers/rtc/librtc.o
 LIBS += drivers/serial/libserial.o
 LIBS += drivers/twserial/libtws.o
+LIBS += drivers/usb/eth/libusb_eth.a
 LIBS += drivers/usb/gadget/libusb_gadget.o
 LIBS += drivers/usb/host/libusb_host.o
 LIBS += drivers/usb/musb/libusb_musb.o
@@ -1091,95 +1092,6 @@ smdk6400_config	:	unconfig
 	@$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx
 	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
 
-#========================================================================
-# MIPS
-#========================================================================
-#########################################################################
-## MIPS32 4Kc
-#########################################################################
-
-incaip_100MHz_config	\
-incaip_133MHz_config	\
-incaip_150MHz_config	\
-incaip_config: unconfig
-	@mkdir -p $(obj)include
-	@[ -z "$(findstring _100MHz,$@)" ] || \
-		echo "#define CPU_CLOCK_RATE 100000000" >>$(obj)include/config.h
-	@[ -z "$(findstring _133MHz,$@)" ] || \
-		echo "#define CPU_CLOCK_RATE 133000000" >>$(obj)include/config.h
-	@[ -z "$(findstring _150MHz,$@)" ] || \
-		echo "#define CPU_CLOCK_RATE 150000000" >>$(obj)include/config.h
-	@$(MKCONFIG) -n $@ -a incaip mips mips incaip
-
-vct_premium_config		\
-vct_premium_small_config	\
-vct_premium_onenand_config	\
-vct_premium_onenand_small_config \
-vct_platinum_config		\
-vct_platinum_small_config	\
-vct_platinum_onenand_config	\
-vct_platinum_onenand_small_config \
-vct_platinumavc_config		\
-vct_platinumavc_small_config	\
-vct_platinumavc_onenand_config	\
-vct_platinumavc_onenand_small_config: unconfig
-	@mkdir -p $(obj)include
-	@[ -z "$(findstring _premium,$@)" ] || \
-		echo "#define CONFIG_VCT_PREMIUM" > $(obj)include/config.h
-	@[ -z "$(findstring _platinum_,$@)" ] || \
-		echo "#define CONFIG_VCT_PLATINUM" > $(obj)include/config.h
-	@[ -z "$(findstring _platinumavc,$@)" ] || \
-		echo "#define CONFIG_VCT_PLATINUMAVC" > $(obj)include/config.h
-	@[ -z "$(findstring _onenand,$@)" ] || \
-		echo "#define CONFIG_VCT_ONENAND" >> $(obj)include/config.h
-	@[ -z "$(findstring _small,$@)" ] || \
-		echo "#define CONFIG_VCT_SMALL_IMAGE" >> $(obj)include/config.h
-	@$(MKCONFIG)  -n $@ -a vct mips mips vct micronas
-
-#########################################################################
-## MIPS32 AU1X00
-#########################################################################
-
-dbau1000_config		:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_DBAU1000 1" >$(obj)include/config.h
-	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
-
-dbau1100_config		:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_DBAU1100 1" >$(obj)include/config.h
-	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
-
-dbau1500_config		:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_DBAU1500 1" >$(obj)include/config.h
-	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
-
-dbau1550_config		:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h
-	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
-
-dbau1550_el_config	:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h
-	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
-
-gth2_config		:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_GTH2 1" >$(obj)include/config.h
-	@$(MKCONFIG) -a $@ mips mips gth2
-
-pb1000_config		:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_PB1000 1" >$(obj)include/config.h
-	@$(MKCONFIG) -a pb1x00 mips mips pb1x00
-
-qemu_mips_config	: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h
-	@$(MKCONFIG) -a qemu-mips mips mips qemu-mips
-
 #========================================================================
 # Nios
 #========================================================================

README

@@ -319,6 +319,11 @@ The following options need to be configured:
 			CONFIG_SYS_PQ2FADS	- PQ2FADS-ZU or PQ2FADS-VR
 			CONFIG_SYS_8272ADS	- MPC8272ADS
 
+- Marvell Family Member
+		CONFIG_SYS_MVFS		- define it if you want to enable
+					  multiple fs option at one time
+					  for marvell soc family
+
 - MPC824X Family Member (if CONFIG_MPC824X is defined)
 		Define exactly one of
 		CONFIG_MPC8240, CONFIG_MPC8245
@@ -892,6 +897,18 @@ The following options need to be configured:
 			automatically converts one 32 bit word to two 16 bit
 			words you may also try CONFIG_SMC911X_32_BIT.
 
+		CONFIG_SH_ETHER
+		Support for Renesas on-chip Ethernet controller
+
+			CONFIG_SH_ETHER_USE_PORT
+			Define the number of ports to be used
+
+			CONFIG_SH_ETHER_PHY_ADDR
+			Define the ETH PHY's address
+
+			CONFIG_SH_ETHER_CACHE_WRITEBACK
+			If this option is set, the driver enables cache flush.
+
 - USB Support:
 		At the moment only the UHCI host controller is
 		supported (PIP405, MIP405, MPC5200); define
@@ -1648,6 +1665,11 @@ The following options need to be configured:
 		SPI EEPROM, also an instance works with Crystal A/D and
 		D/As on the SACSng board)
 
+		CONFIG_SH_SPI
+
+		Enables the driver for SPI controller on SuperH. Currently
+		only SH7757 is supported.
+
 		CONFIG_SPI_X
 
 		Enables extended (16-bit) SPI EEPROM addressing.

arch/arm/cpu/arm1136/start.S

@@ -102,6 +102,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ
@@ -163,15 +167,7 @@ call_board_init_f:
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 	ldr	r0,=0x00000000
 
-#ifdef CONFIG_NAND_SPL
-	bl	nand_boot
-#else
-#ifdef CONFIG_ONENAND_IPL
-	bl	start_oneboot
-#else
 	bl	board_init_f
-#endif /* CONFIG_ONENAND_IPL */
-#endif /* CONFIG_NAND_SPL */
 
 /*------------------------------------------------------------------------------*/
 
@@ -267,14 +263,14 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
  */
 #ifdef CONFIG_NAND_SPL
 	ldr     r0, _nand_boot_ofs
-	adr	r1, _start
-	add	pc, r0, r1
-_nand_boot_ofs
-	: .word nand_boot - _start
+	mov	pc, r0
+
+_nand_boot_ofs:
+	.word nand_boot
 #else
 jump_2_ram:
 	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
+	ldr     r1, _TEXT_BASE
 	add	lr, r0, r1
 	add	lr, lr, r9
 	/* setup parameters for board_init_r */

arch/arm/cpu/arm1136/u-boot.lds

@@ -72,11 +72,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/arm1176/start.S

@@ -121,6 +121,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
@@ -352,9 +356,11 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	cmp	r0, r1
 	bne	clbss_l
 
+#ifndef CONFIG_NAND_SPL
 	bl coloured_LED_init
 	bl red_LED_on
 #endif
+#endif
 
 /*
  * We are done. Do not return, instead branch to second part of board

arch/arm/cpu/arm1176/u-boot.lds

@@ -61,11 +61,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/arm720t/start.S

@@ -91,6 +91,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/arm720t/u-boot.lds

@@ -62,11 +62,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/arm920t/ep93xx/u-boot.lds

@@ -55,5 +55,7 @@ SECTIONS
 	. = ALIGN(4);
 	__bss_start = .;
 	.bss : { *(.bss) }
+	__bss_end__ = .;
+
 	_end = .;
 }

arch/arm/cpu/arm920t/start.S

@@ -87,6 +87,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/arm920t/u-boot.lds

@@ -71,11 +71,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/arm925t/start.S

@@ -97,6 +97,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/arm925t/u-boot.lds

@@ -66,11 +66,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/arm926ejs/pantheon/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Lei Wen <leiwen@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	= cpu.o timer.o dram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm926ejs/pantheon/cpu.c

@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pantheon.h>
+#include <asm/io.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID	(1<<8)
+#define L2C_RAM_SEL	(1<<4)
+
+int arch_cpu_init(void)
+{
+	u32 val;
+	struct panthcpu_registers *cpuregs =
+		(struct panthcpu_registers*) PANTHEON_CPU_BASE;
+
+	struct panthapb_registers *apbclkres =
+		(struct panthapb_registers*) PANTHEON_APBC_BASE;
+
+	struct panthmpmu_registers *mpmu =
+		(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
+
+	/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
+	val = readl(&cpuregs->cpu_conf);
+	val = val | SET_MRVL_ID;
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Turn on clock gating (PMUM_CCGR) */
+	writel(0xFFFFFFFF, &mpmu->ccgr);
+
+	/* Turn on clock gating (PMUM_ACGR) */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on uart2 clock */
+	writel(UARTCLK14745KHZ, &apbclkres->uart0);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK, &apbclkres->gpio);
+
+	icache_enable();
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 id;
+	struct panthcpu_registers *cpuregs =
+		(struct panthcpu_registers*) PANTHEON_CPU_BASE;
+
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+	return 0;
+}
+#endif

arch/arm/cpu/arm926ejs/pantheon/dram.c

@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>,
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pantheon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Pantheon DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet 4.4
+ */
+struct panthddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+	u32	pad[3];
+};
+
+struct panthddr_registers {
+	u8	pad[0x100 - 0x000];
+	struct panthddr_map_registers mmap[2];
+};
+
+/*
+ * panth_sdram_base - reads SDRAM Base Address Register
+ */
+u32 panth_sdram_base(int chip_sel)
+{
+	struct panthddr_registers *ddr_regs =
+		(struct panthddr_registers *)PANTHEON_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * panth_sdram_size - reads SDRAM size
+ */
+u32 panth_sdram_size(int chip_sel)
+{
+	struct panthddr_registers *ddr_regs =
+		(struct panthddr_registers *)PANTHEON_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return ((0x8 << (result - 0x7)) * 1024 * 1024);
+	}
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = panth_sdram_base(i);
+		gd->bd->bi_dram[i].size = panth_sdram_size(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/*
+		 * If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash
+		 */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */

arch/arm/cpu/arm926ejs/pantheon/timer.c

@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pantheon.h>
+
+/*
+ * Timer registers
+ * Refer 6.2.9 in Datasheet
+ */
+struct panthtmr_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr[3];
+};
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+
+/*
+ * For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct panthtmr_registers *panthtimers =
+		(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
+	volatile int loop=100;
+	ulong val;
+
+	writel(COUNT_RD_REQ, &panthtimers->cvwr);
+	while (loop--)
+		val = readl(&panthtimers->cvwr);
+
+	/*
+	 * This stop gcc complain and prevent loop mistake init to 0
+	 */
+	val = readl(&panthtimers->cvwr);
+
+	return val;
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	gd->tbl = read_timer();
+	gd->tbu = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->tbl) {
+		/* normal mode */
+		gd->tbu += now - gd->tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+	}
+	gd->tbl = now;
+
+	return gd->tbu;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+		base);
+}
+
+void set_timer(ulong t)
+{
+	gd->tbu = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime)
+		;
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct panthapb_registers *apb1clkres =
+		(struct panthapb_registers *) PANTHEON_APBC_BASE;
+	struct panthtmr_registers *panthtimers =
+		(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
+
+	/* Enable Timer clock at 3.25 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &panthtimers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &panthtimers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x1, &panthtimers->preload_ctrl[TIMER]);
+
+	/* Enable timer 0 */
+	writel(0x1, &panthtimers->cer);
+	/* init the gd->tbu and gd->tbl value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+#define MPMU_APRR_WDTR	(1<<4)
+#define TMR_WFAR	0xbaba	/* WDT Register First key */
+#define TMP_WSAR	0xeb10	/* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+	struct panthmpmu_registers *mpmu =
+		(struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
+	struct panthtmr_registers *panthtimers =
+		(struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
+	u32 val;
+
+	/* negate hardware reset to the WDT after system reset */
+	val = readl(&mpmu->aprr);
+	val = val | MPMU_APRR_WDTR;
+	writel(val, &mpmu->aprr);
+
+	/* reset/enable WDT clock */
+	writel(APBC_APBCLK, &mpmu->wdtpcr);
+
+	/* clear previous WDT status */
+	writel(TMR_WFAR, &panthtimers->wfar);
+	writel(TMP_WSAR, &panthtimers->wsar);
+	writel(0, &panthtimers->wdt_sts);
+
+	/* set match counter */
+	writel(TMR_WFAR, &panthtimers->wfar);
+	writel(TMP_WSAR, &panthtimers->wsar);
+	writel(0xf, &panthtimers->wdt_match_r);
+
+	/* enable WDT reset */
+	writel(TMR_WFAR, &panthtimers->wfar);
+	writel(TMP_WSAR, &panthtimers->wsar);
+	writel(0x3, &panthtimers->wdt_match_en);
+
+	/*enable functional WDT clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+}

arch/arm/cpu/arm926ejs/start.S

@@ -131,6 +131,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ
@@ -281,7 +285,7 @@ _nand_boot_ofs:
 	.word nand_boot
 #else
 	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
+	ldr	r1, _TEXT_BASE
 	add	lr, r0, r1
 	add	lr, lr, r9
 	/* setup parameters for board_init_r */

arch/arm/cpu/arm926ejs/u-boot.lds

@@ -63,11 +63,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/arm946es/start.S

@@ -103,6 +103,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/arm946es/u-boot.lds

@@ -63,11 +63,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/arm_intcm/start.S

@@ -99,6 +99,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/arm_intcm/u-boot.lds

@@ -63,11 +63,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/armv7/s5p-common/Makefile

@@ -27,6 +27,7 @@ LIB	= $(obj)libs5p-common.o
 
 COBJS-y		+= cpu_info.o
 COBJS-y		+= timer.o
+COBJS-$(CONFIG_PWM)		+= pwm.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))

arch/arm/cpu/armv7/s5p-common/pwm.c

@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/clk.h>
+
+int pwm_enable(int pwm_id)
+{
+	const struct s5p_timer *pwm =
+			(struct s5p_timer *)samsung_get_base_timer();
+	unsigned long tcon;
+
+	tcon = readl(&pwm->tcon);
+	tcon |= TCON_START(pwm_id);
+
+	writel(tcon, &pwm->tcon);
+
+	return 0;
+}
+
+void pwm_disable(int pwm_id)
+{
+	const struct s5p_timer *pwm =
+			(struct s5p_timer *)samsung_get_base_timer();
+	unsigned long tcon;
+
+	tcon = readl(&pwm->tcon);
+	tcon &= ~TCON_START(pwm_id);
+
+	writel(tcon, &pwm->tcon);
+}
+
+static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
+{
+	unsigned long tin_parent_rate;
+	unsigned int div;
+
+	tin_parent_rate = get_pwm_clk();
+
+	for (div = 2; div <= 16; div *= 2) {
+		if ((tin_parent_rate / (div << 16)) < freq)
+			return tin_parent_rate / div;
+	}
+
+	return tin_parent_rate / 16;
+}
+
+#define NS_IN_HZ (1000000000UL)
+
+int pwm_config(int pwm_id, int duty_ns, int period_ns)
+{
+	const struct s5p_timer *pwm =
+			(struct s5p_timer *)samsung_get_base_timer();
+	unsigned int offset;
+	unsigned long tin_rate;
+	unsigned long tin_ns;
+	unsigned long period;
+	unsigned long tcon;
+	unsigned long tcnt;
+	unsigned long timer_rate_hz;
+	unsigned long tcmp;
+
+	/*
+	 * We currently avoid using 64bit arithmetic by using the
+	 * fact that anything faster than 1GHz is easily representable
+	 * by 32bits.
+	 */
+	if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
+		return -ERANGE;
+
+	if (duty_ns > period_ns)
+		return -EINVAL;
+
+	period = NS_IN_HZ / period_ns;
+
+	/* Check to see if we are changing the clock rate of the PWM */
+	tin_rate = pwm_calc_tin(pwm_id, period);
+	timer_rate_hz = tin_rate;
+
+	tin_ns = NS_IN_HZ / tin_rate;
+	tcnt = period_ns / tin_ns;
+
+	/* Note, counters count down */
+	tcmp = duty_ns / tin_ns;
+	tcmp = tcnt - tcmp;
+
+	/*
+	 * the pwm hw only checks the compare register after a decrement,
+	 * so the pin never toggles if tcmp = tcnt
+	 */
+	if (tcmp == tcnt)
+		tcmp--;
+
+	if (tcmp < 0)
+		tcmp = 0;
+
+	/* Update the PWM register block. */
+	offset = pwm_id * 3;
+	if (pwm_id < 4) {
+		writel(tcnt, &pwm->tcntb0 + offset);
+		writel(tcmp, &pwm->tcmpb0 + offset);
+	}
+
+	tcon = readl(&pwm->tcon);
+	tcon |= TCON_UPDATE(pwm_id);
+	if (pwm_id < 4)
+		tcon |= TCON_AUTO_RELOAD(pwm_id);
+	else
+		tcon |= TCON4_AUTO_RELOAD;
+	writel(tcon, &pwm->tcon);
+
+	tcon &= ~TCON_UPDATE(pwm_id);
+	writel(tcon, &pwm->tcon);
+
+	return 0;
+}
+
+int pwm_init(int pwm_id, int div, int invert)
+{
+	u32 val;
+	const struct s5p_timer *pwm =
+			(struct s5p_timer *)samsung_get_base_timer();
+	unsigned long timer_rate_hz;
+	unsigned int offset, prescaler;
+
+	/*
+	 * Timer Freq(HZ) =
+	 *	PWM_CLK / { (prescaler_value + 1) * (divider_value) }
+	 */
+
+	val = readl(&pwm->tcfg0);
+	if (pwm_id < 2) {
+		prescaler = PRESCALER_0;
+		val &= ~0xff;
+		val |= (prescaler & 0xff);
+	} else {
+		prescaler = PRESCALER_1;
+		val &= ~(0xff << 8);
+		val |= (prescaler & 0xff) << 8;
+	}
+	writel(val, &pwm->tcfg0);
+	val = readl(&pwm->tcfg1);
+	val &= ~(0xf << MUX_DIV_SHIFT(pwm_id));
+	val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id);
+	writel(val, &pwm->tcfg1);
+
+	timer_rate_hz = get_pwm_clk() / ((prescaler + 1) *
+			(div + 1));
+
+	timer_rate_hz = timer_rate_hz / 100;
+
+	/* set count value */
+	offset = pwm_id * 3;
+	writel(timer_rate_hz, &pwm->tcntb0 + offset);
+
+	val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id));
+	if (invert && (pwm_id < 4))
+		val |= TCON_INVERTER(pwm_id);
+	writel(val, &pwm->tcon);
+
+	pwm_enable(pwm_id);
+
+	return 0;
+}

arch/arm/cpu/armv7/s5p-common/timer.c

@@ -27,21 +27,9 @@
 #include <asm/io.h>
 #include <asm/arch/pwm.h>
 #include <asm/arch/clk.h>
+#include <pwm.h>
 
-#define PRESCALER_1		(16 - 1)	/* prescaler of timer 2, 3, 4 */
-#define MUX_DIV_2		1		/* 1/2 period */
-#define MUX_DIV_4		2		/* 1/4 period */
-#define MUX_DIV_8		3		/* 1/8 period */
-#define MUX_DIV_16		4		/* 1/16 period */
-#define MUX4_DIV_SHIFT		16
-
-#define TCON_TIMER4_SHIFT	20
-
-static unsigned long count_value;
-
-/* Internal tick units */
-static unsigned long long timestamp;	/* Monotonic incrementing timer */
-static unsigned long lastdec;		/* Last decremneter snapshot */
+DECLARE_GLOBAL_DATA_PTR;
 
 /* macro to read the 16 bit timer */
 static inline struct s5p_timer *s5p_get_base_timer(void)
@@ -51,41 +39,10 @@ static inline struct s5p_timer *s5p_get_base_timer(void)
 
 int timer_init(void)
 {
-	struct s5p_timer *const timer = s5p_get_base_timer();
-	u32 val;
-
-	/*
-	 * @ PWM Timer 4
-	 * Timer Freq(HZ) =
-	 *	PWM_CLK / { (prescaler_value + 1) * (divider_value) }
-	 */
-
-	/* set prescaler : 16 */
-	/* set divider : 2 */
-	writel((PRESCALER_1 & 0xff) << 8, &timer->tcfg0);
-	writel((MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT, &timer->tcfg1);
-
-	/* count_value = 2085937.5(HZ) (per 1 sec)*/
-	count_value = get_pwm_clk() / ((PRESCALER_1 + 1) *
-			(MUX_DIV_2 + 1));
-
-	/* count_value / 100 = 20859.375(HZ) (per 10 msec) */
-	count_value = count_value / 100;
-
-	/* set count value */
-	writel(count_value, &timer->tcntb4);
-	lastdec = count_value;
-
-	val = (readl(&timer->tcon) & ~(0x07 << TCON_TIMER4_SHIFT)) |
-		TCON4_AUTO_RELOAD;
-
-	/* auto reload & manual update */
-	writel(val | TCON4_UPDATE, &timer->tcon);
-
-	/* start PWM timer 4 */
-	writel(val | TCON4_START, &timer->tcon);
-
-	timestamp = 0;
+	/* PWM Timer 4 */
+	pwm_init(4, MUX_DIV_2, 0);
+	pwm_config(4, 0, 0);
+	pwm_enable(4);
 
 	return 0;
 }
@@ -105,14 +62,14 @@ unsigned long get_timer(unsigned long base)
 
 void set_timer(unsigned long t)
 {
-	timestamp = t;
+	gd->tbl = t;
 }
 
 /* delay x useconds */
 void __udelay(unsigned long usec)
 {
 	struct s5p_timer *const timer = s5p_get_base_timer();
-	unsigned long tmo, tmp;
+	unsigned long tmo, tmp, count_value;
 
 	count_value = readl(&timer->tcntb4);
 
@@ -137,7 +94,7 @@ void __udelay(unsigned long usec)
 	tmp = get_timer(0);
 
 	/* if setting this fordward will roll time stamp */
-	/* reset "advancing" timestamp to 0, set lastdec value */
+	/* reset "advancing" timestamp to 0, set lastinc value */
 	/* else, set advancing stamp wake up time */
 	if ((tmo + tmp + 1) < tmp)
 		reset_timer_masked();
@@ -154,23 +111,24 @@ void reset_timer_masked(void)
 	struct s5p_timer *const timer = s5p_get_base_timer();
 
 	/* reset time */
-	lastdec = readl(&timer->tcnto4);
-	timestamp = 0;
+	gd->lastinc = readl(&timer->tcnto4);
+	gd->tbl = 0;
 }
 
 unsigned long get_timer_masked(void)
 {
 	struct s5p_timer *const timer = s5p_get_base_timer();
 	unsigned long now = readl(&timer->tcnto4);
+	unsigned long count_value = readl(&timer->tcntb4);
 
-	if (lastdec >= now)
-		timestamp += lastdec - now;
+	if (gd->lastinc >= now)
+		gd->tbl += gd->lastinc - now;
 	else
-		timestamp += lastdec + count_value - now;
+		gd->tbl += gd->lastinc + count_value - now;
 
-	lastdec = now;
+	gd->lastinc = now;
 
-	return timestamp;
+	return gd->tbl;
 }
 
 /*

arch/arm/cpu/armv7/start.S

@@ -79,6 +79,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/armv7/tegra2/Makefile

@@ -1,14 +1,11 @@
 #
-# Copyright (C) 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+# (C) Copyright 2010,2011 Nvidia Corporation.
 #
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# board/ms7720se/config.mk
+# See file CREDITS for list of people who contributed to this
+# project.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
@@ -24,11 +21,28 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
-
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
 #
 
-CONFIG_SYS_TEXT_BASE = 0x8FFC0000
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	:= lowlevel_init.o
+COBJS	:= board.o sys_info.o timer.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/armv7/tegra2/board.c

@@ -0,0 +1,88 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/pmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
+ * so we are using this value to identify memory size.
+ */
+
+unsigned int query_sdram_size(void)
+{
+	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	reg = readl(&pmc->pmc_scratch20);
+	debug("pmc->pmc_scratch20 (ODMData) = 0x%08lX\n", reg);
+
+	/* bits 31:28 in OdmData are used for RAM size  */
+	switch ((reg) >> 28) {
+	case 1:
+		return 0x10000000;	/* 256 MB */
+	case 2:
+		return 0x20000000;	/* 512 MB */
+	case 3:
+	default:
+		return 0x40000000;	/* 1GB */
+	}
+}
+
+void s_init(void)
+{
+#ifndef CONFIG_ICACHE_OFF
+	icache_enable();
+#endif
+	invalidate_dcache();
+}
+
+int dram_init(void)
+{
+	unsigned long rs;
+
+	/* We do not initialise DRAM here. We just query the size */
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = gd->ram_size = query_sdram_size();
+
+	/* Now check it dynamically */
+	rs = get_ram_size(CONFIG_SYS_SDRAM_BASE, gd->ram_size);
+	if (rs) {
+		printf("dynamic ram_size = %lu\n", rs);
+		gd->bd->bi_dram[0].size = gd->ram_size = rs;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("Board: %s\n", sysinfo.board_string);
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_BOARDINFO */

arch/arm/cpu/armv7/tegra2/config.mk

@@ -1,6 +1,12 @@
 #
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
@@ -17,7 +23,6 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-CONFIG_SYS_TEXT_BASE = 0x8FFC0000
+
+# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI.
+PLATFORM_CPPFLAGS += -march=armv4

arch/arm/cpu/armv7/tegra2/lowlevel_init.S

@@ -0,0 +1,65 @@
+/*
+ * SoC-specific setup info
+ *
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	@ sdram load addr from config file
+
+.global invalidate_dcache
+invalidate_dcache:
+	mov pc, lr
+
+	.align	5
+.global reset_cpu
+reset_cpu:
+	ldr	r1, rstctl			@ get addr for global reset
+						@ reg
+	ldr	r3, [r1]
+	orr	r3, r3, #0x10
+	str	r3, [r1]			@ force reset
+	mov	r0, r0
+_loop_forever:
+	b	_loop_forever
+rstctl:
+	.word	PRM_RSTCTRL
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp, SRAM_STACK
+	str	ip, [sp]
+	mov	ip, lr
+	bl	s_init				@ go setup pll, mux & memory
+	ldr	ip, [sp]
+	mov	lr, ip
+
+	mov	pc, lr				@ back to arch calling code
+
+	@ the literal pools origin
+	.ltorg
+
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK

arch/arm/cpu/armv7/tegra2/sys_info.c

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,21 +23,13 @@
 
 #include <common.h>
 
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
+#ifdef CONFIG_DISPLAY_CPUINFO
+/* Print CPU information */
+int print_cpuinfo(void)
 {
-	printf ("Skipping flash_init\n");
-	return (0);
-}
+	puts("TEGRA2\n");
 
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	printf ("write_buff not implemented\n");
-	return (-1);
+	/* TBD: Add printf of major/minor rev info, stepping, etc. */
+	return 0;
 }
+#endif	/* CONFIG_DISPLAY_CPUINFO */

arch/arm/cpu/armv7/tegra2/timer.c

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Moahmmed Khasim <khasim@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
+
+/* counter runs at 1MHz */
+#define TIMER_CLK	(1000000)
+#define TIMER_LOAD_VAL	0xffffffff
+
+/* timer without interrupts */
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	gd->tbl = t;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+	long tmo = usec * (TIMER_CLK / 1000) / 1000;
+	unsigned long now, last = readl(&timer_base->cntr_1us);
+
+	while (tmo > 0) {
+		now = readl(&timer_base->cntr_1us);
+		if (last > now) /* count up timer overflow */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		else
+			tmo -= now - last;
+		last = now;
+	}
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time, capture current incrementer value time */
+	gd->lastinc = readl(&timer_base->cntr_1us) / (TIMER_CLK/CONFIG_SYS_HZ);
+	gd->tbl = 0;		/* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now;
+
+	/* current tick value */
+	now = readl(&timer_base->cntr_1us) / (TIMER_CLK / CONFIG_SYS_HZ);
+
+	if (now >= gd->lastinc)	/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += (now - gd->lastinc);
+	else	/* we have rollover of incrementer */
+		gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
+				- gd->lastinc) + now;
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/armv7/u-boot.lds

@@ -66,11 +66,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/ixp/start.S

@@ -110,6 +110,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/ixp/u-boot.lds

@@ -63,11 +63,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/lh7a40x/start.S

@@ -87,6 +87,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/lh7a40x/u-boot.lds

@@ -63,11 +63,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/pxa/start.S

@@ -104,6 +104,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/pxa/u-boot.lds

@@ -63,11 +63,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/s3c44b0/start.S

@@ -78,6 +78,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/s3c44b0/u-boot.lds

@@ -63,11 +63,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/cpu/sa1100/start.S

@@ -88,6 +88,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
 	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ

arch/arm/cpu/sa1100/u-boot.lds

@@ -66,11 +66,13 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
 		 . = ALIGN(4);
-		_end = .;
+		__bss_end__ = .;
 	}
 
 	/DISCARD/ : { *(.dynstr*) }

arch/arm/include/asm/arch-armada100/config.h

@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for Armada100 platform
+ */
+
+#ifndef _ARMD1_CONFIG_H
+#define _ARMD1_CONFIG_H
+
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+
+#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
+#define MV_MFPR_BASE		ARMD1_MFPR_BASE
+#define MV_UART_CONSOLE_BASE	ARMD1_UART1_BASE
+#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
+						represents UART Unit Enable */
+
+#endif /* _ARMD1_CONFIG_H */

arch/arm/include/asm/arch-kirkwood/config.h

@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for Kirkwood platform
+ */
+
+#ifndef _KW_CONFIG_H
+#define _KW_CONFIG_H
+
+#if defined (CONFIG_KW88F6281)
+#include <asm/arch/kw88f6281.h>
+#elif defined (CONFIG_KW88F6192)
+#include <asm/arch/kw88f6192.h>
+#else
+#error "SOC Name not defined"
+#endif /* CONFIG_KW88F6281 */
+
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+
+#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Kirkwood has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#define CONFIG_I2C_MVTWSI_BASE	KW_TWSI_BASE
+#define MV_UART_CONSOLE_BASE	KW_UART0_BASE
+#define MV_SATA_BASE		KW_SATA_BASE
+#define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
+#define MV_SATA_PORT1_OFFSET	KW_SATA_PORT1_OFFSET
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL		1
+#endif
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI			1
+#define CONFIG_KIRKWOOD_SPI		1
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		50000000	/*50Mhz */
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_NET_MULTI	/* specify more that one ports available */
+#define CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_KIRKWOOD
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * IDE Support on SATA ports
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#endif /* _KW_CONFIG_H */

arch/arm/include/asm/arch-pantheon/config.h

@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _PANTHEON_CONFIG_H
+#define _PANTHEON_CONFIG_H
+
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+
+#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
+#define MV_MFPR_BASE		PANTHEON_MFPR_BASE
+#define MV_UART_CONSOLE_BASE	PANTHEON_UART1_BASE
+#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
+						represents UART Unit Enable */
+
+#endif /* _PANTHEON_CONFIG_H */

arch/arm/include/asm/arch-pantheon/cpu.h

@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _PANTHEON_CPU_H
+#define _PANTHEON_CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Register Datasheet 9.1
+ */
+struct panthmpmu_registers {
+	u8 pad0[0x0024];
+	u32 ccgr;	/*0x0024*/
+	u8 pad1[0x0200 - 0x024 - 4];
+	u32 wdtpcr;	/*0x0200*/
+	u8 pad2[0x1020 - 0x200 - 4];
+	u32 aprr;	/*0x1020*/
+	u32 acgr;	/*0x1024*/
+};
+
+/*
+ * APB Clock Reset/Control Registers
+ * Refer Register Datasheet 6.14
+ */
+struct panthapb_registers {
+	u32 uart0;	/*0x000*/
+	u32 uart1;	/*0x004*/
+	u32 gpio;	/*0x008*/
+	u8 pad0[0x034 - 0x08 - 4];
+	u32 timers;	/*0x034*/
+};
+
+/*
+ * CPU Interface Registers
+ * Refer Register Datasheet 4.3
+ */
+struct panthcpu_registers {
+	u32 chip_id;		/* Chip Id Reg */
+	u32 pad;
+	u32 cpu_conf;		/* CPU Conf Reg */
+	u32 pad1;
+	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
+	u32 pad2;
+	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
+	u32 mcb_conf;		/* MCB Conf Reg */
+	u32 sys_boot_ctl;	/* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 panth_sdram_base(int);
+u32 panth_sdram_size(int);
+
+#endif /* _PANTHEON_CPU_H */

arch/arm/include/asm/arch-pantheon/mfp.h

@@ -0,0 +1,41 @@
+/*
+ * Based on arch/arm/include/asm/arch-armada100/mfp.h
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __PANTHEON_MFP_H
+#define __PANTHEON_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
+ *
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART2 */
+#define MFP47_UART2_RXD		MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP48_UART2_TXD		MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM
+
+/* More macros can be defined here... */
+
+#define MFP_PIN_MAX	117
+#endif

arch/arm/include/asm/arch-pantheon/pantheon.h

@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _PANTHEON_H
+#define _PANTHEON_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif	/* __ASSEMBLY__ */
+
+#include <asm/arch/cpu.h>
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
+#define APBC_RST        (1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+/* Register Base Addresses */
+#define PANTHEON_DRAM_BASE	0xB0000000
+#define PANTHEON_TIMER_BASE	0xD4014000
+#define PANTHEON_WD_TIMER_BASE	0xD4080000
+#define PANTHEON_APBC_BASE	0xD4015000
+#define PANTHEON_UART1_BASE	0xD4017000
+#define PANTHEON_UART2_BASE	0xD4018000
+#define PANTHEON_GPIO_BASE	0xD4019000
+#define PANTHEON_MFPR_BASE	0xD401E000
+#define PANTHEON_MPMU_BASE	0xD4050000
+#define PANTHEON_CPU_BASE	0xD4282C00
+
+#endif /* _PANTHEON_H */

arch/arm/include/asm/arch-s5pc1xx/mmc.h

@@ -53,10 +53,11 @@ struct s5p_mmc {
 	unsigned char	res3[0x34];
 	unsigned int	control2;
 	unsigned int	control3;
+	unsigned char	res4[4];
 	unsigned int	control4;
-	unsigned char	res4[0x6e];
+	unsigned char	res5[0x6e];
 	unsigned short	hcver;
-	unsigned char	res5[0xFFF02];
+	unsigned char	res6[0xFFF00];
 };
 
 struct mmc_host {

arch/arm/include/asm/arch-s5pc1xx/pwm.h

@@ -22,12 +22,25 @@
 #ifndef __ASM_ARM_ARCH_PWM_H_
 #define __ASM_ARM_ARCH_PWM_H_
 
-/* Interval mode(Auto Reload) of PWM Timer 4 */
+#define PRESCALER_0		(8 - 1)		/* prescaler of timer 0, 1 */
+#define PRESCALER_1		(16 - 1)	/* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1		0		/* 1/1 period */
+#define MUX_DIV_2		1		/* 1/2 period */
+#define MUX_DIV_4		2		/* 1/4 period */
+#define MUX_DIV_8		3		/* 1/8 period */
+#define MUX_DIV_16		4		/* 1/16 period */
+
+#define MUX_DIV_SHIFT(x)	(x * 4)
+
+#define TCON_OFFSET(x)		((x + 1) * (!!x) << 2)
+
+#define TCON_START(x)		(1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x)		(1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x)	(1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x)	(1 << (TCON_OFFSET(x) + 3))
 #define TCON4_AUTO_RELOAD	(1 << 22)
-/* Update TCNTB4 */
-#define TCON4_UPDATE		(1 << 21)
-/* start bit of PWM Timer 4 */
-#define TCON4_START		(1 << 20)
 
 #ifndef __ASSEMBLY__
 struct s5p_timer {

arch/arm/include/asm/arch-s5pc2xx/mmc.h

@@ -53,10 +53,11 @@ struct s5p_mmc {
 	unsigned char	res3[0x34];
 	unsigned int	control2;
 	unsigned int	control3;
+	unsigned char	res4[4];
 	unsigned int	control4;
-	unsigned char	res4[0x6e];
+	unsigned char	res5[0x6e];
 	unsigned short	hcver;
-	unsigned char	res5[0xFF02];
+	unsigned char	res6[0xFF00];
 };
 
 struct mmc_host {

arch/arm/include/asm/arch-s5pc2xx/pwm.h

@@ -22,12 +22,25 @@
 #ifndef __ASM_ARM_ARCH_PWM_H_
 #define __ASM_ARM_ARCH_PWM_H_
 
-/* Interval mode(Auto Reload) of PWM Timer 4 */
+#define PRESCALER_0		(8 - 1)		/* prescaler of timer 0, 1 */
+#define PRESCALER_1		(16 - 1)	/* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1		0		/* 1/1 period */
+#define MUX_DIV_2		1		/* 1/2 period */
+#define MUX_DIV_4		2		/* 1/4 period */
+#define MUX_DIV_8		3		/* 1/8 period */
+#define MUX_DIV_16		4		/* 1/16 period */
+
+#define MUX_DIV_SHIFT(x)	(x * 4)
+
+#define TCON_OFFSET(x)		((x + 1) * (!!x) << 2)
+
+#define TCON_START(x)		(1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x)		(1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x)	(1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x)	(1 << (TCON_OFFSET(x) + 3))
 #define TCON4_AUTO_RELOAD	(1 << 22)
-/* Update TCNTB4 */
-#define TCON4_UPDATE		(1 << 21)
-/* start bit of PWM Timer 4 */
-#define TCON4_START		(1 << 20)
 
 #ifndef __ASSEMBLY__
 struct s5p_timer {

arch/arm/include/asm/arch-tegra2/clk_rst.h

@@ -0,0 +1,165 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CLK_RST_H_
+#define _CLK_RST_H_
+
+/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
+struct clk_rst_ctlr {
+	uint crc_rst_src;		/* _RST_SOURCE_0,	0x00 */
+	uint crc_rst_dev_l;		/* _RST_DEVICES_L_0,	0x04 */
+	uint crc_rst_dev_h;		/* _RST_DEVICES_H_0,	0x08 */
+	uint crc_rst_dev_u;		/* _RST_DEVICES_U_0,	0x0C */
+	uint crc_clk_out_enb_l;		/* _CLK_OUT_ENB_L_0,	0x10 */
+	uint crc_clk_out_enb_h;		/* _CLK_OUT_ENB_H_0,	0x14 */
+	uint crc_clk_out_enb_u;		/* _CLK_OUT_ENB_U_0,	0x18 */
+	uint crc_reserved0;		/* reserved_0,		0x1C */
+	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0,0x20 */
+	uint crc_super_cclk_div;	/* _SUPER_CCLK_DIVIDER_0,0x24 */
+	uint crc_sclk_brst_pol;		/* _SCLK_BURST_POLICY_0, 0x28 */
+	uint crc_super_sclk_div;	/* _SUPER_SCLK_DIVIDER_0,0x2C */
+	uint crc_clk_sys_rate;		/* _CLK_SYSTEM_RATE_0,	0x30 */
+	uint crc_prog_dly_clk;		/* _PROG_DLY_CLK_0,	0x34 */
+	uint crc_aud_sync_clk_rate;	/* _AUDIO_SYNC_CLK_RATE_0,0x38 */
+	uint crc_reserved1;		/* reserved_1,		0x3C */
+	uint crc_cop_clk_skip_plcy;	/* _COP_CLK_SKIP_POLICY_0,0x40 */
+	uint crc_clk_mask_arm;		/* _CLK_MASK_ARM_0,	0x44 */
+	uint crc_misc_clk_enb;		/* _MISC_CLK_ENB_0,	0x48 */
+	uint crc_clk_cpu_cmplx;		/* _CLK_CPU_CMPLX_0,	0x4C */
+	uint crc_osc_ctrl;		/* _OSC_CTRL_0,		0x50 */
+	uint crc_pll_lfsr;		/* _PLL_LFSR_0,		0x54 */
+	uint crc_osc_freq_det;		/* _OSC_FREQ_DET_0,	0x58 */
+	uint crc_osc_freq_det_stat;	/* _OSC_FREQ_DET_STATUS_0,0x5C */
+	uint crc_reserved2[8];		/* reserved_2[8],	0x60-7C */
+
+	uint crc_pllc_base;		/* _PLLC_BASE_0,	0x80 */
+	uint crc_pllc_out;		/* _PLLC_OUT_0,		0x84 */
+	uint crc_reserved3;		/* reserved_3,		0x88 */
+	uint crc_pllc_misc;		/* _PLLC_MISC_0,	0x8C */
+
+	uint crc_pllm_base;		/* _PLLM_BASE_0,	0x90 */
+	uint crc_pllm_out;		/* _PLLM_OUT_0,		0x94 */
+	uint crc_reserved4;		/* reserved_4,		0x98 */
+	uint crc_pllm_misc;		/* _PLLM_MISC_0,	0x9C */
+
+	uint crc_pllp_base;		/* _PLLP_BASE_0,	0xA0 */
+	uint crc_pllp_outa;		/* _PLLP_OUTA_0,	0xA4 */
+	uint crc_pllp_outb;		/* _PLLP_OUTB_0,	0xA8 */
+	uint crc_pllp_misc;		/* _PLLP_MISC_0,	0xAC */
+
+	uint crc_plla_base;		/* _PLLA_BASE_0,	0xB0 */
+	uint crc_plla_out;		/* _PLLA_OUT_0,		0xB4 */
+	uint crc_reserved5;		/* reserved_5,		0xB8 */
+	uint crc_plla_misc;		/* _PLLA_MISC_0,	0xBC */
+
+	uint crc_pllu_base;		/* _PLLU_BASE_0,	0xC0 */
+	uint crc_reserved6;		/* _reserved_6,		0xC4 */
+	uint crc_reserved7;		/* _reserved_7,		0xC8 */
+	uint crc_pllu_misc;		/* _PLLU_MISC_0,	0xCC */
+
+	uint crc_plld_base;		/* _PLLD_BASE_0,	0xD0 */
+	uint crc_reserved8;		/* _reserved_8,		0xD4 */
+	uint crc_reserved9;		/* _reserved_9,		0xD8 */
+	uint crc_plld_misc;		/* _PLLD_MISC_0,	0xDC */
+
+	uint crc_pllx_base;		/* _PLLX_BASE_0,	0xE0 */
+	uint crc_pllx_misc;		/* _PLLX_MISC_0,	0xE4 */
+
+	uint crc_plle_base;		/* _PLLE_BASE_0,	0xE8 */
+	uint crc_plle_misc;		/* _PLLE_MISC_0,	0xEC */
+
+	uint crc_plls_base;		/* _PLLS_BASE_0,	0xF0 */
+	uint crc_plls_misc;		/* _PLLS_MISC_0,	0xF4 */
+	uint crc_reserved10;		/* _reserved_10,	0xF8 */
+	uint crc_reserved11;		/* _reserved_11,	0xFC */
+
+	uint crc_clk_src_i2s1;		/*_I2S1_0,		0x100 */
+	uint crc_clk_src_i2s2;		/*_I2S2_0,		0x104 */
+	uint crc_clk_src_spdif_out;	/*_SPDIF_OUT_0,		0x108 */
+	uint crc_clk_src_spdif_in;	/*_SPDIF_IN_0,		0x10C */
+	uint crc_clk_src_pwm;		/*_PWM_0,		0x110 */
+	uint crc_clk_src_spi1;		/*_SPI1_0,		0x114 */
+	uint crc_clk_src_sbc2;		/*_SBC2_0,		0x118 */
+	uint crc_clk_src_sbc3;		/*_SBC3_0,		0x11C */
+	uint crc_clk_src_xio;		/*_XIO_0,		0x120 */
+	uint crc_clk_src_i2c1;		/*_I2C1_0,		0x124 */
+	uint crc_clk_src_dvc_i2c;	/*_DVC_I2C_0,		0x128 */
+	uint crc_clk_src_twc;		/*_TWC_0,		0x12C */
+	uint crc_reserved12;		/*			0x130 */
+	uint crc_clk_src_sbc1;		/*_SBC1_0,		0x134 */
+	uint crc_clk_src_disp1;		/*_DISP1_0,		0x138 */
+	uint crc_clk_src_disp2;		/*_DISP2_0,		0x13C */
+	uint crc_clk_src_cve;		/*_CVE_0,		0x140 */
+	uint crc_clk_src_ide;		/*_IDE_0,		0x144 */
+	uint crc_clk_src_vi;		/*_VI_0,		0x148 */
+	uint crc_reserved13;		/*			0x14C */
+	uint crc_clk_src_sdmmc1;	/*_SDMMC1_0,		0x150 */
+	uint crc_clk_src_sdmmc2;	/*_SDMMC2_0,		0x154 */
+	uint crc_clk_src_g3d;		/*_G3D_0,		0x158 */
+	uint crc_clk_src_g2d;		/*_G2D_0,		0x15C */
+	uint crc_clk_src_ndflash;	/*_NDFLASH_0,		0x160 */
+	uint crc_clk_src_sdmmc4;	/*_SDMMC4_0,		0x164 */
+	uint crc_clk_src_vfir;		/*_VFIR_0,		0x168 */
+	uint crc_clk_src_epp;		/*_EPP_0,		0x16C */
+	uint crc_clk_src_mp3;		/*_MPE_0,		0x170 */
+	uint crc_clk_src_mipi;		/*_MIPI_0,		0x174 */
+	uint crc_clk_src_uarta;		/*_UARTA_0,		0x178 */
+	uint crc_clk_src_uartb;		/*_UARTB_0,		0x17C */
+	uint crc_clk_src_host1x;	/*_HOST1X_0,		0x180 */
+	uint crc_reserved14;		/*			0x184 */
+	uint crc_clk_src_tvo;		/*_TVO_0,		0x188 */
+	uint crc_clk_src_hdmi;		/*_HDMI_0,		0x18C */
+	uint crc_reserved15;		/*			0x190 */
+	uint crc_clk_src_tvdac;		/*_TVDAC_0,		0x194 */
+	uint crc_clk_src_i2c2;		/*_I2C2_0,		0x198 */
+	uint crc_clk_src_emc;		/*_EMC_0,		0x19C */
+	uint crc_clk_src_uartc;		/*_UARTC_0,		0x1A0 */
+	uint crc_reserved16;		/*			0x1A4 */
+	uint crc_clk_src_vi_sensor;	/*_VI_SENSOR_0,		0x1A8 */
+	uint crc_reserved17;		/*			0x1AC */
+	uint crc_reserved18;		/*			0x1B0 */
+	uint crc_clk_src_sbc4;		/*_SBC4_0,		0x1B4 */
+	uint crc_clk_src_i2c3;		/*_I2C3_0,		0x1B8 */
+	uint crc_clk_src_sdmmc3;	/*_SDMMC3_0,		0x1BC */
+	uint crc_clk_src_uartd;		/*_UARTD_0,		0x1C0 */
+	uint crc_clk_src_uarte;		/*_UARTE_0,		0x1C4 */
+	uint crc_clk_src_vde;		/*_VDE_0,		0x1C8 */
+	uint crc_clk_src_owr;		/*_OWR_0,		0x1CC */
+	uint crc_clk_src_nor;		/*_NOR_0,		0x1D0 */
+	uint crc_clk_src_csite;		/*_CSITE_0,		0x1D4 */
+	uint crc_reserved19[9];		/*			0x1D8-1F8 */
+	uint crc_clk_src_osc;		/*_OSC_0,		0x1FC */
+};
+
+#define PLL_BYPASS		(1 << 31)
+#define PLL_ENABLE		(1 << 30)
+#define PLL_BASE_OVRRIDE	(1 << 28)
+#define PLL_DIVP		(1 << 20)	/* post divider, b22:20 */
+#define PLL_DIVM		0x0C		/* input divider, b4:0 */
+
+#define SWR_UARTD_RST		(1 << 2)
+#define CLK_ENB_UARTD		(1 << 2)
+#define SWR_UARTA_RST		(1 << 6)
+#define CLK_ENB_UARTA		(1 << 6)
+
+#endif	/* CLK_RST_H */

arch/arm/include/asm/arch-tegra2/pinmux.h

@@ -0,0 +1,55 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
+struct pmux_tri_ctlr {
+	uint pmt_reserved0;		/* ABP_MISC_PP_ reserved offset 00 */
+	uint pmt_reserved1;		/* ABP_MISC_PP_ reserved offset 04 */
+	uint pmt_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 08 */
+	uint pmt_reserved2;		/* ABP_MISC_PP_ reserved offset 0C */
+	uint pmt_reserved3;		/* ABP_MISC_PP_ reserved offset 10 */
+	uint pmt_tri_a;			/* _TRI_STATE_REG_A_0, offset 14 */
+	uint pmt_tri_b;			/* _TRI_STATE_REG_B_0, offset 18 */
+	uint pmt_tri_c;			/* _TRI_STATE_REG_C_0, offset 1C */
+	uint pmt_tri_d;			/* _TRI_STATE_REG_D_0, offset 20 */
+	uint pmt_cfg_ctl;		/* _CONFIG_CTL_0, offset 24 */
+
+	uint pmt_reserved[22];		/* ABP_MISC_PP_ reserved offs 28-7C */
+
+	uint pmt_ctl_a;			/* _PIN_MUX_CTL_A_0, offset 80 */
+	uint pmt_ctl_b;			/* _PIN_MUX_CTL_B_0, offset 84 */
+	uint pmt_ctl_c;			/* _PIN_MUX_CTL_C_0, offset 88 */
+	uint pmt_ctl_d;			/* _PIN_MUX_CTL_D_0, offset 8C */
+	uint pmt_ctl_e;			/* _PIN_MUX_CTL_E_0, offset 90 */
+	uint pmt_ctl_f;			/* _PIN_MUX_CTL_F_0, offset 94 */
+	uint pmt_ctl_g;			/* _PIN_MUX_CTL_G_0, offset 98 */
+};
+
+#define Z_GMC			(1 << 29)
+#define Z_IRRX			(1 << 20)
+#define Z_IRTX			(1 << 19)
+
+#endif	/* PINMUX_H */

arch/arm/include/asm/arch-tegra2/pmc.h

@@ -0,0 +1,124 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PMC_H_
+#define _PMC_H_
+
+/* Power Management Controller (APBDEV_PMC_) registers */
+struct pmc_ctlr {
+	uint pmc_cntrl;			/* _CNTRL_0, offset 00 */
+	uint pmc_sec_disable;		/* _SEC_DISABLE_0, offset 04 */
+	uint pmc_pmc_swrst;		/* _PMC_SWRST_0, offset 08 */
+	uint pmc_wake_mask;		/* _WAKE_MASK_0, offset 0C */
+	uint pmc_wake_lvl;		/* _WAKE_LVL_0, offset 10 */
+	uint pmc_wake_status;		/* _WAKE_STATUS_0, offset 14 */
+	uint pmc_sw_wake_status;	/* _SW_WAKE_STATUS_0, offset 18 */
+	uint pmc_dpd_pads_oride;	/* _DPD_PADS_ORIDE_0, offset 1C */
+	uint pmc_dpd_sample;		/* _DPD_PADS_SAMPLE_0, offset 20 */
+	uint pmc_dpd_enable;		/* _DPD_PADS_ENABLE_0, offset 24 */
+	uint pmc_pwrgate_timer_off;	/* _PWRGATE_TIMER_OFF_0, offset 28 */
+	uint pmc_pwrgate_timer_on;	/* _PWRGATE_TIMER_ON_0, offset 2C */
+	uint pmc_pwrgate_toggle;	/* _PWRGATE_TOGGLE_0, offset 30 */
+	uint pmc_remove_clamping;	/* _REMOVE_CLAMPING_CMD_0, offset 34 */
+	uint pmc_pwrgate_status;	/* _PWRGATE_STATUS_0, offset 38 */
+	uint pmc_pwrgood_timer;		/* _PWRGOOD_TIMER_0, offset 3C */
+	uint pmc_blink_timer;		/* _BLINK_TIMER_0, offset 40 */
+	uint pmc_no_iopower;		/* _NO_IOPOWER_0, offset 44 */
+	uint pmc_pwr_det;		/* _PWR_DET_0, offset 48 */
+	uint pmc_pwr_det_latch;		/* _PWR_DET_LATCH_0, offset 4C */
+
+	uint pmc_scratch0;		/* _SCRATCH0_0, offset 50 */
+	uint pmc_scratch1;		/* _SCRATCH1_0, offset 54 */
+	uint pmc_scratch2;		/* _SCRATCH2_0, offset 58 */
+	uint pmc_scratch3;		/* _SCRATCH3_0, offset 5C */
+	uint pmc_scratch4;		/* _SCRATCH4_0, offset 60 */
+	uint pmc_scratch5;		/* _SCRATCH5_0, offset 64 */
+	uint pmc_scratch6;		/* _SCRATCH6_0, offset 68 */
+	uint pmc_scratch7;		/* _SCRATCH7_0, offset 6C */
+	uint pmc_scratch8;		/* _SCRATCH8_0, offset 70 */
+	uint pmc_scratch9;		/* _SCRATCH9_0, offset 74 */
+	uint pmc_scratch10;		/* _SCRATCH10_0, offset 78 */
+	uint pmc_scratch11;		/* _SCRATCH11_0, offset 7C */
+	uint pmc_scratch12;		/* _SCRATCH12_0, offset 80 */
+	uint pmc_scratch13;		/* _SCRATCH13_0, offset 84 */
+	uint pmc_scratch14;		/* _SCRATCH14_0, offset 88 */
+	uint pmc_scratch15;		/* _SCRATCH15_0, offset 8C */
+	uint pmc_scratch16;		/* _SCRATCH16_0, offset 90 */
+	uint pmc_scratch17;		/* _SCRATCH17_0, offset 94 */
+	uint pmc_scratch18;		/* _SCRATCH18_0, offset 98 */
+	uint pmc_scratch19;		/* _SCRATCH19_0, offset 9C */
+	uint pmc_scratch20;		/* _SCRATCH20_0, offset A0 */
+	uint pmc_scratch21;		/* _SCRATCH21_0, offset A4 */
+	uint pmc_scratch22;		/* _SCRATCH22_0, offset A8 */
+	uint pmc_scratch23;		/* _SCRATCH23_0, offset AC */
+
+	uint pmc_secure_scratch0;	/* _SECURE_SCRATCH0_0, offset B0 */
+	uint pmc_secure_scratch1;	/* _SECURE_SCRATCH1_0, offset B4 */
+	uint pmc_secure_scratch2;	/* _SECURE_SCRATCH2_0, offset B8 */
+	uint pmc_secure_scratch3;	/* _SECURE_SCRATCH3_0, offset BC */
+	uint pmc_secure_scratch4;	/* _SECURE_SCRATCH4_0, offset C0 */
+	uint pmc_secure_scratch5;	/* _SECURE_SCRATCH5_0, offset C4 */
+
+	uint pmc_cpupwrgood_timer;	/* _CPUPWRGOOD_TIMER_0, offset C8 */
+	uint pmc_cpupwroff_timer;	/* _CPUPWROFF_TIMER_0, offset CC */
+	uint pmc_pg_mask;		/* _PG_MASK_0, offset D0 */
+	uint pmc_pg_mask_1;		/* _PG_MASK_1_0, offset D4 */
+	uint pmc_auto_wake_lvl;		/* _AUTO_WAKE_LVL_0, offset D8 */
+	uint pmc_auto_wake_lvl_mask;	/* _AUTO_WAKE_LVL_MASK_0, offset DC */
+	uint pmc_wake_delay;		/* _WAKE_DELAY_0, offset E0 */
+	uint pmc_pwr_det_val;		/* _PWR_DET_VAL_0, offset E4 */
+	uint pmc_ddr_pwr;		/* _DDR_PWR_0, offset E8 */
+	uint pmc_usb_debounce_del;	/* _USB_DEBOUNCE_DEL_0, offset EC */
+	uint pmc_usb_ao;		/* _USB_AO_0, offset F0 */
+	uint pmc_crypto_op;		/* _CRYPTO_OP__0, offset F4 */
+	uint pmc_pllp_wb0_override;	/* _PLLP_WB0_OVERRIDE_0, offset F8 */
+
+	uint pmc_scratch24;		/* _SCRATCH24_0, offset FC */
+	uint pmc_scratch25;		/* _SCRATCH24_0, offset 100 */
+	uint pmc_scratch26;		/* _SCRATCH24_0, offset 104 */
+	uint pmc_scratch27;		/* _SCRATCH24_0, offset 108 */
+	uint pmc_scratch28;		/* _SCRATCH24_0, offset 10C */
+	uint pmc_scratch29;		/* _SCRATCH24_0, offset 110 */
+	uint pmc_scratch30;		/* _SCRATCH24_0, offset 114 */
+	uint pmc_scratch31;		/* _SCRATCH24_0, offset 118 */
+	uint pmc_scratch32;		/* _SCRATCH24_0, offset 11C */
+	uint pmc_scratch33;		/* _SCRATCH24_0, offset 120 */
+	uint pmc_scratch34;		/* _SCRATCH24_0, offset 124 */
+	uint pmc_scratch35;		/* _SCRATCH24_0, offset 128 */
+	uint pmc_scratch36;		/* _SCRATCH24_0, offset 12C */
+	uint pmc_scratch37;		/* _SCRATCH24_0, offset 130 */
+	uint pmc_scratch38;		/* _SCRATCH24_0, offset 134 */
+	uint pmc_scratch39;		/* _SCRATCH24_0, offset 138 */
+	uint pmc_scratch40;		/* _SCRATCH24_0, offset 13C */
+	uint pmc_scratch41;		/* _SCRATCH24_0, offset 140 */
+	uint pmc_scratch42;		/* _SCRATCH24_0, offset 144 */
+
+	uint pmc_bo_mirror0;		/* _BOUNDOUT_MIRROR0_0, offset 148 */
+	uint pmc_bo_mirror1;		/* _BOUNDOUT_MIRROR1_0, offset 14C */
+	uint pmc_bo_mirror2;		/* _BOUNDOUT_MIRROR2_0, offset 150 */
+	uint pmc_sys_33v_en;		/* _SYS_33V_EN_0, offset 154 */
+	uint pmc_bo_mirror_access;	/* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
+	uint pmc_gate;			/* _GATE_0, offset 15C */
+};
+
+#endif	/* PMC_H */

arch/arm/include/asm/arch-tegra2/sys_proto.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -21,17 +21,15 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _FPGA_H_
-#define _FPGA_H_
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
 
-static inline u16 fpga_get_reg(unsigned reg)
-{
-	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
-}
+struct tegra2_sysinfo {
+	char *board_string;
+};
 
-static inline void fpga_set_reg(unsigned reg, u16 val)
-{
-	return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
-}
+void invalidate_dcache(void);
+
+extern const struct tegra2_sysinfo sysinfo;
 
 #endif

arch/arm/include/asm/arch-tegra2/tegra2.h

@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_H_
+#define _TEGRA2_H_
+
+#define NV_PA_SDRAM_BASE	0x00000000
+#define NV_PA_TMRUS_BASE	0x60005010
+#define NV_PA_CLK_RST_BASE	0x60006000
+#define NV_PA_APB_MISC_BASE	0x70000000
+#define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
+#define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
+#define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
+#define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
+#define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
+#define NV_PA_PMC_BASE		0x7000E400
+
+#define TEGRA2_SDRC_CS0		NV_PA_SDRAM_BASE
+#define LOW_LEVEL_SRAM_STACK	0x4000FFFC
+
+#ifndef __ASSEMBLY__
+struct timerus {
+	unsigned int cntr_1us;
+};
+#else  /* __ASSEMBLY__ */
+#define PRM_RSTCTRL		NV_PA_PMC_BASE
+#endif
+
+#endif	/* TEGRA2_H */

arch/arm/include/asm/arch-tegra2/uart.h

@@ -0,0 +1,47 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _UART_H_
+#define _UART_H_
+
+/* UART registers */
+struct uart_ctlr {
+	uint uart_thr_dlab_0;		/* UART_THR_DLAB_0_0, offset 00 */
+	uint uart_ier_dlab_0;		/* UART_IER_DLAB_0_0, offset 04 */
+	uint uart_iir_fcr;		/* UART_IIR_FCR_0, offset 08 */
+	uint uart_lcr;			/* UART_LCR_0, offset 0C */
+	uint uart_mcr;			/* UART_MCR_0, offset 10 */
+	uint uart_lsr;			/* UART_LSR_0, offset 14 */
+	uint uart_msr;			/* UART_MSR_0, offset 18 */
+	uint uart_spr;			/* UART_SPR_0, offset 1C */
+	uint uart_irda_csr;		/* UART_IRDA_CSR_0, offset 20 */
+	uint uart_reserved[6];		/* Reserved, unused, offset 24-38*/
+	uint uart_asr;			/* UART_ASR_0, offset 3C */
+};
+
+#define NVRM_PLLP_FIXED_FREQ_KHZ	216000
+#define NV_DEFAULT_DEBUG_BAUD		115200
+
+#define UART_FCR_TRIGGER_3	0x30	/* Mask for trigger set at 3 */
+
+#endif	/* UART_H */

arch/arm/include/asm/io.h

@@ -133,9 +133,9 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
 #define __iormb()	dmb()
 #define __iowmb()	dmb()
 
-#define writeb(v,c)	({ __iowmb(); __arch_putb(v,c); v; })
-#define writew(v,c)	({ __iowmb(); __arch_putw(v,c); v; })
-#define writel(v,c)	({ __iowmb(); __arch_putl(v,c); v; })
+#define writeb(v,c)	({ u8  __v = v; __iowmb(); __arch_putb(__v,c); __v; })
+#define writew(v,c)	({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
+#define writel(v,c)	({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
 
 #define readb(c)	({ u8  __v = __arch_getb(c); __iormb(); __v; })
 #define readw(c)	({ u16 __v = __arch_getw(c); __iormb(); __v; })

arch/arm/include/asm/u-boot-arm.h

@@ -32,6 +32,7 @@
 /* for the following variables, see start.S */
 extern ulong _bss_start_ofs;	/* BSS start relative to _start */
 extern ulong _bss_end_ofs;		/* BSS end relative to _start */
+extern ulong _end_ofs;		/* end of image relative to _start */
 extern ulong IRQ_STACK_START;	/* top of IRQ stack */
 extern ulong FIQ_STACK_START;	/* top of FIQ stack */
 extern ulong _TEXT_BASE;	/* code start */

arch/arm/lib/board.c

@@ -459,7 +459,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
-	monitor_flash_len = _bss_start_ofs;
+	monitor_flash_len = _end_ofs;
 	debug ("monitor flash len: %08lX\n", monitor_flash_len);
 	board_init();	/* Setup chipselects */
 

arch/arm/lib/bootm.c

@@ -327,12 +327,12 @@ void setup_revision_tag(struct tag **in_params)
 }
 #endif  /* CONFIG_REVISION_TAG */
 
-
 static void setup_end_tag (bd_t *bd)
 {
 	params->hdr.tag = ATAG_NONE;
 	params->hdr.size = 0;
 }
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
 
 static ulong get_sp(void)
 {
@@ -341,5 +341,3 @@ static ulong get_sp(void)
 	asm("mov %0, sp" : "=r"(ret) : );
 	return ret;
 }
-
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */

arch/avr32/cpu/start.S

@@ -244,7 +244,7 @@ relocate_code:
 	/* zero out .bss */
 	mov	r0, 0
 	mov	r1, 0
-	lda.w	r9, _end
+	lda.w	r9, __bss_end__
 	sub	r9, r8
 1:	st.d	r10++, r0
 	sub	r9, 8

arch/avr32/include/asm/sections.h

@@ -27,6 +27,6 @@
 extern char _text[], _etext[];
 extern char _data[], __data_lma[], _edata[], __edata_lma[];
 extern char __got_start[], __got_lma[], __got_end[];
-extern char _end[];
+extern char __bss_end__[];
 
 #endif /* __ASM_AVR32_SECTIONS_H */

arch/avr32/lib/board.c

@@ -118,7 +118,7 @@ static int display_banner (void)
 	printf ("\n\n%s\n\n", version_string);
 	printf ("U-Boot code: %08lx -> %08lx  data: %08lx -> %08lx\n",
 		(unsigned long)_text, (unsigned long)_etext,
-		(unsigned long)_data, (unsigned long)_end);
+		(unsigned long)_data, (unsigned long)__bss_end__);
 	return 0;
 }
 
@@ -190,7 +190,7 @@ void board_init_f(ulong board_type)
 	 *  - stack
 	 */
 	addr = CONFIG_SYS_SDRAM_BASE + sdram_size;
-	monitor_len = _end - _text;
+	monitor_len = __bss_end__ - _text;
 
 	/*
 	 * Reserve memory for u-boot code, data and bss.

arch/blackfin/config.mk

@@ -30,7 +30,7 @@ CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
 PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
 PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
 
-LDFLAGS_u-boot += --gc-sections
+LDFLAGS_FINAL += --gc-sections
 LDFLAGS += -m elf32bfin
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
 

arch/i386/config.mk

@@ -21,8 +21,6 @@
 # MA 02111-1307 USA
 #
 
-CROSS_COMPILE ?= i386-linux-
-
 STANDALONE_LOAD_ADDR = 0x40000
 
 PLATFORM_CPPFLAGS += -fno-strict-aliasing
@@ -33,8 +31,12 @@ PLATFORM_CPPFLAGS += $(call cc-option, -ffreestanding)
 PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder,  $(call cc-option, -fno-unit-at-a-time))
 PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector)
 PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2)
-PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__
+PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
+PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
 
-LDFLAGS += --cref
-LDFLAGS_u-boot += --gc-sections
-PLATFORM_RELFLAGS += -ffunction-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
+
+PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
+
+LDFLAGS_FINAL += --gc-sections -pie
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds

arch/i386/cpu/config.mk

@@ -21,6 +21,12 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS +=
+CROSS_COMPILE ?= i386-linux-
 
-PLATFORM_CPPFLAGS += -march=i386 -Werror
+PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ -march=i386 -Werror
+
+# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
+LDPPFLAGS += -DRESET_SEG_START=0xffff0000
+LDPPFLAGS += -DRESET_SEG_SIZE=0x10000
+LDPPFLAGS += -DRESET_VEC_LOC=0xfff0
+LDPPFLAGS += -DSTART_16=0xf800

arch/i386/cpu/cpu.c

@@ -35,6 +35,8 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/processor.h>
+#include <asm/processor-flags.h>
 #include <asm/interrupt.h>
 
 /* Constructor for a conventional segment GDT (or LDT) entry */
@@ -46,13 +48,6 @@
 	 (((base)  & 0x00ffffffULL) << 16) |		\
 	 (((limit) & 0x0000ffffULL)))
 
-/* Simple and small GDT entries for booting only */
-
-#define GDT_ENTRY_32BIT_CS	2
-#define GDT_ENTRY_32BIT_DS	(GDT_ENTRY_32BIT_CS + 1)
-#define GDT_ENTRY_16BIT_CS	(GDT_ENTRY_32BIT_DS + 1)
-#define GDT_ENTRY_16BIT_DS	(GDT_ENTRY_16BIT_CS + 1)
-
 /*
  * Set up the GDT
  */
@@ -92,26 +87,40 @@ static void reload_gdt(void)
 }
 
 
-int cpu_init_f(void)
+int x86_cpu_init_f(void)
 {
+	const u32 em_rst = ~X86_CR0_EM;
+	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
+
 	/* initialize FPU, reset EM, set MP and NE */
 	asm ("fninit\n" \
-	     "movl %cr0, %eax\n" \
-	     "andl $~0x4, %eax\n" \
-	     "orl  $0x22, %eax\n" \
-	     "movl %eax, %cr0\n" );
+	     "movl %%cr0, %%eax\n" \
+	     "andl %0, %%eax\n" \
+	     "orl  %1, %%eax\n" \
+	     "movl %%eax, %%cr0\n" \
+	     : : "i" (em_rst), "i" (mp_ne_set) : "eax");
 
 	return 0;
 }
+int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
 
-int cpu_init_r(void)
+int x86_cpu_init_r(void)
 {
+	const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
+
+	/* turn on the cache and disable write through */
+	asm("movl	%%cr0, %%eax\n"
+	    "andl	%0, %%eax\n"
+	    "movl	%%eax, %%cr0\n"
+	    "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+
 	reload_gdt();
 
 	/* Initialize core interrupt and exception functionality of CPU */
 	cpu_init_interrupts ();
 	return 0;
 }
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {

arch/i386/cpu/interrupts.c

@@ -29,6 +29,8 @@
 
 #include <common.h>
 #include <asm/interrupt.h>
+#include <asm/io.h>
+#include <asm/processor-flags.h>
 
 #define DECLARE_INTERRUPT(x) \
 	".globl irq_"#x"\n" \
@@ -108,6 +110,7 @@ void dump_regs(struct irq_regs *regs)
 {
 	unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
 	unsigned long d0, d1, d2, d3, d6, d7;
+	unsigned long sp;
 
 	printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
 			(u16)regs->xcs, regs->eip, regs->eflags);
@@ -139,6 +142,20 @@ void dump_regs(struct irq_regs *regs)
 	d7 = get_debugreg(7);
 	printf("DR6: %08lx DR7: %08lx\n",
 			d6, d7);
+
+	printf("Stack:\n");
+	sp = regs->esp;
+
+	sp += 64;
+
+	while (sp > (regs->esp - 16)) {
+		if (sp == regs->esp)
+			printf("--->");
+		else
+			printf("    ");
+		printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
+		sp -= 4;
+	}
 }
 
 struct idt_entry {
@@ -221,7 +238,7 @@ int disable_interrupts(void)
 
 	asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
 
-	return (flags&0x200); /* IE flags is bit 9 */
+	return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */
 }
 
 /* IRQ Low-Level Service Routine */

arch/i386/cpu/sc520/Makefile

@@ -32,11 +32,12 @@ include $(TOPDIR)/config.mk
 LIB	:= $(obj)lib$(SOC).o
 
 COBJS-$(CONFIG_SYS_SC520) += sc520.o
+COBJS-$(CONFIG_PCI) += sc520_pci.o
+COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o
 COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
 COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
-COBJS-$(CONFIG_PCI) += sc520_pci.o
 
-SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o
+SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
 
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/i386/cpu/sc520/sc520.c

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Daniel Engstr<74>m, Omicron Ceti AB <daniel@omicron.se>.
+ * Daniel Engstr<74>m, Omicron Ceti AB <daniel@omicron.se>.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,169 +26,43 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/processor-flags.h>
 #include <asm/ic/sc520.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * utility functions for boards based on the AMD sc520
- *
- * void init_sc520(void)
- * unsigned long init_sc520_dram(void)
- */
+sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
 
-volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
-
-void init_sc520(void)
+int cpu_init_f(void)
 {
-	/*
-	 * Set the UARTxCTL register at it's slower,
-	 * baud clock giving us a 1.8432 MHz reference
-	 */
-	writeb(0x07, &sc520_mmcr->uart1ctl);
-	writeb(0x07, &sc520_mmcr->uart2ctl);
-
-	/* first set the timer pin mapping */
-	writeb(0x72, &sc520_mmcr->clksel);	/* no clock frequency selected, use 1.1892MHz */
-
-	/* enable PCI bus arbiter (concurrent mode) */
-	writeb(0x02, &sc520_mmcr->sysarbctl);
-
-	/* enable external grants */
-	writeb(0x1f, &sc520_mmcr->sysarbmenb);
-
-	/* enable posted-writes */
-	writeb(0x04, &sc520_mmcr->hbctl);
-
 	if (CONFIG_SYS_SC520_HIGH_SPEED) {
 		/* set it to 133 MHz and write back */
 		writeb(0x02, &sc520_mmcr->cpuctl);
 		gd->cpu_clk = 133000000;
-		printf("## CPU Speed set to 133MHz\n");
 	} else {
 		/* set it to 100 MHz and write back */
 		writeb(0x01, &sc520_mmcr->cpuctl);
-		printf("## CPU Speed set to 100MHz\n");
 		gd->cpu_clk = 100000000;
 	}
 
-
 	/* wait at least one millisecond */
 	asm("movl	$0x2000, %%ecx\n"
 	    "0:		pushl %%ecx\n"
 	    "popl	%%ecx\n"
 	    "loop 0b\n": : : "ecx");
 
+	return x86_cpu_init_f();
+}
+
+int cpu_init_r(void)
+{
+	/* Disable the PAR used for CAR */
+	writel(0x0000000, &sc520_mmcr->par[2]);
+
 	/* turn on the SDRAM write buffer */
 	writeb(0x11, &sc520_mmcr->dbctl);
 
-	/* turn on the cache and disable write through */
-	asm("movl	%%cr0, %%eax\n"
-	    "andl	$0x9fffffff, %%eax\n"
-	    "movl	%%eax, %%cr0\n"  : : : "eax");
-}
-
-unsigned long init_sc520_dram(void)
-{
-	bd_t *bd = gd->bd;
-
-	u32 dram_present=0;
-	u32 dram_ctrl;
-
-#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
-	/* these memory control registers are set up in the assember part,
-	 * in sc520_asm.S, during 'mem_init'.  If we muck with them here,
-	 * after we are running a stack in RAM, we have troubles.  Besides,
-	 * these refresh and delay values are better ? simply specified
-	 * outright in the include/configs/{cfg} file since the HW designer
-	 * simply dictates it.
-	 */
-#else
-	u8 tmp;
-	u8 val;
-
-	int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
-	int refresh_rate        = CONFIG_SYS_SDRAM_REFRESH_RATE;
-	int ras_cas_delay       = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
-
-	/* set SDRAM speed here */
-
-	refresh_rate /= 78;
-	if (refresh_rate <= 1) {
-		val = 0;	/* 7.8us */
-	} else if (refresh_rate == 2) {
-		val = 1;	/* 15.6us */
-	} else if (refresh_rate == 3 || refresh_rate == 4) {
-		val = 2;	/* 31.2us */
-	} else {
-		val = 3;	/* 62.4us */
-	}
-
-	tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
-	writeb(tmp, &sc520_mmcr->drcctl);
-
-	val = readb(&sc520_mmcr->drctmctl) & 0xf0;
-
-	if (cas_precharge_delay==3) {
-		val |= 0x04;	/* 3T */
-	} else if (cas_precharge_delay==4) {
-		val |= 0x08;	/* 4T */
-	} else if (cas_precharge_delay>4) {
-		val |= 0x0c;
-	}
-
-	if (ras_cas_delay > 3) {
-		val |= 2;
-	} else {
-		val |= 1;
-	}
-	writeb(val, &c520_mmcr->drctmctl);
-#endif
-
-	/*
-	 * We read-back the configuration of the dram
-	 * controller that the assembly code wrote
-	 */
-	dram_ctrl = readl(&sc520_mmcr->drcbendadr);
-
-	bd->bi_dram[0].start = 0;
-	if (dram_ctrl & 0x80) {
-		/* bank 0 enabled */
-		dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
-		bd->bi_dram[0].size = bd->bi_dram[1].start;
-	} else {
-		bd->bi_dram[0].size = 0;
-		bd->bi_dram[1].start = bd->bi_dram[0].start;
-	}
-
-	if (dram_ctrl & 0x8000) {
-		/* bank 1 enabled */
-		dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
-		bd->bi_dram[1].size = bd->bi_dram[2].start -  bd->bi_dram[1].start;
-	} else {
-		bd->bi_dram[1].size = 0;
-		bd->bi_dram[2].start = bd->bi_dram[1].start;
-	}
-
-	if (dram_ctrl & 0x800000) {
-		/* bank 2 enabled */
-		dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
-		bd->bi_dram[2].size = bd->bi_dram[3].start -  bd->bi_dram[2].start;
-	} else {
-		bd->bi_dram[2].size = 0;
-		bd->bi_dram[3].start = bd->bi_dram[2].start;
-	}
-
-	if (dram_ctrl & 0x80000000) {
-		/* bank 3 enabled */
-		dram_present  = (dram_ctrl & 0x7f000000) >> 2;
-		bd->bi_dram[3].size = dram_present -  bd->bi_dram[3].start;
-	} else {
-		bd->bi_dram[3].size = 0;
-	}
-	gd->ram_size = dram_present;
-
-	return dram_present;
+	return x86_cpu_init_r();
 }
 
 #ifdef CONFIG_SYS_SC520_RESET

arch/i386/cpu/sc520/sc520_asm.S

@@ -1,615 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engstr<EFBFBD>m, Omicron Ceti AB <daniel@omicron.se>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* This file is largely based on code obtned from AMD. AMD's original
- * copyright is included below
- */
-
-/*		TITLE	SIZER - Aspen DRAM Sizing Routine.
- * =============================================================================
- *
- *  Copyright 1999 Advanced Micro Devices, Inc.
- * You may redistribute this program and/or modify this program under the terms
- * of the GNU General Public License as published by the Free Software Foundation;
- * either version 2 of the License, or (at your option) any later version.
- *
- *  This program is distributed WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
- * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
- *
- * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
- * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
- * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
- * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
- * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
- * INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY
- * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGES.  BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
- * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
- * LIMITATION MAY NOT APPLY TO YOU.
- *
- * AMD does not assume any responsibility for any errors that may appear in
- * the Materials nor any responsibility to support or update the Materials.
- * AMD retains the right to make changes to its test specifications at any
- * time, without notice.
- * ==============================================================================
- */
-
-/*
- ******************************************************************************
- *
- *  FILE        : sizer.asm - SDRAM DIMM Sizing Algorithm
- *
- *
- *
- *  FUNCTIONS   : sizemem() - jumped to, not called.  To be executed after
- *                reset to determine the size of the SDRAM DIMMs. Initializes
- *		 the memory subsystem.
- *
- *
- *  AUTHOR      : Buddy Fey - Original.
- *
- *
- *  DESCRIPTION : Performs sizing on SDRAM DIMMs on ASPEN processor.
- *                NOTE: This is a small memory model version
- *
- *
- *  INPUTS      : BP contains return address offset
- *		 CACHE is assumed to be disabled.
- *		 The FS segment limit has already been set to big real mode
- *		 (full 32-bit addressing capability)
- *
- *
- *  OUTPUTS     : None
- *
- *
- *  REG USE     :  ax,bx,cx,dx,di,si,bp, fs
- *
- *
- *  REVISION    : See PVCS info below
- *
- *
- *  TEST PLAN CROSS REFERENCE:
- *
- *
- * $Workfile: $
- * $Revision: 1.2 $
- * $Date: 1999/09/22 12:49:33 $
- * $Author: chipf $
- * $Log: sizer.asm $
- * Revision 1.2  1999/09/22 12:49:33  chipf
- * Add legal header
- *
- *******************************************************************************
- */
-
-
-/*******************************************************************************
- *       FUNCTIONAL DESCRIPTION:
- * This routine is called to autodetect the geometry of the DRAM.
- *
- * This routine is called to determine the number of column bits for the DRAM
- * devices in this external bank. This routine assumes that the external bank
- * has been configured for an 11-bit column and for 4 internal banks. This gives
- * us the maximum address reach in memory. By writing a test value to the max
- * address and locating where it aliases to, we can determine the number of valid
- * column bits.
- *
- * This routine is called to determine the number of internal banks each DRAM
- * device has. The external bank (under test) is configured for maximum reach
- * with 11-bit columns and 4 internal banks. This routine will write to a max
- * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if
- * that column is a "don't care". If BA1 does not affect write/read of data,
- * then this device has only 2 internal banks.
- *
- * This routine is called to determine the ending address for this external
- * bank of SDRAM. We write to a max address with a data value and then disable
- * row address bits looking for "don't care" locations. Each "don't care" bit
- * represents a dividing of the maximum density (128M) by 2. By dividing the
- * maximum of 32 4M chunks in an external bank down by all the "don't care" bits
- * determined during sizing, we set the proper density.
- *
- * WARNINGS.
- * bp must be preserved because it is used for return linkage.
- *
- * EXIT
- * nothing returned - but the memory subsystem is enabled
- *******************************************************************************
- */
-
-#include <config.h>
-
-.section .text
-.equ            DRCCTL,     0x0fffef010   /* DRAM control register */
-.equ            DRCTMCTL,   0x0fffef012   /* DRAM timing control register */
-.equ            DRCCFG,     0x0fffef014   /* DRAM bank configuration register */
-.equ            DRCBENDADR, 0x0fffef018   /* DRAM bank ending address register */
-.equ            ECCCTL,     0x0fffef020   /* DRAM ECC control register */
-.equ            ECCINT,     0x0fffefd18   /* DRAM ECC nmi-INT mapping */
-.equ            DBCTL,      0x0fffef040   /* DRAM buffer control register */
-
-.equ            CACHELINESZ, 0x00000010   /* size of our cache line (read buffer) */
-.equ            COL11_ADR,  0x0e001e00    /* 11 col addrs */
-.equ            COL10_ADR,  0x0e000e00    /* 10 col addrs */
-.equ            COL09_ADR,  0x0e000600    /*  9 col addrs */
-.equ            COL08_ADR,  0x0e000200    /*  8 col addrs */
-.equ            ROW14_ADR,  0x0f000000    /* 14 row addrs */
-.equ            ROW13_ADR,  0x07000000    /* 13 row addrs */
-.equ            ROW12_ADR,  0x03000000    /* 12 row addrs */
-.equ            ROW11_ADR,  0x01000000    /* 11 row addrs/also bank switch */
-.equ            ROW10_ADR,  0x00000000    /* 10 row addrs/also bank switch */
-.equ            COL11_DATA, 0x0b0b0b0b    /* 11 col addrs */
-.equ            COL10_DATA, 0x0a0a0a0a    /* 10 col data */
-.equ            COL09_DATA, 0x09090909    /*  9 col data */
-.equ            COL08_DATA, 0x08080808    /*  8 col data */
-.equ            ROW14_DATA, 0x3f3f3f3f    /* 14 row data (MASK) */
-.equ            ROW13_DATA, 0x1f1f1f1f    /* 13 row data (MASK) */
-.equ            ROW12_DATA, 0x0f0f0f0f    /* 12 row data (MASK) */
-.equ            ROW11_DATA, 0x07070707    /* 11 row data/also bank switch (MASK) */
-.equ            ROW10_DATA, 0xaaaaaaaa    /* 10 row data/also bank switch (MASK) */
-
-.globl mem_init
-mem_init:
-	/* Preserve Boot Flags */
-	movl	%ebx, %ebp
-
-	/* initialize dram controller registers */
-	xorw	%ax, %ax
-	movl	$DBCTL, %edi
-	movb	%al, (%edi)		/* disable write buffer */
-
-	movl	$ECCCTL, %edi
-	movb	%al, (%edi)		/* disable ECC */
-
-	movl	$DRCTMCTL, %edi
-	movb	$0x1e, %al		/* Set SDRAM timing for slowest */
-	movb	%al, (%edi)
-
-	/* setup loop to do 4 external banks starting with bank 3 */
-	movl	$0xff000000, %eax	/* enable last bank and setup */
-	movl	$DRCBENDADR, %edi	/* ending address register */
-	movl	%eax, (%edi)
-
-	movl	$DRCCFG, %edi		/* setup */
-	movw	$0xbbbb, %ax		/* dram config register for  */
-	movw	%ax, (%edi)
-
-	/* issue a NOP to all DRAMs */
-	movl	$DRCCTL, %edi		/* setup DRAM control register with */
-	movb	$0x01, %al		/* Disable refresh,disable write buffer */
-	movb	%al, (%edi)
-	movl	$CACHELINESZ, %esi	/* just a dummy address to write for */
-	movw	%ax, (%esi)
-
-	/* delay for 100 usec? */
-	movw	$100, %cx
-sizdelay:
-	loop	sizdelay
-
-	/* issue all banks precharge */
-	movb	$0x02, %al
-	movb	%al, (%edi)
-	movw	%ax, (%esi)
-
-	/* issue 2 auto refreshes to all banks */
-	movb	$0x04, %al	/* Auto refresh cmd */
-	movb	%al, (%edi)
-	movw	$0x02, %cx
-refresh1:
-	movw	%ax, (%esi)
-	loop	refresh1
-
-	/* issue LOAD MODE REGISTER command */
-	movb	$0x03, %al	/* Load mode register cmd */
-	movb	%al, (%edi)
-	movw	%ax, (%esi)
-
-	/* issue 8 more auto refreshes to all banks */
-	movb	$0x04, %al	/* Auto refresh cmd */
-	movb	%al, (%edi)
-	movw	$0x0008, %cx
-refresh2:
-	movw	%ax, (%esi)
-	loop	refresh2
-
-	/* set control register to NORMAL mode */
-	movb	$0x00, %al	/* Normal mode value */
-	movb	%al, (%edi)
-
-	/*
-	 * size dram starting with external bank 3
-	 * moving to external bank 0
-	 */
-	movl	$0x3, %ecx	/* start with external bank 3 */
-
-nextbank:
-
-	/* write col 11 wrap adr */
-	movl	$COL11_ADR, %esi	/* set address to max col (11) wrap addr */
-	movl	$COL11_DATA, %eax	/* pattern for max supported columns(11) */
-	movl	%eax, (%esi)		/* write max col pattern at max col adr */
-	movl	(%esi), %ebx		/* optional read */
-	cmpl	%ebx, %eax		/* to verify write */
-	jnz	bad_ram			/* this ram is bad */
-
-	/* write col 10 wrap adr */
-	movl	$COL10_ADR, %esi	/* set address to 10 col wrap address */
-	movl	$COL10_DATA, %eax	/* pattern for 10 col wrap */
-	movl	%eax, (%esi)		/* write 10 col pattern @ 10 col wrap adr */
-	movl	(%esi), %ebx		/* optional read */
-	cmpl	%ebx, %eax		/* to verify write */
-	jnz	bad_ram			/* this ram is bad */
-
-	/* write col 9 wrap adr */
-	movl	$COL09_ADR, %esi	/* set address to 9 col wrap address */
-	movl	$COL09_DATA, %eax	/* pattern for 9 col wrap */
-	movl	%eax, (%esi)		/* write 9 col pattern @ 9 col wrap adr */
-	movl	(%esi), %ebx		/* optional read */
-	cmpl	%ebx, %eax		/* to verify write */
-	jnz	bad_ram			/* this ram is bad */
-
-	/* write col 8 wrap adr */
-	movl	$COL08_ADR, %esi	/* set address to min(8) col wrap address */
-	movl	$COL08_DATA, %eax	/* pattern for min (8) col wrap */
-	movl	%eax, (%esi)		/* write min col pattern @ min col adr */
-	movl	(%esi), %ebx		/* optional read */
-	cmpl	%ebx, %eax		/* to verify write */
-	jnz	bad_ram			/* this ram is bad */
-
-	/* write row 14 wrap adr */
-	movl	$ROW14_ADR, %esi	/* set address to max row (14) wrap addr */
-	movl	$ROW14_DATA, %eax	/* pattern for max supported rows(14) */
-	movl	%eax, (%esi)		/* write max row pattern at max row adr */
-	movl	(%esi), %ebx		/* optional read */
-	cmpl	%ebx, %eax		/* to verify write */
-	jnz	bad_ram			/* this ram is bad */
-
-	/* write row 13 wrap adr */
-	movl	$ROW13_ADR, %esi	/* set address to 13 row wrap address */
-	movl	$ROW13_DATA, %eax	/* pattern for 13 row wrap */
-	movl	%eax, (%esi)		/* write 13 row pattern @ 13 row wrap adr */
-	movl	(%esi), %ebx		/* optional read */
-	cmpl	%ebx, %eax		/* to verify write */
-	jnz	bad_ram			/* this ram is bad */
-
-	/* write row 12 wrap adr */
-	movl	$ROW12_ADR, %esi	/* set address to 12 row wrap address */
-	movl	$ROW12_DATA, %eax	/* pattern for 12 row wrap */
-	movl	%eax, (%esi)		/* write 12 row pattern @ 12 row wrap adr */
-	movl	(%esi), %ebx		/* optional read */
-	cmpl	%ebx, %eax		/* to verify write */
-	jnz	bad_ram			/* this ram is bad */
-
-	/* write row 11 wrap adr */
-	movl	$ROW11_ADR, %edi	/* set address to 11 row wrap address */
-	movl	$ROW11_DATA, %eax	/* pattern for 11 row wrap */
-	movl	%eax, (%edi)		/* write 11 row pattern @ 11 row wrap adr */
-	movl	(%edi), %ebx		/* optional read */
-	cmpl	%ebx, %eax		/* to verify write */
-	jnz	bad_ram			/* this ram is bad */
-
-	/*
-	 * write row 10 wrap adr --- this write is really to determine
-	 * number of banks
-	 */
-	movl	$ROW10_ADR, %edi	/* set address to 10 row wrap address */
-	movl	$ROW10_DATA, %eax	/* pattern for 10 row wrap (AA) */
-	movl	%eax, (%edi)		/* write 10 row pattern @ 10 row wrap adr */
-	movl	(%edi), %ebx		/* optional read */
-	cmpl	%ebx, %eax		/* to verify write */
-	jnz	bad_ram			/* this ram is bad */
-
-	/*
-	 * read data @ row 12 wrap adr to determine  * banks,
-	 * and read data @ row 14 wrap adr to determine  * rows.
-	 * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
-	 * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
-	 * if data @ row 12 wrap == 11 or 12, we have 4 banks,
-	 */
-	xorw	%di, %di		/* value for 2 banks in DI */
-	movl	(%esi), %ebx		/* read from 12 row wrap to check banks */
-					/* (esi is setup from the write to row 12 wrap) */
-	cmpl	%ebx, %eax		/* check for AA pattern  (eax holds the aa pattern) */
-	jz	only2			/* if pattern == AA, we only have 2 banks */
-
-	/* 4 banks */
-
-	movw	$0x008, %di		/* value for 4 banks in DI (BNK_CNT bit) */
-	cmpl	$ROW11_DATA, %ebx	/* only other legitimate values are 11 */
-	jz	only2
-	cmpl	$ROW12_DATA, %ebx	/* and 12 */
-	jnz	bad_ram			/* its bad if not 11 or 12! */
-
-	/* fall through */
-only2:
- /*
-  * validate row mask
-  */
-	movl	$ROW14_ADR, %esi	/* set address back to max row wrap addr */
-	movl	(%esi), %eax		/* read actual number of rows @ row14 adr */
-
-	cmpl	$ROW11_DATA, %eax	/* row must be greater than 11 pattern */
-	jb	bad_ram
-
-	cmpl	$ROW14_DATA, %eax	/* and row must be less than 14 pattern */
-	ja	bad_ram
-
-	cmpb	%ah, %al		/* verify all 4 bytes of dword same */
-	jnz	bad_ram
-	movl	%eax, %ebx
-	shrl	$16, %ebx
-	cmpw	%bx, %ax
-	jnz	bad_ram
-
-	/*
-	 * read col 11 wrap adr for real column data value
-	 */
-	movl	$COL11_ADR, %esi	/* set address to max col (11) wrap addr */
-	movl	(%esi), %eax		/* read real col number at max col adr */
-
-	/*
-	 * validate column data
-	 */
-	cmpl	$COL08_DATA, %eax	/* col must be greater than 8 pattern */
-	jb	bad_ram
-
-	cmpl	$COL11_DATA, %eax	/* and row must be less than 11 pattern */
-	ja	bad_ram
-
-	subl	$COL08_DATA, %eax	/* normalize column data to zero */
-	jc	bad_ram
-	cmpb	%ah, %al		/* verify all 4 bytes of dword equal */
-	jnz	bad_ram
-	movl	%eax, %edx
-	shrl	$16, %edx
-	cmpw	%dx, %ax
-	jnz	bad_ram
-
-	/*
-	 * merge bank and col data together
-	 */
-	addw	%di, %dx		/* merge of bank and col info in dl */
-
-	/*
-	 * fix ending addr mask based upon col info
-	 */
-	movb	$0x03, %al
-	subb	%dh, %al		/* dh contains the overflow from the bank/col merge  */
-	movb	%bl, %dh		/* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
-	xchgw	%cx, %ax		/* cx = ax = 3 or 2 depending on 2 or 4 bank device */
-	shrb	%cl, %dh
-	incb	%dh			/* ending addr is 1 greater than real end */
-	xchgw	%cx, %ax		/* cx is bank number again */
-
-bad_reint:
-	/*
-	 * issue all banks precharge
-	 */
-	movl	$DRCCTL, %esi		/* setup DRAM control register with */
-	movb	$0x02, %al		/* All banks precharge */
-	movb	%al, (%esi)
-	movl	$CACHELINESZ, %esi	/* address to init read buffer */
-	movw	%ax, (%esi)
-
-	/*
-	 * update ENDING ADDRESS REGISTER
-	 */
-	movl	$DRCBENDADR, %edi	/* DRAM ending address register */
-	movl	%ecx, %ebx
-	addl	%ebx, %edi
-	movb	%dh, (%edi)
-
-	/*
-	 * update CONFIG REGISTER
-	 */
-	xorb	%dh, %dh
-	movw	$0x000f, %bx
-	movw	%cx, %ax
-	shlw	$2, %ax
-	xchgw	%cx, %ax
-	shlw	%cl, %dx
-	shlw	%cl, %bx
-	notw	%bx
-	xchgw	%cx, %ax
-	movl	$DRCCFG, %edi
-	movw	(%edi), %ax
-	andw	%bx, %ax
-	orw	%dx, %ax
-	movw	%ax, (%edi)
-	jcxz	cleanup
-
-	decw	%cx
-	movl	%ecx, %ebx
-	movl	$DRCBENDADR, %edi	/* DRAM ending address register */
-	movb	$0xff, %al
-	addl	%ebx, %edi
-	movb	%al, (%edi)
-
-	/*
-	 * set control register to NORMAL mode
-	 */
-	movl	$DRCCTL, %esi		/* setup DRAM control register with */
-	movb	$0x00, %al		/* Normal mode value */
-	movb	%al, (%esi)
-	movl	$CACHELINESZ, %esi	/* address to init read buffer */
-	movw	%ax, (%esi)
-	jmp	nextbank
-
-cleanup:
-	movl	$DRCBENDADR, %edi	/* DRAM ending address register  */
-	movw	$0x04, %cx
-	xorw	%ax, %ax
-cleanuplp:
-	movb	(%edi), %al
-	orb	%al, %al
-	jz	emptybank
-
-	addb	%ah, %al
-	jns	nottoomuch
-
-	movb	$0x7f, %al
-nottoomuch:
-	movb	%al, %ah
-	orb	$0x80, %al
-	movb	%al, (%edi)
-emptybank:
-	incl	%edi
-	loop	cleanuplp
-
-#if defined CONFIG_SYS_SDRAM_DRCTMCTL
-	/* just have your hardware desinger _GIVE_ you what you need here! */
-	movl	$DRCTMCTL, %edi
-	movb	$CONFIG_SYS_SDRAM_DRCTMCTL, %al
-	movb	%al, (%edi)
-#else
-#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
-	/*
-	 * Set the CAS latency now since it is hard to do
-	 * when we run from the RAM
-	 */
-	movl	$DRCTMCTL, %edi	/* DRAM timing register */
-	movb	(%edi), %al
-#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
-	andb	$0xef, %al
-#endif
-#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
-	orb	$0x10, %al
-#endif
-	movb	%al, (%edi)
-#endif
-#endif
-	movl	$DRCCTL, %edi	/* DRAM Control register */
-	movb	$0x03, %al	/* Load mode register cmd */
-	movb	%al, (%edi)
-	movw	%ax, (%esi)
-
-
-	movl	$DRCCTL, %edi	/* DRAM Control register */
-	movb	$0x18, %al	/*  Enable refresh and NORMAL mode */
-	movb	%al, (%edi)
-
-	jmp	dram_done
-
-bad_ram:
-	xorl	%edx, %edx
-	xorl	%edi, %edi
-	jmp	bad_reint
-
-dram_done:
-	/* Restore Boot Flags */
-	movl	%ebx, %ebp
-	jmp	mem_init_ret
-
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-.globl init_ecc
-init_ecc:
-	/* A nominal memory test: just a byte at each address line */
-	movl	%eax, %ecx
-	shrl	$0x1, %ecx
-	movl	$0x1, %edi
-memtest0:
-	movb	$0xa5, (%edi)
-	cmpb	$0xa5, (%edi)
-	jne	out
-	shrl	$0x1, %ecx
-	andl	%ecx, %ecx
-	jz	set_ecc
-	shll	$0x1, %edi
-	jmp	memtest0
-
-set_ecc:
-	/* clear all ram with a memset */
-	movl	%eax, %ecx
-	xorl	%esi, %esi
-	xorl	%edi, %edi
-	xorl	%eax, %eax
-	shrl	$0x2, %ecx
-	cld
-	rep	stosl
-
-	/* enable read, write buffers */
-	movb	$0x11, %al
-	movl	$DBCTL, %edi
-	movb	%al, (%edi)
-
-	/* enable NMI mapping for ECC */
-	movl	$ECCINT, %edi
-	movb	$0x10, %al
-	movb	%al, (%edi)
-
-	/* Turn on ECC */
-	movl	$ECCCTL, %edi
-	movb	$0x05, %al
-	movb	%al,(%edi)
-
-out:
-	jmp	init_ecc_ret
-#endif
-
-/*
- * Read and decode the sc520 DRCBENDADR MMCR and return the number of
- * available ram bytes in %eax
- */
-.globl get_mem_size
-get_mem_size:
-	movl	$DRCBENDADR, %edi	/* DRAM ending address register */
-
-bank0:	movl	(%edi), %eax
-	movl	%eax, %ecx
-	andl	$0x00000080, %ecx
-	jz	bank1
-	andl	$0x0000007f, %eax
-	shll	$22, %eax
-	movl	%eax, %edx
-
-bank1:	movl	(%edi), %eax
-	movl	%eax, %ecx
-	andl	$0x00008000, %ecx
-	jz	bank2
-	andl	$0x00007f00, %eax
-	shll	$14, %eax
-	movl	%eax, %edx
-
-bank2:	movl	(%edi), %eax
-	movl	%eax, %ecx
-	andl	$0x00800000, %ecx
-	jz	bank3
-	andl	$0x007f0000, %eax
-	shll	$6, %eax
-	movl	%eax, %edx
-
-bank3:	movl	(%edi), %eax
-	movl	%eax, %ecx
-	andl	$0x80000000, %ecx
-	jz	done
-	andl	$0x7f000000, %eax
-	shrl	$2, %eax
-	movl	%eax, %edx
-
-done:
-	movl	%edx, %eax
-	jmp	get_mem_size_ret

arch/i386/cpu/sc520/sc520_car.S

@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2010
+ * Graeme Russ <graeme.russ@gmail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <asm/processor-flags.h>
+#include <asm/ic/sc520.h>
+
+.section .text
+
+.globl car_init
+car_init:
+	/*
+	 * How to enable Cache-As-RAM for the AMD Elan SC520:
+	 *  1. Turn off the CPU Cache (may not be strictly required)
+	 *  2. Set code execution PAR (usually the BOOTCS region) to be
+	 *     non-cachable
+	 *  3. Create a Cachable PAR Region for an area of memory which is
+	 *       a) NOT where the code is being executed
+	 *       b) NOT SDRAM (Controller not initialised yet)
+	 *       c) WILL response to read requests
+	 *     The easiest way to do this is to create a second BOOTCS
+	 *     PAR mappnig with an address != the PAR in step 2
+	 *  4. Issue a wbinvd to invalidate the CPU cache
+	 *  5. Turn on the CPU Cache
+	 *  6. Read 16kB from the cached PAR region setup in step 3
+	 *  7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
+	 *
+	 * The following code uses PAR2 as the cached PAR (PAR0 and PAR1
+	 * are avoided as these are the only two PARs which can be used
+	 * as PCI BUS Memory regions which the board might require)
+	 *
+	 * The configuration of PAR2 must be set in the board configuration
+	 * file as CONFIG_SYS_SC520_CAR_PAR
+	 */
+
+	/* Configure Cache-As-RAM PAR */
+	movl	$CONFIG_SYS_SC520_CAR_PAR, %eax
+	movl	$SC520_PAR2, %edi
+	movl	%eax, (%edi)
+
+	/* Trash the cache then turn it on */
+	wbinvd
+	movl	%cr0, %eax
+	andl	$~(X86_CR0_NW | X86_CR0_CD), %eax
+	movl	%eax, %cr0
+
+	/*
+	 * The cache is now enabled and empty. Map a region of memory to
+	 * it by reading that region.
+	 */
+	movl	$CONFIG_SYS_CAR_ADDR, %esi
+	movl	$CONFIG_SYS_CAR_SIZE, %ecx
+	shrl	$2, %ecx			/* we are reading longs */
+	cld
+	rep	lodsl
+
+	/* Turn off the cache, but don't trash it */
+	movl	%cr0, %eax
+	orl	$(X86_CR0_NW | X86_CR0_CD), %eax
+	movl	%eax, %cr0
+
+	/* Clear the CAR region */
+	xorl	%eax, %eax
+	movl	$CONFIG_SYS_CAR_ADDR, %edi
+	movl	$CONFIG_SYS_CAR_SIZE, %ecx
+	shrl	$2, %ecx			/* we are writing longs */
+	rep	stosl
+
+	/*
+	 * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
+	 * Cache-As-RAM
+	 */
+	jmp	car_init_ret

arch/i386/cpu/sc520/sc520_sdram.c

@@ -0,0 +1,532 @@
+/*
+ * (C) Copyright 2010
+ * Graeme Russ <graeme.russ@gmail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor-flags.h>
+#include <asm/ic/sc520.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sc520_sdram_info {
+	u8 banks;
+	u8 columns;
+	u8 rows;
+	u8 size;
+};
+
+static void sc520_sizemem(void);
+static void sc520_set_dram_timing(void);
+static void sc520_set_dram_refresh_rate(void);
+static void sc520_enable_dram_refresh(void);
+static void sc520_enable_sdram(void);
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+static void sc520_enable_ecc(void)
+#endif
+
+int dram_init_f(void)
+{
+	sc520_sizemem();
+	sc520_set_dram_timing();
+	sc520_set_dram_refresh_rate();
+	sc520_enable_dram_refresh();
+	sc520_enable_sdram();
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+	sc520_enable_ecc();
+#endif
+
+	return 0;
+}
+
+static inline void sc520_dummy_write(void)
+{
+	writew(0x0000, CACHELINESZ);
+}
+static inline void sc520_issue_sdram_op_mode_select(u8 command)
+{
+	writeb(command, &sc520_mmcr->drcctl);
+	sc520_dummy_write();
+}
+
+static inline int check_long(u32 test_long)
+{
+	u8 i;
+	u8 tmp_byte = (u8)(test_long & 0x000000ff);
+
+	for (i = 1; i < 4; i++) {
+		if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte)
+				return -1;
+	}
+
+	return 0;
+}
+
+static inline int write_and_test(u32 data, u32 address)
+{
+	writel(data, address);
+	if (readl(address) == data)
+		return 0; /* Good */
+	else
+		return -1; /* Bad */
+}
+
+static void sc520_enable_sdram(void)
+{
+	u32 par_config;
+
+	/* Enable Writes, Caching and Code Execution to SDRAM */
+	par_config = readl(&sc520_mmcr->par[3]);
+	par_config &= ~(SC520_PAR_EXEC_DIS |
+			SC520_PAR_CACHE_DIS |
+			SC520_PAR_WRITE_DIS);
+	writel(par_config, &sc520_mmcr->par[3]);
+
+	par_config = readl(&sc520_mmcr->par[4]);
+	par_config &= ~(SC520_PAR_EXEC_DIS |
+			SC520_PAR_CACHE_DIS |
+			SC520_PAR_WRITE_DIS);
+	writel(par_config, &sc520_mmcr->par[4]);
+}
+
+static void sc520_set_dram_timing(void)
+{
+	u8 drctmctl = 0x00;
+
+#if defined CONFIG_SYS_SDRAM_DRCTMCTL
+	/* just have your hardware designer _GIVE_ you what you need here! */
+	drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL;
+#else
+	switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) {
+	case 2:
+		break;
+	case 3:
+		drctmctl |= 0x01;
+		break;
+	case 4:
+	default:
+		drctmctl |= 0x02;
+		break;
+	}
+
+	switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) {
+	case 2:
+		break;
+	case 3:
+		drctmctl |= 0x04;
+		break;
+	case 4:
+	default:
+		drctmctl |= 0x08;
+		break;
+
+	case 6:
+		drctmctl |= 0x0c;
+		break;
+	}
+
+	switch (CONFIG_SYS_SDRAM_CAS_LATENCY) {
+	case 2:
+		break;
+	case 3:
+	default:
+		drctmctl |= 0x10;
+		break;
+	}
+#endif
+	writeb(drctmctl, &sc520_mmcr->drctmctl);
+
+	/* Issue load mode register command */
+	sc520_issue_sdram_op_mode_select(0x03);
+}
+
+static void sc520_set_dram_refresh_rate(void)
+{
+	u8 drctl;
+
+	drctl = readb(&sc520_mmcr->drcctl);
+	drctl &= 0xcf;
+
+	switch (CONFIG_SYS_SDRAM_REFRESH_RATE) {
+	case 78:
+		break;
+	case 156:
+	default:
+		drctl |= 0x10;
+		break;
+	case 312:
+		drctl |= 0x20;
+		break;
+	case 624:
+		drctl |= 0x30;
+		break;
+	}
+
+	writeb(drctl, &sc520_mmcr->drcctl);
+}
+
+static void sc520_enable_dram_refresh(void)
+{
+	u8 drctl;
+
+	drctl = readb(&sc520_mmcr->drcctl);
+	drctl &= 0x30; /* keep refresh rate */
+	drctl |= 0x08; /* enable refresh, normal mode */
+
+	writeb(drctl, &sc520_mmcr->drcctl);
+}
+
+static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info)
+{
+	u32 col_data;
+	u32 row_data;
+
+	u32 drcbendadr;
+	u16 drccfg;
+
+	u8 banks = 0x00;
+	u8 columns = 0x00;
+	u8 rows = 0x00;
+
+	bank_info->banks = 0x00;
+	bank_info->columns = 0x00;
+	bank_info->rows = 0x00;
+	bank_info->size = 0x00;
+
+	if ((bank < 0) || (bank > 3)) {
+		printf("Bad Bank ID\n");
+		return;
+	}
+
+	/* Save configuration */
+	drcbendadr = readl(&sc520_mmcr->drcbendadr);
+	drccfg = readw(&sc520_mmcr->drccfg);
+
+	/* Setup SDRAM Bank to largest possible size */
+	writew(0x000b << (bank * 4), &sc520_mmcr->drccfg);
+
+	/* Set ending address for this bank */
+	writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr);
+
+	/* write col 11 wrap adr */
+	if (write_and_test(COL11_DATA, COL11_ADR) != 0)
+		goto restore_and_exit;
+
+	/* write col 10 wrap adr */
+	if (write_and_test(COL10_DATA, COL10_ADR) != 0)
+		goto restore_and_exit;
+
+	/* write col 9 wrap adr */
+	if (write_and_test(COL09_DATA, COL09_ADR) != 0)
+		goto restore_and_exit;
+
+	/* write col 8 wrap adr */
+	if (write_and_test(COL08_DATA, COL08_ADR) != 0)
+		goto restore_and_exit;
+
+	col_data = readl(COL11_ADR);
+
+	/* All four bytes in the read long must be the same */
+	if (check_long(col_data) < 0)
+		goto restore_and_exit;
+
+	if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA))
+		columns = (u8)(col_data & 0x000000ff);
+	else
+		goto restore_and_exit;
+
+	/* write row 14 wrap adr */
+	if (write_and_test(ROW14_DATA, ROW14_ADR) != 0)
+		goto restore_and_exit;
+
+	/* write row 13 wrap adr */
+	if (write_and_test(ROW13_DATA, ROW13_ADR) != 0)
+		goto restore_and_exit;
+
+	/* write row 12 wrap adr */
+	if (write_and_test(ROW12_DATA, ROW12_ADR) != 0)
+		goto restore_and_exit;
+
+	/* write row 11 wrap adr */
+	if (write_and_test(ROW11_DATA, ROW11_ADR) != 0)
+		goto restore_and_exit;
+
+	if (write_and_test(ROW10_DATA, ROW10_ADR) != 0)
+		goto restore_and_exit;
+
+	/*
+	 * read data @ row 12 wrap adr to determine number of banks,
+	 * and read data @ row 14 wrap adr to determine number of rows.
+	 * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
+	 * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
+	 * if data @ row 12 wrap == 11 or 12, we have 4 banks,
+	 */
+	row_data = readl(ROW12_ADR);
+
+	/* All four bytes in the read long must be the same */
+	if (check_long(row_data) != 0)
+		goto restore_and_exit;
+
+	switch (row_data) {
+	case ROW10_DATA:
+		banks = 2;
+		break;
+
+	case ROW11_DATA:
+	case ROW12_DATA:
+		banks = 4;
+		break;
+
+	default:
+		goto restore_and_exit;
+	}
+
+	row_data = readl(ROW14_ADR);
+
+	/* All four bytes in the read long must be the same */
+	if (check_long(row_data) != 0)
+		goto restore_and_exit;
+
+	switch (row_data) {
+	case ROW11_DATA:
+	case ROW12_DATA:
+	case ROW13_DATA:
+	case ROW14_DATA:
+		rows = (u8)(row_data & 0x000000ff);
+		break;
+
+	default:
+		goto restore_and_exit;
+	}
+
+	bank_info->banks = banks;
+	bank_info->columns = columns;
+	bank_info->rows = rows;
+
+	if ((bank_info->banks != 0) &&
+	    (bank_info->columns != 0) &&
+	    (bank_info->rows != 0)) {
+		bank_info->size = bank_info->rows;
+		bank_info->size >>= (11 - bank_info->columns);
+		bank_info->size++;
+	}
+
+restore_and_exit:
+	/* Restore configuration */
+	writel(drcbendadr, &sc520_mmcr->drcbendadr);
+	writew(drccfg, &sc520_mmcr->drccfg);
+}
+
+static void sc520_setup_sizemem(void)
+{
+	u8 i;
+
+	/* Disable write buffer */
+	writeb(0x00, &sc520_mmcr->dbctl);
+
+	/* Disable ECC */
+	writeb(0x00, &sc520_mmcr->eccctl);
+
+	/* Set slowest SDRAM timing */
+	writeb(0x1e, &sc520_mmcr->drctmctl);
+
+	/* Issue a NOP to all SDRAM banks */
+	sc520_issue_sdram_op_mode_select(0x01);
+
+	/* Delay for 100 microseconds */
+	udelay(100);
+
+	/* Issue 'All Banks Precharge' command */
+	sc520_issue_sdram_op_mode_select(0x02);
+
+	/* Issue 2 'Auto Refresh Enable' command */
+	sc520_issue_sdram_op_mode_select(0x04);
+	sc520_dummy_write();
+
+	/* Issue 'Load Mode Register' command */
+	sc520_issue_sdram_op_mode_select(0x03);
+
+	/* Issue 8 more 'Auto Refresh Enable' commands */
+	sc520_issue_sdram_op_mode_select(0x04);
+	for (i = 0; i < 7; i++)
+		sc520_dummy_write();
+
+	/* Set control register to 'Normal Mode' */
+	writeb(0x00, &sc520_mmcr->drcctl);
+}
+
+static void sc520_sizemem(void)
+{
+	struct sc520_sdram_info sdram_info[4];
+	u8 bank_config = 0x00;
+	u8 end_addr = 0x00;
+	u16 drccfg = 0x0000;
+	u32 drcbendadr = 0x00000000;
+	u8 i;
+
+	/* Use PARs to disable caching of maximum allowable 256MB SDRAM */
+	writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[3]);
+	writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[4]);
+
+	sc520_setup_sizemem();
+
+	gd->ram_size = 0;
+
+	/* Size each SDRAM bank */
+	for (i = 0; i <= 3; i++) {
+		sc520_get_bank_info(i, &sdram_info[i]);
+
+		if (sdram_info[i].banks != 0) {
+			/* Update Configuration register */
+			bank_config = sdram_info[i].columns - 8;
+
+			if (sdram_info[i].banks == 4)
+				bank_config |= 0x08;
+
+			drccfg |= bank_config << (i * 4);
+
+			/* Update End Address register */
+			end_addr += sdram_info[i].size;
+			drcbendadr |= (end_addr | 0x80) << (i * 8);
+
+			gd->ram_size += sdram_info[i].size << 22;
+		}
+
+		/* Issue 'All Banks Precharge' command */
+		sc520_issue_sdram_op_mode_select(0x02);
+
+		/* Set control register to 'Normal Mode' */
+		writeb(0x00, &sc520_mmcr->drcctl);
+	}
+
+	writel(drcbendadr, &sc520_mmcr->drcbendadr);
+	writew(drccfg, &sc520_mmcr->drccfg);
+
+	/* Clear PARs preventing caching of SDRAM */
+	writel(0x00000000, &sc520_mmcr->par[3]);
+	writel(0x00000000, &sc520_mmcr->par[4]);
+}
+
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+static void sc520_enable_ecc(void)
+
+	/* A nominal memory test: just a byte at each address line */
+	movl	%eax, %ecx
+	shrl	$0x1, %ecx
+	movl	$0x1, %edi
+memtest0:
+	movb	$0xa5, (%edi)
+	cmpb	$0xa5, (%edi)
+	jne	out
+	shrl	$0x1, %ecx
+	andl	%ecx, %ecx
+	jz	set_ecc
+	shll	$0x1, %edi
+	jmp	memtest0
+
+set_ecc:
+	/* clear all ram with a memset */
+	movl	%eax, %ecx
+	xorl	%esi, %esi
+	xorl	%edi, %edi
+	xorl	%eax, %eax
+	shrl	$0x2, %ecx
+	cld
+	rep	stosl
+
+	/* enable read, write buffers */
+	movb	$0x11, %al
+	movl	$DBCTL, %edi
+	movb	%al, (%edi)
+
+	/* enable NMI mapping for ECC */
+	movl	$ECCINT, %edi
+	movb	$0x10, %al
+	movb	%al, (%edi)
+
+	/* Turn on ECC */
+	movl	$ECCCTL, %edi
+	movb	$0x05, %al
+	movb	%al,(%edi)
+
+out:
+	jmp	init_ecc_ret
+}
+#endif
+
+int dram_init(void)
+{
+	ulong dram_ctrl;
+	ulong dram_present = 0x00000000;
+
+	/*
+	 * We read-back the configuration of the dram
+	 * controller that the assembly code wrote
+	 */
+	dram_ctrl = readl(&sc520_mmcr->drcbendadr);
+
+	gd->bd->bi_dram[0].start = 0;
+	if (dram_ctrl & 0x80) {
+		/* bank 0 enabled */
+		gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
+		dram_present = gd->bd->bi_dram[1].start;
+		gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start;
+	} else {
+		gd->bd->bi_dram[0].size = 0;
+		gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start;
+	}
+
+	if (dram_ctrl & 0x8000) {
+		/* bank 1 enabled */
+		gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
+		dram_present = gd->bd->bi_dram[2].start;
+		gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start -
+				gd->bd->bi_dram[1].start;
+	} else {
+		gd->bd->bi_dram[1].size = 0;
+		gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start;
+	}
+
+	if (dram_ctrl & 0x800000) {
+		/* bank 2 enabled */
+		gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
+		dram_present = gd->bd->bi_dram[3].start;
+		gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start -
+				gd->bd->bi_dram[2].start;
+	} else {
+		gd->bd->bi_dram[2].size = 0;
+		gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start;
+	}
+
+	if (dram_ctrl & 0x80000000) {
+		/* bank 3 enabled */
+		dram_present  = (dram_ctrl & 0x7f000000) >> 2;
+		gd->bd->bi_dram[3].size = dram_present -
+				gd->bd->bi_dram[3].start;
+	} else {
+		gd->bd->bi_dram[3].size = 0;
+	}
+
+	gd->ram_size = dram_present;
+
+	return 0;
+}

arch/i386/cpu/start.S

@@ -1,7 +1,7 @@
 /*
  *  U-boot - i386 Startup Code
  *
- *  Copyright (c) 2002	Omicron Ceti AB, Daniel Engstr<EFBFBD>m <denaiel@omicron.se>
+ *  Copyright (c) 2002	Omicron Ceti AB, Daniel Engstr<EFBFBD>m <denaiel@omicron.se>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,6 +26,7 @@
 #include <config.h>
 #include <version.h>
 #include <asm/global_data.h>
+#include <asm/processor-flags.h>
 
 
 .section .text
@@ -46,7 +47,7 @@ _i386boot_start:
 
 	/* Turn of cache (this might require a 486-class CPU) */
 	movl	%cr0, %eax
-	orl	$0x60000000, %eax
+	orl	$(X86_CR0_NW | X86_CR0_CD), %eax
 	movl	%eax, %cr0
 	wbinvd
 
@@ -66,78 +67,68 @@ _start:
 	/* Clear the interupt vectors */
 	lidt	blank_idt_ptr
 
-	/* Skip low-level initialization if not starting from cold-reset */
-	movl	%ebx, %ecx
-	andl	$GD_FLG_COLD_BOOT, %ecx
-	jz	skip_mem_init
-
 	/* Early platform init (setup gpio, etc ) */
 	jmp	early_board_init
 .globl early_board_init_ret
 early_board_init_ret:
 
-	/* size memory */
-	jmp	mem_init
-.globl mem_init_ret
-mem_init_ret:
+	/* Initialise Cache-As-RAM */
+	jmp	car_init
+.globl car_init_ret
+car_init_ret:
+	/*
+	 * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
+	 * or fully initialised SDRAM - we really don't care which)
+	 * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
+	 */
+	movl	$CONFIG_SYS_INIT_SP_ADDR, %esp
+	movl	$CONFIG_SYS_INIT_GD_ADDR, %ebp
 
-skip_mem_init:
-	/* fetch memory size (into %eax) */
-	jmp	get_mem_size
-.globl get_mem_size_ret
-get_mem_size_ret:
+	/* Set Boot Flags in Global Data */
+	movl	%ebx, (GD_FLAGS * 4)(%ebp)
 
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-	/* Skip ECC initialization if not starting from cold-reset */
-	movl	%ebx, %ecx
-	andl	$GD_FLG_COLD_BOOT, %ecx
-	jz	init_ecc_ret
-	jmp	init_ecc
-
-.globl init_ecc_ret
-init_ecc_ret:
-#endif
-
-	/* Check we have enough memory for stack */
-	movl	$CONFIG_SYS_STACK_SIZE, %ecx
-	cmpl	%ecx, %eax
-	jb	die
-mem_ok:
-	/* Set stack pointer to upper memory limit*/
-	movl	%eax, %esp
-
-	/* Test the stack */
-	pushl	$0
-	popl	%ecx
-	cmpl	$0, %ecx
-	jne	die
-	push	$0x55aa55aa
-	popl	%ecx
-	cmpl	$0x55aa55aa, %ecx
-	jne	die
-
-	wbinvd
-
-	/* Determine our load offset */
+	/* Determine our load offset (and put in Global Data) */
 	call	1f
 1:	popl	%ecx
 	subl	$1b, %ecx
+	movl	%ecx, (GD_LOAD_OFF * 4)(%ebp)
 
-	/* Set the upper memory limit parameter */
-	subl	$CONFIG_SYS_STACK_SIZE, %eax
-
-	/* Reserve space for global data */
-	subl	$(GD_SIZE * 4), %eax
-
-	/* %eax points to the global data structure */
-	movl	%esp, (GD_RAM_SIZE * 4)(%eax)
-	movl	%ebx, (GD_FLAGS * 4)(%eax)
-	movl	%ecx, (GD_LOAD_OFF * 4)(%eax)
+	/* Set parameter to board_init_f() to boot flags */
+	movl	(GD_FLAGS * 4)(%ebp), %eax
 
 	call	board_init_f	/* Enter, U-boot! */
 
 	/* indicate (lack of) progress */
 	movw	$0x85, %ax
+	jmp	die
+
+.globl relocate_code
+.type relocate_code, @function
+relocate_code:
+	/*
+	 * SDRAM has been initialised, U-Boot code has been copied into
+	 * RAM, BSS has been cleared and relocation adjustments have been
+	 * made. It is now time to jump into the in-RAM copy of U-Boot
+	 *
+	 * %eax = Address of top of stack
+	 * %edx = Address of Global Data
+	 * %ecx = Base address of in-RAM copy of U-Boot
+	 */
+
+	/* Setup stack in RAM */
+	movl	%eax, %esp
+
+	/* Setup call address of in-RAM copy of board_init_r() */
+	movl	$board_init_r, %ebp
+	addl	(GD_RELOC_OFF * 4)(%edx), %ebp
+
+	/* Setup parameters to board_init_r() */
+	movl	%edx, %eax
+	movl	%ecx, %edx
+
+	/* Jump to in-RAM copy of board_init_r() */
+	call	*%ebp
+
 die:	hlt
 	jmp	die
 	hlt

arch/i386/cpu/start16.S

@@ -23,6 +23,7 @@
  */
 
 #include <asm/global_data.h>
+#include <asm/processor-flags.h>
 
 #define BOOT_SEG	0xffff0000	/* linear segment of boot code */
 #define a32		.byte 0x67;
@@ -45,7 +46,7 @@ board_init16_ret:
 
 	/* Turn of cache (this might require a 486-class CPU) */
 	movl	%cr0, %eax
-	orl	$0x60000000, %eax
+	orl	$(X86_CR0_NW & X86_CR0_CD), %eax
 	movl	%eax, %cr0
 	wbinvd
 
@@ -55,7 +56,7 @@ o32 cs	lgdt	gdt_ptr
 
 	/* Now, we enter protected mode */
 	movl	%cr0, %eax
-	orl	$1, %eax
+	orl	$X86_CR0_PE, %eax
 	movl	%eax, %cr0
 
 	/* Flush the prefetch queue */

arch/i386/cpu/u-boot.lds

@@ -73,7 +73,7 @@ SECTIONS
 	/DISCARD/ : { *(.gnu*) }
 
 	/* 16bit realmode trampoline code */
-	.realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
+	.realmode REALMODE_BASE : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
 
 	__realmode_start = LOADADDR(.realmode);
 	__realmode_size = SIZEOF(.realmode);
@@ -84,21 +84,13 @@ SECTIONS
 	__bios_start = LOADADDR(.bios);
 	__bios_size = SIZEOF(.bios);
 
-	/* The load addresses below assumes that the flash
-	 * will be mapped so that 0x387f0000 == 0xffff0000
-	 * at reset time
-	 *
-	 * The fe00 and ff00 offsets of the start32 and start16
-	 * segments are arbitrary, the just have to be mapped
-	 * at reset and the code have to fit.
-	 * The fff0 offset of resetvec is important, however.
+	/*
+	 * The following expressions place the 16-bit Real-Mode code and
+	 * Reset Vector at the end of the Flash ROM
 	 */
-	. = 0xfffffe00;
-	.start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
+	. = START_16;
+	.start16 : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); }
 
-	. = 0xf800;
-	.start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
-
-	. = 0xfff0;
-	.resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
+	. = RESET_VEC_LOC;
+	.resetvec : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
 }

arch/i386/include/asm/global_data.h

@@ -35,7 +35,7 @@
 
 #ifndef __ASSEMBLY__
 
-typedef	struct {
+typedef	struct global_data {
 	bd_t		*bd;
 	unsigned long	flags;
 	unsigned long	baudrate;
@@ -46,6 +46,8 @@ typedef	struct {
 	unsigned long	env_valid;	/* Checksum of Environment valid? */
 	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
 	unsigned long	bus_clk;
+	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
+	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
 	phys_size_t	ram_size;	/* RAM size */
 	unsigned long	reset_status;	/* reset status register at boot */
 	void		**jt;		/* jump table */
@@ -67,11 +69,13 @@ extern gd_t *gd;
 #define GD_ENV_VALID	7
 #define GD_CPU_CLK	8
 #define GD_BUS_CLK	9
-#define GD_RAM_SIZE	10
-#define GD_RESET_STATUS	11
-#define GD_JT		12
+#define GD_RELOC_ADDR	10
+#define GD_START_ADDR_SP	11
+#define GD_RAM_SIZE	12
+#define GD_RESET_STATUS	13
+#define GD_JT		14
 
-#define GD_SIZE		13
+#define GD_SIZE		15
 
 /*
  * Global Data Flags
@@ -87,7 +91,12 @@ extern gd_t *gd;
 #define GD_FLG_COLD_BOOT	0x00100	/* Cold Boot */
 #define GD_FLG_WARM_BOOT	0x00200	/* Warm Boot */
 
-
+#if 0
 #define DECLARE_GLOBAL_DATA_PTR
+#else
+#define XTRN_DECLARE_GLOBAL_DATA_PTR    extern
+#define DECLARE_GLOBAL_DATA_PTR     XTRN_DECLARE_GLOBAL_DATA_PTR \
+gd_t *gd
+#endif
 
 #endif /* __ASM_GBL_DATA_H */

arch/i386/include/asm/ic/sc520.h

@@ -252,16 +252,68 @@ typedef struct sc520_mmcr {
 	u8  pad_0xdc0[0x0240];
 } sc520_mmcr_t;
 
-extern volatile sc520_mmcr_t *sc520_mmcr;
+extern sc520_mmcr_t *sc520_mmcr;
 
 #endif
 
-/* MMCR Offsets (required for assembler code */
-#define SC520_DBCTL		0x0040	/* SDRAM Buffer Control Register */
-#define SC520_PAR14		0x00c0	/* Programmable Address Region 14 Register */
-#define SC520_PAR15		0x00c4	/* Programmable Address Region 15 Register */
-#define SC520_SWTMRMILLI	0x0c60  /* Software Timer Millisecond Count */
-#define SC520_SWTMRMICRO	0x0c62  /* Software Timer Microsecond Count */
+/* Memory Mapped Control Registers (MMCR) Base Address */
+#define SC520_MMCR_BASE		0xfffef000
+
+/* MMCR Addresses (required for assembler code) */
+#define SC520_DRCCTL		(SC520_MMCR_BASE + 0x010)
+#define SC520_DRCTMCTL		(SC520_MMCR_BASE + 0x012)
+#define SC520_DRCCFG		(SC520_MMCR_BASE + 0x014)
+#define SC520_DRCBENDADR	(SC520_MMCR_BASE + 0x018)
+#define SC520_ECCCTL		(SC520_MMCR_BASE + 0x020)
+#define SC520_DBCTL		(SC520_MMCR_BASE + 0x040)
+#define SC520_ECCINT		(SC520_MMCR_BASE + 0xd18)
+
+#define SC520_PAR0		(SC520_MMCR_BASE + 0x088)
+#define SC520_PAR1		(SC520_PAR0 + (0x04 * 1))
+#define SC520_PAR2		(SC520_PAR0 + (0x04 * 2))
+#define SC520_PAR3		(SC520_PAR0 + (0x04 * 3))
+#define SC520_PAR4		(SC520_PAR0 + (0x04 * 4))
+#define SC520_PAR5		(SC520_PAR0 + (0x04 * 5))
+#define SC520_PAR6		(SC520_PAR0 + (0x04 * 6))
+#define SC520_PAR7		(SC520_PAR0 + (0x04 * 7))
+#define SC520_PAR8		(SC520_PAR0 + (0x04 * 8))
+#define SC520_PAR9		(SC520_PAR0 + (0x04 * 9))
+#define SC520_PAR10		(SC520_PAR0 + (0x04 * 10))
+#define SC520_PAR11		(SC520_PAR0 + (0x04 * 11))
+#define SC520_PAR12		(SC520_PAR0 + (0x04 * 12))
+#define SC520_PAR13		(SC520_PAR0 + (0x04 * 13))
+#define SC520_PAR14		(SC520_PAR0 + (0x04 * 14))
+#define SC520_PAR15		(SC520_PAR0 + (0x04 * 15))
+
+/*
+ * PARs for maximum allowable 256MB of SDRAM @ 0x00000000
+ * Two PARs are required due to maximum PAR size of 128MB
+ * These are used in the SDRAM sizing code to disable caching
+ *
+ * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
+ * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
+ * \ / | | | | \----+----/ \-----+------/
+ *  |  | | | |      |            +---------- Start at 0x00000000
+ *  |  | | | |      |                                 0x08000000
+ *  |  | | | |      +----------------------- 128MB Region Size
+ *  |  | | | |                               ((2047 + 1) * 64kB)
+ *  |  | | | +------------------------------ 64kB Page Size
+ *  |  | | +-------------------------------- Writes Enabled
+ *  |  | +---------------------------------- Caching Enabled
+ *  |  +------------------------------------ Execution Enabled
+ *  +--------------------------------------- SDRAM
+ */
+#define SC520_SDRAM1_PAR	0xe3ffc000
+#define SC520_SDRAM2_PAR	0xe3ffc800
+
+#define SC520_PAR_WRITE_DIS	0x04000000
+#define SC520_PAR_CACHE_DIS	0x08000000
+#define SC520_PAR_EXEC_DIS	0x10000000
+
+/*
+ * Programmable Address Regions to cover 256MB SDRAM (Maximum supported)
+ * required for DRAM sizing code
+ */
 
 /* MMCR Register bits (not all of them :) ) */
 
@@ -293,6 +345,33 @@ extern volatile sc520_mmcr_t *sc520_mmcr;
 #define UART2_DIS		0x02	/* UART2 Disable */
 #define UART1_DIS		0x01	/* UART1 Disable */
 
+/*
+ * Defines used for SDRAM Sizing (number of columns and rows)
+ * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the
+ * Elan SC520 Microcontroller User's Manual (Order #22004B)
+ */
+#define CACHELINESZ		0x00000010
+
+#define COL11_ADR		0x0e001e00
+#define COL10_ADR		0x0e000e00
+#define COL09_ADR		0x0e000600
+#define COL08_ADR		0x0e000200
+#define COL11_DATA		0x0b0b0b0b
+#define COL10_DATA		0x0a0a0a0a
+#define COL09_DATA		0x09090909
+#define COL08_DATA		0x08080808
+
+#define ROW14_ADR		0x0f000000
+#define ROW13_ADR		0x07000000
+#define ROW12_ADR		0x03000000
+#define ROW11_ADR		0x01000000
+#define ROW10_ADR		0x00000000
+#define ROW14_DATA		0x3f3f3f3f
+#define ROW13_DATA		0x1f1f1f1f
+#define ROW12_DATA		0x0f0f0f0f
+#define ROW11_DATA		0x07070707
+#define ROW10_DATA		0xaaaaaaaa
+
 /* 0x28000000 - 0x3fffffff is used by the flash banks */
 
 /* 0x40000000 - 0xffffffff is not adressable by the SC520 */

arch/i386/include/asm/processor-flags.h

@@ -0,0 +1,100 @@
+#ifndef _ASM_X86_PROCESSOR_FLAGS_H
+#define _ASM_X86_PROCESSOR_FLAGS_H
+/* Various flags defined: can be included from assembler. */
+
+/*
+ * EFLAGS bits
+ */
+#define X86_EFLAGS_CF	0x00000001 /* Carry Flag */
+#define X86_EFLAGS_PF	0x00000004 /* Parity Flag */
+#define X86_EFLAGS_AF	0x00000010 /* Auxillary carry Flag */
+#define X86_EFLAGS_ZF	0x00000040 /* Zero Flag */
+#define X86_EFLAGS_SF	0x00000080 /* Sign Flag */
+#define X86_EFLAGS_TF	0x00000100 /* Trap Flag */
+#define X86_EFLAGS_IF	0x00000200 /* Interrupt Flag */
+#define X86_EFLAGS_DF	0x00000400 /* Direction Flag */
+#define X86_EFLAGS_OF	0x00000800 /* Overflow Flag */
+#define X86_EFLAGS_IOPL	0x00003000 /* IOPL mask */
+#define X86_EFLAGS_NT	0x00004000 /* Nested Task */
+#define X86_EFLAGS_RF	0x00010000 /* Resume Flag */
+#define X86_EFLAGS_VM	0x00020000 /* Virtual Mode */
+#define X86_EFLAGS_AC	0x00040000 /* Alignment Check */
+#define X86_EFLAGS_VIF	0x00080000 /* Virtual Interrupt Flag */
+#define X86_EFLAGS_VIP	0x00100000 /* Virtual Interrupt Pending */
+#define X86_EFLAGS_ID	0x00200000 /* CPUID detection flag */
+
+/*
+ * Basic CPU control in CR0
+ */
+#define X86_CR0_PE	0x00000001 /* Protection Enable */
+#define X86_CR0_MP	0x00000002 /* Monitor Coprocessor */
+#define X86_CR0_EM	0x00000004 /* Emulation */
+#define X86_CR0_TS	0x00000008 /* Task Switched */
+#define X86_CR0_ET	0x00000010 /* Extension Type */
+#define X86_CR0_NE	0x00000020 /* Numeric Error */
+#define X86_CR0_WP	0x00010000 /* Write Protect */
+#define X86_CR0_AM	0x00040000 /* Alignment Mask */
+#define X86_CR0_NW	0x20000000 /* Not Write-through */
+#define X86_CR0_CD	0x40000000 /* Cache Disable */
+#define X86_CR0_PG	0x80000000 /* Paging */
+
+/*
+ * Paging options in CR3
+ */
+#define X86_CR3_PWT	0x00000008 /* Page Write Through */
+#define X86_CR3_PCD	0x00000010 /* Page Cache Disable */
+
+/*
+ * Intel CPU features in CR4
+ */
+#define X86_CR4_VME	0x00000001 /* enable vm86 extensions */
+#define X86_CR4_PVI	0x00000002 /* virtual interrupts flag enable */
+#define X86_CR4_TSD	0x00000004 /* disable time stamp at ipl 3 */
+#define X86_CR4_DE	0x00000008 /* enable debugging extensions */
+#define X86_CR4_PSE	0x00000010 /* enable page size extensions */
+#define X86_CR4_PAE	0x00000020 /* enable physical address extensions */
+#define X86_CR4_MCE	0x00000040 /* Machine check enable */
+#define X86_CR4_PGE	0x00000080 /* enable global pages */
+#define X86_CR4_PCE	0x00000100 /* enable performance counters at ipl 3 */
+#define X86_CR4_OSFXSR	0x00000200 /* enable fast FPU save and restore */
+#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+#define X86_CR4_VMXE	0x00002000 /* enable VMX virtualization */
+#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
+
+/*
+ * x86-64 Task Priority Register, CR8
+ */
+#define X86_CR8_TPR	0x0000000F /* task priority register */
+
+/*
+ * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
+ */
+
+/*
+ *      NSC/Cyrix CPU configuration register indexes
+ */
+#define CX86_PCR0	0x20
+#define CX86_GCR	0xb8
+#define CX86_CCR0	0xc0
+#define CX86_CCR1	0xc1
+#define CX86_CCR2	0xc2
+#define CX86_CCR3	0xc3
+#define CX86_CCR4	0xe8
+#define CX86_CCR5	0xe9
+#define CX86_CCR6	0xea
+#define CX86_CCR7	0xeb
+#define CX86_PCR1	0xf0
+#define CX86_DIR0	0xfe
+#define CX86_DIR1	0xff
+#define CX86_ARR_BASE	0xc4
+#define CX86_RCR_BASE	0xdc
+
+#ifdef __KERNEL__
+#ifdef CONFIG_VM86
+#define X86_VM_MASK	X86_EFLAGS_VM
+#else
+#define X86_VM_MASK	0 /* No VM86 support */
+#endif
+#endif
+
+#endif /* _ASM_X86_PROCESSOR_FLAGS_H */

arch/i386/include/asm/processor.h

@@ -23,7 +23,10 @@
 
 #ifndef __ASM_PROCESSOR_H_
 #define __ASM_PROCESSOR_H_ 1
-/* Currently this header is unused in the i386 port
- * but some generic files #include <asm/processor.h>
- * so this file is a placeholder. */
+
+#define GDT_ENTRY_32BIT_CS	2
+#define GDT_ENTRY_32BIT_DS	(GDT_ENTRY_32BIT_CS + 1)
+#define GDT_ENTRY_16BIT_CS	(GDT_ENTRY_32BIT_DS + 1)
+#define GDT_ENTRY_16BIT_DS	(GDT_ENTRY_16BIT_CS + 1)
+
 #endif

arch/i386/include/asm/u-boot-i386.h

@@ -25,7 +25,9 @@
 #define _U_BOOT_I386_H_	1
 
 /* cpu/.../cpu.c */
+int x86_cpu_init_r(void);
 int cpu_init_r(void);
+int x86_cpu_init_f(void);
 int cpu_init_f(void);
 
 /* cpu/.../timer.c */
@@ -35,6 +37,7 @@ int register_timer_isr (timer_fnc_t *isr_func);
 
 /* Architecture specific - can be in arch/i386/cpu/, arch/i386/lib/, or $(BOARD)/ */
 int timer_init(void);
+int dram_init_f(void);
 
 /* cpu/.../interrupts.c */
 int cpu_init_interrupts(void);

arch/i386/lib/board.c

@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Daniel Engstr<74>m, Omicron Ceti AB, daniel@omicron.se
+ * Daniel Engstr<74>m, Omicron Ceti AB, daniel@omicron.se
  *
  * (C) Copyright 2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -45,7 +45,15 @@
 #include <miiphy.h>
 #endif
 
-DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Pointer to initial global data area
+ *
+ * Here we initialize it.
+ */
+#undef	XTRN_DECLARE_GLOBAL_DATA_PTR
+#define XTRN_DECLARE_GLOBAL_DATA_PTR	/* empty = allocate here */
+DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
+
 
 /* Exports from the Linker Script */
 extern ulong __text_start;
@@ -148,15 +156,33 @@ static void display_flash_config (ulong size)
  */
 typedef int (init_fnc_t) (void);
 
-init_fnc_t *init_sequence[] = {
+static int calculate_relocation_address(void);
+static int copy_uboot_to_ram(void);
+static int clear_bss(void);
+static int do_elf_reloc_fixups(void);
+
+init_fnc_t *init_sequence_f[] = {
+	cpu_init_f,
+	board_early_init_f,
+	env_init,
+	init_baudrate,
+	serial_init,
+	console_init_f,
+	dram_init_f,
+	calculate_relocation_address,
+	copy_uboot_to_ram,
+	clear_bss,
+	do_elf_reloc_fixups,
+
+	NULL,
+};
+
+init_fnc_t *init_sequence_r[] = {
 	cpu_init_r,		/* basic cpu dependent setup */
 	board_early_init_r,	/* basic board dependent setup */
 	dram_init,		/* configure available RAM banks */
 	interrupt_init,		/* set up exceptions */
 	timer_init,
-	env_init,		/* initialize environment */
-	init_baudrate,		/* initialze baudrate settings */
-	serial_init,		/* serial communications setup */
 	display_banner,
 	display_dram_config,
 
@@ -165,88 +191,101 @@ init_fnc_t *init_sequence[] = {
 
 gd_t *gd;
 
-/*
- * Load U-Boot into RAM, initialize BSS, perform relocation adjustments
- */
-void board_init_f (ulong gdp)
+static int calculate_relocation_address(void)
 {
 	void *text_start = &__text_start;
-	void *data_end = &__data_end;
-	void *rel_dyn_start = &__rel_dyn_start;
-	void *rel_dyn_end = &__rel_dyn_end;
-	void *bss_start = &__bss_start;
 	void *bss_end = &__bss_end;
-
-	ulong *dst_addr;
-	ulong *src_addr;
-	ulong *end_addr;
-
 	void *dest_addr;
 	ulong rel_offset;
-	Elf32_Rel *re_src;
-	Elf32_Rel *re_end;
 
 	/* Calculate destination RAM Address and relocation offset */
-	dest_addr  = (void *)gdp - (bss_end - text_start);
-	rel_offset = text_start - dest_addr;
+	dest_addr = (void *)gd->ram_size;
+	dest_addr -= CONFIG_SYS_STACK_SIZE;
+	dest_addr -= (bss_end - text_start);
+	rel_offset = dest_addr - text_start;
 
-	/* Perform low-level initialization only when cold booted */
-	if (((gd_t *)gdp)->flags & GD_FLG_COLD_BOOT) {
-		/* First stage CPU initialization */
-		if (cpu_init_f() != 0)
-			hang();
+	gd->start_addr_sp = gd->ram_size;
+	gd->relocaddr = (ulong)dest_addr;
+	gd->reloc_off = rel_offset;
 
-		/* First stage Board initialization */
-		if (board_early_init_f() != 0)
-			hang();
-	}
+	return 0;
+}
 
-	/* Copy U-Boot into RAM */
-	dst_addr = (ulong *)dest_addr;
-	src_addr = (ulong *)(text_start + ((gd_t *)gdp)->load_off);
-	end_addr = (ulong *)(data_end  + ((gd_t *)gdp)->load_off);
+static int copy_uboot_to_ram(void)
+{
+	ulong *dst_addr = (ulong *)gd->relocaddr;
+	ulong *src_addr = (ulong *)&__text_start;
+	ulong *end_addr = (ulong *)&__data_end;
 
 	while (src_addr < end_addr)
 		*dst_addr++ = *src_addr++;
 
-	/* Clear BSS */
-	dst_addr = (ulong *)(bss_start - rel_offset);
-	end_addr = (ulong *)(bss_end - rel_offset);
+	return 0;
+}
+
+static int clear_bss(void)
+{
+	void *bss_start = &__bss_start;
+	void *bss_end = &__bss_end;
+
+	ulong *dst_addr = (ulong *)(bss_start + gd->reloc_off);
+	ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);;
 
 	while (dst_addr < end_addr)
 		*dst_addr++ = 0x00000000;
 
-	/* Perform relocation adjustments */
-	re_src = (Elf32_Rel *)(rel_dyn_start + ((gd_t *)gdp)->load_off);
-	re_end = (Elf32_Rel *)(rel_dyn_end + ((gd_t *)gdp)->load_off);
+	return 0;
+}
+
+static int do_elf_reloc_fixups(void)
+{
+	Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start);
+	Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);
 
 	do {
 		if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE)
-			if (*(Elf32_Addr *)(re_src->r_offset - rel_offset) >= CONFIG_SYS_TEXT_BASE)
-				*(Elf32_Addr *)(re_src->r_offset - rel_offset) -= rel_offset;
+			if (*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) >= CONFIG_SYS_TEXT_BASE)
+				*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) += gd->reloc_off;
 	} while (re_src++ < re_end);
 
-	((gd_t *)gdp)->reloc_off = rel_offset;
-	((gd_t *)gdp)->flags |= GD_FLG_RELOC;
+	return 0;
+}
+
+/*
+ * Load U-Boot into RAM, initialize BSS, perform relocation adjustments
+ */
+void board_init_f(ulong boot_flags)
+{
+	init_fnc_t **init_fnc_ptr;
+
+	for (init_fnc_ptr = init_sequence_f; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	gd->flags |= GD_FLG_RELOC;
 
 	/* Enter the relocated U-Boot! */
-	(board_init_r - rel_offset)((gd_t *)gdp, (ulong)dest_addr);
+	relocate_code(gd->start_addr_sp, gd, gd->relocaddr);
 
-	/* NOTREACHED - board_init_f() does not return */
+	/* NOTREACHED - relocate_code() does not return */
 	while(1);
 }
 
 void board_init_r(gd_t *id, ulong dest_addr)
 {
 	char *s;
-	int i;
 	ulong size;
 	static bd_t bd_data;
+	static gd_t gd_data;
 	init_fnc_t **init_fnc_ptr;
 
 	show_boot_progress(0x21);
 
-	gd = id;
+	/* Global data pointer is now writable */
+	gd = &gd_data;
+	memcpy(gd, id, sizeof(gd_t));
+
 	/* compiler optimization barrier needed for GCC >= 3.4 */
 	__asm__ __volatile__("": : :"memory");
 
@@ -259,12 +298,9 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	mem_malloc_init((((ulong)dest_addr - CONFIG_SYS_MALLOC_LEN)+3)&~3,
 			CONFIG_SYS_MALLOC_LEN);
 
-	for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) {
-		show_boot_progress(0xa130|i);
-
-		if ((*init_fnc_ptr)() != 0) {
+	for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
 			hang ();
-		}
 	}
 	show_boot_progress(0x23);
 

arch/i386/lib/realmode.c

@@ -27,7 +27,6 @@
 #include <asm/realmode.h>
 
 
-#define REALMODE_BASE    ((char*)0x7c0)
 #define REALMODE_MAILBOX ((char*)0xe00)
 
 
@@ -41,13 +40,14 @@ int realmode_setup(void)
 	ulong realmode_size = (ulong)&__realmode_size;
 
 	/* copy the realmode switch code */
-	if (realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) {
+	if (realmode_size > (REALMODE_MAILBOX - (char *)REALMODE_BASE)) {
 		printf("realmode switch too large (%ld bytes, max is %d)\n",
-		       realmode_size, (REALMODE_MAILBOX-REALMODE_BASE));
+		       realmode_size,
+		       (REALMODE_MAILBOX - (char *)REALMODE_BASE));
 		return -1;
 	}
 
-	memcpy(REALMODE_BASE, (void*)realmode_start, realmode_size);
+	memcpy((char *)REALMODE_BASE, (void *)realmode_start, realmode_size);
 	asm("wbinvd\n");
 
 	return 0;

arch/m68k/lib/board.c

@@ -76,7 +76,7 @@ static char *failed = "*** failed ***\n";
 #include <environment.h>
 
 extern ulong __init_end;
-extern ulong _end;
+extern ulong __bss_end__;
 
 extern	void timer_init(void);
 
@@ -252,7 +252,7 @@ board_init_f (ulong bootflag)
 	 *	- monitor code
 	 *	- board info struct
 	 */
-	len = (ulong)&_end - CONFIG_SYS_MONITOR_BASE;
+	len = (ulong)&__bss_end__ - CONFIG_SYS_MONITOR_BASE;
 
 	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
 

arch/microblaze/cpu/irq.S

@@ -60,7 +60,6 @@ _interrupt_handler:
 	addik	r1, r1, -124
 	brlid	r15, interrupt_handler
 	nop
-	nop
 	addik	r1, r1, 124
 	lwi	r31, r1, -120
 	lwi	r30, r1, -116
@@ -93,22 +92,6 @@ _interrupt_handler:
 	lwi	r3, r1, -8
 	lwi	r2, r1, -4
 
-	/* enable_interrupt */
-#ifdef XILINX_USE_MSR_INSTR
-	msrset	r0, 2
-#else
-	/* FIXME unstable in stressed mode - two irqs */
-	nop
-	addi	r1, r1, -4
-	swi	r12, r1, 0
-	mfs	r12, rmsr
-	ori	r12, r12, 2
-	mts	rmsr, r12
-	lwi	r12, r1, 0
-	addi	r1, r1, 4
-	nop
-#endif
-	bra	r14
-	nop
+	rtid	r14, 0
 	nop
 	.size _interrupt_handler,.-_interrupt_handler

arch/microblaze/include/asm/asm.h

@@ -62,7 +62,7 @@
 #define NOP	__asm__ __volatile__ ("nop");
 
 /* use machine status registe USE_MSR_REG */
-#ifdef XILINX_USE_MSR_INSTR
+#if XILINX_USE_MSR_INSTR == 1
 #define MSRSET(val) \
 	__asm__ __volatile__ ("msrset r0," #val );
 

arch/nios2/config.mk

@@ -31,5 +31,5 @@ PLATFORM_CPPFLAGS += -G0
 
 LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
 
-LDFLAGS_u-boot += --gc-sections
+LDFLAGS_FINAL += --gc-sections
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections

arch/nios2/cpu/start.S

@@ -100,12 +100,12 @@ _cur:	movhi	r5, %hi(_cur - _start)
 3:
 
 	/* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
-	 * and between __bss_start and _end.
+	 * and between __bss_start and __bss_end__.
 	 */
 	 movhi	r5, %hi(__bss_start)
 	 ori	r5, r5, %lo(__bss_start)
-	 movhi	r6, %hi(_end)
-	 ori	r6, r6, %lo(_end)
+	 movhi	r6, %hi(__bss_end__)
+	 ori	r6, r6, %lo(__bss_end__)
 	 beq	r5, r6, 5f
 
 4:	stwio	r0, 0(r5)

arch/nios2/cpu/u-boot.lds

@@ -103,7 +103,7 @@ SECTIONS
 	  *(.scommon)
 	}
 	. = ALIGN(4);
-	_end = .;
+	__bss_end__ = .;
 	PROVIDE (end = .);
 
 	/* DEBUG -- symbol table, string table, etc. etc.

arch/nios2/include/asm/gpio.h

@@ -26,6 +26,11 @@ static inline int gpio_request(unsigned gpio, const char *label)
 	return 0;
 }
 
+static inline int gpio_free(unsigned gpio)
+{
+	return 0;
+}
+
 static inline int gpio_direction_input(unsigned gpio)
 {
 	writel(1, CONFIG_SYS_GPIO_BASE + (gpio << 2));
@@ -47,12 +52,19 @@ static inline void gpio_set_value(unsigned gpio, int value)
 {
 	writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2));
 }
+
+static inline int gpio_is_valid(int number)
+{
+	return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH;
+}
 #else
 extern int gpio_request(unsigned gpio, const char *label);
+extern int gpio_free(unsigned gpio);
 extern int gpio_direction_input(unsigned gpio);
 extern int gpio_direction_output(unsigned gpio, int value);
 extern int gpio_get_value(unsigned gpio);
 extern void gpio_set_value(unsigned gpio, int value);
+extern int gpio_is_valid(int number);
 #endif /* CONFIG_SYS_GPIO_BASE */
 
 #endif /* _ASM_NIOS2_GPIO_H_ */

arch/nios2/include/asm/posix_types.h

@@ -17,7 +17,7 @@ typedef unsigned short	__kernel_ipc_pid_t;
 typedef unsigned short	__kernel_uid_t;
 typedef unsigned short	__kernel_gid_t;
 typedef unsigned long	__kernel_size_t;
-typedef int		__kernel_ssize_t;
+typedef long		__kernel_ssize_t;
 typedef int		__kernel_ptrdiff_t;
 typedef long		__kernel_time_t;
 typedef long		__kernel_suseconds_t;

arch/powerpc/config.mk

@@ -24,7 +24,7 @@
 CROSS_COMPILE ?= ppc_8xx-
 
 STANDALONE_LOAD_ADDR = 0x40000
-LDFLAGS_u-boot = --gc-sections
+LDFLAGS_FINAL += --gc-sections
 PLATFORM_RELFLAGS += -mrelocatable -ffunction-sections -fdata-sections
 PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
 PLATFORM_LDFLAGS  += -n

arch/powerpc/cpu/74xx_7xx/start.S

@@ -77,7 +77,7 @@
 	GOT_ENTRY(transfer_to_handler)
 
 	GOT_ENTRY(__init_end)
-	GOT_ENTRY(_end)
+	GOT_ENTRY(__bss_end__)
 	GOT_ENTRY(__bss_start)
 	END_GOT
 
@@ -722,7 +722,7 @@ in_ram:
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(__bss_start)
-	lwz	r4,GOT(_end)
+	lwz	r4,GOT(__bss_end__)
 
 	cmplw	0, r3, r4
 	beq	6f

arch/powerpc/cpu/74xx_7xx/u-boot.lds

@@ -87,6 +87,6 @@ SECTIONS
    *(COMMON)
    . = ALIGN(4);
   }
-  _end = . ;
+  __bss_end__ = . ;
   PROVIDE (end = .);
 }