Prepare v2011.09-rc2

Signed-off-by: Wolfgang Denk <wd@denx.de>

.gitignore

@@ -46,6 +46,7 @@
 
 /include/generated/
 /lib/asm-offsets.s
+/arch/*/cpu/asm-offsets.s
 
 # stgit generated dirs
 patches-*

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2011
 PATCHLEVEL = 09
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else

arch/arm/cpu/arm1176/start.S

@@ -358,7 +358,7 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 
 #ifndef CONFIG_NAND_SPL
 	bl coloured_LED_init
-	bl red_LED_on
+	bl red_led_on
 #endif
 #endif
 

arch/arm/cpu/arm720t/start.S

@@ -234,7 +234,7 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	bne	clbss_l
 
 	bl coloured_LED_init
-	bl red_LED_on
+	bl red_led_on
 #endif
 
 /*

arch/arm/cpu/arm920t/ep93xx/led.c

@@ -45,22 +45,22 @@ inline void switch_LED_off(uint8_t led)
 	saved_state[led] = STATUS_LED_OFF;
 }
 
-void red_LED_on(void)
+void red_led_on(void)
 {
 	switch_LED_on(STATUS_LED_RED);
 }
 
-void red_LED_off(void)
+void red_led_off(void)
 {
 	switch_LED_off(STATUS_LED_RED);
 }
 
-void green_LED_on(void)
+void green_led_on(void)
 {
 	switch_LED_on(STATUS_LED_GREEN);
 }
 
-void green_LED_off(void)
+void green_led_off(void)
 {
 	switch_LED_off(STATUS_LED_GREEN);
 }
@@ -74,14 +74,14 @@ void __led_toggle(led_id_t mask)
 {
 	if (STATUS_LED_RED == mask) {
 		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
-			red_LED_off();
+			red_led_off();
 		else
-			red_LED_on();
+			red_led_on();
 	} else if (STATUS_LED_GREEN == mask) {
 		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
-			green_LED_off();
+			green_led_off();
 		else
-			green_LED_on();
+			green_led_on();
 	}
 }
 
@@ -89,13 +89,13 @@ void __led_set(led_id_t mask, int state)
 {
 	if (STATUS_LED_RED == mask) {
 		if (STATUS_LED_ON == state)
-			red_LED_on();
+			red_led_on();
 		else
-			red_LED_off();
+			red_led_off();
 	} else if (STATUS_LED_GREEN == mask) {
 		if (STATUS_LED_ON == state)
-			green_LED_on();
+			green_led_on();
 		else
-			green_LED_off();
+			green_led_off();
 	}
 }

arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S

@@ -34,8 +34,8 @@ lowlevel_init:
 	str lr, [r1]
 
 	/* Turn on both LEDs */
-	bl red_LED_on
-	bl green_LED_on
+	bl red_led_on
+	bl green_led_on
 
 	/* Configure flash wait states before we switch to the PLL */
 	bl flash_cfg
@@ -44,14 +44,14 @@ lowlevel_init:
 	bl pll_cfg
 
 	/* Turn off the Green LED and leave the Red LED on */
-	bl green_LED_off
+	bl green_led_off
 
 	/* Setup SDRAM */
 	bl sdram_cfg
 
 	/* Turn on Green LED, Turn off the Red LED */
-	bl green_LED_on
-	bl red_LED_off
+	bl green_led_on
+	bl red_led_off
 
 	/* FIXME: we use async mode for now */
 	mrc p15, 0, r0, c1, c0, 0

arch/arm/cpu/arm920t/start.S

@@ -277,7 +277,7 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	bne	clbss_l
 
 	bl coloured_LED_init
-	bl red_LED_on
+	bl red_led_on
 #endif
 
 /*

arch/arm/cpu/arm925t/start.S

@@ -271,7 +271,7 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	bne	clbss_l
 
 	bl coloured_LED_init
-	bl red_LED_on
+	bl red_led_on
 #endif
 
 /*

arch/arm/cpu/arm926ejs/at91/led.c

@@ -29,36 +29,36 @@
 #include <asm/arch/gpio.h>
 
 #ifdef CONFIG_RED_LED
-void red_LED_on(void)
+void red_led_on(void)
 {
 	at91_set_gpio_value(CONFIG_RED_LED, 1);
 }
 
-void red_LED_off(void)
+void red_led_off(void)
 {
 	at91_set_gpio_value(CONFIG_RED_LED, 0);
 }
 #endif
 
 #ifdef CONFIG_GREEN_LED
-void green_LED_on(void)
+void green_led_on(void)
 {
 	at91_set_gpio_value(CONFIG_GREEN_LED, 0);
 }
 
-void green_LED_off(void)
+void green_led_off(void)
 {
 	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
 }
 #endif
 
 #ifdef CONFIG_YELLOW_LED
-void yellow_LED_on(void)
+void yellow_led_on(void)
 {
 	at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
 }
 
-void yellow_LED_off(void)
+void yellow_led_off(void)
 {
 	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
 }

arch/arm/cpu/arm926ejs/start.S

@@ -270,7 +270,7 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	bne	clbss_l
 
 	bl coloured_LED_init
-	bl red_LED_on
+	bl red_led_on
 #endif
 
 /*

arch/arm/cpu/arm_intcm/start.S

@@ -238,7 +238,7 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	bne	clbss_l
 
 	bl coloured_LED_init
-	bl red_LED_on
+	bl red_led_on
 #endif
 
 /*

arch/arm/cpu/armv7/omap-common/gpio.c

@@ -40,6 +40,9 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 
+#define OMAP_GPIO_DIR_OUT	0
+#define OMAP_GPIO_DIR_IN	1
+
 static inline const struct gpio_bank *get_gpio_bank(int gpio)
 {
 	return &omap_gpio_bank[gpio >> 5];
@@ -53,17 +56,17 @@ static inline int get_gpio_index(int gpio)
 static inline int gpio_valid(int gpio)
 {
 	if (gpio < 0)
-		return -1;
+		return -EINVAL;
 	if (gpio < 192)
 		return 0;
-	return -1;
+	return -EINVAL;
 }
 
 static int check_gpio(int gpio)
 {
 	if (gpio_valid(gpio) < 0) {
 		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
-		return -1;
+		return -EINVAL;
 	}
 	return 0;
 }
@@ -89,14 +92,29 @@ static void _set_gpio_direction(const struct gpio_bank *bank, int gpio,
 	__raw_writel(l, reg);
 }
 
-void omap_set_gpio_direction(int gpio, int is_input)
+/**
+ * Get the direction of the GPIO by reading the GPIO_OE register
+ * corresponding to the specified bank.
+ */
+static int _get_gpio_direction(const struct gpio_bank *bank, int gpio)
 {
-	const struct gpio_bank *bank;
+	void *reg = bank->base;
+	u32 v;
 
-	if (check_gpio(gpio) < 0)
-		return;
-	bank = get_gpio_bank(gpio);
-	_set_gpio_direction(bank, get_gpio_index(gpio), is_input);
+	switch (bank->method) {
+	case METHOD_GPIO_24XX:
+		reg += OMAP_GPIO_OE;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	v = __raw_readl(reg);
+
+	if (v & (1 << gpio))
+		return OMAP_GPIO_DIR_IN;
+	else
+		return OMAP_GPIO_DIR_OUT;
 }
 
 static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio,
@@ -121,20 +139,27 @@ static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio,
 	__raw_writel(l, reg);
 }
 
-void omap_set_gpio_dataout(int gpio, int enable)
+/**
+ * Set value of the specified gpio
+ */
+void gpio_set_value(int gpio, int value)
 {
 	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
 		return;
 	bank = get_gpio_bank(gpio);
-	_set_gpio_dataout(bank, get_gpio_index(gpio), enable);
+	_set_gpio_dataout(bank, get_gpio_index(gpio), value);
 }
 
-int omap_get_gpio_datain(int gpio)
+/**
+ * Get value of the specified gpio
+ */
+int gpio_get_value(int gpio)
 {
 	const struct gpio_bank *bank;
 	void *reg;
+	int input;
 
 	if (check_gpio(gpio) < 0)
 		return -EINVAL;
@@ -142,7 +167,17 @@ int omap_get_gpio_datain(int gpio)
 	reg = bank->base;
 	switch (bank->method) {
 	case METHOD_GPIO_24XX:
-		reg += OMAP_GPIO_DATAIN;
+		input = _get_gpio_direction(bank, get_gpio_index(gpio));
+		switch (input) {
+		case OMAP_GPIO_DIR_IN:
+			reg += OMAP_GPIO_DATAIN;
+			break;
+		case OMAP_GPIO_DIR_OUT:
+			reg += OMAP_GPIO_DATAOUT;
+			break;
+		default:
+			return -EINVAL;
+		}
 		break;
 	default:
 		return -EINVAL;
@@ -151,12 +186,45 @@ int omap_get_gpio_datain(int gpio)
 			& (1 << get_gpio_index(gpio))) != 0;
 }
 
-static void _reset_gpio(const struct gpio_bank *bank, int gpio)
+/**
+ * Set gpio direction as input
+ */
+int gpio_direction_input(unsigned gpio)
 {
+	const struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return -EINVAL;
+
+	bank = get_gpio_bank(gpio);
 	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
+
+	return 0;
 }
 
-int omap_request_gpio(int gpio)
+/**
+ * Set gpio direction as output
+ */
+int gpio_direction_output(unsigned gpio, int value)
+{
+	const struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return -EINVAL;
+
+	bank = get_gpio_bank(gpio);
+	_set_gpio_dataout(bank, get_gpio_index(gpio), value);
+	_set_gpio_direction(bank, get_gpio_index(gpio), 0);
+
+	return 0;
+}
+
+/**
+ * Request a gpio before using it.
+ *
+ * NOTE: Argument 'label' is unused.
+ */
+int gpio_request(int gpio, const char *label)
 {
 	if (check_gpio(gpio) < 0)
 		return -EINVAL;
@@ -164,7 +232,10 @@ int omap_request_gpio(int gpio)
 	return 0;
 }
 
-void omap_free_gpio(int gpio)
+/**
+ * Reset and free the gpio after using it.
+ */
+void gpio_free(unsigned gpio)
 {
 	const struct gpio_bank *bank;
 
@@ -172,5 +243,5 @@ void omap_free_gpio(int gpio)
 		return;
 	bank = get_gpio_bank(gpio);
 
-	_reset_gpio(bank, gpio);
+	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
 }

arch/arm/cpu/armv7/omap3/sys_info.c

@@ -46,6 +46,12 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
 				"3.1.2"};
 #endif /* CONFIG_DISPLAY_CPUINFO */
 
+/* this is the revision table for 37xx CPUs */
+static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
+				"1.0",
+				"1.1",
+				"1.2"};
+
 /*****************************************************************
  * dieid_num_r(void) - read and set die ID
  *****************************************************************/
@@ -347,7 +353,12 @@ int print_cpuinfo (void)
 		sec_s = "?";
 	}
 
-	printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
+	if (CPU_OMAP36XX == get_cpu_family())
+		printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
+			cpu_family_s, cpu_s, sec_s,
+			rev_s_37xx[get_cpu_rev()], max_clk);
+	else
+		printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
 			cpu_family_s, cpu_s, sec_s,
 			rev_s[get_cpu_rev()], max_clk);
 

arch/arm/cpu/armv7/omap4/board.c

@@ -70,6 +70,67 @@ u32 omap_boot_mode(void)
 {
 	return omap4_boot_mode;
 }
+
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+static void do_io_settings(void)
+{
+	u32 lpddr2io;
+	struct control_lpddr2io_regs *lpddr2io_regs =
+		(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
+	struct omap4_sys_ctrl_regs *const ctrl =
+		(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+
+	u32 omap4_rev = omap_revision();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+	else
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
+
+	/* EMIF1 */
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+	/* No pull for GR10 as per hw team's recommendation */
+	writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+		&lpddr2io_regs->control_lpddr2io1_2);
+	writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
+
+	/* EMIF2 */
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+	/* No pull for GR10 as per hw team's recommendation */
+	writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+		&lpddr2io_regs->control_lpddr2io2_2);
+	writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
+
+	/*
+	 * Some of these settings (TRIM values) come from eFuse and are
+	 * in turn programmed in the eFuse at manufacturing time after
+	 * calibration of the device. Do the software over-ride only if
+	 * the device is not correctly trimmed
+	 */
+	if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
+
+		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+			&ctrl->control_ldosram_iva_voltage_ctrl);
+
+		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+			&ctrl->control_ldosram_mpu_voltage_ctrl);
+
+		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+			&ctrl->control_ldosram_core_voltage_ctrl);
+	}
+
+	if (!readl(&ctrl->control_efuse_1))
+		writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
+
+	if (!readl(&ctrl->control_efuse_2))
+		writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
+}
 #endif
 
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
@@ -197,6 +258,7 @@ void s_init(void)
 	set_mux_conf_regs();
 #ifdef CONFIG_SPL_BUILD
 	preloader_console_init();
+	do_io_settings();
 #endif
 	prcm_init();
 #ifdef CONFIG_SPL_BUILD

arch/arm/cpu/armv7/omap4/clocks.c

@@ -31,6 +31,7 @@
  */
 #include <common.h>
 #include <asm/omap_common.h>
+#include <asm/gpio.h>
 #include <asm/arch/clocks.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/utils.h>
@@ -481,8 +482,8 @@ static void do_scale_tps62361(u32 reg, u32 volt_mv)
 	 * VSEL1 is grounded on board. So the following selects
 	 * VSEL1 = 0 and VSEL0 = 1
 	 */
-	omap_set_gpio_direction(TPS62361_VSEL0_GPIO, 0);
-	omap_set_gpio_dataout(TPS62361_VSEL0_GPIO, 1);
+	gpio_direction_output(TPS62361_VSEL0_GPIO, 0);
+	gpio_set_value(TPS62361_VSEL0_GPIO, 1);
 
 	temp = TPS62361_I2C_SLAVE_ADDR |
 	    (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |

arch/arm/cpu/armv7/omap4/emif.c

@@ -963,10 +963,11 @@ static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
 	return 1;
 }
 
-static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
 			struct lpddr2_device_details *lpddr2_dev_details)
 {
 	u32 phy;
+	u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
 	if (!lpddr2_dev_details)
@@ -985,40 +986,6 @@ static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
 
 	return lpddr2_dev_details;
 }
-
-void emif_get_device_details(u32 emif_nr,
-		struct lpddr2_device_details *cs0_device_details,
-		struct lpddr2_device_details *cs1_device_details)
-{
-	u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
-
-	if (running_from_sdram()) {
-		/*
-		 * We can not do automatic discovery running from SDRAM
-		 * Most likely we came here by mistake. Indicate error
-		 * by returning NULL
-		 */
-		cs0_device_details = NULL;
-		cs1_device_details = NULL;
-	} else {
-		/*
-		 * Automatically find the device details:
-		 *
-		 * Reset the PHY after each call to get_lpddr2_details().
-		 * If there is nothing connected to a given chip select
-		 * (typically CS1) mode register reads will mess up with
-		 * the PHY state and subsequent initialization won't work.
-		 * PHY reset brings back PHY to a good state.
-		 */
-		cs0_device_details =
-		    get_lpddr2_details(base, CS0, cs0_device_details);
-		emif_reset_phy(base);
-
-		cs1_device_details =
-		    get_lpddr2_details(base, CS1, cs1_device_details);
-		emif_reset_phy(base);
-	}
-}
 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
 
 static void do_sdram_init(u32 base)
@@ -1051,10 +1018,12 @@ static void do_sdram_init(u32 base)
 	 * - Obtained from user otherwise
 	 */
 	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
-	emif_get_device_details(emif_nr, &cs0_dev_details,
-				&cs1_dev_details);
-	dev_details.cs0_device_details = &cs0_dev_details;
-	dev_details.cs1_device_details = &cs1_dev_details;
+	emif_reset_phy(base);
+	dev_details.cs0_device_details = emif_get_device_details(base, CS0,
+						&cs0_dev_details);
+	dev_details.cs1_device_details = emif_get_device_details(base, CS1,
+						&cs1_dev_details);
+	emif_reset_phy(base);
 
 	/* Return if no devices on this EMIF */
 	if (!dev_details.cs0_device_details &&
@@ -1094,30 +1063,6 @@ static void do_sdram_init(u32 base)
 	debug("<<do_sdram_init() %x\n", base);
 }
 
-void sdram_init_pads(void)
-{
-	u32 lpddr2io;
-	struct control_lpddr2io_regs *lpddr2io_regs =
-		(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
-	u32 omap4_rev = omap_revision();
-
-	if (omap4_rev == OMAP4430_ES1_0)
-		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
-	else if (omap4_rev == OMAP4430_ES2_0)
-		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
-	else
-		return;		/* Post ES2.1 reset values will work */
-
-	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
-	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
-	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
-	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
-	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
-	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
-
-	writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
-}
-
 static void emif_post_init_config(u32 base)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -1274,7 +1219,6 @@ void sdram_init(void)
 	debug("in_sdram = %d\n", in_sdram);
 
 	if (!in_sdram) {
-		sdram_init_pads();
 		bypass_dpll(&prcm->cm_clkmode_dpll_core);
 	}
 

arch/arm/cpu/armv7/omap4/sdram_elpida.c

@@ -141,24 +141,24 @@ static const struct lpddr2_device_details elpida_2G_S4_details = {
 	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
 };
 
-static void emif_get_device_details_sdp(u32 emif_nr,
-		struct lpddr2_device_details *cs0_device_details,
-		struct lpddr2_device_details *cs1_device_details)
+struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
 {
 	u32 omap_rev = omap_revision();
 
 	/* EMIF1 & EMIF2 have identical configuration */
-	*cs0_device_details = elpida_2G_S4_details;
-
-	if (omap_rev == OMAP4430_ES1_0)
-		cs1_device_details = NULL;
-	else
-		*cs1_device_details = elpida_2G_S4_details;
+	if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
+		/* Nothing connected on CS1 for ES1.0 */
+		return NULL;
+	} else {
+		/* In all other cases Elpida 2G device */
+		*lpddr2_dev_details = elpida_2G_S4_details;
+		return lpddr2_dev_details;
+	}
 }
 
-void emif_get_device_details(u32 emif_nr,
-		struct lpddr2_device_details *cs0_device_details,
-		struct lpddr2_device_details *cs1_device_details)
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
 	__attribute__((weak, alias("emif_get_device_details_sdp")));
 
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */

arch/arm/cpu/ixp/start.S

@@ -340,7 +340,7 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	bne	clbss_l
 
 	bl coloured_LED_init
-	bl red_LED_on
+	bl red_led_on
 #endif
 
 /*

arch/arm/cpu/s3c44b0/start.S

@@ -223,7 +223,7 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	bne	clbss_l
 
 	bl coloured_LED_init
-	bl red_LED_on
+	bl red_led_on
 #endif
 
 /*

arch/arm/include/asm/arch-omap3/omap3.h

@@ -191,6 +191,16 @@ struct gpio {
 #define CPU_3XX_ES312		7
 #define CPU_3XX_MAX_REV		8
 
+/*
+ * 37xx real hardware:
+ * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
+ */
+
+#define CPU_37XX_ES10		0
+#define CPU_37XX_ES11		1
+#define CPU_37XX_ES12		2
+#define CPU_37XX_MAX_REV	3
+
 #define CPU_3XX_ID_SHIFT	28
 
 #define WIDTH_8BIT		0x0000

arch/arm/include/asm/arch-omap4/emif.h

@@ -593,17 +593,6 @@ struct dmm_lisa_map_regs {
 	u32 dmm_lisa_map_3;
 };
 
-struct control_lpddr2io_regs {
-	u32 control_lpddr2io1_0;
-	u32 control_lpddr2io1_1;
-	u32 control_lpddr2io1_2;
-	u32 control_lpddr2io1_3;
-	u32 control_lpddr2io2_0;
-	u32 control_lpddr2io2_1;
-	u32 control_lpddr2io2_2;
-	u32 control_lpddr2io2_3;
-};
-
 #define CS0	0
 #define CS1	1
 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
@@ -823,13 +812,6 @@ struct control_lpddr2io_regs {
 /* MR16 value: refresh full array(no partial array self refresh) */
 #define MR16_REF_FULL_ARRAY	0
 
-/* LPDDR2 IO regs */
-#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
-#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
-
-/* CONTROL_EFUSE_2 */
-#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
-
 /*
  * Maximum number of entries we keep in our array of timing tables
  * We need not keep all the speed bins supported by the device
@@ -1029,9 +1011,8 @@ struct emif_regs {
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
 #else
-void emif_get_device_details(u32 emif_nr,
-		struct lpddr2_device_details *cs0_device_details,
-		struct lpddr2_device_details *cs1_device_details);
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details);
 void emif_get_device_timings(u32 emif_nr,
 		const struct lpddr2_device_timings **cs0_device_timings,
 		const struct lpddr2_device_timings **cs1_device_timings);

arch/arm/include/asm/arch-omap4/omap4.h

@@ -54,8 +54,6 @@
 /* LPDDR2 IO regs */
 #define LPDDR2_IO_REGS_BASE	0x4A100638
 
-#define CONTROL_EFUSE_2		0x4A100704
-
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE		0x4A002204
 
@@ -84,6 +82,9 @@
 /* GPMC */
 #define OMAP44XX_GPMC_BASE	0x50000000
 
+/* SYSTEM CONTROL MODULE */
+#define SYSCTRL_GENERAL_CORE_BASE	0x4A002000
+
 /*
  * Hardware Register Details
  */
@@ -108,6 +109,22 @@
 #define PRM_RSTCTRL		PRM_DEVICE_BASE
 #define PRM_RSTCTRL_RESET	0x01
 
+/* Control Module */
+#define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
+#define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
+#define CONTROL_EFUSE_1_OVERRIDE	0x1C4D0110
+#define CONTROL_EFUSE_2_OVERRIDE	0x00084000
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN	0x7C7C7C7C
+#define LPDDR2IO_GR10_WD_MASK				(3 << 17)
+#define CONTROL_LPDDR2IO_3_VAL		0xA0888C00
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
 #ifndef __ASSEMBLY__
 
 struct s32ktimer {
@@ -115,6 +132,30 @@ struct s32ktimer {
 	unsigned int s32k_cr;	/* 0x10 */
 };
 
+struct omap4_sys_ctrl_regs {
+	unsigned int pad1[129];
+	unsigned int control_id_code;			/* 0x4A002204 */
+	unsigned int pad11[22];
+	unsigned int control_std_fuse_opp_bgap;		/* 0x4a002260 */
+	unsigned int pad2[47];
+	unsigned int control_ldosram_iva_voltage_ctrl;	/* 0x4A002320 */
+	unsigned int control_ldosram_mpu_voltage_ctrl;	/* 0x4A002324 */
+	unsigned int control_ldosram_core_voltage_ctrl;	/* 0x4A002328 */
+	unsigned int pad3[260341];
+	unsigned int control_efuse_1;			/* 0x4A100700 */
+	unsigned int control_efuse_2;			/* 0x4A100704 */
+};
+
+struct control_lpddr2io_regs {
+	unsigned int control_lpddr2io1_0;
+	unsigned int control_lpddr2io1_1;
+	unsigned int control_lpddr2io1_2;
+	unsigned int control_lpddr2io1_3;
+	unsigned int control_lpddr2io2_0;
+	unsigned int control_lpddr2io2_1;
+	unsigned int control_lpddr2io2_2;
+	unsigned int control_lpddr2io2_3;
+};
 #endif /* __ASSEMBLY__ */
 
 /*

arch/arm/include/asm/omap_gpio.h

@@ -49,17 +49,4 @@ extern const struct gpio_bank *const omap_gpio_bank;
 
 #define METHOD_GPIO_24XX	4
 
-/* This is the interface */
-
-/* Request a gpio before using it */
-int omap_request_gpio(int gpio);
-/* Reset and free a gpio after using it */
-void omap_free_gpio(int gpio);
-/* Sets the gpio as input or output */
-void omap_set_gpio_direction(int gpio, int is_input);
-/* Set or clear a gpio output */
-void omap_set_gpio_dataout(int gpio, int enable);
-/* Get the value of a gpio input */
-int omap_get_gpio_datain(int gpio);
-
 #endif /* _GPIO_H_ */

arch/arm/lib/board.c

@@ -87,22 +87,22 @@ extern void rtl8019_get_enetaddr (uchar * addr);
 inline void __coloured_LED_init(void) {}
 void coloured_LED_init(void)
 	__attribute__((weak, alias("__coloured_LED_init")));
-inline void __red_LED_on(void) {}
-void red_LED_on(void) __attribute__((weak, alias("__red_LED_on")));
-inline void __red_LED_off(void) {}
-void red_LED_off(void) __attribute__((weak, alias("__red_LED_off")));
-inline void __green_LED_on(void) {}
-void green_LED_on(void) __attribute__((weak, alias("__green_LED_on")));
-inline void __green_LED_off(void) {}
-void green_LED_off(void) __attribute__((weak, alias("__green_LED_off")));
-inline void __yellow_LED_on(void) {}
-void yellow_LED_on(void) __attribute__((weak, alias("__yellow_LED_on")));
-inline void __yellow_LED_off(void) {}
-void yellow_LED_off(void) __attribute__((weak, alias("__yellow_LED_off")));
-inline void __blue_LED_on(void) {}
-void blue_LED_on(void) __attribute__((weak, alias("__blue_LED_on")));
-inline void __blue_LED_off(void) {}
-void blue_LED_off(void) __attribute__((weak, alias("__blue_LED_off")));
+inline void __red_led_on(void) {}
+void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
+inline void __red_led_off(void) {}
+void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
+inline void __green_led_on(void) {}
+void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
+inline void __green_led_off(void) {}
+void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
+inline void __yellow_led_on(void) {}
+void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
+inline void __yellow_led_off(void) {}
+void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
+inline void __blue_led_on(void) {}
+void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
+inline void __blue_led_off(void) {}
+void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
 
 /*
  ************************************************************************

arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

@@ -656,6 +656,13 @@ phys_size_t initdram(int board_type)
 	program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 #endif
 
+	/*
+	 * Flush the dcache before removing the TLB with caches
+	 * enabled. Otherwise this might lead to problems later on,
+	 * e.g. while booting Linux (as seen on ICON-440SPe).
+	 */
+	flush_dcache();
+
 	/*
 	 * Now after initialization (auto-calibration and ECC generation)
 	 * remove the TLB entries with caches enabled and program again with

arch/powerpc/include/asm/u-boot.h

@@ -132,7 +132,7 @@ typedef struct bd_info {
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	int		bi_phynum[4];           /* Determines phy mapping */
 	int		bi_phymode[4];          /* Determines phy mode */
-#elif defined(CONFIG_405EP) || defined(CONFIG_440)
+#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440)
 	int		bi_phynum[2];           /* Determines phy mapping */
 	int		bi_phymode[2];          /* Determines phy mode */
 #else

board/atmel/at91rm9200ek/led.c

@@ -36,37 +36,37 @@
 #define	YELLOW_LED	(1<<1)
 #define	RED_LED		(1<<2)
 
-void	green_LED_on(void)
+void	green_led_on(void)
 {
 	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(GREEN_LED, &pio->piob.codr);
 }
 
-void	 yellow_LED_on(void)
+void	 yellow_led_on(void)
 {
 	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(YELLOW_LED, &pio->piob.codr);
 }
 
-void	 red_LED_on(void)
+void	 red_led_on(void)
 {
 	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(RED_LED, &pio->piob.codr);
 }
 
-void	green_LED_off(void)
+void	green_led_off(void)
 {
 	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(GREEN_LED, &pio->piob.sodr);
 }
 
-void	yellow_LED_off(void)
+void	yellow_led_off(void)
 {
 	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(YELLOW_LED, &pio->piob.sodr);
 }
 
-void	red_LED_off(void)
+void	red_led_off(void)
 {
 	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 	writel(RED_LED, &pio->piob.sodr);

board/cm_t35/leds.c

@@ -20,26 +20,26 @@
  */
 #include <common.h>
 #include <status_led.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 
 static unsigned int leds[] = { GREEN_LED_GPIO };
 
 void __led_init(led_id_t mask, int state)
 {
-	if (omap_request_gpio(leds[mask]) != 0) {
+	if (gpio_request(leds[mask], "") != 0) {
 		printf("%s: failed requesting GPIO%u\n", __func__, leds[mask]);
 		return;
 	}
 
-	omap_set_gpio_direction(leds[mask], 0);
+	gpio_direction_output(leds[mask], 0);
 }
 
 void __led_set(led_id_t mask, int state)
 {
-	omap_set_gpio_dataout(leds[mask], state == STATUS_LED_ON);
+	gpio_set_value(leds[mask], state == STATUS_LED_ON);
 }
 
 void __led_toggle(led_id_t mask)
 {
-	omap_set_gpio_dataout(leds[mask], !omap_get_gpio_datain(leds[mask]));
+	gpio_set_value(leds[mask], !gpio_get_value(leds[mask]));
 }

board/comelit/dig297/dig297.c

@@ -42,7 +42,7 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/mach-types.h>
 #include "dig297.h"
 
@@ -177,13 +177,13 @@ static void setup_net_chip(void)
 	       &ctrl_base->gpmc_nadv_ale);
 
 	/* Make GPIO 12 as output pin and send a magic pulse through it */
-	if (!omap_request_gpio(NET_LAN9221_RESET_GPIO)) {
-		omap_set_gpio_direction(NET_LAN9221_RESET_GPIO, 0);
-		omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 1);
+	if (!gpio_request(NET_LAN9221_RESET_GPIO, "")) {
+		gpio_direction_output(NET_LAN9221_RESET_GPIO, 0);
+		gpio_set_value(NET_LAN9221_RESET_GPIO, 1);
 		udelay(1);
-		omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 0);
+		gpio_set_value(NET_LAN9221_RESET_GPIO, 0);
 		udelay(31000);	/* Should be >= 30ms according to datasheet */
-		omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 1);
+		gpio_set_value(NET_LAN9221_RESET_GPIO, 1);
 	}
 }
 #endif /* CONFIG_CMD_NET */

board/eukrea/cpu9260/led.c

@@ -51,49 +51,49 @@ void coloured_LED_init(void)
 	at91_set_pio_value(CONFIG_BLUE_LED, 1);
 }
 
-void red_LED_off(void)
+void red_led_off(void)
 {
 	at91_set_pio_value(CONFIG_RED_LED, 1);
 	saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
 }
 
-void green_LED_off(void)
+void green_led_off(void)
 {
 	at91_set_pio_value(CONFIG_GREEN_LED, 1);
 	saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
 }
 
-void yellow_LED_off(void)
+void yellow_led_off(void)
 {
 	at91_set_pio_value(CONFIG_YELLOW_LED, 1);
 	saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
 }
 
-void blue_LED_off(void)
+void blue_led_off(void)
 {
 	at91_set_pio_value(CONFIG_BLUE_LED, 1);
 	saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
 }
 
-void red_LED_on(void)
+void red_led_on(void)
 {
 	at91_set_pio_value(CONFIG_RED_LED, 0);
 	saved_state[STATUS_LED_RED] = STATUS_LED_ON;
 }
 
-void green_LED_on(void)
+void green_led_on(void)
 {
 	at91_set_pio_value(CONFIG_GREEN_LED, 0);
 	saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
 }
 
-void yellow_LED_on(void)
+void yellow_led_on(void)
 {
 	at91_set_pio_value(CONFIG_YELLOW_LED, 0);
 	saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
 }
 
-void blue_LED_on(void)
+void blue_led_on(void)
 {
 	at91_set_pio_value(CONFIG_BLUE_LED, 0);
 	saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
@@ -108,24 +108,24 @@ void __led_toggle(led_id_t mask)
 {
 	if (STATUS_LED_BLUE == mask) {
 		if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
-			blue_LED_off();
+			blue_led_off();
 		else
-			blue_LED_on();
+			blue_led_on();
 	} else if (STATUS_LED_RED == mask) {
 		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
-			red_LED_off();
+			red_led_off();
 		else
-			red_LED_on();
+			red_led_on();
 	} else if (STATUS_LED_GREEN == mask) {
 		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
-			green_LED_off();
+			green_led_off();
 		else
-			green_LED_on();
+			green_led_on();
 	} else if (STATUS_LED_YELLOW == mask) {
 		if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
-			yellow_LED_off();
+			yellow_led_off();
 		else
-			yellow_LED_on();
+			yellow_led_on();
 	}
 }
 
@@ -133,23 +133,23 @@ void __led_set(led_id_t mask, int state)
 {
 	if (STATUS_LED_BLUE == mask) {
 		if (STATUS_LED_ON == state)
-			blue_LED_on();
+			blue_led_on();
 		else
-			blue_LED_off();
+			blue_led_off();
 	} else if (STATUS_LED_RED == mask) {
 		if (STATUS_LED_ON == state)
-			red_LED_on();
+			red_led_on();
 		else
-			red_LED_off();
+			red_led_off();
 	} else if (STATUS_LED_GREEN == mask) {
 		if (STATUS_LED_ON == state)
-			green_LED_on();
+			green_led_on();
 		else
-			green_LED_off();
+			green_led_off();
 	} else if (STATUS_LED_YELLOW == mask) {
 		if (STATUS_LED_ON == state)
-			yellow_LED_on();
+			yellow_led_on();
 		else
-			yellow_LED_off();
+			yellow_led_off();
 	}
 }

board/isee/igep0020/igep0020.c

@@ -24,7 +24,7 @@
 #include <netdev.h>
 #include <twl4030.h>
 #include <asm/io.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/mux.h>
@@ -81,13 +81,13 @@ static void setup_net_chip(void)
 		&ctrl_base->gpmc_nadv_ale);
 
 	/* Make GPIO 64 as output pin and send a magic pulse through it */
-	if (!omap_request_gpio(64)) {
-		omap_set_gpio_direction(64, 0);
-		omap_set_gpio_dataout(64, 1);
+	if (!gpio_request(64, "")) {
+		gpio_direction_output(64, 0);
+		gpio_set_value(64, 1);
 		udelay(1);
-		omap_set_gpio_dataout(64, 0);
+		gpio_set_value(64, 0);
 		udelay(1);
-		omap_set_gpio_dataout(64, 1);
+		gpio_set_value(64, 1);
 	}
 }
 #endif

board/karo/tx25/tx25.c

@@ -28,6 +28,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/imx25-pinmux.h>
+#include <asm/gpio.h>
 
 static void mdelay(int n)
 {

board/keymile/common/ivm.c

@@ -206,8 +206,8 @@ static int ivm_analyze_block2(unsigned char *buf, int len)
 	unsigned char	valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
 	unsigned long	count;
 
-	/* IVM_MacAddress */
-	sprintf((char *)valbuf, "%pM", buf);
+	/* IVM_MAC Adress begins at offset 1 */
+	sprintf((char *)valbuf, "%pM", buf + 1);
 	ivm_set_value("IVM_MacAddress", (char *)valbuf);
 	/* if an offset is defined, add it */
 #if defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)

board/logicpd/zoom2/debug_board.c

@@ -22,7 +22,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/io.h>
 #include <asm/arch/mux.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 
 #define DEBUG_BOARD_CONNECTED		1
 #define DEBUG_BOARD_NOT_CONNECTED	0
@@ -33,14 +33,14 @@ static void zoom2_debug_board_detect (void)
 {
 	int val = 0;
 
-	if (!omap_request_gpio(158)) {
+	if (!gpio_request(158, "")) {
 		/*
 		 * GPIO to query for debug board
 		 * 158 db board query
 		 */
-		omap_set_gpio_direction(158, 1);
-		val = omap_get_gpio_datain(158);
-		omap_free_gpio(158);
+		gpio_direction_input(158);
+		val = gpio_get_value(158);
+		gpio_free(158);
 	}
 
 	if (!val)

board/logicpd/zoom2/led.c

@@ -22,7 +22,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 
 static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
 
@@ -36,58 +36,58 @@ static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
 #define ZOOM2_LED_BLUE	154
 #define ZOOM2_LED_BLUE2	61
 
-void red_LED_off (void)
+void red_led_off(void)
 {
 	/* red */
-	if (!omap_request_gpio(ZOOM2_LED_RED)) {
-		omap_set_gpio_direction(ZOOM2_LED_RED, 0);
-		omap_set_gpio_dataout(ZOOM2_LED_RED, 0);
+	if (!gpio_request(ZOOM2_LED_RED, "")) {
+		gpio_direction_output(ZOOM2_LED_RED, 0);
+		gpio_set_value(ZOOM2_LED_RED, 0);
 	}
 	saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
 }
 
-void blue_LED_off (void)
+void blue_led_off(void)
 {
 	/* blue */
-	if (!omap_request_gpio(ZOOM2_LED_BLUE)) {
-		omap_set_gpio_direction(ZOOM2_LED_BLUE, 0);
-		omap_set_gpio_dataout(ZOOM2_LED_BLUE, 0);
+	if (!gpio_request(ZOOM2_LED_BLUE, "")) {
+		gpio_direction_output(ZOOM2_LED_BLUE, 0);
+		gpio_set_value(ZOOM2_LED_BLUE, 0);
 	}
 
 	/* blue 2 */
-	if (!omap_request_gpio(ZOOM2_LED_BLUE2)) {
-		omap_set_gpio_direction(ZOOM2_LED_BLUE2, 0);
-		omap_set_gpio_dataout(ZOOM2_LED_BLUE2, 0);
+	if (!gpio_request(ZOOM2_LED_BLUE2, "")) {
+		gpio_direction_output(ZOOM2_LED_BLUE2, 0);
+		gpio_set_value(ZOOM2_LED_BLUE2, 0);
 	}
 	saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
 }
 
-void red_LED_on (void)
+void red_led_on(void)
 {
-	blue_LED_off ();
+	blue_led_off();
 
 	/* red */
-	if (!omap_request_gpio(ZOOM2_LED_RED)) {
-		omap_set_gpio_direction(ZOOM2_LED_RED, 0);
-		omap_set_gpio_dataout(ZOOM2_LED_RED, 1);
+	if (!gpio_request(ZOOM2_LED_RED, "")) {
+		gpio_direction_output(ZOOM2_LED_RED, 0);
+		gpio_set_value(ZOOM2_LED_RED, 1);
 	}
 	saved_state[STATUS_LED_RED] = STATUS_LED_ON;
 }
 
-void blue_LED_on (void)
+void blue_led_on(void)
 {
-	red_LED_off ();
+	red_led_off();
 
 	/* blue */
-	if (!omap_request_gpio(ZOOM2_LED_BLUE)) {
-		omap_set_gpio_direction(ZOOM2_LED_BLUE, 0);
-		omap_set_gpio_dataout(ZOOM2_LED_BLUE, 1);
+	if (!gpio_request(ZOOM2_LED_BLUE, "")) {
+		gpio_direction_output(ZOOM2_LED_BLUE, 0);
+		gpio_set_value(ZOOM2_LED_BLUE, 1);
 	}
 
 	/* blue 2 */
-	if (!omap_request_gpio(ZOOM2_LED_BLUE2)) {
-		omap_set_gpio_direction(ZOOM2_LED_BLUE2, 0);
-		omap_set_gpio_dataout(ZOOM2_LED_BLUE2, 1);
+	if (!gpio_request(ZOOM2_LED_BLUE2, "")) {
+		gpio_direction_output(ZOOM2_LED_BLUE2, 0);
+		gpio_set_value(ZOOM2_LED_BLUE2, 1);
 	}
 
 	saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
@@ -102,14 +102,14 @@ void __led_toggle (led_id_t mask)
 {
 	if (STATUS_LED_BLUE == mask) {
 		if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
-			blue_LED_off ();
+			blue_led_off();
 		else
-			blue_LED_on ();
+			blue_led_on();
 	} else if (STATUS_LED_RED == mask) {
 		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
-			red_LED_off ();
+			red_led_off();
 		else
-			red_LED_on ();
+			red_led_on();
 	}
 }
 
@@ -117,13 +117,13 @@ void __led_set (led_id_t mask, int state)
 {
 	if (STATUS_LED_BLUE == mask) {
 		if (STATUS_LED_ON == state)
-			blue_LED_on ();
+			blue_led_on();
 		else
-			blue_LED_off ();
+			blue_led_off();
 	} else if (STATUS_LED_RED == mask) {
 		if (STATUS_LED_ON == state)
-			red_LED_on ();
+			red_led_on();
 		else
-			red_LED_off ();
+			red_led_off();
 	}
 }

board/logicpd/zoom2/zoom2.c

@@ -36,7 +36,7 @@
 #include <twl4030.h>
 #include <asm/io.h>
 #include <asm/arch/mmc_host_def.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
@@ -90,12 +90,12 @@ void zoom2_identify(void)
 	 * and they are not commonly used.  They are mentioned here
 	 * only for completeness.
 	 */
-	if (!omap_request_gpio(94)) {
+	if (!gpio_request(94, "")) {
 		unsigned int val;
 
-		omap_set_gpio_direction(94, 1);
-		val = omap_get_gpio_datain(94);
-		omap_free_gpio(94);
+		gpio_direction_input(94);
+		val = gpio_get_value(94);
+		gpio_free(94);
 
 		if (val)
 			revision = ZOOM2_REVISION_BETA;

board/overo/overo.c

@@ -36,7 +36,7 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/mach-types.h>
 #include "overo.h"
 
@@ -106,21 +106,21 @@ int get_board_revision(void)
 {
 	int revision;
 
-	if (!omap_request_gpio(112) &&
-	    !omap_request_gpio(113) &&
-	    !omap_request_gpio(115)) {
+	if (!gpio_request(112, "") &&
+	    !gpio_request(113, "") &&
+	    !gpio_request(115, "")) {
 
-		omap_set_gpio_direction(112, 1);
-		omap_set_gpio_direction(113, 1);
-		omap_set_gpio_direction(115, 1);
+		gpio_direction_input(112);
+		gpio_direction_input(113);
+		gpio_direction_input(115);
 
-		revision = omap_get_gpio_datain(115) << 2 |
-			   omap_get_gpio_datain(113) << 1 |
-			   omap_get_gpio_datain(112);
+		revision = gpio_get_value(115) << 2 |
+			   gpio_get_value(113) << 1 |
+			   gpio_get_value(112);
 
-		omap_free_gpio(112);
-		omap_free_gpio(113);
-		omap_free_gpio(115);
+		gpio_free(112);
+		gpio_free(113);
+		gpio_free(115);
 	} else {
 		printf("Error: unable to acquire board revision GPIOs\n");
 		revision = -1;
@@ -139,21 +139,21 @@ int get_sdio2_config(void)
 {
 	int sdio_direct;
 
-	if (!omap_request_gpio(130) && !omap_request_gpio(139)) {
+	if (!gpio_request(130, "") && !gpio_request(139, "")) {
 
-		omap_set_gpio_direction(130, 0);
-		omap_set_gpio_direction(139, 1);
+		gpio_direction_output(130, 0);
+		gpio_direction_input(139);
 
 		sdio_direct = 1;
-		omap_set_gpio_dataout(130, 0);
-		if (omap_get_gpio_datain(139) == 0) {
-			omap_set_gpio_dataout(130, 1);
-			if (omap_get_gpio_datain(139) == 1)
+		gpio_set_value(130, 0);
+		if (gpio_get_value(139) == 0) {
+			gpio_set_value(130, 1);
+			if (gpio_get_value(139) == 1)
 				sdio_direct = 0;
 		}
 
-		omap_free_gpio(130);
-		omap_free_gpio(139);
+		gpio_free(130);
+		gpio_free(139);
 	} else {
 		printf("Error: unable to acquire sdio2 clk GPIOs\n");
 		sdio_direct = -1;
@@ -322,13 +322,13 @@ static void setup_net_chip(void)
 		&ctrl_base->gpmc_nadv_ale);
 
 	/* Make GPIO 64 as output pin and send a magic pulse through it */
-	if (!omap_request_gpio(64)) {
-		omap_set_gpio_direction(64, 0);
-		omap_set_gpio_dataout(64, 1);
+	if (!gpio_request(64, "")) {
+		gpio_direction_output(64, 0);
+		gpio_set_value(64, 1);
 		udelay(1);
-		omap_set_gpio_dataout(64, 0);
+		gpio_set_value(64, 0);
 		udelay(1);
-		omap_set_gpio_dataout(64, 1);
+		gpio_set_value(64, 1);
 	}
 }
 #endif

board/ti/beagle/beagle.c

@@ -38,7 +38,7 @@
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/mach-types.h>
 #ifdef CONFIG_USB_EHCI
 #include <usb.h>
@@ -116,21 +116,21 @@ int get_board_revision(void)
 {
 	int revision;
 
-	if (!omap_request_gpio(171) &&
-	    !omap_request_gpio(172) &&
-	    !omap_request_gpio(173)) {
+	if (!gpio_request(171, "") &&
+	    !gpio_request(172, "") &&
+	    !gpio_request(173, "")) {
 
-		omap_set_gpio_direction(171, 1);
-		omap_set_gpio_direction(172, 1);
-		omap_set_gpio_direction(173, 1);
+		gpio_direction_input(171);
+		gpio_direction_input(172);
+		gpio_direction_input(173);
 
-		revision = omap_get_gpio_datain(173) << 2 |
-			   omap_get_gpio_datain(172) << 1 |
-			   omap_get_gpio_datain(171);
+		revision = gpio_get_value(173) << 2 |
+			   gpio_get_value(172) << 1 |
+			   gpio_get_value(171);
 
-		omap_free_gpio(171);
-		omap_free_gpio(172);
-		omap_free_gpio(173);
+		gpio_free(171);
+		gpio_free(172);
+		gpio_free(173);
 	} else {
 		printf("Error: unable to acquire board revision GPIOs\n");
 		revision = -1;
@@ -387,7 +387,7 @@ int board_mmc_init(bd_t *bis)
 int ehci_hcd_stop(void)
 {
 	pr_debug("Resetting OMAP3 EHCI\n");
-	omap_set_gpio_dataout(GPIO_PHY_RESET, 0);
+	gpio_set_value(GPIO_PHY_RESET, 0);
 	writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
 	/* disable USB clocks */
 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
@@ -415,9 +415,9 @@ int ehci_hcd_init(void)
 	pr_debug("Initializing OMAP3 ECHI\n");
 
 	/* Put the PHY in RESET */
-	omap_request_gpio(GPIO_PHY_RESET);
-	omap_set_gpio_direction(GPIO_PHY_RESET, 0);
-	omap_set_gpio_dataout(GPIO_PHY_RESET, 0);
+	gpio_request(GPIO_PHY_RESET, "");
+	gpio_direction_output(GPIO_PHY_RESET, 0);
+	gpio_set_value(GPIO_PHY_RESET, 0);
 
 	/* Hold the PHY in RESET for enough time till DIR is high */
 	/* Refer: ISSUE1 */
@@ -469,7 +469,7 @@ int ehci_hcd_init(void)
 	 * PHY is settled and ready
 	 */
 	udelay(10);
-	omap_set_gpio_dataout(GPIO_PHY_RESET, 1);
+	gpio_set_value(GPIO_PHY_RESET, 1);
 
 	hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
 	hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
@@ -508,10 +508,10 @@ int do_userbutton (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		gpio = 4;
 		break;
 	}
-	omap_request_gpio(gpio);
-	omap_set_gpio_direction(gpio, 1);
+	gpio_request(gpio, "");
+	gpio_direction_input(gpio);
 	printf("The user button is currently ");
-	if(omap_get_gpio_datain(gpio))
+	if (gpio_get_value(gpio))
 	{
 		button = 1;
 		printf("PRESSED.\n");
@@ -522,7 +522,7 @@ int do_userbutton (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		printf("NOT pressed.\n");
 	}
 
-	omap_free_gpio(gpio);
+	gpio_free(gpio);
 
 	return !button;
 }

board/ti/beagle/led.c

@@ -22,19 +22,19 @@
 #include <asm/arch/cpu.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 
 /* GPIO pins for the LEDs */
 #define BEAGLE_LED_USR0	150
 #define BEAGLE_LED_USR1	149
 
 #ifdef STATUS_LED_GREEN
-void green_LED_off (void)
+void green_led_off(void)
 {
 	__led_set (STATUS_LED_GREEN, 0);
 }
 
-void green_LED_on (void)
+void green_led_on(void)
 {
 	__led_set (STATUS_LED_GREEN, 1);
 }
@@ -57,10 +57,10 @@ void __led_toggle (led_id_t mask)
 		toggle_gpio = BEAGLE_LED_USR1;
 #endif
 	if (toggle_gpio) {
-		if (!omap_request_gpio(toggle_gpio)) {
-			omap_set_gpio_direction(toggle_gpio, 0);
-			state = omap_get_gpio_dataout(toggle_gpio);
-			omap_set_gpio_dataout(toggle_gpio, !state);
+		if (!gpio_request(toggle_gpio, "")) {
+			gpio_direction_output(toggle_gpio, 0);
+			state = gpio_get_value(toggle_gpio);
+			gpio_set_value(toggle_gpio, !state);
 		}
 	}
 }
@@ -69,17 +69,17 @@ void __led_set (led_id_t mask, int state)
 {
 #ifdef STATUS_LED_BIT
 	if (STATUS_LED_BIT & mask) {
-		if (!omap_request_gpio(BEAGLE_LED_USR0)) {
-			omap_set_gpio_direction(BEAGLE_LED_USR0, 0);
-			omap_set_gpio_dataout(BEAGLE_LED_USR0, state);
+		if (!gpio_request(BEAGLE_LED_USR0, "")) {
+			gpio_direction_output(BEAGLE_LED_USR0, 0);
+			gpio_set_value(BEAGLE_LED_USR0, state);
 		}
 	}
 #endif
 #ifdef STATUS_LED_BIT1
 	if (STATUS_LED_BIT1 & mask) {
-		if (!omap_request_gpio(BEAGLE_LED_USR1)) {
-			omap_set_gpio_direction(BEAGLE_LED_USR1, 0);
-			omap_set_gpio_dataout(BEAGLE_LED_USR1, state);
+		if (!gpio_request(BEAGLE_LED_USR1, "")) {
+			gpio_direction_output(BEAGLE_LED_USR1, 0);
+			gpio_set_value(BEAGLE_LED_USR1, state);
 		}
 	}
 #endif

board/ti/evm/evm.c

@@ -34,7 +34,7 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <i2c.h>
 #include <asm/mach-types.h>
 #include "evm.h"
@@ -196,21 +196,21 @@ static void reset_net_chip(void)
 		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
 	}
 
-	ret = omap_request_gpio(rst_gpio);
+	ret = gpio_request(rst_gpio, "");
 	if (ret < 0) {
 		printf("Unable to get GPIO %d\n", rst_gpio);
 		return ;
 	}
 
 	/* Configure as output */
-	omap_set_gpio_direction(rst_gpio, 0);
+	gpio_direction_output(rst_gpio, 0);
 
 	/* Send a pulse on the GPIO pin */
-	omap_set_gpio_dataout(rst_gpio, 1);
+	gpio_set_value(rst_gpio, 1);
 	udelay(1);
-	omap_set_gpio_dataout(rst_gpio, 0);
+	gpio_set_value(rst_gpio, 0);
 	udelay(1);
-	omap_set_gpio_dataout(rst_gpio, 1);
+	gpio_set_value(rst_gpio, 1);
 }
 
 int board_eth_init(bd_t *bis)

board/ti/panda/panda_mux_data.h

@@ -23,8 +23,8 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-#ifndef _SDP4430_MUX_DATA_H
-#define _SDP4430_MUX_DATA_H
+#ifndef _PANDA_MUX_DATA_H_
+#define _PANDA_MUX_DATA_H_
 
 #include <asm/arch/mux_omap4.h>
 
@@ -43,7 +43,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
 	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
 	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
+	{GPMC_A22, (M3)},						/* gpio_46 */
 	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
 	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
 	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
@@ -57,9 +57,9 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
+	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
 	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (M1)},						/* dsi1_te0 */
+	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
 	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
 	{C2C_DATA14, (M1)},						/* dsi2_te0 */
 	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
@@ -104,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
-	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
+	{ABE_MCBSP1_CLKX, (IEN | M0)},					/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | M0)},					/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -115,7 +115,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
 	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
 	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
-	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
+	{ABE_DMIC_DIN2, (PTU | IEN | M3)},				/* gpio_121 */
 	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
 	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
 	{UART2_RTS, (M0)},						/* uart2_rts */
@@ -141,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -155,12 +155,12 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
 	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
 	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
+	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
 	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
 	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
 	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
-	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
+	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
+	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
 	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
 	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
 	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
@@ -171,13 +171,13 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
 	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
+	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
+	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
+	{SYS_BOOT3, (M3)},						/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -212,19 +212,16 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
 	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD1_FREF_CLK3_REQ, M7},					/* safe mode */
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
-	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD1_FREF_CLK4_REQ, (PTU | M3)},	/* led status_1 */
+	{PAD0_FREF_CLK4_OUT, (PTU | M3)},	/* led status_2 */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
 	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
 	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
 	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
-	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
-	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
-	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif /* _SDP4430_MUX_DATA_H */
+#endif /* _PANDA_MUX_DATA_H_ */

board/ti/sdp4430/sdp4430_mux_data.h

@@ -212,19 +212,16 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
 	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 - Debug led-1 */
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
-	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 - Debug led-2 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 - Debug led-3 */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
 	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
 	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
 	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
-	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
-	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
-	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
 #endif /* _SDP4430_MUX_DATA_H */

common/cmd_led.c

@@ -57,16 +57,16 @@ static const led_tbl_t led_commands[] = {
 #endif
 #endif
 #ifdef STATUS_LED_GREEN
-	{ "green", STATUS_LED_GREEN, green_LED_off, green_LED_on, NULL },
+	{ "green", STATUS_LED_GREEN, green_led_off, green_led_on, NULL },
 #endif
 #ifdef STATUS_LED_YELLOW
-	{ "yellow", STATUS_LED_YELLOW, yellow_LED_off, yellow_LED_on, NULL },
+	{ "yellow", STATUS_LED_YELLOW, yellow_led_off, yellow_led_on, NULL },
 #endif
 #ifdef STATUS_LED_RED
-	{ "red", STATUS_LED_RED, red_LED_off, red_LED_on, NULL },
+	{ "red", STATUS_LED_RED, red_led_off, red_led_on, NULL },
 #endif
 #ifdef STATUS_LED_BLUE
-	{ "blue", STATUS_LED_BLUE, blue_LED_off, blue_LED_on, NULL },
+	{ "blue", STATUS_LED_BLUE, blue_led_off, blue_led_on, NULL },
 #endif
 	{ NULL, 0, NULL, NULL, NULL }
 };

doc/README.omap3

@@ -98,24 +98,24 @@ gpio
 
 To set a bit :
 
-	if (!omap_request_gpio(N)) {
-		omap_set_gpio_direction(N, 0);
-		omap_set_gpio_dataout(N, 1);
+	if (!gpio_request(N, "")) {
+		gpio_direction_output(N, 0);
+		gpio_set_value(N, 1);
 	}
 
 To clear a bit :
 
-	if (!omap_request_gpio(N)) {
-		omap_set_gpio_direction(N, 0);
-		omap_set_gpio_dataout(N, 0);
+	if (!gpio_request(N, "")) {
+		gpio_direction_output(N, 0);
+		gpio_set_value(N, 0);
 	}
 
 To read a bit :
 
-	if (!omap_request_gpio(N)) {
-		omap_set_gpio_direction(N, 1);
-		val = omap_get_gpio_datain(N);
-		omap_free_gpio(N);
+	if (!gpio_request(N, "")) {
+		gpio_direction_input(N);
+		val = gpio_get_value(N);
+		gpio_free(N);
 	}
 	if (val)
 		printf("GPIO N is set\n");

drivers/i2c/omap24xx_i2c.c

@@ -31,8 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define I2C_TIMEOUT	1000
 
-static void wait_for_bb (void);
-static u16 wait_for_pin (void);
+static void wait_for_bb(void);
+static u16 wait_for_pin(void);
 static void flush_fifo(void);
 
 static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
@@ -40,7 +40,7 @@ static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
 static unsigned int bus_initialized[I2C_BUS_MAX];
 static unsigned int current_bus;
 
-void i2c_init (int speed, int slaveadd)
+void i2c_init(int speed, int slaveadd)
 {
 	int psc, fsscll, fssclh;
 	int hsscll = 0, hssclh = 0;
@@ -107,9 +107,9 @@ void i2c_init (int speed, int slaveadd)
 		sclh = (unsigned int)fssclh;
 	}
 
-	if (readw (&i2c_base->con) & I2C_CON_EN) {
-		writew (0, &i2c_base->con);
-		udelay (50000);
+	if (readw(&i2c_base->con) & I2C_CON_EN) {
+		writew(0, &i2c_base->con);
+		udelay(50000);
 	}
 
 	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
@@ -130,35 +130,36 @@ void i2c_init (int speed, int slaveadd)
 	writew(sclh, &i2c_base->sclh);
 
 	/* own address */
-	writew (slaveadd, &i2c_base->oa);
-	writew (I2C_CON_EN, &i2c_base->con);
+	writew(slaveadd, &i2c_base->oa);
+	writew(I2C_CON_EN, &i2c_base->con);
 
 	/* have to enable intrrupts or OMAP i2c module doesn't work */
-	writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
+	writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
 		I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
-	udelay (1000);
+	udelay(1000);
 	flush_fifo();
-	writew (0xFFFF, &i2c_base->stat);
-	writew (0, &i2c_base->cnt);
+	writew(0xFFFF, &i2c_base->stat);
+	writew(0, &i2c_base->cnt);
 
 	if (gd->flags & GD_FLG_RELOC)
 		bus_initialized[current_bus] = 1;
 }
 
-static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
 {
 	int i2c_error = 0;
 	u16 status;
 
 	/* wait until bus not busy */
-	wait_for_bb ();
+	wait_for_bb();
 
 	/* one byte only */
-	writew (1, &i2c_base->cnt);
+	writew(1, &i2c_base->cnt);
 	/* set slave address */
-	writew (devaddr, &i2c_base->sa);
+	writew(devaddr, &i2c_base->sa);
 	/* no stop bit needed here */
-	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
+	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
+	      I2C_CON_TRX, &i2c_base->con);
 
 	/* send register offset */
 	while (1) {
@@ -196,7 +197,7 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 		}
 		if (status & I2C_STAT_RRDY) {
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
-    defined(CONFIG_OMAP44XX)
+	defined(CONFIG_OMAP44XX)
 			*value = readb(&i2c_base->data);
 #else
 			*value = readw(&i2c_base->data);
@@ -211,79 +212,8 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 
 read_exit:
 	flush_fifo();
-	writew (0xFFFF, &i2c_base->stat);
-	writew (0, &i2c_base->cnt);
-	return i2c_error;
-}
-
-static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
-{
-	int i2c_error = 0;
-	u16 status;
-
-	/* wait until bus not busy */
-	wait_for_bb ();
-
-	/* two bytes */
-	writew (2, &i2c_base->cnt);
-	/* set slave address */
-	writew (devaddr, &i2c_base->sa);
-	/* stop bit needed here */
-	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
-		I2C_CON_STP, &i2c_base->con);
-
-	while (1) {
-		status = wait_for_pin();
-		if (status == 0 || status & I2C_STAT_NACK) {
-			i2c_error = 1;
-			goto write_exit;
-		}
-		if (status & I2C_STAT_XRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
-    defined(CONFIG_OMAP44XX)
-			/* send register offset */
-			writeb(regoffset, &i2c_base->data);
-			writew(I2C_STAT_XRDY, &i2c_base->stat);
-
-			while (1) {
-				status = wait_for_pin();
-				if (status == 0 || status & I2C_STAT_NACK) {
-					i2c_error = 1;
-					goto write_exit;
-				}
-				if (status & I2C_STAT_XRDY) {
-					/* send data */
-					writeb(value, &i2c_base->data);
-					writew(I2C_STAT_XRDY, &i2c_base->stat);
-				}
-				if (status & I2C_STAT_ARDY) {
-					writew(I2C_STAT_ARDY, &i2c_base->stat);
-					break;
-				}
-			}
-			break;
-#else
-			/* send out two bytes */
-			writew((value << 8) + regoffset, &i2c_base->data);
-			writew(I2C_STAT_XRDY, &i2c_base->stat);
-#endif
-		}
-		if (status & I2C_STAT_ARDY) {
-			writew(I2C_STAT_ARDY, &i2c_base->stat);
-			break;
-		}
-	}
-
-	wait_for_bb();
-
-	status = readw(&i2c_base->stat);
-	if (status & I2C_STAT_NACK)
-		i2c_error = 1;
-
-write_exit:
-	flush_fifo();
-	writew (0xFFFF, &i2c_base->stat);
-	writew (0, &i2c_base->cnt);
+	writew(0xFFFF, &i2c_base->stat);
+	writew(0, &i2c_base->cnt);
 	return i2c_error;
 }
 
@@ -293,38 +223,37 @@ static void flush_fifo(void)
 	/* note: if you try and read data when its not there or ready
 	 * you get a bus error
 	 */
-	while(1){
+	while (1) {
 		stat = readw(&i2c_base->stat);
-		if(stat == I2C_STAT_RRDY){
+		if (stat == I2C_STAT_RRDY) {
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
-    defined(CONFIG_OMAP44XX)
+	defined(CONFIG_OMAP44XX)
 			readb(&i2c_base->data);
 #else
 			readw(&i2c_base->data);
 #endif
-			writew(I2C_STAT_RRDY,&i2c_base->stat);
+			writew(I2C_STAT_RRDY, &i2c_base->stat);
 			udelay(1000);
-		}else
+		} else
 			break;
 	}
 }
 
-int i2c_probe (uchar chip)
+int i2c_probe(uchar chip)
 {
 	u16 status;
 	int res = 1; /* default = fail */
 
-	if (chip == readw (&i2c_base->oa)) {
+	if (chip == readw(&i2c_base->oa))
 		return res;
-	}
 
 	/* wait until bus not busy */
-	wait_for_bb ();
+	wait_for_bb();
 
 	/* try to write one byte */
-	writew (1, &i2c_base->cnt);
+	writew(1, &i2c_base->cnt);
 	/* set slave address */
-	writew (chip, &i2c_base->sa);
+	writew(chip, &i2c_base->sa);
 	/* stop bit needed here */
 	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
 	       I2C_CON_STP, &i2c_base->con);
@@ -339,29 +268,30 @@ int i2c_probe (uchar chip)
 	writew(0, &i2c_base->con);
 
 	flush_fifo();
-	writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
+	/* don't allow any more data in... we don't want it. */
+	writew(0, &i2c_base->cnt);
 	writew(0xFFFF, &i2c_base->stat);
 	return res;
 }
 
-int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
 	int i;
 
 	if (alen > 1) {
-		printf ("I2C read: addr len %d not supported\n", alen);
+		printf("I2C read: addr len %d not supported\n", alen);
 		return 1;
 	}
 
 	if (addr + len > 256) {
-		printf ("I2C read: address out of range\n");
+		printf("I2C read: address out of range\n");
 		return 1;
 	}
 
 	for (i = 0; i < len; i++) {
-		if (i2c_read_byte (chip, addr + i, &buffer[i])) {
-			printf ("I2C read: I/O error\n");
-			i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+		if (i2c_read_byte(chip, addr + i, &buffer[i])) {
+			printf("I2C read: I/O error\n");
+			i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 			return 1;
 		}
 	}
@@ -369,65 +299,116 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
 	return 0;
 }
 
-int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
 	int i;
+	u16 status;
+	int i2c_error = 0;
 
 	if (alen > 1) {
-		printf ("I2C read: addr len %d not supported\n", alen);
+		printf("I2C write: addr len %d not supported\n", alen);
 		return 1;
 	}
 
 	if (addr + len > 256) {
-		printf ("I2C read: address out of range\n");
+		printf("I2C write: address 0x%x + 0x%x out of range\n",
+				addr, len);
 		return 1;
 	}
 
+	/* wait until bus not busy */
+	wait_for_bb();
+
+	/* start address phase - will write regoffset + len bytes data */
+	/* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
+	writew(alen + len, &i2c_base->cnt);
+	/* set slave address */
+	writew(chip, &i2c_base->sa);
+	/* stop bit needed here */
+	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
+		I2C_CON_STP, &i2c_base->con);
+
+	/* Send address byte */
+	status = wait_for_pin();
+
+	if (status == 0 || status & I2C_STAT_NACK) {
+		i2c_error = 1;
+		printf("error waiting for i2c address ACK (status=0x%x)\n",
+		      status);
+		goto write_exit;
+	}
+
+	if (status & I2C_STAT_XRDY) {
+		writeb(addr & 0xFF, &i2c_base->data);
+		writew(I2C_STAT_XRDY, &i2c_base->stat);
+	} else {
+		i2c_error = 1;
+		printf("i2c bus not ready for transmit (status=0x%x)\n",
+		      status);
+		goto write_exit;
+	}
+
+	/* address phase is over, now write data */
 	for (i = 0; i < len; i++) {
-		if (i2c_write_byte (chip, addr + i, buffer[i])) {
-			printf ("I2C read: I/O error\n");
-			i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-			return 1;
+		status = wait_for_pin();
+
+		if (status == 0 || status & I2C_STAT_NACK) {
+			i2c_error = 1;
+			printf("i2c error waiting for data ACK (status=0x%x)\n",
+					status);
+			goto write_exit;
+		}
+
+		if (status & I2C_STAT_XRDY) {
+			writeb(buffer[i], &i2c_base->data);
+			writew(I2C_STAT_XRDY, &i2c_base->stat);
+		} else {
+			i2c_error = 1;
+			printf("i2c bus not ready for Tx (i=%d)\n", i);
+			goto write_exit;
 		}
 	}
 
-	return 0;
+write_exit:
+	flush_fifo();
+	writew(0xFFFF, &i2c_base->stat);
+	return i2c_error;
 }
 
-static void wait_for_bb (void)
+static void wait_for_bb(void)
 {
 	int timeout = I2C_TIMEOUT;
 	u16 stat;
 
 	writew(0xFFFF, &i2c_base->stat);	/* clear current interrupts...*/
-	while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
-		writew (stat, &i2c_base->stat);
+	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
+		writew(stat, &i2c_base->stat);
 		udelay(1000);
 	}
 
 	if (timeout <= 0) {
-		printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
-			readw (&i2c_base->stat));
+		printf("timed out in wait_for_bb: I2C_STAT=%x\n",
+			readw(&i2c_base->stat));
 	}
 	writew(0xFFFF, &i2c_base->stat);	 /* clear delayed stuff*/
 }
 
-static u16 wait_for_pin (void)
+static u16 wait_for_pin(void)
 {
 	u16 status;
 	int timeout = I2C_TIMEOUT;
 
 	do {
-		udelay (1000);
-		status = readw (&i2c_base->stat);
-	} while (  !(status &
+		udelay(1000);
+		status = readw(&i2c_base->stat);
+	} while (!(status &
 		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
 		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
 		    I2C_STAT_AL)) && timeout--);
 
 	if (timeout <= 0) {
-		printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
-			readw (&i2c_base->stat));
+		printf("timed out in wait_for_pin: I2C_STAT=%x\n",
+			readw(&i2c_base->stat));
 		writew(0xFFFF, &i2c_base->stat);
 		status = 0;
 	}
@@ -442,7 +423,7 @@ int i2c_set_bus_num(unsigned int bus)
 		return -1;
 	}
 
-#if I2C_BUS_MAX==3
+#if I2C_BUS_MAX == 3
 	if (bus == 2)
 		i2c_base = (struct i2c *)I2C_BASE3;
 	else
@@ -454,7 +435,7 @@ int i2c_set_bus_num(unsigned int bus)
 
 	current_bus = bus;
 
-	if(!bus_initialized[current_bus])
+	if (!bus_initialized[current_bus])
 		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	return 0;

drivers/mtd/spi/spi_flash.c

@@ -233,7 +233,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
 			goto out;
 	}
 
-	debug("SF: Successfully erased %lu bytes @ %#x\n",
+	debug("SF: Successfully erased %zu bytes @ %#x\n",
 	      len * erase_size, start);
 
  out:

include/configs/da830evm.h

@@ -28,6 +28,7 @@
  * Board
  */
 #define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_SPIFLASH
 
 /*
  * SoC Configuration
@@ -48,8 +49,9 @@
  */
 #define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
 #define PHYS_SDRAM_1			0xc0000000 /* SDRAM Start */
-#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1 /* memtest start addr */
-#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 16*1024*1024) /* 16MB test */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+						(32 << 20))
 #define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
 #define CONFIG_STACKSIZE	(256*1024) /* regular stack */
 
@@ -145,8 +147,8 @@
 #define CONFIG_DAVINCI_SPI
 #define CONFIG_SYS_SPI_BASE		DAVINCI_SPI0_BASE
 #define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI0_CLKID)
-#define CONFIG_SF_DEFAULT_SPEED		50000000
-#define CONFIG_SYS_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
 #endif
 
 /*
@@ -162,12 +164,12 @@
 #undef CONFIG_MISC_INIT_R
 #undef CONFIG_BOOTDELAY
 #define CONFIG_BOOTFILE		"uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT	"DA830-evm > " /* Command Prompt */
+#define CONFIG_SYS_PROMPT	"U-Boot > " /* Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16 /* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE	/* Won't work with hush so far, may be later */
 #define CONFIG_SYS_HUSH_PARSER
@@ -180,7 +182,7 @@
 /*
  * Linux Information
  */
-#define LINUX_BOOT_PARAM_ADDR	(CONFIG_SYS_MEMTEST_START + 0x100)
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS		"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp"
@@ -201,7 +203,6 @@
 #define CONFIG_CMD_MEMORY
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_EEPROM
 
 #ifndef CONFIG_DRIVER_TI_EMAC
 #undef CONFIG_CMD_NET
@@ -223,6 +224,7 @@
 #undef CONFIG_CMD_IMLS
 #undef CONFIG_CMD_FLASH
 #define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
 #define CONFIG_CMD_SAVEENV
 #endif
 

include/configs/km/km83xx-common.h

@@ -284,12 +284,7 @@
 
 /*
  * Internal Definitions
- *
- * Boot Flags
  */
-#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02 /* Software reboot */
-
 #define BOOTFLASH_START	0xF0000000
 
 #define CONFIG_KM_CONSOLE_TTY	"ttyS0"

include/configs/omap3_beagle.h

@@ -118,7 +118,7 @@
 #define CONFIG_I2C_MULTI_BUS		1
 
 /* Probe all devices */
-#define CONFIG_SYS_I2C_NOPROBES		{0x0, 0x0}
+#define CONFIG_SYS_I2C_NOPROBES		{{0x0, 0x0}}
 
 /* USB */
 #define CONFIG_MUSB_UDC			1
@@ -215,7 +215,6 @@
 	"loadaddr=0x80200000\0" \
 	"rdaddr=0x81000000\0" \
 	"usbtty=cdc_acm\0" \
-	"usbethaddr=de:ad:be:ef\0" \
 	"bootfile=uImage.beagle\0" \
 	"console=ttyS2,115200n8\0" \
 	"mpurate=auto\0" \

include/configs/omap4_common.h

@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * TI OMAP4 common configuration settings
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_OMAP4_COMMON_H
+#define __CONFIG_OMAP4_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP44XX		1	/* which is a 44XX */
+#define CONFIG_OMAP4430		1	/* which is in a 4430 */
+#define CONFIG_ARCH_CPU_INIT
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap4.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			38400000	/* Clock output from T2 */
+#define V_SCLK                   V_OSCK
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT		1
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 128k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE	SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK			48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+/* I2C  */
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_I2C_MULTI_BUS		1
+
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER		1
+
+/* MMC */
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_OMAP_HSMMC		1
+#define CONFIG_SYS_MMC_SET_DEV		1
+#define CONFIG_DOS_PARTITION		1
+
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH	1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2		/* EXT2 Support                 */
+#define CONFIG_CMD_FAT		/* FAT support                  */
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support                  */
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support   */
+#undef CONFIG_CMD_IMLS		/* List all found images        */
+
+/*
+ * Environment setup
+ */
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"vram=${vram} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"fi; " \
+		"fi; " \
+	"fi"
+
+#define CONFIG_AUTO_COMPLETE		1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4030D800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310		1
+#define CONFIG_SYS_PL310_BASE	0x48242000
+#endif
+
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE		0x40304350
+#define CONFIG_SPL_MAX_SIZE		(38 * 1024)
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+
+#endif /* __CONFIG_OMAP4_COMMON_H */

include/configs/omap4_panda.h

@@ -4,6 +4,7 @@
  * Steve Sakoman  <steve@sakoman.com>
  *
  * Configuration settings for the TI OMAP4 Panda board.
+ * See omap4_common.h for OMAP4 common part
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -24,253 +25,19 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_PANDA_H
+#define __CONFIG_PANDA_H
 
 /*
  * High Level Configuration Options
  */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP44XX		1	/* which is a 44XX */
-#define CONFIG_OMAP4430		1	/* which is in a 4430 */
 #define CONFIG_PANDA		1	/* working with Panda */
-#define CONFIG_ARCH_CPU_INIT
 
-/* Get CPU defs */
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
-
-/* Display CPU and Board Info */
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-/* Clock Defines */
-#define V_OSCK			38400000	/* Clock output from T2 */
-#define V_SCLK                   V_OSCK
-
-#undef CONFIG_USE_IRQ				/* no support for IRQs */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-#define CONFIG_OF_LIBFDT		1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 256k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE			(256 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
-/* Vector Base */
-#define CONFIG_SYS_CA9_VECTOR_BASE	SRAM_ROM_VECT_BASE
-
-/*
- * Hardware drivers
- */
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK			48000000
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+#include <configs/omap4_common.h>
 
+/* ENV related config options */
 #define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
 
-/* I2C  */
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_SYS_I2C_BUS		0
-#define CONFIG_SYS_I2C_BUS_SELECT	1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
-#define CONFIG_I2C_MULTI_BUS		1
-
-/* TWL6030 */
-#define CONFIG_TWL6030_POWER		1
-
-/* MMC */
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_SYS_MMC_SET_DEV		1
-#define CONFIG_DOS_PARTITION		1
-
-/* USB */
-#define CONFIG_MUSB_UDC			1
-#define CONFIG_USB_OMAP3		1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE		1
-#define CONFIG_USB_TTY			1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH	1
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_EXT2		/* EXT2 Support                 */
-#define CONFIG_CMD_FAT		/* FAT support                  */
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support                  */
-
-/* Disabled commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA		/* FPGA configuration Support   */
-#undef CONFIG_CMD_IMLS		/* List all found images        */
-
-/*
- * Environment setup
- */
-
-#define CONFIG_BOOTDELAY	3
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=0x82000000\0" \
-	"console=ttyS2,115200n8\0" \
-	"usbtty=cdc_acm\0" \
-	"vram=16M\0" \
-	"mmcdev=0\0" \
-	"mmcroot=/dev/mmcblk0p2 rw\0" \
-	"mmcrootfstype=ext3 rootwait\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"vram=${vram} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
-		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
-	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
-		"run mmcargs; " \
-		"bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"if mmc rescan ${mmcdev}; then " \
-		"if run loadbootscript; then " \
-			"run bootscript; " \
-		"else " \
-			"if run loaduimage; then " \
-				"run mmcboot; " \
-			"fi; " \
-		"fi; " \
-	"fi"
-
-#define CONFIG_AUTO_COMPLETE		1
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP	/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"Panda # "
-#define CONFIG_SYS_CBSIZE		512
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
 
-/*
- * memtest setup
- */
-#define CONFIG_SYS_MEMTEST_START	0x80000000
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x80000000
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE		GPT2_BASE
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128 << 10)	/* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack */
-#endif
-
-/*
- * SDRAM Memory Map
- * Even though we use two CS all the memory
- * is mapped to one contiguous block
- */
-#define CONFIG_NR_DRAM_BANKS	1
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4030D800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310		1
-#define CONFIG_SYS_PL310_BASE	0x48242000
-#endif
-
-/* Defines for SDRAM init */
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE		0x40304350
-#define CONFIG_SPL_MAX_SIZE		(38 * 1024)
-#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SPL_BSS_START_ADDR	0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE		0x80100000
-
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_PANDA_H */

include/configs/omap4_sdp4430.h

@@ -5,6 +5,7 @@
  * Steve Sakoman  <steve@sakoman.com>
  *
  * Configuration settings for the TI SDP4430 board.
+ * See omap4_common.h for OMAP4 common part
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,258 +26,25 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_SDP4430_H
+#define __CONFIG_SDP4430_H
 
 /*
  * High Level Configuration Options
  */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP44XX		1	/* which is a 44XX */
-#define CONFIG_OMAP4430		1	/* which is in a 4430 */
 #define CONFIG_4430SDP		1	/* working with SDP */
-#define CONFIG_ARCH_CPU_INIT
 
-/* Get CPU defs */
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
+#include <configs/omap4_common.h>
 
-/* Display CPU and Board Info */
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-/* Clock Defines */
-#define V_OSCK			38400000	/* Clock output from T2 */
-#define V_SCLK                   V_OSCK
-
-#undef CONFIG_USE_IRQ				/* no support for IRQs */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_OF_LIBFDT		1
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 128k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE			(128 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
-/* Vector Base */
-#define CONFIG_SYS_CA9_VECTOR_BASE	SRAM_ROM_VECT_BASE
-
-/*
- * Hardware drivers
- */
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK			48000000
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		UART3_BASE
-
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-/* I2C  */
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_SYS_I2C_BUS		0
-#define CONFIG_SYS_I2C_BUS_SELECT	1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
-#define CONFIG_I2C_MULTI_BUS		1
-
-/* TWL6030 */
-#define CONFIG_TWL6030_POWER		1
+/* Battery Charger */
 #define CONFIG_CMD_BAT			1
 
-/* MMC */
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_SYS_MMC_SET_DEV		1
-#define CONFIG_DOS_PARTITION		1
-
-/* MMC ENV related defines */
+/* ENV related config options */
 #define CONFIG_ENV_IS_IN_MMC		1
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
 #define CONFIG_ENV_OFFSET		0xE0000
-
-/* USB */
-#define CONFIG_MUSB_UDC			1
-#define CONFIG_USB_OMAP3		1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE		1
-#define CONFIG_USB_TTY			1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH	1
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_EXT2		/* EXT2 Support                 */
-#define CONFIG_CMD_FAT		/* FAT support                  */
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support                  */
 #define CONFIG_CMD_SAVEENV
 
-/* Disabled commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA		/* FPGA configuration Support   */
-#undef CONFIG_CMD_IMLS		/* List all found images        */
-
-/*
- * Environment setup
- */
-
-#define CONFIG_BOOTDELAY	3
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=0x82000000\0" \
-	"console=ttyS2,115200n8\0" \
-	"usbtty=cdc_acm\0" \
-	"vram=16M\0" \
-	"mmcdev=0\0" \
-	"mmcroot=/dev/mmcblk0p2 rw\0" \
-	"mmcrootfstype=ext3 rootwait\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"vram=${vram} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
-		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
-	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
-		"run mmcargs; " \
-		"bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"if mmc rescan ${mmcdev}; then " \
-		"if run loadbootscript; then " \
-			"run bootscript; " \
-		"else " \
-			"if run loaduimage; then " \
-				"run mmcboot; " \
-			"fi; " \
-		"fi; " \
-	"fi"
-
-#define CONFIG_AUTO_COMPLETE		1
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP	/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP4430 SDP # "
-#define CONFIG_SYS_CBSIZE		512
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
 
-/*
- * memtest setup
- */
-#define CONFIG_SYS_MEMTEST_START	0x80000000
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x80000000
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE		GPT2_BASE
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128 << 10)	/* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack */
-#endif
-
-/*
- * SDRAM Memory Map
- * Even though we use two CS all the memory
- * is mapped to one contiguous block
- */
-#define CONFIG_NR_DRAM_BANKS	1
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4030D800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310		1
-#define CONFIG_SYS_PL310_BASE	0x48242000
-#endif
-
-/* Defines for SDRAM init */
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE		0x40304350
-#define CONFIG_SPL_MAX_SIZE		(38 * 1024)
-#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SPL_BSS_START_ADDR	0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE		0x80100000
-
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_SDP4430_H */

include/configs/tx25.h

@@ -25,9 +25,7 @@
 /*
  * KARO TX25 board - SoC Configuration
  */
-#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_MX25
-#define CONFIG_TX25
 #define CONFIG_MX25_CLK32		32000	/* OSC32K frequency */
 #define CONFIG_SYS_HZ			1000
 
@@ -56,9 +54,9 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
 
 /*
  * Memory Info
@@ -85,17 +83,19 @@
 /*
  * Serial Info
  */
-#define CONFIG_MXC_UART		1
-#define CONFIG_SYS_MX25_UART1	1
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX25_UART1
 #define CONFIG_CONS_INDEX	1	/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200	/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+#define CONFIG_MXC_GPIO
+
 /*
  * Flash & Environment
  */
 /* No NOR flash present */
-#define CONFIG_SYS_NO_FLASH	1
+#define CONFIG_SYS_NO_FLASH
 #define	CONFIG_ENV_IS_IN_NAND
 #define	CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
 #define CONFIG_ENV_SIZE		(128 * 1024)	/* 128 kB NAND block size */

include/configs/xpedite550x.h

@@ -441,12 +441,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
 
-/*
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM		0x02		/* Software reboot */
-
 /*
  * Environment Configuration
  */

include/status_led.h

@@ -357,24 +357,24 @@ extern void __led_set (led_id_t mask, int state);
  */
 #ifndef	__ASSEMBLY__
 extern void	coloured_LED_init (void);
-extern void	red_LED_on(void);
-extern void	red_LED_off(void);
-extern void	green_LED_on(void);
-extern void	green_LED_off(void);
-extern void	yellow_LED_on(void);
-extern void	yellow_LED_off(void);
-extern void	blue_LED_on(void);
-extern void	blue_LED_off(void);
+extern void	red_led_on(void);
+extern void	red_led_off(void);
+extern void	green_led_on(void);
+extern void	green_led_off(void);
+extern void	yellow_led_on(void);
+extern void	yellow_led_off(void);
+extern void	blue_led_on(void);
+extern void	blue_led_off(void);
 #else
 	.extern LED_init
-	.extern red_LED_on
-	.extern red_LED_off
-	.extern yellow_LED_on
-	.extern yellow_LED_off
-	.extern green_LED_on
-	.extern green_LED_off
-	.extern blue_LED_on
-	.extern blue_LED_off
+	.extern red_led_on
+	.extern red_led_off
+	.extern yellow_led_on
+	.extern yellow_led_off
+	.extern green_led_on
+	.extern green_led_off
+	.extern blue_led_on
+	.extern blue_led_off
 #endif
 
 #endif	/* CONFIG_STATUS_LED	*/

net/bootp.c

@@ -164,8 +164,8 @@ static void auto_load(void)
 			return;
 		}
 #endif
-	TftpStart();
 	}
+	TftpStart();
 }
 
 #if !defined(CONFIG_CMD_DHCP)

net/eth.c

@@ -227,12 +227,7 @@ int eth_register(struct eth_device *dev)
 {
 	struct eth_device *d;
 
-	size_t len = strlen(dev->name);
-	if (len >= NAMESIZE) {
-		printf("Network driver name is too long (%zu >= %zu): %s\n",
-						len, NAMESIZE, dev->name);
-		return -1;
-	}
+	assert(strlen(dev->name) < NAMESIZE);
 
 	if (!eth_devices) {
 		eth_current = eth_devices = dev;