Prepare v2014.04-rc1

Signed-off-by: Tom Rini <trini@ti.com>

.gitignore

@@ -5,16 +5,20 @@
 #
 # Normal rules
 #
-
-*.rej
-*.orig
-*.a
+.*
 *.o
+*.o.*
+*.a
+*.s
 *.su
-*~
+*.mod.c
+*.i
+*.lst
+*.order
+*.elf
 *.swp
-*.patch
 *.bin
+*.patch
 *.cfgtmp
 *.dts.tmp
 
@@ -24,7 +28,6 @@
 #
 # Top-level generic files
 #
-
 /MLO*
 /SPL
 /System.map
@@ -45,24 +48,29 @@
 /u-boot.lds
 /u-boot.ubl
 /u-boot.ais
-/u-boot.dtb
 /u-boot.sb
-/u-boot.bd
-/u-boot.geany
+
+#
+# git files that we don't want to ignore even it they are dot-files
+#
+!.gitignore
+!.mailmap
 
 #
 # Generated files
 #
 
-*.depend*
 /LOG
 /errlog
 /reloc_off
 
+!/spl/Makefile
+/spl/*
+/tpl/
+
 /include/generated/
 /include/spl-autoconf.mk
 /include/tpl-autoconf.mk
-asm-offsets.s
 
 # stgit generated dirs
 patches-*
@@ -89,5 +97,6 @@ GRTAGS
 GSYMS
 GTAGS
 
-# spl ais files
-/spl/*.ais
+*.orig
+*~
+\#*#

CREDITS

@@ -143,7 +143,7 @@ W: www.freescale.com
 
 N: Dr. Wolfgang Grandegger
 E: wg@denx.de
-D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
+D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
 W: www.denx.de
 
 N: Peter Figuli

MAKEALL

@@ -18,6 +18,7 @@ usage()
 	  -c CPU,    --cpu CPU         Build all boards with cpu CPU
 	  -v VENDOR, --vendor VENDOR   Build all boards with vendor VENDOR
 	  -s SOC,    --soc SOC         Build all boards with soc SOC
+	  -b BOARD,  --board BOARD     Build all boards with board name BOARD
 	  -l,        --list            List all targets to be built
 	  -m,        --maintainers     List all targets and maintainer email
 	  -M,        --mails           List all targets and all affilated emails
@@ -59,8 +60,8 @@ usage()
 	exit ${ret}
 }
 
-SHORT_OPTS="ha:c:v:s:lmMCnr"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check,continue,rebuild-errors"
+SHORT_OPTS="ha:c:v:s:b:lmMCnr"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:,board:,list,maintainers,mails,check,continue,rebuild-errors"
 
 # Option processing based on util-linux-2.13/getopt-parse.bash
 
@@ -121,6 +122,17 @@ while true ; do
 		fi
 		SELECTED='y'
 		shift 2 ;;
+	-b|--board)
+		# echo "Option BOARD: argument \`$2'"
+		if [ "$opt_b" ] ; then
+			opt_b="${opt_b%)} || \$6 == \"$2\" || \$7 == \"$2\")"
+		else
+			# We need to check the 7th field too
+			# for boards whose 6th field is "-"
+			opt_b="(\$6 == \"$2\" || \$7 == \"$2\")"
+		fi
+		SELECTED='y'
+		shift 2 ;;
 	-C|--check)
 		CHECK='C=1'
 		shift ;;
@@ -158,6 +170,7 @@ FILTER="\$1 !~ /^#/"
 [ "$opt_c" ] && FILTER="${FILTER} && $opt_c"
 [ "$opt_s" ] && FILTER="${FILTER} && $opt_s"
 [ "$opt_v" ] && FILTER="${FILTER} && $opt_v"
+[ "$opt_b" ] && FILTER="${FILTER} && $opt_b"
 
 if [ "$SELECTED" ] ; then
 	SELECTED=$(awk '('"$FILTER"') { print $7 }' boards.cfg)
@@ -224,86 +237,84 @@ OLDEST_IDX=1
 RC=0
 
 # Helper funcs for parsing boards.cfg
-boards_by_field()
+targets_by_field()
 {
-	FS="[ \t]+"
-	[ -n "$3" ] && FS="$3"
-	awk \
-		-v field="$1" \
-		-v select="$2" \
-		-F "$FS" \
-		'($1 !~ /^#/ && $field == select) { print $7 }' \
-		boards.cfg
+	field=$1
+	regexp=$2
+
+	awk '($1 !~ /^#/ && $'"$field"' ~ /^'"$regexp"'$/) { print $7 }' \
+								boards.cfg
 }
-boards_by_arch() { boards_by_field 2 "$@" ; }
-boards_by_cpu()  { boards_by_field 3 "$@" "[: \t]+" ; }
-boards_by_soc()  { boards_by_field 4 "$@" ; }
+
+targets_by_arch() { targets_by_field 2 "$@" ; }
+targets_by_cpu()  { targets_by_field 3 "$@" ; targets_by_field 3 "$@:.*" ; }
+targets_by_soc()  { targets_by_field 4 "$@" ; }
 
 #########################################################################
 ## MPC5xx Systems
 #########################################################################
 
-LIST_5xx="$(boards_by_cpu mpc5xx)"
+LIST_5xx="$(targets_by_cpu mpc5xx)"
 
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
 
-LIST_5xxx="$(boards_by_cpu mpc5xxx)"
+LIST_5xxx="$(targets_by_cpu mpc5xxx)"
 
 #########################################################################
 ## MPC512x Systems
 #########################################################################
 
-LIST_512x="$(boards_by_cpu mpc512x)"
+LIST_512x="$(targets_by_cpu mpc512x)"
 
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
 
-LIST_8xx="$(boards_by_cpu mpc8xx)"
+LIST_8xx="$(targets_by_cpu mpc8xx)"
 
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
 
-LIST_4xx="$(boards_by_cpu ppc4xx)"
+LIST_4xx="$(targets_by_cpu ppc4xx)"
 
 #########################################################################
 ## MPC824x Systems
 #########################################################################
 
-LIST_824x="$(boards_by_cpu mpc824x)"
+LIST_824x="$(targets_by_cpu mpc824x)"
 
 #########################################################################
 ## MPC8260 Systems (includes 8250, 8255 etc.)
 #########################################################################
 
-LIST_8260="$(boards_by_cpu mpc8260)"
+LIST_8260="$(targets_by_cpu mpc8260)"
 
 #########################################################################
 ## MPC83xx Systems (includes 8349, etc.)
 #########################################################################
 
-LIST_83xx="$(boards_by_cpu mpc83xx)"
+LIST_83xx="$(targets_by_cpu mpc83xx)"
 
 #########################################################################
 ## MPC85xx Systems (includes 8540, 8560 etc.)
 #########################################################################
 
-LIST_85xx="$(boards_by_cpu mpc85xx)"
+LIST_85xx="$(targets_by_cpu mpc85xx)"
 
 #########################################################################
 ## MPC86xx Systems
 #########################################################################
 
-LIST_86xx="$(boards_by_cpu mpc86xx)"
+LIST_86xx="$(targets_by_cpu mpc86xx)"
 
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
 
-LIST_74xx_7xx="$(boards_by_cpu 74xx_7xx)"
+LIST_74xx_7xx="$(targets_by_cpu 74xx_7xx)"
 
 #########################################################################
 ## PowerPC groups
@@ -339,61 +350,71 @@ LIST_ppc="		\
 ## StrongARM Systems
 #########################################################################
 
-LIST_SA="$(boards_by_cpu sa1100)"
+LIST_SA="$(targets_by_cpu sa1100)"
 
 #########################################################################
 ## ARM7 Systems
 #########################################################################
 
-LIST_ARM7="$(boards_by_cpu arm720t)"
+LIST_ARM7="$(targets_by_cpu arm720t)"
 
 #########################################################################
 ## ARM9 Systems
 #########################################################################
 
-LIST_ARM9="$(boards_by_cpu arm920t)	\
-	$(boards_by_cpu arm926ejs)	\
-	$(boards_by_cpu arm946es)	\
+LIST_ARM9="$(targets_by_cpu arm920t)	\
+	$(targets_by_cpu arm926ejs)	\
+	$(targets_by_cpu arm946es)	\
 "
 
 #########################################################################
 ## ARM11 Systems
 #########################################################################
-LIST_ARM11="$(boards_by_cpu arm1136)	\
-	$(boards_by_cpu arm1176)	\
+LIST_ARM11="$(targets_by_cpu arm1136)	\
+	$(targets_by_cpu arm1176)	\
 "
 
 #########################################################################
 ## ARMV7 Systems
 #########################################################################
 
-LIST_ARMV7="$(boards_by_cpu armv7)"
+LIST_ARMV7="$(targets_by_cpu armv7)"
+
+#########################################################################
+## ARMV8 Systems
+#########################################################################
+
+LIST_ARMV8="$(targets_by_cpu armv8)"
 
 #########################################################################
 ## AT91 Systems
 #########################################################################
 
-LIST_at91="$(boards_by_soc at91)"
+LIST_at91="$(targets_by_soc at91)"
 
 #########################################################################
 ## Xscale Systems
 #########################################################################
 
-LIST_pxa="$(boards_by_cpu pxa)"
+LIST_pxa="$(targets_by_cpu pxa)"
 
-LIST_ixp="$(boards_by_cpu ixp)"
+LIST_ixp="$(targets_by_cpu ixp)"
 
 #########################################################################
 ## SPEAr Systems
 #########################################################################
 
-LIST_spear="$(boards_by_soc spear)"
+LIST_spear="$(targets_by_soc spear)"
 
 #########################################################################
 ## ARM groups
 #########################################################################
 
-LIST_arm="$(boards_by_arch arm)"
+LIST_arm="$(targets_by_arch arm |		\
+	for ARMV8_TARGET in $LIST_ARMV8;	\
+		do sed "/$ARMV8_TARGET/d";	\
+	done)					\
+"
 
 #########################################################################
 ## MIPS Systems		(default = big endian)
@@ -447,66 +468,72 @@ LIST_mips_el="			\
 ## OpenRISC Systems
 #########################################################################
 
-LIST_openrisc="$(boards_by_arch openrisc)"
+LIST_openrisc="$(targets_by_arch openrisc)"
 
 #########################################################################
 ## x86 Systems
 #########################################################################
 
-LIST_x86="$(boards_by_arch x86)"
+LIST_x86="$(targets_by_arch x86)"
 
 #########################################################################
 ## Nios-II Systems
 #########################################################################
 
-LIST_nios2="$(boards_by_arch nios2)"
+LIST_nios2="$(targets_by_arch nios2)"
 
 #########################################################################
 ## MicroBlaze Systems
 #########################################################################
 
-LIST_microblaze="$(boards_by_arch microblaze)"
+LIST_microblaze="$(targets_by_arch microblaze)"
 
 #########################################################################
 ## ColdFire Systems
 #########################################################################
 
-LIST_m68k="$(boards_by_arch m68k)"
+LIST_m68k="$(targets_by_arch m68k)"
 LIST_coldfire=${LIST_m68k}
 
 #########################################################################
 ## AVR32 Systems
 #########################################################################
 
-LIST_avr32="$(boards_by_arch avr32)"
+LIST_avr32="$(targets_by_arch avr32)"
 
 #########################################################################
 ## Blackfin Systems
 #########################################################################
 
-LIST_blackfin="$(boards_by_arch blackfin)"
+LIST_blackfin="$(targets_by_arch blackfin)"
 
 #########################################################################
 ## SH Systems
 #########################################################################
 
-LIST_sh2="$(boards_by_cpu sh2)"
-LIST_sh3="$(boards_by_cpu sh3)"
-LIST_sh4="$(boards_by_cpu sh4)"
+LIST_sh2="$(targets_by_cpu sh2)"
+LIST_sh3="$(targets_by_cpu sh3)"
+LIST_sh4="$(targets_by_cpu sh4)"
 
-LIST_sh="$(boards_by_arch sh)"
+LIST_sh="$(targets_by_arch sh)"
 
 #########################################################################
 ## SPARC Systems
 #########################################################################
 
-LIST_sparc="$(boards_by_arch sparc)"
+LIST_sparc="$(targets_by_arch sparc)"
 
 #########################################################################
 ## NDS32 Systems
 #########################################################################
 
-LIST_nds32="$(boards_by_arch nds32)"
+LIST_nds32="$(targets_by_arch nds32)"
+
+#########################################################################
+## ARC Systems
+#########################################################################
+
+LIST_arc="$(targets_by_arch arc)"
 
 #-----------------------------------------------------------------------
 
@@ -518,7 +545,7 @@ get_target_location() {
 	local vendor=""
 
 	# Automatic mode
-	local line=`awk -F '\ +' '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
+	local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
 	if [ -z "${line}" ] ; then echo "" ; return ; fi
 
 	set ${line}
@@ -556,7 +583,7 @@ get_target_location() {
 get_target_maintainers() {
 	local name=`echo $1 | cut -d : -f 3`
 
-	local line=`awk -F '\ +' '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
+	local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
 	if [ -z "${line}" ]; then
 		echo ""
 		return ;
@@ -571,7 +598,7 @@ get_target_arch() {
 	local target=$1
 
 	# Automatic mode
-	local line=`egrep -i "^[[:space:]]*${target}[[:space:]]" boards.cfg`
+	local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
 
 	if [ -z "${line}" ] ; then echo "" ; return ; fi
 
@@ -647,8 +674,6 @@ build_target() {
 		output_dir="${OUTPUT_PREFIX}"
 	fi
 
-	export BUILD_DIR="${output_dir}"
-
 	target_arch=$(get_target_arch ${target})
 	eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr '[:lower:]' '[:upper:]'`
 	if [ "${cross_toolchain}" ] ; then
@@ -659,6 +684,10 @@ build_target() {
 	    MAKE=make
 	fi
 
+	if [  "${output_dir}" != "." ] ; then
+		MAKE="${MAKE} O=${output_dir}"
+	fi
+
 	${MAKE} distclean >/dev/null
 	${MAKE} -s ${target}_config
 
@@ -673,7 +702,7 @@ build_target() {
 	if [ $BUILD_MANY == 1 ] ; then
 		trap - TERM
 
-		${MAKE} -s tidy
+		${MAKE} -s clean
 
 		if [ -s ${LOG_DIR}/${target}.ERR ] ; then
 			cp ${LOG_DIR}/${target}.ERR ${OUTPUT_PREFIX}/ERR/${target}

README

@@ -423,9 +423,10 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 		This value denotes start offset of DSP CCSR space.
 
-		CONFIG_SYS_FSL_DDR_EMU
-		Specify emulator support for DDR. Some DDR features such as
-		deskew training are not available.
+		CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+		Single Source Clock is clocking mode present in some of FSL SoC's.
+		In this mode, a single differential clock is used to supply
+		clocks to the sysclock, ddrclock and usbclock.
 
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
@@ -433,6 +434,59 @@ The following options need to be configured:
 		Defines the endianess of the CPU. Implementation of those
 		values is arch specific.
 
+		CONFIG_SYS_FSL_DDR
+		Freescale DDR driver in use. This type of DDR controller is
+		found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
+		SoCs.
+
+		CONFIG_SYS_FSL_DDR_ADDR
+		Freescale DDR memory-mapped register base.
+
+		CONFIG_SYS_FSL_DDR_EMU
+		Specify emulator support for DDR. Some DDR features such as
+		deskew training are not available.
+
+		CONFIG_SYS_FSL_DDRC_GEN1
+		Freescale DDR1 controller.
+
+		CONFIG_SYS_FSL_DDRC_GEN2
+		Freescale DDR2 controller.
+
+		CONFIG_SYS_FSL_DDRC_GEN3
+		Freescale DDR3 controller.
+
+		CONFIG_SYS_FSL_DDRC_ARM_GEN3
+		Freescale DDR3 controller for ARM-based SoCs.
+
+		CONFIG_SYS_FSL_DDR1
+		Board config to use DDR1. It can be enabled for SoCs with
+		Freescale DDR1 or DDR2 controllers, depending on the board
+		implemetation.
+
+		CONFIG_SYS_FSL_DDR2
+		Board config to use DDR2. It can be eanbeld for SoCs with
+		Freescale DDR2 or DDR3 controllers, depending on the board
+		implementation.
+
+		CONFIG_SYS_FSL_DDR3
+		Board config to use DDR3. It can be enabled for SoCs with
+		Freescale DDR3 controllers.
+
+		CONFIG_SYS_FSL_IFC_BE
+		Defines the IFC controller register space as Big Endian
+
+		CONFIG_SYS_FSL_IFC_LE
+		Defines the IFC controller register space as Little Endian
+
+		CONFIG_SYS_FSL_PBL_PBI
+		It enables addition of RCW (Power on reset configuration) in built image.
+		Please refer doc/README.pblimage for more details
+
+		CONFIG_SYS_FSL_PBL_RCW
+		It adds PBI(pre-boot instructions) commands in u-boot build image.
+		PBI commands can be used to configure SoC before it starts the execution.
+		Please refer doc/README.pblimage for more details
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -705,6 +759,11 @@ The following options need to be configured:
 		the "silent" environment variable. See
 		doc/README.silent for more information.
 
+		CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default
+			is 0x00.
+		CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default
+			is 0xa0.
+
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
@@ -779,6 +838,22 @@ The following options need to be configured:
 		as a convenience, when switching between booting from
 		RAM and NFS.
 
+- Bootcount:
+		CONFIG_BOOTCOUNT_LIMIT
+		Implements a mechanism for detecting a repeating reboot
+		cycle, see:
+		http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
+
+		CONFIG_BOOTCOUNT_ENV
+		If no softreset save registers are found on the hardware
+		"bootcount" is stored in the environment. To prevent a
+		saveenv on all reboots, the environment variable
+		"upgrade_available" is used. If "upgrade_available" is
+		0, "bootcount" is always 0, if "upgrade_available" is
+		1 "bootcount" is incremented in the environment.
+		So the Userspace Applikation must set the "upgrade_available"
+		and "bootcount" variable to 0, if a boot was successfully.
+
 - Pre-Boot Commands:
 		CONFIG_PREBOOT
 
@@ -827,6 +902,7 @@ The following options need to be configured:
 		CONFIG_CMD_BSP		* Board specific commands
 		CONFIG_CMD_BOOTD	  bootd
 		CONFIG_CMD_CACHE	* icache, dcache
+		CONFIG_CMD_CLK   	* clock command support
 		CONFIG_CMD_CONSOLE	  coninfo
 		CONFIG_CMD_CRC32	* crc32
 		CONFIG_CMD_DATE		* support for RTC, date/time...
@@ -843,9 +919,12 @@ The following options need to be configured:
 		CONFIG_CMD_ELF		* bootelf, bootvx
 		CONFIG_CMD_ENV_CALLBACK	* display details about env callbacks
 		CONFIG_CMD_ENV_FLAGS	* display details about env flags
+		CONFIG_CMD_ENV_EXISTS	* check existence of env variable
 		CONFIG_CMD_EXPORTENV	* export the environment
 		CONFIG_CMD_EXT2		* ext2 command support
 		CONFIG_CMD_EXT4		* ext4 command support
+		CONFIG_CMD_FS_GENERIC	* filesystem commands (e.g. load, ls)
+					  that work for multiple fs types
 		CONFIG_CMD_SAVEENV	  saveenv
 		CONFIG_CMD_FDC		* Floppy Disk Support
 		CONFIG_CMD_FAT		* FAT command support
@@ -1027,7 +1106,6 @@ The following options need to be configured:
 
 - GPIO Support:
 		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
-		CONFIG_PCA953X_INFO	- enable pca953x info command
 
 		The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
 		chip-ngpio pairs that tell the PCA953X driver the number of
@@ -1362,6 +1440,13 @@ The following options need to be configured:
 			for your device
 			- CONFIG_USBD_PRODUCTID 0xFFFF
 
+		Some USB device drivers may need to check USB cable attachment.
+		In this case you can enable following config in BoardName.h:
+			CONFIG_USB_CABLE_CHECK
+			This enables function definition:
+			- usb_cable_connected() in include/usb.h
+			Implementation of this function is board-specific.
+
 - ULPI Layer Support:
 		The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
 		the generic ULPI layer. The generic layer accesses the ULPI PHY
@@ -1951,6 +2036,21 @@ CBFS (Coreboot Filesystem) support
 		kernel). Defining CONFIG_STATUS_LED enables this
 		feature in U-Boot.
 
+		Additional options:
+
+		CONFIG_GPIO_LED
+		The status LED can be connected to a GPIO pin.
+		In such cases, the gpio_led driver can be used as a
+		status LED backend implementation. Define CONFIG_GPIO_LED
+		to include the gpio_led driver in the U-Boot binary.
+
+		CONFIG_GPIO_LED_INVERTED_TABLE
+		Some GPIO connected LEDs may have inverted polarity in which
+		case the GPIO high value corresponds to LED off state and
+		GPIO low value corresponds to LED on state.
+		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
+		with a list of GPIO LEDs that have inverted polarity.
+
 - CAN Support:	CONFIG_CAN_DRIVER
 
 		Defining CONFIG_CAN_DRIVER enables CAN driver support
@@ -1994,15 +2094,82 @@ CBFS (Coreboot Filesystem) support
 		    second bus.
 
 		- drivers/i2c/tegra_i2c.c:
-		 - activate this driver with CONFIG_SYS_I2C_TEGRA
-		 - This driver adds 4 i2c buses with a fix speed from
-		   100000 and the slave addr 0!
+		  - activate this driver with CONFIG_SYS_I2C_TEGRA
+		  - This driver adds 4 i2c buses with a fix speed from
+		    100000 and the slave addr 0!
 
 		- drivers/i2c/ppc4xx_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_PPC4XX
 		  - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
 		  - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
 
+		- drivers/i2c/i2c_mxc.c
+		  - activate this driver with CONFIG_SYS_I2C_MXC
+		  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
+		  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
+		  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
+		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
+		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
+		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
+		If thoses defines are not set, default value is 100000
+		for speed, and 0 for slave.
+
+		- drivers/i2c/rcar_i2c.c:
+		  - activate this driver with CONFIG_SYS_I2C_RCAR
+		  - This driver adds 4 i2c buses
+
+		  - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
+		  - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
+		  - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
+		  - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
+		  - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
+		  - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
+		  - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
+		  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
+		  - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
+
+		- drivers/i2c/sh_i2c.c:
+		  - activate this driver with CONFIG_SYS_I2C_SH
+		  - This driver adds from 2 to 5 i2c buses
+
+		  - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
+		  - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
+		  - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
+		  - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
+		  - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
+		  - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
+		  - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
+		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
+		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
+		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+		  - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
+		  - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
+		  - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
+
+		- drivers/i2c/omap24xx_i2c.c
+		  - activate this driver with CONFIG_SYS_I2C_OMAP24XX
+		  - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
+		  - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
+		  - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
+		  - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
+		  - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
+
+		- drivers/i2c/zynq_i2c.c
+		  - activate this driver with CONFIG_SYS_I2C_ZYNQ
+		  - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
+		  - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
+
+		- drivers/i2c/s3c24x0_i2c.c:
+		  - activate this driver with CONFIG_SYS_I2C_S3C24X0
+		  - This driver adds i2c buses (11 for Exynos5250, Exynos5420
+		    9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
+		    with a fix speed from 100000 and the slave addr 0!
+
 		additional defines:
 
 		CONFIG_SYS_NUM_I2C_BUSES
@@ -2607,6 +2774,12 @@ CBFS (Coreboot Filesystem) support
 		Define this option to use the Bank addr/Extended addr
 		support on SPI flashes which has size > 16Mbytes.
 
+		CONFIG_SF_DUAL_FLASH		Dual flash memories
+
+		Define this option to use dual flash support where two flash
+		memories can be connected with a given cs line.
+		currently Xilinx Zynq qspi support these type of connections.
+
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 
@@ -2677,7 +2850,7 @@ CBFS (Coreboot Filesystem) support
 		CONFIG_RSA
 
 		This enables the RSA algorithm used for FIT image verification
-		in U-Boot. See doc/uImage/signature for more information.
+		in U-Boot. See doc/uImage.FIT/signature.txt for more information.
 
 		The signing part is build into mkimage regardless of this
 		option.
@@ -3109,7 +3282,7 @@ FIT uImage format:
 
 		CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 		Set for the SPL on PPC mpc8xxx targets, support for
-		arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+		drivers/ddr/fsl/libddr.o in SPL binary.
 
 		CONFIG_SPL_COMMON_INIT_DDR
 		Set for common ddr init with serial presence detect in
@@ -3123,6 +3296,9 @@ FIT uImage format:
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
 
+		CONFIG_SPL_NAND_BOOT
+		Add support NAND boot
+
 		CONFIG_SYS_NAND_U_BOOT_OFFS
 		Location in NAND to read U-Boot from
 
@@ -4266,6 +4442,9 @@ Low Level (hardware related) configuration options:
 
 		NOTE : currently only supported on AM335x platforms.
 
+- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
+		Enables the RTC32K OSC on AM33xx based plattforms
+
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 
@@ -5105,6 +5284,15 @@ when your kernel is intended to use an initial ramdisk:
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 
+The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i"
+option performs the converse operation of the mkimage's second form (the "-d"
+option). Given an image built by mkimage, the dumpimage extracts a "data file"
+from the image:
+
+	tools/dumpimage -i image -p position data_file
+	  -i ==> extract from the 'image' a specific 'data_file', \
+	   indexed by 'position'
+
 
 Installing a Linux Image:
 -------------------------

api/Makefile

@@ -4,21 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libapi.o
-
-COBJS-$(CONFIG_API) += api.o api_display.o api_net.o api_storage.o \
-		       api_platform-$(ARCH).o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y += api.o api_display.o api_net.o api_storage.o
+obj-$(CONFIG_ARM) += api_platform-arm.o
+obj-$(CONFIG_PPC) += api_platform-powerpc.o

arch/arc/config.mk

@@ -0,0 +1,31 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifndef CONFIG_SYS_BIG_ENDIAN
+CONFIG_SYS_LITTLE_ENDIAN = 1
+endif
+
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+CROSS_COMPILE ?= arc-buildroot-linux-uclibc-
+endif
+
+ifdef CONFIG_SYS_BIG_ENDIAN
+CROSS_COMPILE ?= arceb-buildroot-linux-uclibc-
+PLATFORM_LDFLAGS += -EB
+endif
+
+PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2
+
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+# Needed for relocation
+LDFLAGS_FINAL += -pie
+
+# Load address for standalone apps
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000
+
+# Support generic board on ARC
+__HAVE_ARCH_GENERIC_BOARD := y

arch/arc/cpu/arc700/Makefile

@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	+= start.o
+
+obj-y	+= cache.o
+obj-y	+= cpu.o
+obj-y	+= interrupts.o
+obj-y	+= reset.o
+obj-y	+= timer.o

arch/arc/cpu/arc700/cache.c

@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arcregs.h>
+
+/* Bit values in IC_CTRL */
+#define IC_CTRL_CACHE_DISABLE	(1 << 0)
+
+/* Bit values in DC_CTRL */
+#define DC_CTRL_CACHE_DISABLE	(1 << 0)
+#define DC_CTRL_INV_MODE_FLUSH	(1 << 6)
+#define DC_CTRL_FLUSH_STATUS	(1 << 8)
+
+int icache_status(void)
+{
+	return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
+	       IC_CTRL_CACHE_DISABLE;
+}
+
+void icache_enable(void)
+{
+	write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
+		      ~IC_CTRL_CACHE_DISABLE);
+}
+
+void icache_disable(void)
+{
+	write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+		      IC_CTRL_CACHE_DISABLE);
+}
+
+void invalidate_icache_all(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	/* Any write to IC_IVIC register triggers invalidation of entire I$ */
+	write_aux_reg(ARC_AUX_IC_IVIC, 1);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+
+int dcache_status(void)
+{
+	return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
+		DC_CTRL_CACHE_DISABLE;
+}
+
+void dcache_enable(void)
+{
+	write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
+		      ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
+}
+
+void dcache_disable(void)
+{
+	write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
+		      DC_CTRL_CACHE_DISABLE);
+}
+
+void flush_dcache_all(void)
+{
+	/* Do flush of entire cache */
+	write_aux_reg(ARC_AUX_DC_FLSH, 1);
+
+	/* Wait flush end */
+	while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+		;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+static void dcache_flush_line(unsigned addr)
+{
+#if (CONFIG_ARC_MMU_VER > 2)
+	write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+	write_aux_reg(ARC_AUX_DC_FLDL, addr);
+
+	/* Wait flush end */
+	while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+		;
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+	/*
+	 * Invalidate I$ for addresses range just flushed from D$.
+	 * If we try to execute data flushed above it will be valid/correct
+	 */
+#if (CONFIG_ARC_MMU_VER > 2)
+	write_aux_reg(ARC_AUX_IC_PTAG, addr);
+#endif
+	write_aux_reg(ARC_AUX_IC_IVIL, addr);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	unsigned int addr;
+
+	start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+	end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+	for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
+		dcache_flush_line(addr);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	unsigned int addr;
+
+	start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+	end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+	for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
+#if (CONFIG_ARC_MMU_VER > 2)
+		write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+		write_aux_reg(ARC_AUX_DC_IVDL, addr);
+	}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_all(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
+	write_aux_reg(ARC_AUX_DC_IVDC, 1);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}

arch/arc/cpu/arc700/config.mk

@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mA7

arch/arc/cpu/arc700/cpu.c

@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_SYS_ICACHE_OFF
+	icache_disable();
+#else
+	icache_enable();
+	invalidate_icache_all();
+#endif
+
+	flush_dcache_all();
+#ifdef CONFIG_SYS_DCACHE_OFF
+	dcache_disable();
+#else
+	dcache_enable();
+#endif
+	timer_init();
+
+/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
+	if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
+		gd->arch.running_on_hw = 0;
+	else
+		gd->arch.running_on_hw = 1;
+
+	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int arch_early_init_r(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}

arch/arc/cpu/arc700/interrupts.c

@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/ptrace.h>
+
+/* Bit values in STATUS32 */
+#define E1_MASK		(1 << 1)	/* Level 1 interrupts enable */
+#define E2_MASK		(1 << 2)	/* Level 2 interrupts enable */
+
+int interrupt_init(void)
+{
+	return 0;
+}
+
+/*
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts(void)
+{
+	int status = read_aux_reg(ARC_AUX_STATUS32);
+	int state = (status | E1_MASK | E2_MASK) ? 1 : 0;
+
+	status &= ~(E1_MASK | E2_MASK);
+	/* STATUS32 register is updated indirectly with "FLAG" instruction */
+	__asm__("flag %0" : : "r" (status));
+	return state;
+}
+
+void enable_interrupts(void)
+{
+	unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
+
+	status |= E1_MASK | E2_MASK;
+	/* STATUS32 register is updated indirectly with "FLAG" instruction */
+	__asm__("flag %0" : : "r" (status));
+}
+
+static void print_reg_file(long *reg_rev, int start_num)
+{
+	unsigned int i;
+
+	/* Print 3 registers per line */
+	for (i = start_num; i < start_num + 25; i++) {
+		printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
+		if (((i + 1) % 3) == 0)
+			printf("\n");
+
+		/* Because pt_regs has registers reversed */
+		reg_rev--;
+	}
+
+	/* Add new-line if none was inserted in the end of loop above */
+	if (((i + 1) % 3) != 0)
+		printf("\n");
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
+	       regs->ret, regs->blink, regs->status32);
+	printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
+	printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
+	       regs->sp, regs->fp);
+	printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
+	       regs->lp_end, regs->lp_count);
+
+	print_reg_file(&(regs->r0), 0);
+}
+
+void bad_mode(struct pt_regs *regs)
+{
+	if (regs)
+		show_regs(regs);
+
+	panic("Resetting CPU ...\n");
+}
+
+void do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+	printf("Memory error exception @ 0x%lx\n", address);
+	bad_mode(regs);
+}
+
+void do_instruction_error(unsigned long address, struct pt_regs *regs)
+{
+	printf("Instruction error exception @ 0x%lx\n", address);
+	bad_mode(regs);
+}
+
+void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
+{
+	printf("Machine check exception @ 0x%lx\n", address);
+	bad_mode(regs);
+}
+
+void do_interrupt_handler(void)
+{
+	printf("Interrupt fired\n");
+	bad_mode(0);
+}
+
+void do_itlb_miss(struct pt_regs *regs)
+{
+	printf("I TLB miss exception\n");
+	bad_mode(regs);
+}
+
+void do_dtlb_miss(struct pt_regs *regs)
+{
+	printf("D TLB miss exception\n");
+	bad_mode(regs);
+}
+
+void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
+{
+	printf("TLB protection violation or misaligned access @ 0x%lx\n",
+	       address);
+	bad_mode(regs);
+}
+
+void do_privilege_violation(struct pt_regs *regs)
+{
+	printf("Privilege violation exception\n");
+	bad_mode(regs);
+}
+
+void do_trap(struct pt_regs *regs)
+{
+	printf("Trap exception\n");
+	bad_mode(regs);
+}
+
+void do_extension(struct pt_regs *regs)
+{
+	printf("Extension instruction exception\n");
+	bad_mode(regs);
+}

arch/arc/cpu/arc700/reset.c

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <command.h>
+#include <common.h>
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	printf("Put your restart handler here\n");
+
+#ifdef DEBUG
+	/* Stop debug session here */
+	__asm__("brk");
+#endif
+	return 0;
+}

arch/arc/cpu/arc700/start.S

@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arcregs.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a    reg1, [reg2, x]  => Pre Incr
+ *      Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab   reg1, [reg2, x]  => Post Incr
+ *      Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+	st.a	\reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+	lr	%r9, [\aux]
+	PUSH	%r9
+.endm
+
+.macro  SAVE_R1_TO_R24
+	PUSH	%r1
+	PUSH	%r2
+	PUSH	%r3
+	PUSH	%r4
+	PUSH	%r5
+	PUSH	%r6
+	PUSH	%r7
+	PUSH	%r8
+	PUSH	%r9
+	PUSH	%r10
+	PUSH	%r11
+	PUSH	%r12
+	PUSH	%r13
+	PUSH	%r14
+	PUSH	%r15
+	PUSH	%r16
+	PUSH	%r17
+	PUSH	%r18
+	PUSH	%r19
+	PUSH	%r20
+	PUSH	%r21
+	PUSH	%r22
+	PUSH	%r23
+	PUSH	%r24
+.endm
+
+.macro SAVE_ALL_SYS
+
+	st	%r0, [%sp]
+	lr	%r0, [%ecr]
+	st	%r0, [%sp, 8]	/* ECR */
+	st	%sp, [%sp, 4]
+
+	SAVE_R1_TO_R24
+	PUSH	%r25
+	PUSH	%gp
+	PUSH	%fp
+	PUSH	%blink
+	PUSHAX	%eret
+	PUSHAX	%erstatus
+	PUSH	%lp_count
+	PUSHAX	%lp_end
+	PUSHAX	%lp_start
+	PUSHAX	%erbta
+.endm
+
+.align 4
+.globl _start
+_start:
+	/* Critical system events */
+	j	reset			/* 0 - 0x000 */
+	j	memory_error		/* 1 - 0x008 */
+	j	instruction_error	/* 2 - 0x010 */
+
+	/* Device interrupts */
+.rept	29
+	j	interrupt_handler	/* 3:31 - 0x018:0xF8 */
+.endr
+	/* Exceptions */
+	j	EV_MachineCheck		/* 0x100, Fatal Machine check  (0x20) */
+	j	EV_TLBMissI		/* 0x108, Intruction TLB miss  (0x21) */
+	j	EV_TLBMissD		/* 0x110, Data TLB miss        (0x22) */
+	j	EV_TLBProtV		/* 0x118, Protection Violation (0x23)
+							or Misaligned Access  */
+	j	EV_PrivilegeV		/* 0x120, Privilege Violation  (0x24) */
+	j	EV_Trap			/* 0x128, Trap exception       (0x25) */
+	j	EV_Extension		/* 0x130, Extn Intruction Excp (0x26) */
+
+memory_error:
+	SAVE_ALL_SYS
+	lr	%r0, [%efa]
+	mov	%r1, %sp
+	j	do_memory_error
+
+instruction_error:
+	SAVE_ALL_SYS
+	lr	%r0, [%efa]
+	mov	%r1, %sp
+	j	do_instruction_error
+
+interrupt_handler:
+	/* Todo - save and restore CPU context when interrupts will be in use */
+	bl	do_interrupt_handler
+	rtie
+
+EV_MachineCheck:
+	SAVE_ALL_SYS
+	lr	%r0, [%efa]
+	mov	%r1, %sp
+	j	do_machine_check_fault
+
+EV_TLBMissI:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_itlb_miss
+
+EV_TLBMissD:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_dtlb_miss
+
+EV_TLBProtV:
+	SAVE_ALL_SYS
+	lr	%r0, [%efa]
+	mov	%r1, %sp
+	j	do_tlb_prot_violation
+
+EV_PrivilegeV:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_privilege_violation
+
+EV_Trap:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_trap
+
+EV_Extension:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_extension
+
+
+reset:
+	/* Setup interrupt vector base that matches "__text_start" */
+	sr	__text_start, [ARC_AUX_INTR_VEC_BASE]
+
+	/* Setup stack pointer */
+	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
+	mov	%fp, %sp
+
+	/* Clear bss */
+	mov	%r0, __bss_start
+	mov	%r1, __bss_end
+
+clear_bss:
+	st.ab	0, [%r0, 4]
+	brlt	%r0, %r1, clear_bss
+
+	/* Zero the one and only argument of "board_init_f" */
+	mov_s	%r0, 0
+	j	board_init_f
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = start_addr_sp
+ * r1 = new__gd
+ * r2 = relocaddr
+ */
+.align 4
+.globl	relocate_code
+relocate_code:
+	/*
+	 * r0-r12 might be clobbered by C functions
+	 * so we use r13-r16 for storage here
+	 */
+	mov	%r13, %r0		/* save addr_sp */
+	mov	%r14, %r1		/* save addr of gd */
+	mov	%r15, %r2		/* save addr of destination */
+
+	mov	%r16, %r2		/* %r9 - relocation offset */
+	sub	%r16, %r16, __image_copy_start
+
+/* Set up the stack */
+stack_setup:
+	mov	%sp, %r13
+	mov	%fp, %sp
+
+/* Check if monitor is loaded right in place for relocation */
+	mov	%r0, __image_copy_start
+	cmp	%r0, %r15		/* skip relocation if code loaded */
+	bz	do_board_init_r		/* in target location already */
+
+/* Copy data (__image_copy_start - __image_copy_end) to new location */
+	mov	%r1, %r15
+	mov	%r2, __image_copy_end
+	sub	%r2, %r2, %r0		/* r3 <- amount of bytes to copy */
+	asr	%r2, %r2, 2		/* r3 <- amount of words to copy */
+	mov	%lp_count, %r2
+	lp	copy_end
+	ld.ab	%r2,[%r0,4]
+	st.ab	%r2,[%r1,4]
+copy_end:
+
+/* Fix relocations related issues */
+	bl	do_elf_reloc_fixups
+#ifndef CONFIG_SYS_ICACHE_OFF
+	bl	invalidate_icache_all
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	bl	flush_dcache_all
+#endif
+
+/* Update position of intterupt vector table */
+	lr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Read current position */
+	add	%r0, %r0, %r16			/* Update address */
+	sr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Write new position */
+
+do_board_init_r:
+/* Prepare for exection of "board_init_r" in relocated monitor */
+	mov	%r2, board_init_r	/* old address of "board_init_r()" */
+	add	%r2, %r2, %r16		/* new address of "board_init_r()" */
+	mov	%r0, %r14		/* 1-st parameter: gd_t */
+	mov	%r1, %r15		/* 2-nd parameter: dest_addr */
+	j	[%r2]

arch/arc/cpu/arc700/timer.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arcregs.h>
+
+#define NH_MODE	(1 << 1)	/* Disable timer if CPU is halted */
+
+int timer_init(void)
+{
+	write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
+	/* Set max value for counter/timer */
+	write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
+	/* Set initial count value and restart counter/timer */
+	write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
+	return 0;
+}
+
+unsigned long timer_read_counter(void)
+{
+	return read_aux_reg(ARC_AUX_TIMER0_CNT);
+}

arch/arc/cpu/arc700/u-boot.lds

@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
+OUTPUT_ARCH(arc)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :	{
+		*(.__text_start)
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.text_end :
+	{
+		*(.__text_end)
+	}
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+	.rel_dyn_start : {
+		*(.__rel_dyn_start)
+	}
+
+	.rela.dyn : {
+		*(.rela.dyn)
+	}
+
+	.rel_dyn_end : {
+		*(.__rel_dyn_end)
+	}
+
+	. = ALIGN(4);
+	.bss_start : {
+		*(.__bss_start);
+	}
+
+	.bss : {
+		*(.bss*)
+	}
+
+	.bss_end : {
+		*(.__bss_end);
+	}
+
+	. = ALIGN(4);
+	.image_copy_end : {
+		*(.__image_copy_end)
+		*(.__init_end)
+	}
+}

arch/arc/include/asm/arch-arc700/hardware.h

@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file is only required to allow compilation of "designware_i2c" driver.
+ * Which explicitly includes <asm/arch/hardware.h>.
+ */

arch/arc/include/asm/arcregs.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_ARCREGS_H
+#define _ASM_ARC_ARCREGS_H
+
+/*
+ * ARC architecture has additional address space - auxiliary registers.
+ * These registers are mostly used for configuration purposes.
+ * These registers are not memory mapped and special commands are used for
+ * access: "lr"/"sr".
+ */
+
+#define ARC_AUX_IDENTITY	0x04
+#define ARC_AUX_STATUS32	0x0a
+
+/* Instruction cache related auxiliary registers */
+#define ARC_AUX_IC_IVIC		0x10
+#define ARC_AUX_IC_CTRL		0x11
+#define ARC_AUX_IC_IVIL		0x19
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_AUX_IC_PTAG		0x1E
+#endif
+
+/* Timer related auxiliary registers */
+#define ARC_AUX_TIMER0_CNT	0x21	/* Timer 0 count */
+#define ARC_AUX_TIMER0_CTRL	0x22	/* Timer 0 control */
+#define ARC_AUX_TIMER0_LIMIT	0x23	/* Timer 0 limit */
+
+#define ARC_AUX_INTR_VEC_BASE	0x25
+
+/* Data cache related auxiliary registers */
+#define ARC_AUX_DC_IVDC		0x47
+#define ARC_AUX_DC_CTRL		0x48
+
+#define ARC_AUX_DC_IVDL		0x4A
+#define ARC_AUX_DC_FLSH		0x4B
+#define ARC_AUX_DC_FLDL		0x4C
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_AUX_DC_PTAG		0x5C
+#endif
+
+#ifndef __ASSEMBLY__
+/* Accessors for auxiliary registers */
+#define read_aux_reg(reg)	__builtin_arc_lr(reg)
+
+/* gcc builtin sr needs reg param to be long immediate */
+#define write_aux_reg(reg_immed, val)		\
+		__builtin_arc_sr((unsigned int)val, reg_immed)
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARC_ARCREGS_H */

arch/arc/include/asm/bitops.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_BITOPS_H
+#define __ASM_ARC_BITOPS_H
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __ASM_ARC_BITOPS_H */

arch/arc/include/asm/byteorder.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_BYTEORDER_H
+#define __ASM_ARC_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+	#define __BYTEORDER_HAS_U64__
+	#define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __LITTLE_ENDIAN__
+	#include <linux/byteorder/little_endian.h>
+#else
+	#include <linux/byteorder/big_endian.h>
+#endif	/* CONFIG_SYS_BIG_ENDIAN */
+
+#endif	/* ASM_ARC_BYTEORDER_H */

arch/arc/include/asm/cache.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_CACHE_H
+#define __ASM_ARC_CACHE_H
+
+#include <config.h>
+
+/*
+ * The current upper bound for ARC L1 data cache line sizes is 128 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	128
+#endif
+
+#endif /* __ASM_ARC_CACHE_H */

arch/arc/include/asm/config.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_CONFIG_H_
+#define __ASM_ARC_CONFIG_H_
+
+#define CONFIG_LMB
+
+#endif /*__ASM_ARC_CONFIG_H_ */

arch/arc/include/asm/errno.h

@@ -0,0 +1 @@
+#include <asm-generic/errno.h>

arch/arc/include/asm/global_data.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__ASM_ARC_GLOBAL_DATA_H
+#define __ASM_ARC_GLOBAL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+	int running_on_hw;
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("r25")
+
+#endif /* __ASM_ARC_GLOBAL_DATA_H */

arch/arc/include/asm/io.h

@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_IO_H
+#define __ASM_ARC_IO_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+	/* Not yet implemented */
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+	u8 b;
+
+	__asm__ __volatile__("ldb%U1	%0, %1\n"
+			     : "=r" (b)
+			     : "m" (*(volatile u8 __force *)addr)
+			     : "memory");
+	return b;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+	u16 s;
+
+	__asm__ __volatile__("ldw%U1	%0, %1\n"
+			     : "=r" (s)
+			     : "m" (*(volatile u16 __force *)addr)
+			     : "memory");
+	return s;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+	u32 w;
+
+	__asm__ __volatile__("ld%U1	%0, %1\n"
+			     : "=r" (w)
+			     : "m" (*(volatile u32 __force *)addr)
+			     : "memory");
+	return w;
+}
+
+#define readb __raw_readb
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+	return __le16_to_cpu(__raw_readw(addr));
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+	return __le32_to_cpu(__raw_readl(addr));
+}
+
+static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
+{
+	__asm__ __volatile__("stb%U1	%0, %1\n"
+			     :
+			     : "r" (b), "m" (*(volatile u8 __force *)addr)
+			     : "memory");
+}
+
+static inline void __raw_writew(u16 s, volatile void __iomem *addr)
+{
+	__asm__ __volatile__("stw%U1	%0, %1\n"
+			     :
+			     : "r" (s), "m" (*(volatile u16 __force *)addr)
+			     : "memory");
+}
+
+static inline void __raw_writel(u32 w, volatile void __iomem *addr)
+{
+	__asm__ __volatile__("st%U1	%0, %1\n"
+			     :
+			     : "r" (w), "m" (*(volatile u32 __force *)addr)
+			     : "memory");
+}
+
+#define writeb __raw_writeb
+#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr)
+#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr)
+
+static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "stb.ab	r8, [r1, 1]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (bytelen)
+			      : "r8");
+	return bytelen;
+}
+
+static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "stw.ab	r8, [r1, 2]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (wordlen)
+			      : "r8");
+	return wordlen;
+}
+
+static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab	r8, [r1, 4]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (longlen)
+			      : "r8");
+	return longlen;
+}
+
+static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
+{
+	__asm__ __volatile__ ("1:ldb.ab	r8, [r1, 1]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (bytelen)
+			      : "r8");
+	return bytelen;
+}
+
+static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
+{
+	__asm__ __volatile__ ("1:ldw.ab	r8, [r1, 2]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (wordlen)
+			      : "r8");
+	return wordlen;
+}
+
+static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
+{
+	__asm__ __volatile__ ("1:ld.ab	r8, [r1, 4]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (longlen)
+			      : "r8");
+	return longlen;
+}
+
+#define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v)	out_arch(l, le32, a, v)
+#define out_le16(a, v)	out_arch(w, le16, a, v)
+
+#define in_le32(a)	in_arch(l, le32, a)
+#define in_le16(a)	in_arch(w, le16, a)
+
+#define out_be32(a, v)	out_arch(l, be32, a, v)
+#define out_be16(a, v)	out_arch(w, be16, a, v)
+
+#define in_be32(a)	in_arch(l, be32, a)
+#define in_be16(a)	in_arch(w, be16, a)
+
+#define out_8(a, v)	__raw_writeb(v, a)
+#define in_8(a)		__raw_readb(a)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#endif	/* __ASM_ARC_IO_H */

arch/arc/include/asm/posix_types.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_POSIX_TYPES_H
+#define __ASM_ARC_POSIX_TYPES_H
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+#endif	/* __ASM_ARC_POSIX_TYPES_H */

arch/arc/include/asm/ptrace.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_PTRACE_H
+#define __ASM_ARC_PTRACE_H
+
+struct pt_regs {
+	long bta;
+	long lp_start;
+	long lp_end;
+	long lp_count;
+	long status32;
+	long ret;
+	long blink;
+	long fp;
+	long r26;	/* gp */
+	long r25;
+	long r24;
+	long r23;
+	long r22;
+	long r21;
+	long r20;
+	long r19;
+	long r18;
+	long r17;
+	long r16;
+	long r15;
+	long r14;
+	long r13;
+	long r12;
+	long r11;
+	long r10;
+	long r9;
+	long r8;
+	long r7;
+	long r6;
+	long r5;
+	long r4;
+	long r3;
+	long r2;
+	long r1;
+	long r0;
+	long sp;
+	long ecr;
+};
+
+#endif /* __ASM_ARC_PTRACE_H */

arch/arc/include/asm/sections.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_SECTIONS_H
+#define __ASM_ARC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern ulong __text_end;
+
+#endif /* __ASM_ARC_SECTIONS_H */

arch/arc/include/asm/string.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_STRING_H
+#define __ASM_ARC_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_STRCHR
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRLEN
+
+extern void *memset(void *ptr, int, __kernel_size_t);
+extern void *memcpy(void *, const void *, __kernel_size_t);
+extern void memzero(void *ptr, __kernel_size_t n);
+extern int memcmp(const void *, const void *, __kernel_size_t);
+extern char *strchr(const char *s, int c);
+extern char *strcpy(char *dest, const char *src);
+extern int strcmp(const char *cs, const char *ct);
+extern __kernel_size_t strlen(const char *);
+
+#endif /* __ASM_ARC_STRING_H */

arch/arc/include/asm/types.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_TYPES_H
+#define __ASM_ARC_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __ASM_ARC_TYPES_H */

arch/arc/include/asm/u-boot-arc.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_U_BOOT_ARC_H__
+#define __ASM_ARC_U_BOOT_ARC_H__
+
+int arch_early_init_r(void);
+
+#endif	/* __ASM_ARC_U_BOOT_ARC_H__ */

arch/arc/include/asm/u-boot.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_U_BOOT_H__
+#define __ASM_ARC_U_BOOT_H__
+
+#include <asm-generic/u-boot.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_ARC
+
+#endif	/* __ASM_ARC_U_BOOT_H__ */

arch/arc/include/asm/unaligned.h

@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>

arch/arc/lib/Makefile

@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sections.o
+obj-y += relocate.o
+obj-y += strchr-700.o
+obj-y += strcmp.o
+obj-y += strcpy-700.o
+obj-y += strlen.o
+obj-y += memcmp.o
+obj-y += memcpy-700.o
+obj-y += memset.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o

arch/arc/lib/bootm.c

@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong get_sp(void)
+{
+	ulong ret;
+
+	asm("mov %0, sp" : "=r"(ret) : );
+	return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+	ulong sp;
+
+	/*
+	 * Booting a (Linux) kernel image
+	 *
+	 * Allocate space for command line and board info - the
+	 * address should be as high as possible within the reach of
+	 * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+	 * memory, which means far enough below the current stack
+	 * pointer.
+	 */
+	sp = get_sp();
+	debug("## Current stack ends at 0x%08lx ", sp);
+
+	/* adjust sp by 4K to be safe */
+	sp -= 4096;
+	lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
+}
+
+static int cleanup_before_linux(void)
+{
+	disable_interrupts();
+	flush_dcache_all();
+	invalidate_icache_all();
+
+	return 0;
+}
+
+/* Subcommand: PREP */
+static void boot_prep_linux(bootm_headers_t *images)
+{
+	if (image_setup_linux(images))
+		hang();
+}
+
+/* Subcommand: GO */
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+	void (*kernel_entry)(int zero, int arch, uint params);
+	unsigned int r0, r2;
+	int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
+	kernel_entry = (void (*)(int, int, uint))images->ep;
+
+	debug("## Transferring control to Linux (at address %08lx)...\n",
+	      (ulong) kernel_entry);
+	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+	printf("\nStarting kernel ...%s\n\n", fake ?
+	       "(fake run for tracing)" : "");
+	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+
+	cleanup_before_linux();
+
+	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+		r0 = 2;
+		r2 = (unsigned int)images->ft_addr;
+	} else {
+		r0 = 1;
+		r2 = (unsigned int)getenv("bootargs");
+	}
+
+	if (!fake)
+		kernel_entry(r0, 0, r2);
+}
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	/* No need for those on ARC */
+	if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
+		return -1;
+
+	if (flag & BOOTM_STATE_OS_PREP) {
+		boot_prep_linux(images);
+		return 0;
+	}
+
+	if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+		boot_jump_linux(images, flag);
+		return 0;
+	}
+
+	boot_prep_linux(images);
+	boot_jump_linux(images, flag);
+	return 0;
+}

arch/arc/lib/memcmp.S

@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifdef __LITTLE_ENDIAN__
+#define WORD2 r2
+#define SHIFT r3
+#else /* __BIG_ENDIAN__ */
+#define WORD2 r3
+#define SHIFT r2
+#endif /* _ENDIAN__ */
+
+.global memcmp
+.align 4
+memcmp:
+	or	%r12, %r0, %r1
+	asl_s	%r12, %r12, 30
+	sub	%r3, %r2, 1
+	brls	%r2, %r12, .Lbytewise
+	ld	%r4, [%r0, 0]
+	ld	%r5, [%r1, 0]
+	lsr.f	%lp_count, %r3, 3
+	lpne	.Loop_end
+	ld_s	WORD2, [%r0, 4]
+	ld_s	%r12, [%r1, 4]
+	brne	%r4, %r5, .Leven
+	ld.a	%r4, [%r0, 8]
+	ld.a	%r5, [%r1, 8]
+	brne	WORD2, %r12, .Lodd
+.Loop_end:
+	asl_s	SHIFT, SHIFT, 3
+	bhs_s	.Last_cmp
+	brne	%r4, %r5, .Leven
+	ld	%r4, [%r0, 4]
+	ld	%r5, [%r1, 4]
+#ifdef __LITTLE_ENDIAN__
+	nop_s
+	/* one more load latency cycle */
+.Last_cmp:
+	xor	%r0, %r4, %r5
+	bset	%r0, %r0, SHIFT
+	sub_s	%r1, %r0, 1
+	bic_s	%r1, %r1, %r0
+	norm	%r1, %r1
+	b.d	.Leven_cmp
+	and	%r1, %r1, 24
+.Leven:
+	xor	%r0, %r4, %r5
+	sub_s	%r1, %r0, 1
+	bic_s	%r1, %r1, %r0
+	norm	%r1, %r1
+	/* slow track insn */
+	and	%r1, %r1, 24
+.Leven_cmp:
+	asl	%r2, %r4, %r1
+	asl	%r12, %r5, %r1
+	lsr_s	%r2, %r2, 1
+	lsr_s	%r12, %r12, 1
+	j_s.d	[%blink]
+	sub	%r0, %r2, %r12
+	.balign	4
+.Lodd:
+	xor	%r0, WORD2, %r12
+	sub_s	%r1, %r0, 1
+	bic_s	%r1, %r1, %r0
+	norm	%r1, %r1
+	/* slow track insn */
+	and	%r1, %r1, 24
+	asl_s	%r2, %r2, %r1
+	asl_s	%r12, %r12, %r1
+	lsr_s	%r2, %r2, 1
+	lsr_s	%r12, %r12, 1
+	j_s.d	[%blink]
+	sub	%r0, %r2, %r12
+#else /* __BIG_ENDIAN__ */
+.Last_cmp:
+	neg_s	SHIFT, SHIFT
+	lsr	%r4, %r4, SHIFT
+	lsr	%r5, %r5, SHIFT
+	/* slow track insn */
+.Leven:
+	sub.f	%r0, %r4, %r5
+	mov.ne	%r0, 1
+	j_s.d	[%blink]
+	bset.cs	%r0, %r0, 31
+.Lodd:
+	cmp_s	WORD2, %r12
+
+	mov_s	%r0, 1
+	j_s.d	[%blink]
+	bset.cs	%r0, %r0, 31
+#endif /* _ENDIAN__ */
+	.balign	4
+.Lbytewise:
+	breq	%r2, 0, .Lnil
+	ldb	%r4, [%r0, 0]
+	ldb	%r5, [%r1, 0]
+	lsr.f	%lp_count, %r3
+	lpne	.Lbyte_end
+	ldb_s	%r3, [%r0, 1]
+	ldb	%r12, [%r1, 1]
+	brne	%r4, %r5, .Lbyte_even
+	ldb.a	%r4, [%r0, 2]
+	ldb.a	%r5, [%r1, 2]
+	brne	%r3, %r12, .Lbyte_odd
+.Lbyte_end:
+	bcc	.Lbyte_even
+	brne	%r4, %r5, .Lbyte_even
+	ldb_s	%r3, [%r0, 1]
+	ldb_s	%r12, [%r1, 1]
+.Lbyte_odd:
+	j_s.d	[%blink]
+	sub	%r0, %r3, %r12
+.Lbyte_even:
+	j_s.d	[%blink]
+	sub	%r0, %r4, %r5
+.Lnil:
+	j_s.d	[%blink]
+	mov	%r0, 0

arch/arc/lib/memcpy-700.S

@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.global memcpy
+.align 4
+memcpy:
+	or	%r3, %r0, %r1
+	asl_s	%r3, %r3, 30
+	mov_s	%r5, %r0
+	brls.d	%r2, %r3, .Lcopy_bytewise
+	sub.f	%r3, %r2, 1
+	ld_s	%r12, [%r1, 0]
+	asr.f	%lp_count, %r3, 3
+	bbit0.d	%r3, 2, .Lnox4
+	bmsk_s	%r2, %r2, 1
+	st.ab	%r12, [%r5, 4]
+	ld.a	%r12, [%r1, 4]
+.Lnox4:
+	lppnz	.Lendloop
+	ld_s	%r3, [%r1, 4]
+	st.ab	%r12, [%r5, 4]
+	ld.a	%r12, [%r1, 8]
+	st.ab	%r3, [%r5, 4]
+.Lendloop:
+	breq	%r2, 0, .Last_store
+	ld	%r3, [%r5, 0]
+#ifdef __LITTLE_ENDIAN__
+	add3	%r2, -1, %r2
+	/* uses long immediate */
+	xor_s	%r12, %r12, %r3
+	bmsk	%r12, %r12, %r2
+	xor_s	%r12, %r12, %r3
+#else /* __BIG_ENDIAN__ */
+	sub3	%r2, 31, %r2
+	/* uses long immediate */
+	xor_s	%r3, %r3, %r12
+	bmsk	%r3, %r3, %r2
+	xor_s	%r12, %r12, %r3
+#endif /* _ENDIAN__ */
+.Last_store:
+	j_s.d	[%blink]
+	st	%r12, [%r5, 0]
+
+	.balign	4
+.Lcopy_bytewise:
+	jcs	[%blink]
+	ldb_s	%r12, [%r1, 0]
+	lsr.f	%lp_count, %r3
+	bhs_s	.Lnox1
+	stb.ab	%r12, [%r5, 1]
+	ldb.a	%r12, [%r1, 1]
+.Lnox1:
+	lppnz	.Lendbloop
+	ldb_s	%r3, [%r1, 1]
+	stb.ab	%r12, [%r5, 1]
+	ldb.a	%r12, [%r1, 2]
+	stb.ab	%r3, [%r5, 1]
+.Lendbloop:
+	j_s.d	[%blink]
+	stb	%r12, [%r5, 0]

arch/arc/lib/memset.S

@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SMALL	7 /* Must be at least 6 to deal with alignment/loop issues.  */
+
+.global memset
+.align 4
+memset:
+	mov_s	%r4, %r0
+	or	%r12, %r0, %r2
+	bmsk.f	%r12, %r12, 1
+	extb_s	%r1, %r1
+	asl	%r3, %r1, 8
+	beq.d	.Laligned
+	or_s	%r1, %r1, %r3
+	brls	%r2, SMALL, .Ltiny
+	add	%r3, %r2, %r0
+	stb	%r1, [%r3, -1]
+	bclr_s	%r3, %r3, 0
+	stw	%r1, [%r3, -2]
+	bmsk.f	%r12, %r0, 1
+	add_s	%r2, %r2, %r12
+	sub.ne	%r2, %r2, 4
+	stb.ab	%r1, [%r4, 1]
+	and	%r4, %r4, -2
+	stw.ab	%r1, [%r4, 2]
+	and	%r4, %r4, -4
+
+	.balign	4
+.Laligned:
+	asl	%r3, %r1, 16
+	lsr.f	%lp_count, %r2, 2
+	or_s	%r1, %r1, %r3
+	lpne	.Loop_end
+	st.ab	%r1, [%r4, 4]
+.Loop_end:
+	j_s	[%blink]
+
+	.balign	4
+.Ltiny:
+	mov.f	%lp_count, %r2
+	lpne	.Ltiny_end
+	stb.ab	%r1, [%r4, 1]
+.Ltiny_end:
+	j_s	[%blink]
+
+/*
+ * memzero: @r0 = mem, @r1 = size_t
+ * memset:  @r0 = mem, @r1 = char, @r2 = size_t
+ */
+
+.global memzero
+.align 4
+memzero:
+	/* adjust bzero args to memset args */
+	mov	%r2, %r1
+	mov	%r1, 0
+	/* tail call so need to tinker with blink */
+	b	memset

arch/arc/lib/relocate.c

@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <elf.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Base functionality is taken from x86 version with added ARC-specifics
+ */
+int do_elf_reloc_fixups(void)
+{
+	Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
+	Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
+
+	Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
+	Elf32_Addr *offset_ptr_ram;
+
+	do {
+		/* Get the location from the relocation entry */
+		offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
+
+		/* Check that the location of the relocation is in .text */
+		if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE &&
+		    offset_ptr_rom > last_offset) {
+			unsigned int val;
+			/* Switch to the in-RAM version */
+			offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
+							gd->reloc_off);
+
+			/*
+			 * Use "memcpy" because target location might be
+			 * 16-bit aligned on ARC so we may need to read
+			 * byte-by-byte. On attempt to read entire word by
+			 * CPU throws an exception
+			 */
+			memcpy(&val, offset_ptr_ram, sizeof(int));
+
+			/* If location in ".text" section swap value */
+			if ((unsigned int)offset_ptr_rom <
+			    (unsigned int)&__text_end)
+				val = (val << 16) | (val >> 16);
+
+			/* Check that the target points into .text */
+			if (val >= CONFIG_SYS_TEXT_BASE && val <=
+			    (unsigned int)&__bss_end) {
+				val += gd->reloc_off;
+				/* If location in ".text" section swap value */
+				if ((unsigned int)offset_ptr_rom <
+				    (unsigned int)&__text_end)
+					val = (val << 16) | (val >> 16);
+				memcpy(offset_ptr_ram, &val, sizeof(int));
+			} else {
+				debug("   %p: rom reloc %x, ram %p, value %x, limit %x\n",
+				      re_src, re_src->r_offset, offset_ptr_ram,
+				      val, (unsigned int)&__bss_end);
+			}
+		} else {
+			debug("   %p: rom reloc %x, last %p\n", re_src,
+			      re_src->r_offset, last_offset);
+		}
+		last_offset = offset_ptr_rom;
+
+	} while (++re_src < re_end);
+
+	return 0;
+}

arch/arc/lib/sections.c

@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * For some reason linker sets linker-generated symbols to zero in PIE mode.
+ * A work-around is substitution of linker-generated symbols with
+ * compiler-generated symbols which are properly handled by linker in PAE mode.
+ */
+
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
+char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
+char __text_start[0] __attribute__((section(".__text_start")));
+char __text_end[0] __attribute__((section(".__text_end")));
+char __init_end[0] __attribute__((section(".__init_end")));

arch/arc/lib/strchr-700.S

@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * ARC700 has a relatively long pipeline and branch prediction, so we want
+ * to avoid branches that are hard to predict.  On the other hand, the
+ * presence of the norm instruction makes it easier to operate on whole
+ * words branch-free.
+ */
+
+.global strchr
+.align 4
+strchr:
+	extb_s	%r1, %r1
+	asl	%r5, %r1, 8
+	bmsk	%r2, %r0, 1
+	or	%r5, %r5, %r1
+	mov_s	%r3, 0x01010101
+	breq.d	%r2, %r0, .Laligned
+	asl	%r4, %r5, 16
+	sub_s	%r0, %r0, %r2
+	asl	%r7, %r2, 3
+	ld_s	%r2, [%r0]
+#ifdef __LITTLE_ENDIAN__
+	asl	%r7, %r3, %r7
+#else /* __BIG_ENDIAN__ */
+	lsr	%r7, %r3, %r7
+#endif /* _ENDIAN__ */
+	or	%r5, %r5, %r4
+	ror	%r4, %r3
+	sub	%r12, %r2, %r7
+	bic_s	%r12, %r12, %r2
+	and	%r12, %r12, %r4
+	brne.d	%r12, 0, .Lfound0_ua
+	xor	%r6, %r2, %r5
+	ld.a	%r2, [%r0, 4]
+	sub	%r12, %r6, %r7
+	bic	%r12, %r12, %r6
+#ifdef __LITTLE_ENDIAN__
+	and	%r7, %r12, %r4
+	/* For speed, we want this branch to be unaligned. */
+	breq	%r7, 0, .Loop
+	/* Likewise this one */
+	b	.Lfound_char
+#else /* __BIG_ENDIAN__ */
+	and	%r12, %r12, %r4
+	/* For speed, we want this branch to be unaligned. */
+	breq	%r12, 0, .Loop
+	lsr_s	%r12, %r12, 7
+	bic 	%r2, %r7, %r6
+	b.d	.Lfound_char_b
+	and_s	%r2, %r2, %r12
+#endif /* _ENDIAN__ */
+	/* We require this code address to be unaligned for speed...  */
+.Laligned:
+	ld_s	%r2, [%r0]
+	or	%r5, %r5, %r4
+	ror	%r4, %r3
+	/* ... so that this code address is aligned, for itself and ...  */
+.Loop:
+	sub	%r12, %r2, %r3
+	bic_s	%r12, %r12, %r2
+	and	%r12, %r12, %r4
+	brne.d	%r12, 0, .Lfound0
+	xor	%r6, %r2, %r5
+	ld.a	%r2, [%r0, 4]
+	sub	%r12, %r6, %r3
+	bic	%r12, %r12, %r6
+	and	%r7, %r12, %r4
+	breq	%r7, 0, .Loop
+	/*
+	 *... so that this branch is unaligned.
+	 * Found searched-for character.
+	 * r0 has already advanced to next word.
+	 */
+#ifdef __LITTLE_ENDIAN__
+	/*
+	 * We only need the information about the first matching byte
+	 * (i.e. the least significant matching byte) to be exact,
+	 * hence there is no problem with carry effects.
+	 */
+.Lfound_char:
+	sub	%r3, %r7, 1
+	bic	%r3, %r3, %r7
+	norm	%r2, %r3
+	sub_s	%r0, %r0, 1
+	asr_s	%r2, %r2, 3
+	j.d	[%blink]
+	sub_s	%r0, %r0, %r2
+
+	.balign	4
+.Lfound0_ua:
+	mov	%r3, %r7
+.Lfound0:
+	sub	%r3, %r6, %r3
+	bic	%r3, %r3, %r6
+	and	%r2, %r3, %r4
+	or_s	%r12, %r12, %r2
+	sub_s	%r3, %r12, 1
+	bic_s	%r3, %r3, %r12
+	norm	%r3, %r3
+	add_s	%r0, %r0, 3
+	asr_s	%r12, %r3, 3
+	asl.f	0, %r2, %r3
+	sub_s	%r0, %r0, %r12
+	j_s.d	[%blink]
+	mov.pl	%r0, 0
+#else /* __BIG_ENDIAN__ */
+.Lfound_char:
+	lsr	%r7, %r7, 7
+
+	bic	%r2, %r7, %r6
+.Lfound_char_b:
+	norm	%r2, %r2
+	sub_s	%r0, %r0, 4
+	asr_s	%r2, %r2, 3
+	j.d	[%blink]
+	add_s	%r0, %r0, %r2
+
+.Lfound0_ua:
+	mov_s	%r3, %r7
+.Lfound0:
+	asl_s	%r2, %r2, 7
+	or	%r7, %r6, %r4
+	bic_s	%r12, %r12, %r2
+	sub	%r2, %r7, %r3
+	or	%r2, %r2, %r6
+	bic	%r12, %r2, %r12
+	bic.f	%r3, %r4, %r12
+	norm	%r3, %r3
+
+	add.pl	%r3, %r3, 1
+	asr_s	%r12, %r3, 3
+	asl.f	0, %r2, %r3
+	add_s	%r0, %r0, %r12
+	j_s.d	[%blink]
+	mov.mi	%r0, 0
+#endif /* _ENDIAN__ */

arch/arc/lib/strcmp.S

@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This is optimized primarily for the ARC700.
+ * It would be possible to speed up the loops by one cycle / word
+ * respective one cycle / byte by forcing double source 1 alignment, unrolling
+ * by a factor of two, and speculatively loading the second word / byte of
+ * source 1; however, that would increase the overhead for loop setup / finish,
+ * and strcmp might often terminate early.
+ */
+
+.global strcmp
+.align 4
+strcmp:
+	or	%r2, %r0, %r1
+	bmsk_s	%r2, %r2, 1
+	brne	%r2, 0, .Lcharloop
+	mov_s	%r12, 0x01010101
+	ror	%r5, %r12
+.Lwordloop:
+	ld.ab	%r2, [%r0, 4]
+	ld.ab	%r3, [%r1, 4]
+	nop_s
+	sub	%r4, %r2, %r12
+	bic	%r4, %r4, %r2
+	and	%r4, %r4, %r5
+	brne	%r4, 0, .Lfound0
+	breq	%r2 ,%r3, .Lwordloop
+#ifdef	__LITTLE_ENDIAN__
+	xor	%r0, %r2, %r3	/* mask for difference */
+	sub_s	%r1, %r0, 1
+	bic_s	%r0, %r0, %r1	/* mask for least significant difference bit */
+	sub	%r1, %r5, %r0
+	xor	%r0, %r5, %r1	/* mask for least significant difference byte */
+	and_s	%r2, %r2, %r0
+	and_s	%r3, %r3, %r0
+#endif /* _ENDIAN__ */
+	cmp_s	%r2, %r3
+	mov_s	%r0, 1
+	j_s.d	[%blink]
+	bset.lo	%r0, %r0, 31
+
+	.balign	4
+#ifdef __LITTLE_ENDIAN__
+.Lfound0:
+	xor	%r0, %r2, %r3	/* mask for difference */
+	or	%r0, %r0, %r4	/* or in zero indicator */
+	sub_s	%r1, %r0, 1
+	bic_s	%r0, %r0, %r1	/* mask for least significant difference bit */
+	sub	%r1, %r5, %r0
+	xor	%r0, %r5, %r1	/* mask for least significant difference byte */
+	and_s	%r2, %r2, %r0
+	and_s	%r3, %r3, %r0
+	sub.f	%r0, %r2, %r3
+	mov.hi	%r0, 1
+	j_s.d	[%blink]
+	bset.lo	%r0, %r0, 31
+#else /* __BIG_ENDIAN__ */
+	/*
+	 * The zero-detection above can mis-detect 0x01 bytes as zeroes
+	 * because of carry-propagateion from a lower significant zero byte.
+	 * We can compensate for this by checking that bit0 is zero.
+	 * This compensation is not necessary in the step where we
+	 * get a low estimate for r2, because in any affected bytes
+	 * we already have 0x00 or 0x01, which will remain unchanged
+	 * when bit 7 is cleared.
+	 */
+	.balign	4
+.Lfound0:
+	lsr	%r0, %r4, 8
+	lsr_s	%r1, %r2
+	bic_s	%r2, %r2, %r0	/* get low estimate for r2 and get ... */
+	bic_s	%r0, %r0, %r1	/* <this is the adjusted mask for zeros> */
+	or_s	%r3, %r3, %r0	/* ... high estimate r3 so that r2 > r3 will */
+	cmp_s	%r3, %r2	/* ... be independent of trailing garbage */
+	or_s	%r2, %r2, %r0	/* likewise for r3 > r2 */
+	bic_s	%r3, %r3, %r0
+	rlc	%r0, 0		/* r0 := r2 > r3 ? 1 : 0 */
+	cmp_s	%r2, %r3
+	j_s.d	[%blink]
+	bset.lo	%r0, %r0, 31
+#endif /* _ENDIAN__ */
+
+	.balign	4
+.Lcharloop:
+	ldb.ab	%r2,[%r0,1]
+	ldb.ab	%r3,[%r1,1]
+	nop_s
+	breq	%r2, 0, .Lcmpend
+	breq	%r2, %r3, .Lcharloop
+.Lcmpend:
+	j_s.d	[%blink]
+	sub	%r0, %r2, %r3

arch/arc/lib/strcpy-700.S

@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * If dst and src are 4 byte aligned, copy 8 bytes at a time.
+ * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
+ * it 8 byte aligned.  Thus, we can do a little read-ahead, without
+ * dereferencing a cache line that we should not touch.
+ * Note that short and long instructions have been scheduled to avoid
+ * branch stalls.
+ * The beq_s to r3z could be made unaligned & long to avoid a stall
+ * there, but it is not likely to be taken often, and it would also be likely
+ * to cost an unaligned mispredict at the next call.
+ */
+
+.global strcpy
+.align 4
+strcpy:
+	or	%r2, %r0, %r1
+	bmsk_s	%r2, %r2, 1
+	brne.d	%r2, 0, charloop
+	mov_s	%r10, %r0
+	ld_s	%r3, [%r1, 0]
+	mov	%r8, 0x01010101
+	bbit0.d	%r1, 2, loop_start
+	ror	%r12, %r8
+	sub	%r2, %r3, %r8
+	bic_s	%r2, %r2, %r3
+	tst_s	%r2,%r12
+	bne	r3z
+	mov_s	%r4,%r3
+	.balign 4
+loop:
+	ld.a	%r3, [%r1, 4]
+	st.ab	%r4, [%r10, 4]
+loop_start:
+	ld.a	%r4, [%r1, 4]
+	sub	%r2, %r3, %r8
+	bic_s	%r2, %r2, %r3
+	tst_s	%r2, %r12
+	bne_s	r3z
+	st.ab	%r3, [%r10, 4]
+	sub	%r2, %r4, %r8
+	bic	%r2, %r2, %r4
+	tst	%r2, %r12
+	beq	loop
+	mov_s	%r3, %r4
+#ifdef __LITTLE_ENDIAN__
+r3z:	bmsk.f	%r1, %r3, 7
+	lsr_s	%r3, %r3, 8
+#else /* __BIG_ENDIAN__ */
+r3z:	lsr.f	%r1, %r3, 24
+	asl_s	%r3, %r3, 8
+#endif /* _ENDIAN__ */
+	bne.d	r3z
+	stb.ab	%r1, [%r10, 1]
+	j_s	[%blink]
+
+	.balign	4
+charloop:
+	ldb.ab	%r3, [%r1, 1]
+	brne.d	%r3, 0, charloop
+	stb.ab	%r3, [%r10, 1]
+	j	[%blink]

arch/arc/lib/strlen.S

@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.global strlen
+.align 4
+strlen:
+	or	%r3, %r0, 7
+	ld	%r2, [%r3, -7]
+	ld.a	%r6, [%r3, -3]
+	mov	%r4, 0x01010101
+	/* uses long immediate */
+#ifdef __LITTLE_ENDIAN__
+	asl_s	%r1, %r0, 3
+	btst_s	%r0, 2
+	asl	%r7, %r4, %r1
+	ror	%r5, %r4
+	sub	%r1, %r2, %r7
+	bic_s	%r1, %r1, %r2
+	mov.eq	%r7, %r4
+	sub	%r12, %r6, %r7
+	bic	%r12, %r12, %r6
+	or.eq	%r12, %r12, %r1
+	and	%r12, %r12, %r5
+	brne	%r12, 0, .Learly_end
+#else /* __BIG_ENDIAN__ */
+	ror	%r5, %r4
+	btst_s	%r0, 2
+	mov_s	%r1, 31
+	sub3	%r7, %r1, %r0
+	sub	%r1, %r2, %r4
+	bic_s	%r1, %r1, %r2
+	bmsk	%r1, %r1, %r7
+	sub	%r12, %r6, %r4
+	bic	%r12, %r12, %r6
+	bmsk.ne	%r12, %r12, %r7
+	or.eq	%r12, %r12, %r1
+	and	%r12, %r12, %r5
+	brne	%r12, 0, .Learly_end
+#endif /* _ENDIAN__ */
+
+.Loop:
+	ld_s	%r2, [%r3, 4]
+	ld.a	%r6, [%r3, 8]
+	/* stall for load result */
+	sub	%r1, %r2, %r4
+	bic_s	%r1, %r1, %r2
+	sub	%r12, %r6, %r4
+	bic	%r12, %r12, %r6
+	or	%r12, %r12, %r1
+	and	%r12, %r12, %r5
+	breq	%r12, 0, .Loop
+.Lend:
+	and.f	%r1, %r1, %r5
+	sub.ne	%r3, %r3, 4
+	mov.eq	%r1, %r12
+#ifdef __LITTLE_ENDIAN__
+	sub_s	%r2, %r1, 1
+	bic_s	%r2, %r2, %r1
+	norm	%r1, %r2
+	sub_s	%r0, %r0, 3
+	lsr_s	%r1, %r1, 3
+	sub	%r0, %r3, %r0
+	j_s.d	[%blink]
+	sub	%r0, %r0, %r1
+#else /* __BIG_ENDIAN__ */
+	lsr_s	%r1, %r1, 7
+	mov.eq	%r2, %r6
+	bic_s	%r1, %r1, %r2
+	norm	%r1, %r1
+	sub	%r0, %r3, %r0
+	lsr_s	%r1, %r1, 3
+	j_s.d	[%blink]
+	add	%r0, %r0, %r1
+#endif /* _ENDIAN */
+.Learly_end:
+	b.d	.Lend
+	sub_s.ne %r1, %r1, %r1

arch/arm/config.mk

@@ -17,7 +17,9 @@ endif
 
 LDFLAGS_FINAL += --gc-sections
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-		     -fno-common -ffixed-r9 -msoft-float
+		     -fno-common -ffixed-r9
+PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
+      $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 
 # Support generic board on ARM
 __HAVE_ARCH_GENERIC_BOARD := y
@@ -103,3 +105,10 @@ ALL-y += checkarmreloc
 # such usage by requiring word relocations.
 PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
 endif
+
+# limit ourselves to the sections we want in the .bin.
+ifdef CONFIG_ARM64
+OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+else
+OBJCFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
+endif

arch/arm/cpu/Makefile

@@ -0,0 +1,3 @@
+obj-$(CONFIG_AT91FAMILY) += at91-common/
+obj-$(CONFIG_TEGRA) += $(SOC)-common/
+obj-$(CONFIG_TEGRA) += tegra-common/

arch/arm/cpu/arm1136/Makefile

@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o

arch/arm/cpu/arm1136/config.mk

@@ -7,13 +7,6 @@
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
 
 ifneq ($(CONFIG_IMX_CONFIG),)
 ifdef CONFIG_SPL
@@ -21,6 +14,6 @@ ifdef CONFIG_SPL_BUILD
 ALL-y	+= $(OBJTREE)/SPL
 endif
 else
-ALL-y	+= $(obj)u-boot.imx
+ALL-y	+= u-boot.imx
 endif
 endif

arch/arm/cpu/arm1136/mx31/Makefile

@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= timer.o
-COBJS	+= devices.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= generic.o
+obj-y	+= timer.o
+obj-y	+= devices.o

arch/arm/cpu/arm1136/mx35/Makefile

@@ -7,28 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= timer.o
-COBJS	+= mx35_sdram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= generic.o
+obj-y	+= timer.o
+obj-y	+= mx35_sdram.o

arch/arm/cpu/arm1176/Makefile

@@ -8,27 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o

arch/arm/cpu/arm1176/bcm2835/Makefile

@@ -12,26 +12,5 @@
 # GNU General Public License for more details.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	:= lowlevel_init.o
-COBJS	:= init.o reset.o timer.o mbox.o
-
-SRCS	:= $(SOBJS:.o=.c) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= lowlevel_init.o
+obj-y	+= init.o reset.o timer.o mbox.o

arch/arm/cpu/arm1176/bcm2835/config.mk

@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2012 Stephen Warren
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# Don't attempt to override the target CPU/ABI options;
-# the Raspberry Pi toolchain does the right thing by default.
-PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS))
-PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS))

arch/arm/cpu/arm1176/bcm2835/mbox.c

@@ -8,7 +8,7 @@
 #include <asm/io.h>
 #include <asm/arch/mbox.h>
 
-#define TIMEOUT (100 * 1000) /* 100mS in uS */
+#define TIMEOUT 1000 /* ms */
 
 int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
 {

arch/arm/cpu/arm1176/bcm2835/timer.c

@@ -18,11 +18,6 @@
 #include <asm/io.h>
 #include <asm/arch/timer.h>
 
-int timer_init(void)
-{
-	return 0;
-}
-
 ulong get_timer_us(ulong base)
 {
 	struct bcm2835_timer_regs *regs =

arch/arm/cpu/arm1176/config.mk

@@ -7,11 +7,3 @@
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5t
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
-			$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

arch/arm/cpu/arm1176/tnetv107x/Makefile

@@ -2,28 +2,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= aemif.o clock.o init.o mux.o timer.o
-SOBJS	+= lowlevel_init.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= aemif.o clock.o init.o mux.o timer.o
+obj-y	+= lowlevel_init.o

arch/arm/cpu/arm720t/Makefile

@@ -5,27 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+extra-y	= start.o
+obj-y	= interrupts.o cpu.o
 
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= interrupts.o cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_TEGRA) += tegra-common/

arch/arm/cpu/arm720t/config.mk

@@ -7,11 +7,3 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
-			$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

arch/arm/cpu/arm720t/tegra-common/Makefile

@@ -7,26 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libtegra-common.o
-
-COBJS-$(CONFIG_SPL_BUILD) += spl.o
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-y	+= cpu.o

arch/arm/cpu/arm720t/tegra-common/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -49,57 +49,107 @@ int get_num_cpus(void)
  * Timing tables for each SOC for all four oscillator options.
  */
 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
-	/* T20: 1 GHz */
-	/*  n,  m, p, cpcon */
-	{{ 1000, 13, 0, 12},	/* OSC 13M */
-	 { 625,  12, 0, 8},	/* OSC 19.2M */
-	 { 1000, 12, 0, 12},	/* OSC 12M */
-	 { 1000, 26, 0, 12},	/* OSC 26M */
+	/*
+	 * T20: 1 GHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      22:20    3
+	 * PLLX_BASE  n      17: 8   10
+	 * PLLX_BASE  m       4: 0    5
+	 * PLLX_MISC  cpcon  11: 8    4
+	 */
+	{
+		{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+		{ .n =  625, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
+		{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+		{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+	},
+	/*
+	 * T25: 1.2 GHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      22:20    3
+	 * PLLX_BASE  n      17: 8   10
+	 * PLLX_BASE  m       4: 0    5
+	 * PLLX_MISC  cpcon  11: 8    4
+	 */
+	{
+		{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+		{ .n = 750, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
+		{ .n = 600, .m =  6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+		{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+	},
+	/*
+	 * T30: 1.4 GHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      22:20    3
+	 * PLLX_BASE  n      17: 8   10
+	 * PLLX_BASE  m       4: 0    5
+	 * PLLX_MISC  cpcon  11: 8    4
+	 */
+	{
+		{ .n = 862, .m =  8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
+		{ .n = 583, .m =  8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
+		{ .n = 700, .m =  6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
+		{ .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
+	},
+	/*
+	 * T114: 700 MHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      23:20    4
+	 * PLLX_BASE  n      15: 8    8
+	 * PLLX_BASE  m       7: 0    8
+	 */
+	{
+		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
 	},
 
-	/* T25: 1.2 GHz */
-	{{ 923, 10, 0, 12},
-	 { 750, 12, 0, 8},
-	 { 600,  6, 0, 12},
-	 { 600, 13, 0, 12},
-	},
-
-	/* T30: 1.4 GHz */
-	{{ 862, 8, 0, 8},
-	 { 583, 8, 0, 4},
-	 { 700, 6, 0, 8},
-	 { 700, 13, 0, 8},
-	},
-
-	/* T114: 1.4 GHz */
-	{{ 862, 8, 0, 8},
-	 { 583, 8, 0, 4},
-	 { 696, 12, 0, 8},
-	 { 700, 13, 0, 8},
+	/*
+	 * T124: 700 MHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      23:20    4
+	 * PLLX_BASE  n      15: 8    8
+	 * PLLX_BASE  m       7: 0    8
+	 */
+	{
+		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
 	},
 };
 
-void adjust_pllp_out_freqs(void)
+static inline void pllx_set_iddq(void)
 {
+#if defined(CONFIG_TEGRA124)
 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
 	u32 reg;
 
-	/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
-	reg = readl(&pll->pll_out[0]);	/* OUTA, contains OUT2 / OUT1 */
-	reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
-		| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
-	writel(reg, &pll->pll_out[0]);
-
-	reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
-	reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
-		| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
-	writel(reg, &pll->pll_out[1]);
+	/* Disable IDDQ */
+	reg = readl(&clkrst->crc_pllx_misc3);
+	reg &= ~PLLX_IDDQ_MASK;
+	writel(reg, &clkrst->crc_pllx_misc3);
+	udelay(2);
+	debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
+	      readl(&clkrst->crc_pllx_misc3));
+#endif
 }
 
 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 		u32 divp, u32 cpcon)
 {
+	int chip = tegra_get_chip();
 	u32 reg;
 
 	/* If PLLX is already enabled, just return */
@@ -110,31 +160,41 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 
 	debug(" pllx_set_rate entry\n");
 
+	pllx_set_iddq();
+
 	/* Set BYPASS, m, n and p to PLLX_BASE */
 	reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
 	reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
 	writel(reg, &pll->pll_base);
 
 	/* Set cpcon to PLLX_MISC */
-	reg = (cpcon << PLL_CPCON_SHIFT);
+	if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
+		reg = (cpcon << PLL_CPCON_SHIFT);
+	else
+		reg = 0;
 
 	/* Set dccon to PLLX_MISC if freq > 600MHz */
 	if (divn > 600)
 		reg |= (1 << PLL_DCCON_SHIFT);
 	writel(reg, &pll->pll_misc);
 
-	/* Enable PLLX */
-	reg = readl(&pll->pll_base);
-	reg |= PLL_ENABLE_MASK;
-
 	/* Disable BYPASS */
+	reg = readl(&pll->pll_base);
 	reg &= ~PLL_BYPASS_MASK;
 	writel(reg, &pll->pll_base);
+	debug("pllx_set_rate: base = 0x%08X\n", reg);
 
 	/* Set lock_enable to PLLX_MISC */
 	reg = readl(&pll->pll_misc);
 	reg |= PLL_LOCK_ENABLE_MASK;
 	writel(reg, &pll->pll_misc);
+	debug("pllx_set_rate: misc = 0x%08X\n", reg);
+
+	/* Enable PLLX last, once it's all configured */
+	reg = readl(&pll->pll_base);
+	reg |= PLL_ENABLE_MASK;
+	writel(reg, &pll->pll_base);
+	debug("pllx_set_rate: base final = 0x%08X\n", reg);
 
 	return 0;
 }
@@ -168,12 +228,6 @@ void init_pllx(void)
 	/* set pllx */
 	sel = &tegra_pll_x_table[chip_sku][osc];
 	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
-
-	/* adjust PLLP_out1-4 on T3x/T114 */
-	if (soc_type >= CHIPID_TEGRA30) {
-		debug("  init_pllx: adjusting PLLP out freqs\n");
-		adjust_pllp_out_freqs();
-	}
 }
 
 void enable_cpu_clock(int enable)
@@ -295,7 +349,6 @@ void reset_A9_cpu(int reset)
 void clock_enable_coresight(int enable)
 {
 	u32 rst, src = 2;
-	int soc_type;
 
 	debug("clock_enable_coresight entry\n");
 	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
@@ -304,20 +357,11 @@ void clock_enable_coresight(int enable)
 	if (enable) {
 		/*
 		 * Put CoreSight on PLLP_OUT0 and divide it down as per
-		 * PLLP base frequency based on SoC type (T20/T30/T114).
+		 * PLLP base frequency based on SoC type (T20/T30+).
 		 * Clock divider request would setup CSITE clock as 144MHz
 		 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
 		 */
-
-		soc_type = tegra_get_chip();
-		if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
-			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
-		else if (soc_type == CHIPID_TEGRA20)
-			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
-		else
-			printf("%s: Unknown SoC type %X!\n",
-				 __func__, soc_type);
-
+		src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
 		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
 
 		/* Unlock the CPU CoreSight interfaces */

arch/arm/cpu/arm720t/tegra-common/cpu.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2014
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -11,9 +11,12 @@
 #define IO_STABILIZATION_DELAY	(1000)
 
 #if defined(CONFIG_TEGRA20)
-#define NVBL_PLLP_KHZ	(216000)
-#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
-#define NVBL_PLLP_KHZ	(408000)
+#define NVBL_PLLP_KHZ	216000
+#define CSITE_KHZ	144000
+#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
+	defined(CONFIG_TEGRA124)
+#define NVBL_PLLP_KHZ	408000
+#define CSITE_KHZ	204000
 #else
 #error "Unknown Tegra chip!"
 #endif
@@ -68,3 +71,4 @@ int tegra_get_chip(void);
 int tegra_get_sku_info(void);
 int tegra_get_chip_sku(void);
 void adjust_pllp_out_freqs(void);
+void pmic_enable_cpu_vdd(void);

arch/arm/cpu/arm720t/tegra114/Makefile

@@ -17,26 +17,5 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-#COBJS-y	+= cpu.o t11x.o
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+#obj-y	+= cpu.o t11x.o
+obj-y	+= cpu.o

arch/arm/cpu/arm720t/tegra114/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -68,7 +68,7 @@ static void enable_cpu_clocks(void)
 	/* Wait for PLL-X to lock */
 	do {
 		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
-	} while ((reg & (1 << 27)) == 0);
+	} while ((reg & PLL_LOCK_MASK) == 0);
 
 	/* Wait until all clocks are stable */
 	udelay(PLL_STABILIZATION_DELAY);
@@ -126,18 +126,6 @@ void t114_init_clocks(void)
 	/* Set active CPU cluster to G */
 	clrbits_le32(&flow->cluster_control, 1);
 
-	/*
-	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-	 * at 108 MHz. This is glitch free as only the source is changed, no
-	 * special precaution needed.
-	 */
-	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-	writel(val, &clkrst->crc_sclk_brst_pol);
-
 	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
 
 	debug("Setting up PLLX\n");
@@ -204,45 +192,43 @@ void t114_init_clocks(void)
 	debug("t114_init_clocks exit\n");
 }
 
-static int is_partition_powered(u32 mask)
+static bool is_partition_powered(u32 partid)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 
 	/* Get power gate status */
 	reg = readl(&pmc->pmc_pwrgate_status);
-	return (reg & mask) == mask;
+	return !!(reg & (1 << partid));
 }
 
-static int is_clamp_enabled(u32 mask)
+static bool is_clamp_enabled(u32 partid)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 
-	/* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
-	reg = readl(&pmc->pmc_pwrgate_timer_on);
-	return (reg & mask) == mask;
+	/* Get clamp status. */
+	reg = readl(&pmc->pmc_clamp_status);
+	return !!(reg & (1 << partid));
 }
 
-static void power_partition(u32 status, u32 partid)
+static void power_partition(u32 partid)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
-	debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
+	debug("%s: part ID = %08X\n", __func__, partid);
 	/* Is the partition already on? */
-	if (!is_partition_powered(status)) {
+	if (!is_partition_powered(partid)) {
 		/* No, toggle the partition power state (OFF -> ON) */
 		debug("power_partition, toggling state\n");
-		clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
+		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
 
 		/* Wait for the power to come up */
-		while (!is_partition_powered(status))
+		while (!is_partition_powered(partid))
 			;
 
 		/* Wait for the clamp status to be cleared */
-		while (is_clamp_enabled(status))
+		while (is_clamp_enabled(partid))
 			;
 
 		/* Give I/O signals time to stabilize */
@@ -257,13 +243,13 @@ void powerup_cpus(void)
 	/* We boot to the fast cluster */
 	debug("powerup_cpus entry: G cluster\n");
 	/* Power up the fast cluster rail partition */
-	power_partition(CRAIL, CRAILID);
+	power_partition(CRAIL);
 
 	/* Power up the fast cluster non-CPU partition */
-	power_partition(C0NC, C0NCID);
+	power_partition(C0NC);
 
 	/* Power up the fast cluster CPU0 partition */
-	power_partition(CE0, CE0ID);
+	power_partition(CE0);
 }
 
 void start_cpu(u32 reset_vector)

arch/arm/cpu/arm720t/tegra124/Makefile

@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= cpu.o

arch/arm/cpu/arm720t/tegra124/config.mk

@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2010-2013
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#/
+USE_PRIVATE_LIBGCC = yes

arch/arm/cpu/arm720t/tegra124/cpu.c

@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ahb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/ap.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra124-specific CPU init code */
+
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("enable_cpu_power_rail entry\n");
+
+	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+	pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
+	pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+
+	pmic_enable_cpu_vdd();
+
+	/*
+	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+	 * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
+	 */
+	writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
+
+	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+}
+
+static void enable_cpu_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("enable_cpu_clocks entry\n");
+
+	/* Wait for PLL-X to lock */
+	do {
+		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+		debug("%s: PLLX base = 0x%08X\n", __func__, reg);
+	} while ((reg & PLL_LOCK_MASK) == 0);
+
+	debug("%s: PLLX locked, delay for stable clocks\n", __func__);
+	/* Wait until all clocks are stable */
+	udelay(PLL_STABILIZATION_DELAY);
+
+	debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
+	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+	debug("%s: Enabling clock to all CPUs\n", __func__);
+	/* Enable the clock to all CPUs */
+	reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
+		CLR_CPU0_CLK_STP;
+	writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
+
+	debug("%s: Enabling main CPU complex clocks\n", __func__);
+	/* Always enable the main CPU complex clocks */
+	clock_enable(PERIPH_ID_CPU);
+	clock_enable(PERIPH_ID_CPULP);
+	clock_enable(PERIPH_ID_CPUG);
+
+	debug("%s: Done\n", __func__);
+}
+
+static void remove_cpu_resets(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("remove_cpu_resets entry\n");
+
+	/* Take the slow and fast partitions out of reset */
+	reg = CLR_NONCPURESET;
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the slow cluster */
+	reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+		CLR_L2RESET | CLR_PRESETDBG;
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the fast cluster */
+	reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+		CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
+		CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
+		CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
+		CLR_L2RESET | CLR_PRESETDBG;
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The Tegra124 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void tegra124_init_clocks(void)
+{
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 val;
+
+	debug("tegra124_init_clocks entry\n");
+
+	/* Set active CPU cluster to G */
+	clrbits_le32(&flow->cluster_control, 1);
+
+	/* Change the oscillator drive strength */
+	val = readl(&clkrst->crc_osc_ctrl);
+	val &= ~OSC_XOFS_MASK;
+	val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
+	writel(val, &clkrst->crc_osc_ctrl);
+
+	/* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
+	val = readl(&pmc->pmc_osc_edpd_over);
+	val &= ~PMC_XOFS_MASK;
+	val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
+	writel(val, &pmc->pmc_osc_edpd_over);
+
+	/* Set HOLD_CKE_LOW_EN to 1 */
+	setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
+
+	debug("Setting up PLLX\n");
+	init_pllx();
+
+	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+	writel(val, &clkrst->crc_clk_sys_rate);
+
+	/* Enable clocks to required peripherals. TBD - minimize this list */
+	debug("Enabling clocks\n");
+
+	clock_set_enable(PERIPH_ID_CACHE2, 1);
+	clock_set_enable(PERIPH_ID_GPIO, 1);
+	clock_set_enable(PERIPH_ID_TMR, 1);
+	clock_set_enable(PERIPH_ID_CPU, 1);
+	clock_set_enable(PERIPH_ID_EMC, 1);
+	clock_set_enable(PERIPH_ID_I2C5, 1);
+	clock_set_enable(PERIPH_ID_APBDMA, 1);
+	clock_set_enable(PERIPH_ID_MEM, 1);
+	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+	clock_set_enable(PERIPH_ID_MSELECT, 1);
+	clock_set_enable(PERIPH_ID_DVFS, 1);
+
+	/*
+	 * Set MSELECT clock source as PLLP (00), and ask for a clock
+	 * divider that would set the MSELECT clock at 102MHz for a
+	 * PLLP base of 408MHz.
+	 */
+	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+				    CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
+
+	/* Give clock time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+
+	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+	/* Give clock time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+
+	/* Take required peripherals out of reset */
+	debug("Taking periphs out of reset\n");
+	reset_set_enable(PERIPH_ID_CACHE2, 0);
+	reset_set_enable(PERIPH_ID_GPIO, 0);
+	reset_set_enable(PERIPH_ID_TMR, 0);
+	reset_set_enable(PERIPH_ID_COP, 0);
+	reset_set_enable(PERIPH_ID_EMC, 0);
+	reset_set_enable(PERIPH_ID_I2C5, 0);
+	reset_set_enable(PERIPH_ID_APBDMA, 0);
+	reset_set_enable(PERIPH_ID_MEM, 0);
+	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+	reset_set_enable(PERIPH_ID_MSELECT, 0);
+	reset_set_enable(PERIPH_ID_DVFS, 0);
+
+	debug("tegra124_init_clocks exit\n");
+}
+
+static bool is_partition_powered(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Get power gate status */
+	reg = readl(&pmc->pmc_pwrgate_status);
+	return !!(reg & (1 << partid));
+}
+
+static void power_partition(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("%s: part ID = %08X\n", __func__, partid);
+	/* Is the partition already on? */
+	if (!is_partition_powered(partid)) {
+		/* No, toggle the partition power state (OFF -> ON) */
+		debug("power_partition, toggling state\n");
+		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+		/* Wait for the power to come up */
+		while (!is_partition_powered(partid))
+			;
+
+		/* Give I/O signals time to stabilize */
+		udelay(IO_STABILIZATION_DELAY);
+	}
+}
+
+void powerup_cpus(void)
+{
+	debug("powerup_cpus entry\n");
+
+	/* We boot to the fast cluster */
+	debug("powerup_cpus entry: G cluster\n");
+
+	/* Power up the fast cluster rail partition */
+	debug("powerup_cpus: CRAIL\n");
+	power_partition(CRAIL);
+
+	/* Power up the fast cluster non-CPU partition */
+	debug("powerup_cpus: C0NC\n");
+	power_partition(C0NC);
+
+	/* Power up the fast cluster CPU0 partition */
+	debug("powerup_cpus: CE0\n");
+	power_partition(CE0);
+
+	debug("powerup_cpus: done\n");
+}
+
+void start_cpu(u32 reset_vector)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+	tegra124_init_clocks();
+
+	/* Set power-gating timer multiplier */
+	clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
+	setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+
+	enable_cpu_power_rail();
+	enable_cpu_clocks();
+	clock_enable_coresight(1);
+	remove_cpu_resets();
+	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+	powerup_cpus();
+	debug("start_cpu exit, should continue @ reset_vector\n");
+}

arch/arm/cpu/arm720t/tegra20/Makefile

@@ -7,25 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= cpu.o

arch/arm/cpu/arm720t/tegra30/Makefile

@@ -17,25 +17,4 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= cpu.o

arch/arm/cpu/arm720t/tegra30/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -84,18 +84,6 @@ void t30_init_clocks(void)
 	/* Set active CPU cluster to G */
 	clrbits_le32(flow->cluster_control, 1 << 0);
 
-	/*
-	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-	 * at 108 MHz. This is glitch free as only the source is changed, no
-	 * special precaution needed.
-	 */
-	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-	writel(val, &clkrst->crc_sclk_brst_pol);
-
 	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
 
 	val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |

arch/arm/cpu/arm920t/Makefile

@@ -5,29 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+extra-y	= start.o
 
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS-y	+= cpu.o
-COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= cpu.o
+obj-$(CONFIG_USE_IRQ)	+= interrupts.o

arch/arm/cpu/arm920t/a320/Makefile

@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	+= reset.o
-COBJS	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= reset.o
+obj-y	+= timer.o

arch/arm/cpu/arm920t/at91/Makefile

@@ -5,30 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	+= lowlevel_init.o
-COBJS	+= reset.o
-COBJS	+= timer.o
-COBJS	+= clock.o
-COBJS	+= cpu.o
-COBJS	+= at91rm9200_devices.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= lowlevel_init.o
+obj-y	+= reset.o
+obj-y	+= timer.o
+obj-y	+= clock.o
+obj-y	+= cpu.o
+obj-y	+= at91rm9200_devices.o

arch/arm/cpu/arm920t/config.mk

@@ -6,10 +6,3 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

arch/arm/cpu/arm920t/ep93xx/Makefile

@@ -16,26 +16,6 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(TOPDIR)/config.mk
 
-LIB = $(obj)lib$(SOC).o
-
-COBJS   = cpu.o led.o speed.o timer.o
-SOBJS   = lowlevel_init.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:    $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y   = cpu.o led.o speed.o timer.o
+obj-y   += lowlevel_init.o

arch/arm/cpu/arm920t/imx/Makefile

@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= speed.o
-COBJS	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= generic.o
+obj-y	+= speed.o
+obj-y	+= timer.o

arch/arm/cpu/arm920t/ks8695/Makefile

@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	= lowlevel_init.o
-
-COBJS	= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= lowlevel_init.o
+obj-y	+= timer.o

arch/arm/cpu/arm920t/s3c24x0/Makefile

@@ -5,28 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_USE_IRQ) += interrupts.o
-COBJS-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
-COBJS-y	+= speed.o
-COBJS-y	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_USE_IRQ) += interrupts.o
+obj-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
+obj-y	+= speed.o
+obj-y	+= timer.o

arch/arm/cpu/arm926ejs/Makefile

@@ -5,33 +5,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o cache.o
+extra-y	= start.o
+obj-y	= cpu.o cache.o
 
 ifdef	CONFIG_SPL_BUILD
 ifdef	CONFIG_SPL_NO_CPU_SUPPORT_CODE
-START	:=
+extra-y	:=
 endif
 endif
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm926ejs/armada100/Makefile

@@ -6,25 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= cpu.o timer.o dram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpu.o timer.o dram.o

arch/arm/cpu/arm926ejs/at91/Makefile

@@ -5,46 +5,25 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_AT91CAP9)	+= at91cap9_devices.o
-COBJS-$(CONFIG_AT91SAM9260)	+= at91sam9260_devices.o
-COBJS-$(CONFIG_AT91SAM9G20)	+= at91sam9260_devices.o
-COBJS-$(CONFIG_AT91SAM9XE)	+= at91sam9260_devices.o
-COBJS-$(CONFIG_AT91SAM9261)	+= at91sam9261_devices.o
-COBJS-$(CONFIG_AT91SAM9G10)	+= at91sam9261_devices.o
-COBJS-$(CONFIG_AT91SAM9263)	+= at91sam9263_devices.o
-COBJS-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
-COBJS-$(CONFIG_AT91SAM9M10G45)	+= at91sam9m10g45_devices.o
-COBJS-$(CONFIG_AT91SAM9G45)	+= at91sam9m10g45_devices.o
-COBJS-$(CONFIG_AT91SAM9N12)	+= at91sam9n12_devices.o
-COBJS-$(CONFIG_AT91SAM9X5)	+= at91sam9x5_devices.o
-COBJS-$(CONFIG_AT91_EFLASH)	+= eflash.o
-COBJS-$(CONFIG_AT91_LED)	+= led.o
-COBJS-y += clock.o
-COBJS-y += cpu.o
-COBJS-y	+= reset.o
-COBJS-y	+= timer.o
+obj-$(CONFIG_AT91CAP9)	+= at91cap9_devices.o
+obj-$(CONFIG_AT91SAM9260)	+= at91sam9260_devices.o
+obj-$(CONFIG_AT91SAM9G20)	+= at91sam9260_devices.o
+obj-$(CONFIG_AT91SAM9XE)	+= at91sam9260_devices.o
+obj-$(CONFIG_AT91SAM9261)	+= at91sam9261_devices.o
+obj-$(CONFIG_AT91SAM9G10)	+= at91sam9261_devices.o
+obj-$(CONFIG_AT91SAM9263)	+= at91sam9263_devices.o
+obj-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
+obj-$(CONFIG_AT91SAM9M10G45)	+= at91sam9m10g45_devices.o
+obj-$(CONFIG_AT91SAM9G45)	+= at91sam9m10g45_devices.o
+obj-$(CONFIG_AT91SAM9N12)	+= at91sam9n12_devices.o
+obj-$(CONFIG_AT91SAM9X5)	+= at91sam9x5_devices.o
+obj-$(CONFIG_AT91_EFLASH)	+= eflash.o
+obj-$(CONFIG_AT91_LED)	+= led.o
+obj-y += clock.o
+obj-y += cpu.o
+obj-y	+= reset.o
+obj-y	+= timer.o
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS-y	:= lowlevel_init.o
+obj-y	+= lowlevel_init.o
 endif
-
-SRCS    := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS    := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm926ejs/at91/led.c

@@ -7,43 +7,41 @@
  */
 
 #include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
+#include <asm/gpio.h>
 #include <asm/arch/gpio.h>
 
 #ifdef CONFIG_RED_LED
 void red_led_on(void)
 {
-	at91_set_gpio_value(CONFIG_RED_LED, 1);
+	gpio_set_value(CONFIG_RED_LED, 1);
 }
 
 void red_led_off(void)
 {
-	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	gpio_set_value(CONFIG_RED_LED, 0);
 }
 #endif
 
 #ifdef CONFIG_GREEN_LED
 void green_led_on(void)
 {
-	at91_set_gpio_value(CONFIG_GREEN_LED, 0);
+	gpio_set_value(CONFIG_GREEN_LED, 0);
 }
 
 void green_led_off(void)
 {
-	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	gpio_set_value(CONFIG_GREEN_LED, 1);
 }
 #endif
 
 #ifdef CONFIG_YELLOW_LED
 void yellow_led_on(void)
 {
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+	gpio_set_value(CONFIG_YELLOW_LED, 0);
 }
 
 void yellow_led_off(void)
 {
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+	gpio_set_value(CONFIG_YELLOW_LED, 1);
 }
 #endif

arch/arm/cpu/arm926ejs/config.mk

@@ -6,13 +6,6 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv5te
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
 
 ifneq ($(CONFIG_IMX_CONFIG),)
 ifdef CONFIG_SPL
@@ -20,6 +13,6 @@ ifdef CONFIG_SPL_BUILD
 ALL-y	+= $(OBJTREE)/SPL
 endif
 else
-ALL-y	+= $(obj)u-boot.imx
+ALL-y	+= u-boot.imx
 endif
 endif

arch/arm/cpu/arm926ejs/davinci/Makefile

@@ -7,44 +7,22 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y				+= cpu.o misc.o timer.o psc.o pinmux.o reset.o
-COBJS-$(CONFIG_DA850_LOWLEVEL)	+= da850_lowlevel.o
-COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
-COBJS-$(CONFIG_SOC_DM365)	+= dm365.o
-COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
-COBJS-$(CONFIG_SOC_DM646X)	+= dm646x.o
-COBJS-$(CONFIG_SOC_DA830)	+= da830_pinmux.o
-COBJS-$(CONFIG_SOC_DA850)	+= da850_pinmux.o
-COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
+obj-y				+= cpu.o misc.o timer.o psc.o pinmux.o reset.o
+obj-$(CONFIG_DA850_LOWLEVEL)	+= da850_lowlevel.o
+obj-$(CONFIG_SOC_DM355)	+= dm355.o
+obj-$(CONFIG_SOC_DM365)	+= dm365.o
+obj-$(CONFIG_SOC_DM644X)	+= dm644x.o
+obj-$(CONFIG_SOC_DM646X)	+= dm646x.o
+obj-$(CONFIG_SOC_DA830)	+= da830_pinmux.o
+obj-$(CONFIG_SOC_DA850)	+= da850_pinmux.o
+obj-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
 
 ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_SPL_FRAMEWORK)	+= spl.o
-COBJS-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
-COBJS-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
+obj-$(CONFIG_SPL_FRAMEWORK)	+= spl.o
+obj-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
+obj-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
 endif
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS	+= lowlevel_init.o
+obj-y	+= lowlevel_init.o
 endif
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm926ejs/davinci/config.mk

@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 ifndef CONFIG_SPL_BUILD
-ALL-$(CONFIG_SPL_FRAMEWORK)	+= $(obj)u-boot.ais
+ALL-$(CONFIG_SPL_FRAMEWORK)	+= u-boot.ais
 endif

arch/arm/cpu/arm926ejs/kirkwood/Makefile

@@ -6,29 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= cpu.o
-COBJS-y	+= dram.o
-COBJS-y	+= mpp.o
-COBJS-y	+= timer.o
-COBJS-y	+= cache.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpu.o
+obj-y	+= dram.o
+obj-y	+= mpp.o
+obj-y	+= timer.o
+obj-y	+= cache.o

arch/arm/cpu/arm926ejs/lpc32xx/Makefile

@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB     = $(obj)lib$(SOC).o
-
-COBJS   = cpu.o clk.o devices.o timer.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS    := $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:    $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y   = cpu.o clk.o devices.o timer.o

arch/arm/cpu/arm926ejs/mb86r0x/Makefile

@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= clock.o reset.o timer.o
-SOBJS	=
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= clock.o reset.o timer.o

arch/arm/cpu/arm926ejs/mx25/Makefile

@@ -4,25 +4,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= generic.o timer.o reset.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= generic.o timer.o reset.o

arch/arm/cpu/arm926ejs/mx25/timer.c

@@ -21,65 +21,8 @@
  */
 
 #include <common.h>
-#include <div64.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp	(gd->arch.tbl)
-#define lastinc		(gd->arch.lastinc)
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-#ifdef CONFIG_MX25_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, MXC_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= MXC_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * MXC_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / MXC_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
 
 /* nothing really to do with interrupts, just starts up a counter. */
 /* The 32KHz 32-bit timer overruns in 134217 seconds */
@@ -104,63 +47,3 @@ int timer_init(void)
 
 	return 0;
 }
-
-unsigned long long get_ticks(void)
-{
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	ulong now = readl(&gpt->counter); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	ulong tbclk;
-
-	tbclk = MXC_CLK32;
-	return tbclk;
-}

arch/arm/cpu/arm926ejs/mx27/Makefile

@@ -4,25 +4,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= generic.o reset.o timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= generic.o reset.o timer.o

arch/arm/cpu/arm926ejs/mxs/Makefile

@@ -5,40 +5,20 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+extra-$(CONFIG_SPL_BUILD) := start.o
 
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= clock.o mxs.o iomux.o timer.o
+obj-y	= clock.o mxs.o iomux.o timer.o
 
 ifdef	CONFIG_SPL_BUILD
-COBJS	+= spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
+obj-y	+= spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
 endif
 
-SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
 # Specify the target for use in elftosb call
-ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
-ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
+MKIMAGE_TARGET-$(CONFIG_MX23) = mx23
+MKIMAGE_TARGET-$(CONFIG_MX28) = mx28
 
-$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd
+$(OBJTREE)/mxsimage.cfg: $(SRCTREE)/$(CPUDIR)/$(SOC)/mxsimage.$(MKIMAGE_TARGET-y).cfg
 	sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
 
-$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd
-		elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/mxsimage.cfg
+	$(OBJTREE)/tools/mkimage -n $(OBJTREE)/mxsimage.cfg -T mxsimage $@

arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg

@@ -1,6 +1,6 @@
 SECTION 0x0 BOOTABLE
  TAG LAST
- LOAD     0x0        spl/u-boot-spl.bin
+ LOAD     0x0        OBJTREE/spl/u-boot-spl.bin
  CALL     0x14       0x0
- LOAD     0x40000100 u-boot.bin
+ LOAD     0x40000100 OBJTREE/u-boot.bin
  CALL     0x40000100 0x0

arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

@@ -1,8 +1,8 @@
 SECTION 0x0 BOOTABLE
  TAG LAST
- LOAD     0x0        spl/u-boot-spl.bin
+ LOAD     0x0        OBJTREE/spl/u-boot-spl.bin
  LOAD IVT 0x8000     0x14
  CALL HAB 0x8000     0x0
- LOAD     0x40000100 u-boot.bin
+ LOAD     0x40000100 OBJTREE/u-boot.bin
  LOAD IVT 0x8000     0x40000100
  CALL HAB 0x8000     0x0

arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

@@ -654,6 +654,8 @@ static void mxs_batt_boot(void)
 	clrsetbits_le32(&power_regs->hw_power_5vctrl,
 		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 		0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+
+	mxs_power_enable_4p2();
 }
 
 /**

arch/arm/cpu/arm926ejs/mxs/start.S

@@ -149,6 +149,15 @@ IRQ_STACK_START_IN:
  */
 
 _reset:
+	/*
+	 * If the CPU is configured in "Wait JTAG connection mode", the stack
+	 * pointer is not configured and is zero. This will cause crash when
+	 * trying to push data onto stack right below here. Load the SP and make
+	 * it point to the end of OCRAM if the SP is zero.
+	 */
+	cmp	sp, #0x00000000
+	ldreq	sp, =CONFIG_SYS_INIT_SP_ADDR
+
 	/*
 	 * Store all registers on old stack pointer, this will allow us later to
 	 * return to the BootROM and let the BootROM load U-Boot into RAM.

arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds

@@ -51,11 +51,13 @@ SECTIONS
 
 	_end = .;
 
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynsym*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.hash*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }

arch/arm/cpu/arm926ejs/nomadik/Makefile

@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= timer.o gpio.o
-SOBJS	= reset.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= timer.o gpio.o
+obj-y	+= reset.o

arch/arm/cpu/arm926ejs/omap/Makefile

@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= timer.o cpuinfo.o
-SOBJS	= reset.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= timer.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o
+obj-y	+= reset.o

arch/arm/cpu/arm926ejs/omap/cpuinfo.c

@@ -13,7 +13,7 @@
 #include <command.h>
 #include <linux/compiler.h>
 
-#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP)
+#if defined(CONFIG_OMAP)
 
 #define omap_readw(x)		*(volatile unsigned short *)(x)
 #define omap_readl(x)		*(volatile unsigned long *)(x)
@@ -239,4 +239,4 @@ int print_cpuinfo (void)
 	return 0;
 }
 
-#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */
+#endif /* #if defined(CONFIG_OMAP) */