Prepare v2015.01

Signed-off-by: Tom Rini <trini@ti.com>

Kconfig

@@ -56,8 +56,6 @@ config CC_OPTIMIZE_FOR_SIZE
 
 	  This option is enabled by default for U-Boot.
 
-endmenu		# General setup
-
 menuconfig EXPERT
         bool "Configure standard U-Boot features (expert users)"
         help
@@ -66,6 +64,8 @@ menuconfig EXPERT
           environments which can tolerate a "non-standard" U-Boot.
           Only use this if you really know what you are doing.
 
+endmenu		# General setup
+
 menu "Boot images"
 
 config SPL_BUILD

MAINTAINERS

@@ -97,6 +97,7 @@ F:	arch/arm/include/asm/imx-common/
 
 ARM MARVELL KIRKWOOD
 M:	Prafulla Wadaskar <prafulla@marvell.com>
+M:	Luka Perkov <luka.perkov@sartura.hr>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-marvell.git
 F:	arch/arm/cpu/arm926ejs/kirkwood/

MAKEALL

@@ -291,12 +291,6 @@ LIST_8xx="$(targets_by_cpu mpc8xx)"
 
 LIST_4xx="$(targets_by_cpu ppc4xx)"
 
-#########################################################################
-## MPC824x Systems
-#########################################################################
-
-LIST_824x="$(targets_by_cpu mpc824x)"
-
 #########################################################################
 ## MPC8260 Systems (includes 8250, 8255 etc.)
 #########################################################################

Makefile

@@ -1,7 +1,7 @@
 VERSION = 2015
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

README

@@ -186,7 +186,6 @@ Directory Hierarchy:
       /mpc5xx		Files specific to Freescale MPC5xx CPUs
       /mpc5xxx		Files specific to Freescale MPC5xxx CPUs
       /mpc8xx		Files specific to Freescale MPC8xx CPUs
-      /mpc824x		Files specific to Freescale MPC824x CPUs
       /mpc8260		Files specific to Freescale MPC8260 CPUs
       /mpc85xx		Files specific to Freescale MPC85xx CPUs
       /ppc4xx		Files specific to AMCC PowerPC 4xx CPUs
@@ -326,10 +325,6 @@ The following options need to be configured:
 					  multiple fs option at one time
 					  for marvell soc family
 
-- MPC824X Family Member (if CONFIG_MPC824X is defined)
-		Define exactly one of
-		CONFIG_MPC8240, CONFIG_MPC8245
-
 - 8xx CPU Options: (if using an MPC8xx CPU)
 		CONFIG_8xx_GCLK_FREQ	- deprecated: CPU clock if
 					  get_gclk_freq() cannot work
@@ -407,11 +402,11 @@ The following options need to be configured:
 
 		CONFIG_A003399_NOR_WORKAROUND
 		Enables a workaround for IFC erratum A003399. It is only
-		requred during NOR boot.
+		required during NOR boot.
 
 		CONFIG_A008044_WORKAROUND
 		Enables a workaround for T1040/T1042 erratum A008044. It is only
-		requred during NAND boot and valid for Rev 1.0 SoC revision
+		required during NAND boot and valid for Rev 1.0 SoC revision
 
 		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 
@@ -443,7 +438,7 @@ The following options need to be configured:
 		time of U-boot entry and is required to be re-initialized.
 
 		CONFIG_DEEP_SLEEP
-		Inidcates this SoC supports deep sleep feature. If deep sleep is
+		Indicates this SoC supports deep sleep feature. If deep sleep is
 		supported, core will start to execute uboot when wakes up.
 
 - Generic CPU options:
@@ -757,7 +752,7 @@ The following options need to be configured:
 
 		CONFIG_MEMSIZE_IN_BYTES		[relevant for MIPS only]
 
-		When transferring memsize parameter to linux, some versions
+		When transferring memsize parameter to Linux, some versions
 		expect it to be in bytes, others in MB.
 		Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
 
@@ -1967,7 +1962,7 @@ CBFS (Coreboot Filesystem) support
 
 		CONFIG_LCD_ALIGNMENT
 
-		Normally the LCD is page-aligned (tyically 4KB). If this is
+		Normally the LCD is page-aligned (typically 4KB). If this is
 		defined then the LCD will be aligned to this value instead.
 		For ARM it is sometimes useful to use MMU_SECTION_SIZE
 		here, since it is cheaper to change data cache settings on
@@ -2043,7 +2038,7 @@ CBFS (Coreboot Filesystem) support
 		can be displayed via the splashscreen support or the
 		bmp command.
 
-- Do compresssing for memory range:
+- Do compressing for memory range:
 		CONFIG_CMD_ZIP
 
 		If this option is set, it would use zlib deflate method
@@ -2406,7 +2401,7 @@ CBFS (Coreboot Filesystem) support
 		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
 		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
 		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
-		If thoses defines are not set, default value is 100000
+		If those defines are not set, default value is 100000
 		for speed, and 0 for slave.
 
 		- drivers/i2c/rcar_i2c.c:
@@ -2439,7 +2434,7 @@ CBFS (Coreboot Filesystem) support
 		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
 		  - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
 		  - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
-		  - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
+		  - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
 
 		- drivers/i2c/omap24xx_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_OMAP24XX
@@ -2483,7 +2478,7 @@ CBFS (Coreboot Filesystem) support
 		additional defines:
 
 		CONFIG_SYS_NUM_I2C_BUSES
-		Hold the number of i2c busses you want to use. If you
+		Hold the number of i2c buses you want to use. If you
 		don't use/have i2c muxes on your i2c bus, this
 		is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
 		omit this define.
@@ -2499,7 +2494,7 @@ CBFS (Coreboot Filesystem) support
 		define.
 
 		CONFIG_SYS_I2C_BUSES
-		hold a list of busses you want to use, only used if
+		hold a list of buses you want to use, only used if
 		CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
 		a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
 		CONFIG_SYS_NUM_I2C_BUSES = 9:
@@ -2837,14 +2832,14 @@ CBFS (Coreboot Filesystem) support
 
 		CONFIG_SYS_FPGA_WAIT_INIT
 
-		Maximum time to wait for the INIT_B line to deassert
-		after PROB_B has been deasserted during a Virtex II
+		Maximum time to wait for the INIT_B line to de-assert
+		after PROB_B has been de-asserted during a Virtex II
 		FPGA configuration sequence. The default time is 500
 		ms.
 
 		CONFIG_SYS_FPGA_WAIT_BUSY
 
-		Maximum time to wait for BUSY to deassert during
+		Maximum time to wait for BUSY to de-assert during
 		Virtex II FPGA configuration. The default is 5 ms.
 
 		CONFIG_SYS_FPGA_WAIT_CONFIG
@@ -2996,11 +2991,11 @@ CBFS (Coreboot Filesystem) support
 		of the backslashes before semicolons and special
 		symbols.
 
-- Commandline Editing and History:
+- Command Line Editing and History:
 		CONFIG_CMDLINE_EDITING
 
 		Enable editing and History functions for interactive
-		commandline input operations
+		command line input operations
 
 - Default Environment:
 		CONFIG_EXTRA_ENV_SETTINGS
@@ -3051,7 +3046,7 @@ CBFS (Coreboot Filesystem) support
 		CONFIG_DELAY_ENVIRONMENT
 
 		Normally the environment is loaded when the board is
-		intialised so that it is available to U-Boot. This inhibits
+		initialised so that it is available to U-Boot. This inhibits
 		that so that the environment is not available until
 		explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
 		this is instead controlled by the value of
@@ -3097,7 +3092,7 @@ CBFS (Coreboot Filesystem) support
 
 		Define this option to use dual flash support where two flash
 		memories can be connected with a given cs line.
-		currently Xilinx Zynq qspi support these type of connections.
+		Currently Xilinx Zynq qspi supports these type of connections.
 
 		CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
 		enable the W#/Vpp signal to disable writing to the status
@@ -3772,7 +3767,7 @@ FIT uImage format:
 
 		CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 		Define this if you need to first read the OOB and then the
-		data. This is used for example on davinci plattforms.
+		data. This is used, for example, on davinci platforms.
 
 		CONFIG_SPL_OMAP3_ID_NAND
 		Support for an OMAP3-specific set of functions to return the
@@ -4005,7 +4000,7 @@ Configuration Settings:
 		This feature allocates regions with increasing addresses
 		within the region. calloc() is supported, but realloc()
 		is not available. free() is supported but does nothing.
-		The memory will be freed (or in fact just forgotton) when
+		The memory will be freed (or in fact just forgotten) when
 		U-Boot relocates itself.
 
 		Pre-relocation malloc() is only supported on ARM and sandbox
@@ -4016,6 +4011,25 @@ Configuration Settings:
 		boards which do not use the full malloc in SPL (which is
 		enabled with CONFIG_SYS_SPL_MALLOC_START).
 
+- CONFIG_SYS_NONCACHED_MEMORY:
+		Size of non-cached memory area. This area of memory will be
+		typically located right below the malloc() area and mapped
+		uncached in the MMU. This is useful for drivers that would
+		otherwise require a lot of explicit cache maintenance. For
+		some drivers it's also impossible to properly maintain the
+		cache. For example if the regions that need to be flushed
+		are not a multiple of the cache-line size, *and* padding
+		cannot be allocated between the regions to align them (i.e.
+		if the HW requires a contiguous array of regions, and the
+		size of each region is not cache-aligned), then a flush of
+		one region may result in overwriting data that hardware has
+		written to another region in the same cache-line. This can
+		happen for example in network drivers where descriptors for
+		buffers are typically smaller than the CPU cache-line (e.g.
+		16 bytes vs. 32 or 64 bytes).
+
+		Non-cached memory is only supported on 32-bit ARM at present.
+
 - CONFIG_SYS_BOOTM_LEN:
 		Normally compressed uImages are limited to an
 		uncompressed size of 8 MBytes. If this is not enough,
@@ -4147,8 +4161,8 @@ Configuration Settings:
 
 	The format of the list is:
 		type_attribute = [s|d|x|b|i|m]
-		access_atribute = [a|r|o|c]
-		attributes = type_attribute[access_atribute]
+		access_attribute = [a|r|o|c]
+		attributes = type_attribute[access_attribute]
 		entry = variable_name[:attributes]
 		list = entry[,list]
 
@@ -4168,7 +4182,7 @@ Configuration Settings:
 
 	- CONFIG_ENV_FLAGS_LIST_DEFAULT
 		Define this to a list (string) to define the ".flags"
-		envirnoment variable in the default or embedded environment.
+		environment variable in the default or embedded environment.
 
 	- CONFIG_ENV_FLAGS_LIST_STATIC
 		Define this to a list (string) to define validation that
@@ -4194,7 +4208,7 @@ Configuration Settings:
 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
 	This is set by OMAP boards for the max time that reset should
 	be asserted. See doc/README.omap-reset-time for details on how
-	the value can be calulated on a given board.
+	the value can be calculated on a given board.
 
 - CONFIG_USE_STDINT
 	If stdint.h is available with your toolchain you can define this
@@ -4295,7 +4309,7 @@ accordingly!
 	  provision.
 
 BE CAREFUL! The first access to the environment happens quite early
-in U-Boot initalization (when we try to get the setting of for the
+in U-Boot initialization (when we try to get the setting of for the
 console baudrate). You *MUST* have mapped your NVRAM area then, or
 U-Boot will hang.
 
@@ -4518,16 +4532,16 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
                               table, or the whole device D if has no partition
                               table.
                - "D:auto": first partition in device D with bootable flag set.
-                           If none, first valid paratition in device D. If no
+                           If none, first valid partition in device D. If no
                            partition table then means device D.
 
        - FAT_ENV_FILE:
 
          It's a string of the FAT file name. This file use to store the
-         envrionment.
+         environment.
 
        - CONFIG_FAT_WRITE:
-         This should be defined. Otherwise it cannot save the envrionment file.
+         This should be defined. Otherwise it cannot save the environment file.
 
 - CONFIG_ENV_IS_IN_MMC:
 
@@ -4710,7 +4724,7 @@ Low Level (hardware related) configuration options:
 		if CONFIG_SYS_FDC_HW_INIT is defined, then the function
 		fdc_hw_init() is called at the beginning of the FDC
 		setup. fdc_hw_init() must be provided by the board
-		source code. It is used to make hardware dependant
+		source code. It is used to make hardware-dependent
 		initializations.
 
 - CONFIG_IDE_AHB:
@@ -4719,7 +4733,7 @@ Low Level (hardware related) configuration options:
 		When software is doing ATA command and data transfer to
 		IDE devices through IDE-AHB controller, some additional
 		registers accessing to these kind of IDE-AHB controller
-		is requierd.
+		is required.
 
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
@@ -4832,7 +4846,7 @@ Low Level (hardware related) configuration options:
 		required.
 
 - CONFIG_PCI_ENUM_ONLY
-		Only scan through and get the devices on the busses.
+		Only scan through and get the devices on the buses.
 		Don't do any setup work, presumably because someone or
 		something has already done it, and we don't need to do it
 		a second time.	Useful for platforms that are pre-booted
@@ -5454,7 +5468,7 @@ List of environment variables (most likely not complete):
 
   npe_ucode	- set load address for the NPE microcode
 
-  silent_linux  - If set then linux will be told to boot silently, by
+  silent_linux  - If set then Linux will be told to boot silently, by
 		  changing the console to be empty. If "yes" it will be
 		  made silent. If "no" it will not be made silent. If
 		  unset, then it will be made silent if the U-Boot console
@@ -5541,7 +5555,7 @@ Callback functions for environment variables:
 ---------------------------------------------
 
 For some environment variables, the behavior of u-boot needs to change
-when their values are changed.  This functionailty allows functions to
+when their values are changed.  This functionality allows functions to
 be associated with arbitrary variables.  On creation, overwrite, or
 deletion, the callback will provide the opportunity for some side
 effect to happen or for the change to be rejected.
@@ -5564,7 +5578,7 @@ Callbacks can also be associated by defining the ".callbacks" variable
 with the same list format above.  Any association in ".callbacks" will
 override any association in the static list. You can define
 CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
-".callbacks" envirnoment variable in the default or embedded environment.
+".callbacks" environment variable in the default or embedded environment.
 
 
 Command Line Parsing:
@@ -6329,7 +6343,7 @@ code for the initialization procedures:
 * Initialized global data (data segment) is read-only. Do not attempt
   to write it.
 
-* Do not use any uninitialized global data (or implicitely initialized
+* Do not use any uninitialized global data (or implicitly initialized
   as zero data - BSS segment) at all - this is undefined, initiali-
   zation is performed later (when relocating to RAM).
 
@@ -6337,7 +6351,7 @@ code for the initialization procedures:
   that.
 
 Having only the stack as writable memory limits means we cannot use
-normal global data to share information beween the code. But it
+normal global data to share information between the code. But it
 turned out that the implementation of U-Boot can be greatly
 simplified by making a global data structure (gd_t) available to all
 functions. We could pass a pointer to this data as argument to _all_
@@ -6468,7 +6482,7 @@ System Initialization:
 
 In the reset configuration, U-Boot starts at the reset entry point
 (on most PowerPC systems at address 0x00000100). Because of the reset
-configuration for CS0# this is a mirror of the onboard Flash memory.
+configuration for CS0# this is a mirror of the on board Flash memory.
 To be able to re-map memory U-Boot then jumps to its link address.
 To be able to implement the initialization code in C, a (small!)
 initial stack is set up in the internal Dual Ported RAM (in case CPUs
@@ -6584,7 +6598,7 @@ coding style; see the file "Documentation/CodingStyle" and the script
 
 Source files originating from a different project (for example the
 MTD subsystem) are generally exempt from these guidelines and are not
-reformated to ease subsequent migration to newer versions of those
+reformatted to ease subsequent migration to newer versions of those
 sources.
 
 Please note that U-Boot is implemented in C (and to some small parts in

arch/arc/Makefile

@@ -6,3 +6,18 @@ head-y := arch/arc/cpu/$(CPU)/start.o
 
 libs-y += arch/arc/cpu/$(CPU)/
 libs-y += arch/arc/lib/
+
+# MetaWare debugger doesn't support PIE (position-independent executable)
+# so the only way to load U-Boot in MDB is to fake it by:
+#   1. Reset PIE flag in ELF header
+#   2. Strip all debug information from elf
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+	EXEC_TYPE_OFFSET=16
+else
+	EXEC_TYPE_OFFSET=17
+endif
+
+mdbtrick: u-boot
+	$(Q)printf '\x02' | dd of=u-boot bs=1 seek=$(EXEC_TYPE_OFFSET) count=1 \
+		conv=notrunc &> /dev/null
+	$(Q)$(CROSS_COMPILE)strip -g u-boot

arch/arm/config.mk

@@ -26,7 +26,9 @@ PLATFORM_CPPFLAGS += -D__ARM__
 
 # Choose between ARM/Thumb instruction sets
 ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
-PF_CPPFLAGS_ARM := $(call cc-option, -mthumb -mthumb-interwork,\
+AFLAGS_IMPLICIT_IT	:= $(call as-option,-Wa$(comma)-mimplicit-it=always)
+PF_CPPFLAGS_ARM		:= $(AFLAGS_IMPLICIT_IT) \
+			$(call cc-option, -mthumb -mthumb-interwork,\
 			$(call cc-option,-marm,)\
 			$(call cc-option,-mno-thumb-interwork,)\
 		)

arch/arm/cpu/arm926ejs/mx25/Makefile

@@ -5,3 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	= generic.o timer.o reset.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y	+= relocate.o
+endif

arch/arm/cpu/arm926ejs/mx25/generic.c

@@ -181,7 +181,7 @@ int print_cpuinfo(void)
 		(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
 		((cpurev & 0x8000) ? " unknown" : ""),
 		strmhz(buf, imx_get_armclk()));
-	printf("Reset cause: %s\n\n", get_reset_cause());
+	printf("Reset cause: %s\n", get_reset_cause());
 	return 0;
 }
 #endif

arch/arm/cpu/arm926ejs/mx25/relocate.S

@@ -0,0 +1,23 @@
+/*
+ *  relocate - i.MX25-specific vector relocation
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX25 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+	.section	.text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+	bx	lr
+
+ENDPROC(relocate_vectors)

arch/arm/cpu/armv7/am33xx/board.c

@@ -294,7 +294,6 @@ void s_init(void)
 	save_omap_boot_params();
 #endif
 	watchdog_disable();
-	timer_init();
 	set_uart_mux_conf();
 	setup_clocks_for_console();
 	uart_soft_reset();

arch/arm/cpu/armv7/exynos/Kconfig

@@ -24,6 +24,10 @@ config TARGET_TRATS2
 config TARGET_ODROID
 	bool "Exynos4412 Odroid board"
 
+config TARGET_ODROID_XU3
+	bool "Exynos5422 Odroid board"
+	select OF_CONTROL
+
 config TARGET_ARNDALE
 	bool "Exynos5250 Arndale board"
 	select CPU_V7_HAS_NONSEC

arch/arm/cpu/armv7/exynos/clock.c

@@ -848,6 +848,8 @@ static unsigned long exynos5420_get_mmc_clk(int dev_index)
 
 	if (sel == 0x3)
 		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x4)
+		sclk = get_pll_clk(SPLL);
 	else if (sel == 0x6)
 		sclk = get_pll_clk(EPLL);
 	else

arch/arm/cpu/armv7/keystone/init.c

@@ -15,6 +15,16 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/psc_defs.h>
 
+#define MAX_PCI_PORTS		2
+enum pci_mode	{
+	ENDPOINT,
+	LEGACY_ENDPOINT,
+	ROOTCOMPLEX,
+};
+
+#define DEVCFG_MODE_MASK		(BIT(2) | BIT(1))
+#define DEVCFG_MODE_SHIFT		1
+
 void chip_configuration_unlock(void)
 {
 	__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
@@ -68,6 +78,24 @@ void osr_init(void)
 }
 #endif
 
+/* Function to set up PCIe mode */
+static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
+{
+	u32 val = __raw_readl(KS2_DEVCFG);
+
+	if (pcie_port >= MAX_PCI_PORTS)
+		return;
+
+	/**
+	 * each pci port has two bits for mode and it starts at
+	 * bit 1. So use port number to get the right bit position.
+	 */
+	pcie_port <<= 1;
+	val &= ~(DEVCFG_MODE_MASK << pcie_port);
+	val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
+	__raw_writel(val, KS2_DEVCFG);
+}
+
 int arch_cpu_init(void)
 {
 	chip_configuration_unlock();
@@ -77,8 +105,13 @@ int arch_cpu_init(void)
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+
+	/* Initialize the PCIe-0 to work as Root Complex */
+	config_pcie_mode(0, ROOTCOMPLEX);
 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
+	/* Initialize the PCIe-1 to work as Root Complex */
+	config_pcie_mode(1, ROOTCOMPLEX);
 #endif
 #ifdef CONFIG_SOC_K2L
 	osr_init();

arch/arm/cpu/armv7/mx6/clock.c

@@ -434,6 +434,56 @@ static u32 get_mmdc_ch0_clk(void)
 }
 #endif
 
+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+	u32 reg = 0;
+	/* Enable QuadSPI clock */
+	switch (qspi_num) {
+	case 0:
+		/* disable the clock gate */
+		clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+		/* set 50M  : (50 = 396 / 2 / 4) */
+		reg = readl(&imx_ccm->cscmr1);
+		reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+			 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+		reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+			(2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+		writel(reg, &imx_ccm->cscmr1);
+
+		/* enable the clock gate */
+		setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+		break;
+	case 1:
+		/*
+		 * disable the clock gate
+		 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+		 * disable both of them.
+		 */
+		clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+			     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+		/* set 50M  : (50 = 396 / 2 / 4) */
+		reg = readl(&imx_ccm->cs2cdr);
+		reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+			 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+			 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+		reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+			MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+		writel(reg, &imx_ccm->cs2cdr);
+
+		/*enable the clock gate*/
+		setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+			     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+		break;
+	default:
+		break;
+	}
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 int enable_fec_anatop_clock(enum enet_freq freq)
 {
@@ -746,10 +796,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_SATA_CLK:
 		return get_ahb_clk();
 	default:
+		printf("Unsupported MXC CLK: %d\n", clk);
 		break;
 	}
 
-	return -1;
+	return 0;
 }
 
 /*

arch/arm/cpu/armv7/omap-common/boot-common.c

@@ -9,12 +9,14 @@
  */
 
 #include <common.h>
+#include <ahci.h>
 #include <spl.h>
 #include <asm/omap_common.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <watchdog.h>
+#include <scsi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -143,3 +145,10 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	image_entry((u32 *)&gd->arch.omap_boot_params);
 }
 #endif
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+void arch_preboot_os(void)
+{
+	ahci_reset(DWC_AHSATA_BASE);
+}
+#endif

arch/arm/cpu/armv7/omap-common/sata.c

@@ -85,3 +85,9 @@ void scsi_init(void)
 	init_sata(0);
 	scsi_scan(1);
 }
+
+void scsi_bus_reset(void)
+{
+	ahci_reset(DWC_AHSATA_BASE);
+	ahci_init(DWC_AHSATA_BASE);
+}

arch/arm/cpu/armv7/omap-common/timer.c

@@ -41,11 +41,6 @@ int timer_init(void)
 	writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
 		&timer_base->tclr);
 
-	/* reset time, capture current incrementer value time */
-	gd->arch.lastinc = readl(&timer_base->tcrr) /
-					(TIMER_CLOCK / CONFIG_SYS_HZ);
-	gd->arch.tbl = 0;	/* start "advancing" time stamp from 0 */
-
 	return 0;
 }
 

arch/arm/cpu/armv7/omap4/sdram_elpida.c

@@ -121,8 +121,6 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 		*regs = &emif_regs_elpida_380_mhz_1cs;
 	else if (omap4_rev == OMAP4430_ES2_0)
 		*regs = &emif_regs_elpida_200_mhz_2cs;
-	else if (omap4_rev == OMAP4430_ES2_3)
-		*regs = &emif_regs_elpida_400_mhz_1cs;
 	else if (omap4_rev < OMAP4470_ES1_0)
 		*regs = &emif_regs_elpida_400_mhz_2cs;
 	else
@@ -138,8 +136,6 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 
 	if (omap_rev == OMAP4430_ES1_0)
 		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
-	else if (omap_rev == OMAP4430_ES2_3)
-		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 	else if (omap_rev < OMAP4460_ES1_0)
 		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 	else

arch/arm/cpu/armv7/socfpga/lowlevel_init.S

@@ -7,13 +7,6 @@
 #include <config.h>
 #include <version.h>
 
-/* Save the parameter pass in by previous boot loader */
-.global save_boot_params
-save_boot_params:
-	/* no parameter to save */
-	bx	lr
-
-
 /* Set up the platform, once the cpu has been initialized */
 .globl lowlevel_init
 lowlevel_init:

arch/arm/cpu/armv7/socfpga/misc.c

@@ -9,6 +9,7 @@
 #include <altera.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <watchdog.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/system_manager.h>
 #include <asm/arch/dwmmc.h>
@@ -150,14 +151,23 @@ static inline void socfpga_fpga_add(void) {}
 
 int arch_cpu_init(void)
 {
+#ifdef CONFIG_HW_WATCHDOG
+	/*
+	 * In case the watchdog is enabled, make sure to (re-)configure it
+	 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
+	 * timeout value is still active which might too short for Linux
+	 * booting.
+	 */
+	hw_watchdog_init();
+#else
 	/*
 	 * If the HW watchdog is NOT enabled, make sure it is not running,
 	 * for example because it was enabled in the preloader. This might
 	 * trigger a watchdog-triggered reboot of Linux kernel later.
 	 */
-#ifndef CONFIG_HW_WATCHDOG
 	socfpga_watchdog_reset();
 #endif
+
 	return 0;
 }
 

arch/arm/cpu/armv7/uniphier/Kconfig

@@ -65,6 +65,13 @@ config DRAM_INIT
 	bool
 	default SPL_BUILD
 
+config CMD_DDRPHY_DUMP
+	bool "Enable dump command of DDR PHY parameters"
+	depends on !SPL_BUILD
+	help
+	  The command "ddrphy" shows the resulting parameters of DDR PHY
+	  training; it is useful for the evaluation of DDR PHY training.
+
 choice
 	prompt "DDR3 Frequency select"
 	depends on DRAM_INIT

arch/arm/cpu/armv7/uniphier/Makefile

@@ -10,11 +10,13 @@ obj-y += reset.o
 obj-y += cache_uniphier.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
 obj-y += dram_init.o
+obj-$(CONFIG_DRAM_INIT) += ddrphy_training.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
 obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
 obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
 obj-$(CONFIG_UNIPHIER_SMP) += smp.o
 obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
+obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
 
 obj-y += board_common.o
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o

arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c

@@ -0,0 +1,229 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+/* Select either decimal or hexadecimal */
+#if 1
+#define PRINTF_FORMAT "%2d"
+#else
+#define PRINTF_FORMAT "%02x"
+#endif
+/* field separator */
+#define FS "   "
+
+static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
+{
+	return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
+}
+
+static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
+{
+	int ch, p, dx;
+	struct ddrphy __iomem *phy;
+
+	for (ch = 0; ch < NR_DDRCH; ch++) {
+		for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
+			phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
+
+			for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+				printf("CH%dP%dDX%d:", ch, p, dx);
+				(*callback)(&phy->dx[dx]);
+				printf("\n");
+			}
+		}
+	}
+}
+
+static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+	int i;
+
+	for (i = 0; i < 10; i++)
+		printf(FS PRINTF_FORMAT, read_bdl(dx, i));
+
+	printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
+}
+
+void wbdl_dump(void)
+{
+	printf("\n--- Write Bit Delay Line ---\n");
+	printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  DQS  (WDQD)\n");
+
+	dump_loop(&__wbdl_dump);
+}
+
+static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+	int i;
+
+	for (i = 15; i < 24; i++)
+		printf(FS PRINTF_FORMAT, read_bdl(dx, i));
+
+	printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
+}
+
+void rbdl_dump(void)
+{
+	printf("\n--- Read Bit Delay Line ---\n");
+	printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  (RDQSD)\n");
+
+	dump_loop(&__rbdl_dump);
+}
+
+static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
+{
+	int rank;
+	u32 lcdlr0 = readl(&dx->lcdlr[0]);
+	u32 gtr = readl(&dx->gtr);
+
+	for (rank = 0; rank < 4; rank++) {
+		u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
+		u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
+
+		printf(FS PRINTF_FORMAT "%sT", wld,
+		       wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
+	}
+}
+
+void wld_dump(void)
+{
+	printf("\n--- Write Leveling Delay ---\n");
+	printf("            Rank0   Rank1   Rank2   Rank3\n");
+
+	dump_loop(&__wld_dump);
+}
+
+static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
+{
+	int rank;
+	u32 lcdlr2 = readl(&dx->lcdlr[2]);
+	u32 gtr = readl(&dx->gtr);
+
+	for (rank = 0; rank < 4; rank++) {
+		u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
+		u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
+
+		printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
+	}
+}
+
+void dqsgd_dump(void)
+{
+	printf("\n--- DQS Gating Delay ---\n");
+	printf("            Rank0   Rank1   Rank2   Rank3\n");
+
+	dump_loop(&__dqsgd_dump);
+}
+
+static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+	int i;
+	u32 mdl = readl(&dx->mdlr);
+	for (i = 0; i < 3; i++)
+		printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
+}
+
+void mdl_dump(void)
+{
+	printf("\n--- Master Delay Line ---\n");
+	printf("          IPRD TPRD MDLD\n");
+
+	dump_loop(&__mdl_dump);
+}
+
+#define REG_DUMP(x) \
+	{ u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
+					p - (u32 *)phy, #x, p, readl(p)); }
+
+void reg_dump(void)
+{
+	int ch, p;
+	struct ddrphy __iomem *phy;
+
+	printf("\n--- DDR PHY registers ---\n");
+
+	for (ch = 0; ch < NR_DDRCH; ch++) {
+		for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
+			printf("== Ch%d, PHY%d ==\n", ch, p);
+			printf(" No: Name      : Address  : Data\n");
+
+			phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
+
+			REG_DUMP(ridr);
+			REG_DUMP(pir);
+			REG_DUMP(pgcr[0]);
+			REG_DUMP(pgcr[1]);
+			REG_DUMP(pgsr[0]);
+			REG_DUMP(pgsr[1]);
+			REG_DUMP(pllcr);
+			REG_DUMP(ptr[0]);
+			REG_DUMP(ptr[1]);
+			REG_DUMP(ptr[2]);
+			REG_DUMP(ptr[3]);
+			REG_DUMP(ptr[4]);
+			REG_DUMP(acmdlr);
+			REG_DUMP(acbdlr);
+			REG_DUMP(dxccr);
+			REG_DUMP(dsgcr);
+			REG_DUMP(dcr);
+			REG_DUMP(dtpr[0]);
+			REG_DUMP(dtpr[1]);
+			REG_DUMP(dtpr[2]);
+			REG_DUMP(mr0);
+			REG_DUMP(mr1);
+			REG_DUMP(mr2);
+			REG_DUMP(mr3);
+			REG_DUMP(dx[0].gcr);
+			REG_DUMP(dx[0].gtr);
+			REG_DUMP(dx[1].gcr);
+			REG_DUMP(dx[1].gtr);
+		}
+	}
+}
+
+static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *cmd = argv[1];
+
+	if (argc == 1)
+		cmd = "all";
+
+	if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
+		wbdl_dump();
+
+	if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
+		rbdl_dump();
+
+	if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
+		wld_dump();
+
+	if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
+		dqsgd_dump();
+
+	if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
+		mdl_dump();
+
+	if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
+		reg_dump();
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	ddr,	2,	1,	do_ddr,
+	"UniPhier DDR PHY parameters dumper",
+	"- dump all of the followings\n"
+	"ddr wbdl - dump Write Bit Delay\n"
+	"ddr rbdl - dump Read Bit Delay\n"
+	"ddr wld - dump Write Leveling\n"
+	"ddr dqsgd - dump DQS Gating Delay\n"
+	"ddr mdl - dump Master Delay Line\n"
+	"ddr reg - dump registers\n"
+);

arch/arm/cpu/armv7/uniphier/cmd_pinmon.c

@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <asm/arch/boot-device.h>
+#include <asm/arch/sbc-regs.h>
 
 static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -15,6 +16,8 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	mode_sel = get_boot_mode_sel();
 
+	printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
+
 	puts("Boot Mode Pin:\n");
 
 	for (table = boot_device_table; strlen(table->info); table++) {

arch/arm/cpu/armv7/uniphier/ddrphy_training.c

@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
+{
+	int dx;
+	u32 __iomem tmp, *p;
+
+	for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+		p = &phy->dx[dx].gcr;
+
+		tmp = readl(p);
+		/* Specify the rank that should be write leveled */
+		tmp &= ~DXGCR_WLRKEN_MASK;
+		tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
+		writel(tmp, p);
+	}
+
+	p = &phy->dtcr;
+
+	tmp = readl(p);
+	/* Specify the rank used during data bit deskew and eye centering */
+	tmp &= ~DTCR_DTRANK_MASK;
+	tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
+	/* Use Multi-Purpose Register for DQS gate training */
+	tmp |= DTCR_DTMPR;
+	/* Specify the rank enabled for data-training */
+	tmp &= ~DTCR_RNKEN_MASK;
+	tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
+	writel(tmp, p);
+}
+
+struct ddrphy_init_sequence {
+	char *description;
+	u32 init_flag;
+	u32 done_flag;
+	u32 err_flag;
+};
+
+static struct ddrphy_init_sequence init_sequence[] = {
+	{
+		"DRAM Initialization",
+		PIR_DRAMRST | PIR_DRAMINIT,
+		PGSR0_DIDONE,
+		PGSR0_DIERR
+	},
+	{
+		"Write Leveling",
+		PIR_WL,
+		PGSR0_WLDONE,
+		PGSR0_WLERR
+	},
+	{
+		"Read DQS Gate Training",
+		PIR_QSGATE,
+		PGSR0_QSGDONE,
+		PGSR0_QSGERR
+	},
+	{
+		"Write Leveling Adjustment",
+		PIR_WLADJ,
+		PGSR0_WLADONE,
+		PGSR0_WLAERR
+	},
+	{
+		"Read Bit Deskew",
+		PIR_RDDSKW,
+		PGSR0_RDDONE,
+		PGSR0_RDERR
+	},
+	{
+		"Write Bit Deskew",
+		PIR_WRDSKW,
+		PGSR0_WDDONE,
+		PGSR0_WDERR
+	},
+	{
+		"Read Eye Training",
+		PIR_RDEYE,
+		PGSR0_REDONE,
+		PGSR0_REERR
+	},
+	{
+		"Write Eye Training",
+		PIR_WREYE,
+		PGSR0_WEDONE,
+		PGSR0_WEERR
+	}
+};
+
+int ddrphy_training(struct ddrphy __iomem *phy)
+{
+	int i;
+	u32 pgsr0;
+	u32 init_flag = PIR_INIT;
+	u32 done_flag = PGSR0_IDONE;
+	int timeout = 50000; /* 50 msec is long enough */
+#ifdef DISPLAY_ELAPSED_TIME
+	ulong start = get_timer(0);
+#endif
+
+	for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+		init_flag |= init_sequence[i].init_flag;
+		done_flag |= init_sequence[i].done_flag;
+	}
+
+	writel(init_flag, &phy->pir);
+
+	do {
+		if (--timeout < 0) {
+#ifndef CONFIG_SPL_BUILD
+			printf("%s: error: timeout during DDR training\n",
+								__func__);
+#endif
+			return -1;
+		}
+		udelay(1);
+		pgsr0 = readl(&phy->pgsr[0]);
+	} while ((pgsr0 & done_flag) != done_flag);
+
+	for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+		if (pgsr0 & init_sequence[i].err_flag) {
+#ifndef CONFIG_SPL_BUILD
+			printf("%s: error: %s failed\n", __func__,
+						init_sequence[i].description);
+#endif
+			return -1;
+		}
+	}
+
+#ifdef DISPLAY_ELAPSED_TIME
+	printf("%s: info: elapsed time %ld msec\n", get_timer(start));
+#endif
+
+	return 0;
+}

arch/arm/cpu/armv7/uniphier/lowlevel_init.S

@@ -26,6 +26,10 @@ ENTRY(lowlevel_init)
 	orr	r0, r0, #(CR_C | CR_M)		@ enable MMU and Dcache
 	mcr	p15, 0, r0, c1, c0, 0
 
+#ifdef CONFIG_DEBUG_LL
+	bl	setup_lowlevel_debug
+#endif
+
 	/*
 	 * Now we are using the page table embedded in the Boot ROM.
 	 * It is not handy since it is not a straight mapped table for sLD3.

arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile

@@ -5,7 +5,8 @@
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
 obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
 obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
 								clkrst_init.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
-obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
+obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o

arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c

@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+	u32 tmp;
+
+	writel(0x0300c473, &phy->pgcr[1]);
+	if (freq == 1333) {
+		writel(0x0a806844, &phy->ptr[0]);
+		writel(0x208e0124, &phy->ptr[1]);
+	} else {
+		writel(0x0c807d04, &phy->ptr[0]);
+		writel(0x2710015E, &phy->ptr[1]);
+	}
+	writel(0x00083DEF, &phy->ptr[2]);
+	if (freq == 1333) {
+		writel(0x0f051616, &phy->ptr[3]);
+		writel(0x06ae08d6, &phy->ptr[4]);
+	} else {
+		writel(0x12061A80, &phy->ptr[3]);
+		writel(0x08027100, &phy->ptr[4]);
+	}
+	writel(0xF004001A, &phy->dsgcr);
+
+	/* change the value of the on-die pull-up/pull-down registors */
+	tmp = readl(&phy->dxccr);
+	tmp &= ~0x0ee0;
+	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+	writel(tmp, &phy->dxccr);
+
+	writel(0x0000040B, &phy->dcr);
+	if (freq == 1333) {
+		writel(0x85589955, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a8253c0, &phy->dtpr[1]);
+		else
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		writel(0x5002c200, &phy->dtpr[2]);
+		writel(0x00000b51, &phy->mr0);
+	} else {
+		writel(0x999cbb66, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a82dbc0, &phy->dtpr[1]);
+		else
+			writel(0x1a878400, &phy->dtpr[1]);
+		writel(0xa00214f8, &phy->dtpr[2]);
+		writel(0x00000d71, &phy->mr0);
+	}
+	writel(0x00000006, &phy->mr1);
+	if (freq == 1333)
+		writel(0x00000290, &phy->mr2);
+	else
+		writel(0x00000298, &phy->mr2);
+
+	writel(0x00000800, &phy->mr3);
+
+	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+		;
+
+	writel(0x0300C473, &phy->pgcr[1]);
+	writel(0x0000005D, &phy->zq[0].cr[1]);
+}

arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S

@@ -0,0 +1,29 @@
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/sg-regs.h>
+
+#define UART_CLK		36864000
+#include <asm/arch/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+		init_debug_uart	r0, r1, r2
+
+		/* UART Port 0 */
+		set_pinsel	85, 1, r0, r1
+		set_pinsel	88, 1, r0, r1
+
+		ldr		r0, =SG_IECTRL
+		ldr		r1, [r0]
+		orr		r1, r1, #1
+		str		r1, [r0]
+
+		mov		pc, lr
+ENDPROC(setup_lowlevel_debug)

arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c

@@ -12,6 +12,13 @@
 
 void sbc_init(void)
 {
+	u32 tmp;
+
+	/* system bus output enable */
+	tmp = readl(PC0CTRL);
+	tmp &= 0xfffffcff;
+	writel(tmp, PC0CTRL);
+
 	/* XECS1: sub/boot memory (boot swap = off/on) */
 	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
 	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);

arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c

@@ -7,6 +7,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/umc-regs.h>
+#include <asm/arch/ddrphy-regs.h>
 
 static inline void umc_start_ssif(void __iomem *ssif_base)
 {
@@ -125,6 +126,8 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
 	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
 	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
 	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+	void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+	void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
 
 	umc_dram_init_start(dramcont0);
 	umc_dram_init_start(dramcont1);
@@ -133,8 +136,18 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
 
 	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
+	ddrphy_init(phy0_0, freq, size_ch0);
+
+	ddrphy_prepare_training(phy0_0, 0);
+	ddrphy_training(phy0_0);
+
 	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
+	ddrphy_init(phy1_0, freq, size_ch1);
+
+	ddrphy_prepare_training(phy1_0, 1);
+	ddrphy_training(phy1_0);
+
 	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
 	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
 

arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile

@@ -5,6 +5,7 @@
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
 obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
 obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
-obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
+obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o

arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c

@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+	u32 tmp;
+
+	writel(0x0300c473, &phy->pgcr[1]);
+	if (freq == 1333) {
+		writel(0x0a806844, &phy->ptr[0]);
+		writel(0x208e0124, &phy->ptr[1]);
+	} else {
+		writel(0x0c807d04, &phy->ptr[0]);
+		writel(0x2710015E, &phy->ptr[1]);
+	}
+	writel(0x00083DEF, &phy->ptr[2]);
+	if (freq == 1333) {
+		writel(0x0f051616, &phy->ptr[3]);
+		writel(0x06ae08d6, &phy->ptr[4]);
+	} else {
+		writel(0x12061A80, &phy->ptr[3]);
+		writel(0x08027100, &phy->ptr[4]);
+	}
+	writel(0xF004001A, &phy->dsgcr);
+
+	/* change the value of the on-die pull-up/pull-down registors */
+	tmp = readl(&phy->dxccr);
+	tmp &= ~0x0ee0;
+	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+	writel(tmp, &phy->dxccr);
+
+	writel(0x0000040B, &phy->dcr);
+	if (freq == 1333) {
+		writel(0x85589955, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		else
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		writel(0x5002c200, &phy->dtpr[2]);
+		writel(0x00000b51, &phy->mr0);
+	} else {
+		writel(0x999cbb66, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a878400, &phy->dtpr[1]);
+		else
+			writel(0x1a878400, &phy->dtpr[1]);
+		writel(0xa00214f8, &phy->dtpr[2]);
+		writel(0x00000d71, &phy->mr0);
+	}
+	writel(0x00000006, &phy->mr1);
+	if (freq == 1333)
+		writel(0x00000290, &phy->mr2);
+	else
+		writel(0x00000298, &phy->mr2);
+
+	writel(0x00000000, &phy->mr3);
+
+	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+		;
+
+	writel(0x0300C473, &phy->pgcr[1]);
+	writel(0x0000005D, &phy->zq[0].cr[1]);
+}

arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S

@@ -0,0 +1,39 @@
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/sc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+#define UART_CLK		73728000
+#include <asm/arch/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+		ldr		r0, =SC_CLKCTRL
+		ldr		r1, [r0]
+		orr		r1, r1, #SC_CLKCTRL_CLK_PERI
+		str		r1, [r0]
+
+		init_debug_uart	r0, r1, r2
+
+		/* UART Port 0 */
+		set_pinsel	127, 0, r0, r1
+		set_pinsel	128, 0, r0, r1
+
+		ldr		r0, =SG_LOADPINCTRL
+		mov		r1, #1
+		str		r1, [r0]
+
+		ldr		r0, =SG_IECTRL
+		ldr		r1, [r0]
+		orr		r1, r1, #1
+		str		r1, [r0]
+
+		mov		pc, lr
+ENDPROC(setup_lowlevel_debug)

arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c

@@ -7,6 +7,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/umc-regs.h>
+#include <asm/arch/ddrphy-regs.h>
 
 static inline void umc_start_ssif(void __iomem *ssif_base)
 {
@@ -94,6 +95,10 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
 	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
 	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
 	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+	void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+	void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
+	void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+	void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
 
 	umc_dram_init_start(dramcont0);
 	umc_dram_init_start(dramcont1);
@@ -102,12 +107,32 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
 
 	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
+	ddrphy_init(phy0_0, freq, size_ch0);
+
+	ddrphy_prepare_training(phy0_0, 0);
+	ddrphy_training(phy0_0);
+
 	writel(0x00000103, dramcont0 + UMC_DIOCTLA);
 
+	ddrphy_init(phy0_1, freq, size_ch0);
+
+	ddrphy_prepare_training(phy0_1, 1);
+	ddrphy_training(phy0_1);
+
 	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
+	ddrphy_init(phy1_0, freq, size_ch1);
+
+	ddrphy_prepare_training(phy1_0, 0);
+	ddrphy_training(phy1_0);
+
 	writel(0x00000103, dramcont1 + UMC_DIOCTLA);
 
+	ddrphy_init(phy1_1, freq, size_ch1);
+
+	ddrphy_prepare_training(phy1_1, 1);
+	ddrphy_training(phy1_1);
+
 	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
 	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
 

arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile

@@ -5,7 +5,8 @@
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
 obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
 obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
 								clkrst_init.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
-obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
+obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o

arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+	u32 tmp;
+
+	writel(0x0300c473, &phy->pgcr[1]);
+	if (freq == 1333) {
+		writel(0x0a806844, &phy->ptr[0]);
+		writel(0x208e0124, &phy->ptr[1]);
+	} else {
+		writel(0x0c807d04, &phy->ptr[0]);
+		writel(0x2710015E, &phy->ptr[1]);
+	}
+	writel(0x00083DEF, &phy->ptr[2]);
+	if (freq == 1333) {
+		writel(0x0f051616, &phy->ptr[3]);
+		writel(0x06ae08d6, &phy->ptr[4]);
+	} else {
+		writel(0x12061A80, &phy->ptr[3]);
+		writel(0x08027100, &phy->ptr[4]);
+	}
+	writel(0xF004001A, &phy->dsgcr);
+
+	/* change the value of the on-die pull-up/pull-down registors */
+	tmp = readl(&phy->dxccr);
+	tmp &= ~0x0ee0;
+	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+	writel(tmp, &phy->dxccr);
+
+	writel(0x0000040B, &phy->dcr);
+	if (freq == 1333) {
+		writel(0x85589955, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		else
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		writel(0x5002c200, &phy->dtpr[2]);
+		writel(0x00000b51, &phy->mr0);
+	} else {
+		writel(0x999cbb66, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a878400, &phy->dtpr[1]);
+		else
+			writel(0x1a878400, &phy->dtpr[1]);
+		writel(0xa00214f8, &phy->dtpr[2]);
+		writel(0x00000d71, &phy->mr0);
+	}
+	writel(0x00000006, &phy->mr1);
+	if (freq == 1333)
+		writel(0x00000290, &phy->mr2);
+	else
+		writel(0x00000298, &phy->mr2);
+
+#ifdef CONFIG_DDR_STANDARD
+	writel(0x00000000, &phy->mr3);
+#else
+	writel(0x00000800, &phy->mr3);
+#endif
+
+	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+		;
+
+	writel(0x0300C473, &phy->pgcr[1]);
+	writel(0x0000005D, &phy->zq[0].cr[1]);
+}

arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S

@@ -0,0 +1,29 @@
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/sg-regs.h>
+
+#define UART_CLK		80000000
+#include <asm/arch/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+		init_debug_uart	r0, r1, r2
+
+		/* UART Port 0 */
+		set_pinsel	70, 3, r0, r1
+		set_pinsel	71, 3, r0, r1
+
+		ldr		r0, =SG_IECTRL
+		ldr		r1, [r0]
+		orr		r1, r1, #1
+		str		r1, [r0]
+
+		mov		pc, lr
+ENDPROC(setup_lowlevel_debug)

arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c

@@ -12,6 +12,13 @@
 
 void sbc_init(void)
 {
+	u32 tmp;
+
+	/* system bus output enable */
+	tmp = readl(PC0CTRL);
+	tmp &= 0xfffffcff;
+	writel(tmp, PC0CTRL);
+
 #if !defined(CONFIG_SPL_BUILD)
 	/* XECS0 : dummy */
 	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);

arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c

@@ -7,6 +7,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/umc-regs.h>
+#include <asm/arch/ddrphy-regs.h>
 
 static inline void umc_start_ssif(void __iomem *ssif_base)
 {
@@ -105,6 +106,8 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
 	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
 	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
 	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+	void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+	void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
 
 	umc_dram_init_start(dramcont0);
 	umc_dram_init_start(dramcont1);
@@ -113,8 +116,18 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
 
 	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
+	ddrphy_init(phy0_0, freq, size_ch0);
+
+	ddrphy_prepare_training(phy0_0, 0);
+	ddrphy_training(phy0_0);
+
 	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
+	ddrphy_init(phy1_0, freq, size_ch1);
+
+	ddrphy_prepare_training(phy1_0, 1);
+	ddrphy_training(phy1_0);
+
 	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
 	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
 

arch/arm/cpu/armv7/uniphier/support_card.c

@@ -160,12 +160,12 @@ static const struct memory_bank memory_banks_boot_swap_on[] = {
 
 #if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
 static const struct memory_bank memory_banks_boot_swap_off[] = {
-	{0x04000000, 0x04000000},
+	{0x04000000, 0x02000000},
 };
 
 static const struct memory_bank memory_banks_boot_swap_on[] = {
-	{0x00000000, 0x04000000},
-	{0x04000000, 0x04000000},
+	{0x00000000, 0x02000000},
+	{0x04000000, 0x02000000},
 };
 #endif
 

arch/arm/cpu/armv7/virt-dt.c

@@ -90,6 +90,8 @@ static int fdt_psci(void *fdt)
 
 int armv7_update_dt(void *fdt)
 {
+	if (!armv7_boot_nonsec())
+		return 0;
 #ifndef CONFIG_ARMV7_SECURE_BASE
 	/* secure code lives in RAM, keep it alive */
 	fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,

arch/arm/cpu/tegra-common/Makefile

@@ -13,5 +13,7 @@ obj-y += cache.o
 obj-y += clock.o
 obj-y += lowlevel_init.o
 obj-y += pinmux-common.o
+obj-y += powergate.o
+obj-y += xusb-padctl.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
 obj-$(CONFIG_TEGRA124) += vpr.o

arch/arm/cpu/tegra-common/powergate.c

@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+
+#include <asm/io.h>
+#include <asm/types.h>
+
+#include <asm/arch/powergate.h>
+#include <asm/arch/tegra.h>
+
+#define PWRGATE_TOGGLE 0x30
+#define  PWRGATE_TOGGLE_START (1 << 8)
+
+#define REMOVE_CLAMPING 0x34
+
+#define PWRGATE_STATUS 0x38
+
+static int tegra_powergate_set(enum tegra_powergate id, bool state)
+{
+	u32 value, mask = state ? (1 << id) : 0, old_mask;
+	unsigned long start, timeout = 25;
+
+	value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+	old_mask = value & (1 << id);
+
+	if (mask == old_mask)
+		return 0;
+
+	writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
+
+	start = get_timer(0);
+
+	while (get_timer(start) < timeout) {
+		value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+		if ((value & (1 << id)) == mask)
+			return 0;
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int tegra_powergate_power_on(enum tegra_powergate id)
+{
+	return tegra_powergate_set(id, true);
+}
+
+int tegra_powergate_power_off(enum tegra_powergate id)
+{
+	return tegra_powergate_set(id, false);
+}
+
+static int tegra_powergate_remove_clamping(enum tegra_powergate id)
+{
+	unsigned long value;
+
+	/*
+	 * The REMOVE_CLAMPING register has the bits for the PCIE and VDEC
+	 * partitions reversed. This was originally introduced on Tegra20 but
+	 * has since been carried forward for backwards-compatibility.
+	 */
+	if (id == TEGRA_POWERGATE_VDEC)
+		value = 1 << TEGRA_POWERGATE_PCIE;
+	else if (id == TEGRA_POWERGATE_PCIE)
+		value = 1 << TEGRA_POWERGATE_VDEC;
+	else
+		value = 1 << id;
+
+	writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
+
+	return 0;
+}
+
+int tegra_powergate_sequence_power_up(enum tegra_powergate id,
+				      enum periph_id periph)
+{
+	int err;
+
+	reset_set_enable(periph, 1);
+
+	err = tegra_powergate_power_on(id);
+	if (err < 0)
+		return err;
+
+	clock_enable(periph);
+
+	udelay(10);
+
+	err = tegra_powergate_remove_clamping(id);
+	if (err < 0)
+		return err;
+
+	udelay(10);
+
+	reset_set_enable(periph, 0);
+
+	return 0;
+}

arch/arm/cpu/tegra-common/xusb-padctl.c

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+
+#include <asm/arch-tegra/xusb-padctl.h>
+
+struct tegra_xusb_phy * __weak tegra_xusb_phy_get(unsigned int type)
+{
+	return NULL;
+}
+
+int __weak tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
+{
+	return -ENOSYS;
+}
+
+int __weak tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
+{
+	return -ENOSYS;
+}
+
+int __weak tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
+{
+	return -ENOSYS;
+}
+
+int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
+{
+	return -ENOSYS;
+}
+
+void __weak tegra_xusb_padctl_init(const void *fdt)
+{
+}

arch/arm/cpu/tegra124-common/Makefile

@@ -8,3 +8,4 @@
 obj-y	+= clock.o
 obj-y	+= funcmux.o
 obj-y	+= pinmux.o
+obj-y	+= xusb-padctl.o

arch/arm/cpu/tegra124-common/clock.c

@@ -824,3 +824,112 @@ void arch_timer_init(void)
 	writel(val, &sysctr->cntcr);
 	debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
 }
+
+#define PLLE_SS_CNTL 0x68
+#define  PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
+#define  PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
+#define  PLLE_SS_CNTL_SSCINVERT (1 << 15)
+#define  PLLE_SS_CNTL_SSCCENTER (1 << 14)
+#define  PLLE_SS_CNTL_SSCBYP (1 << 12)
+#define  PLLE_SS_CNTL_INTERP_RESET (1 << 11)
+#define  PLLE_SS_CNTL_BYPASS_SS (1 << 10)
+#define  PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
+
+#define PLLE_BASE 0x0e8
+#define  PLLE_BASE_ENABLE (1 << 30)
+#define  PLLE_BASE_LOCK_OVERRIDE (1 << 29)
+#define  PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
+#define  PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
+#define  PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
+
+#define PLLE_MISC 0x0ec
+#define  PLLE_MISC_IDDQ_SWCTL (1 << 14)
+#define  PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
+#define  PLLE_MISC_LOCK_ENABLE (1 << 9)
+#define  PLLE_MISC_PTS (1 << 8)
+#define  PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
+#define  PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
+
+#define PLLE_AUX 0x48c
+#define  PLLE_AUX_SEQ_ENABLE (1 << 24)
+#define  PLLE_AUX_ENABLE_SWCTL (1 << 4)
+
+int tegra_plle_enable(void)
+{
+	unsigned int m = 1, n = 200, cpcon = 13;
+	u32 value;
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+	value &= ~PLLE_BASE_LOCK_OVERRIDE;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
+	value |= PLLE_AUX_ENABLE_SWCTL;
+	value &= ~PLLE_AUX_SEQ_ENABLE;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
+
+	udelay(1);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+	value |= PLLE_MISC_IDDQ_SWCTL;
+	value &= ~PLLE_MISC_IDDQ_OVERRIDE;
+	value |= PLLE_MISC_LOCK_ENABLE;
+	value |= PLLE_MISC_PTS;
+	value |= PLLE_MISC_VREG_BG_CTRL(3);
+	value |= PLLE_MISC_VREG_CTRL(2);
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+	udelay(5);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+	value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
+		 PLLE_SS_CNTL_BYPASS_SS;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+	value &= ~PLLE_BASE_PLDIV_CML(0xf);
+	value &= ~PLLE_BASE_NDIV(0xff);
+	value &= ~PLLE_BASE_MDIV(0xff);
+	value |= PLLE_BASE_PLDIV_CML(cpcon);
+	value |= PLLE_BASE_NDIV(n);
+	value |= PLLE_BASE_MDIV(m);
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+	udelay(1);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+	value |= PLLE_BASE_ENABLE;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+	/* wait for lock */
+	udelay(300);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+	value &= ~PLLE_SS_CNTL_SSCINVERT;
+	value &= ~PLLE_SS_CNTL_SSCCENTER;
+
+	value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
+	value &= ~PLLE_SS_CNTL_SSCINC(0xff);
+	value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
+
+	value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
+	value |= PLLE_SS_CNTL_SSCINC(0x01);
+	value |= PLLE_SS_CNTL_SSCMAX(0x25);
+
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+	value &= ~PLLE_SS_CNTL_SSCBYP;
+	value &= ~PLLE_SS_CNTL_BYPASS_SS;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+	udelay(1);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+	value &= ~PLLE_SS_CNTL_INTERP_RESET;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+	udelay(1);
+
+	return 0;
+}

arch/arm/cpu/tegra124-common/xusb-padctl.c

@@ -0,0 +1,716 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/xusb-padctl.h>
+
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+
+#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
+
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
+
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
+
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
+
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
+
+enum tegra124_function {
+	TEGRA124_FUNC_SNPS,
+	TEGRA124_FUNC_XUSB,
+	TEGRA124_FUNC_UART,
+	TEGRA124_FUNC_PCIE,
+	TEGRA124_FUNC_USB3,
+	TEGRA124_FUNC_SATA,
+	TEGRA124_FUNC_RSVD,
+};
+
+static const char *const tegra124_functions[] = {
+	"snps",
+	"xusb",
+	"uart",
+	"pcie",
+	"usb3",
+	"sata",
+	"rsvd",
+};
+
+static const unsigned int tegra124_otg_functions[] = {
+	TEGRA124_FUNC_SNPS,
+	TEGRA124_FUNC_XUSB,
+	TEGRA124_FUNC_UART,
+	TEGRA124_FUNC_RSVD,
+};
+
+static const unsigned int tegra124_usb_functions[] = {
+	TEGRA124_FUNC_SNPS,
+	TEGRA124_FUNC_XUSB,
+};
+
+static const unsigned int tegra124_pci_functions[] = {
+	TEGRA124_FUNC_PCIE,
+	TEGRA124_FUNC_USB3,
+	TEGRA124_FUNC_SATA,
+	TEGRA124_FUNC_RSVD,
+};
+
+struct tegra_xusb_padctl_lane {
+	const char *name;
+
+	unsigned int offset;
+	unsigned int shift;
+	unsigned int mask;
+	unsigned int iddq;
+
+	const unsigned int *funcs;
+	unsigned int num_funcs;
+};
+
+#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)	\
+	{								\
+		.name = _name,						\
+		.offset = _offset,					\
+		.shift = _shift,					\
+		.mask = _mask,						\
+		.iddq = _iddq,						\
+		.num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions),	\
+		.funcs = tegra124_##_funcs##_functions,			\
+	}
+
+static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
+	TEGRA124_LANE("otg-0",  0x004,  0, 0x3, 0, otg),
+	TEGRA124_LANE("otg-1",  0x004,  2, 0x3, 0, otg),
+	TEGRA124_LANE("otg-2",  0x004,  4, 0x3, 0, otg),
+	TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
+	TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
+	TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
+	TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
+	TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
+	TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
+	TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
+	TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
+	TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
+};
+
+struct tegra_xusb_phy_ops {
+	int (*prepare)(struct tegra_xusb_phy *phy);
+	int (*enable)(struct tegra_xusb_phy *phy);
+	int (*disable)(struct tegra_xusb_phy *phy);
+	int (*unprepare)(struct tegra_xusb_phy *phy);
+};
+
+struct tegra_xusb_phy {
+	const struct tegra_xusb_phy_ops *ops;
+
+	struct tegra_xusb_padctl *padctl;
+};
+
+struct tegra_xusb_padctl_pin {
+	const struct tegra_xusb_padctl_lane *lane;
+
+	unsigned int func;
+	int iddq;
+};
+
+#define MAX_GROUPS 3
+#define MAX_PINS 6
+
+struct tegra_xusb_padctl_group {
+	const char *name;
+
+	const char *pins[MAX_PINS];
+	unsigned int num_pins;
+
+	const char *func;
+	int iddq;
+};
+
+struct tegra_xusb_padctl_config {
+	const char *name;
+
+	struct tegra_xusb_padctl_group groups[MAX_GROUPS];
+	unsigned int num_groups;
+};
+
+struct tegra_xusb_padctl {
+	struct fdt_resource regs;
+
+	unsigned int enable;
+
+	struct tegra_xusb_phy phys[2];
+
+	const struct tegra_xusb_padctl_lane *lanes;
+	unsigned int num_lanes;
+
+	const char *const *functions;
+	unsigned int num_functions;
+
+	struct tegra_xusb_padctl_config config;
+};
+
+static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
+			       unsigned long offset)
+{
+	return readl(padctl->regs.start + offset);
+}
+
+static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
+				 u32 value, unsigned long offset)
+{
+	writel(value, padctl->regs.start + offset);
+}
+
+static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
+{
+	u32 value;
+
+	if (padctl->enable++ > 0)
+		return 0;
+
+	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
+	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+	udelay(100);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
+	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+	udelay(100);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
+	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+	return 0;
+}
+
+static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
+{
+	u32 value;
+
+	if (padctl->enable == 0) {
+		error("tegra-xusb-padctl: unbalanced enable/disable");
+		return 0;
+	}
+
+	if (--padctl->enable > 0)
+		return 0;
+
+	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
+	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+	udelay(100);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
+	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+	udelay(100);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
+	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+	return 0;
+}
+
+static int phy_prepare(struct tegra_xusb_phy *phy)
+{
+	return tegra_xusb_padctl_enable(phy->padctl);
+}
+
+static int phy_unprepare(struct tegra_xusb_phy *phy)
+{
+	return tegra_xusb_padctl_disable(phy->padctl);
+}
+
+static int pcie_phy_enable(struct tegra_xusb_phy *phy)
+{
+	struct tegra_xusb_padctl *padctl = phy->padctl;
+	int err = -ETIMEDOUT;
+	unsigned long start;
+	u32 value;
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+	value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
+	value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
+		 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
+		 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+	value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+
+	start = get_timer(0);
+
+	while (get_timer(start) < 50) {
+		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+		if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
+			err = 0;
+			break;
+		}
+	}
+
+	return err;
+}
+
+static int pcie_phy_disable(struct tegra_xusb_phy *phy)
+{
+	struct tegra_xusb_padctl *padctl = phy->padctl;
+	u32 value;
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+	value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+
+	return 0;
+}
+
+static int sata_phy_enable(struct tegra_xusb_phy *phy)
+{
+	struct tegra_xusb_padctl *padctl = phy->padctl;
+	int err = -ETIMEDOUT;
+	unsigned long start;
+	u32 value;
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+	value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
+	value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+	value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
+	value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+	value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+	value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+	start = get_timer(0);
+
+	while (get_timer(start) < 50) {
+		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+		if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
+			err = 0;
+			break;
+		}
+	}
+
+	return err;
+}
+
+static int sata_phy_disable(struct tegra_xusb_phy *phy)
+{
+	struct tegra_xusb_padctl *padctl = phy->padctl;
+	u32 value;
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+	value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+	value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+	value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
+	value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+	value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
+	value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
+	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+
+	return 0;
+}
+
+static const struct tegra_xusb_phy_ops pcie_phy_ops = {
+	.prepare = phy_prepare,
+	.enable = pcie_phy_enable,
+	.disable = pcie_phy_disable,
+	.unprepare = phy_unprepare,
+};
+
+static const struct tegra_xusb_phy_ops sata_phy_ops = {
+	.prepare = phy_prepare,
+	.enable = sata_phy_enable,
+	.disable = sata_phy_disable,
+	.unprepare = phy_unprepare,
+};
+
+static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
+	.phys = {
+		[0] = {
+			.ops = &pcie_phy_ops,
+		},
+		[1] = {
+			.ops = &sata_phy_ops,
+		},
+	},
+};
+
+static const struct tegra_xusb_padctl_lane *
+tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
+{
+	unsigned int i;
+
+	for (i = 0; i < padctl->num_lanes; i++)
+		if (strcmp(name, padctl->lanes[i].name) == 0)
+			return &padctl->lanes[i];
+
+	return NULL;
+}
+
+static int
+tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
+				 struct tegra_xusb_padctl_group *group,
+				 const void *fdt, int node)
+{
+	unsigned int i;
+	int len, err;
+
+	group->name = fdt_get_name(fdt, node, &len);
+
+	len = fdt_count_strings(fdt, node, "nvidia,lanes");
+	if (len < 0) {
+		error("tegra-xusb-padctl: failed to parse \"nvidia,lanes\" property");
+		return -EINVAL;
+	}
+
+	group->num_pins = len;
+
+	for (i = 0; i < group->num_pins; i++) {
+		err = fdt_get_string_index(fdt, node, "nvidia,lanes", i,
+					   &group->pins[i]);
+		if (err < 0) {
+			error("tegra-xusb-padctl: failed to read string from \"nvidia,lanes\" property");
+			return -EINVAL;
+		}
+	}
+
+	group->num_pins = len;
+
+	err = fdt_get_string(fdt, node, "nvidia,function", &group->func);
+	if (err < 0) {
+		error("tegra-xusb-padctl: failed to parse \"nvidia,func\" property");
+		return -EINVAL;
+	}
+
+	group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1);
+
+	return 0;
+}
+
+static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
+					   const char *name)
+{
+	unsigned int i;
+
+	for (i = 0; i < padctl->num_functions; i++)
+		if (strcmp(name, padctl->functions[i]) == 0)
+			return i;
+
+	return -ENOENT;
+}
+
+static int
+tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
+				     const struct tegra_xusb_padctl_lane *lane,
+				     const char *name)
+{
+	unsigned int i;
+	int func;
+
+	func = tegra_xusb_padctl_find_function(padctl, name);
+	if (func < 0)
+		return func;
+
+	for (i = 0; i < lane->num_funcs; i++)
+		if (lane->funcs[i] == func)
+			return i;
+
+	return -ENOENT;
+}
+
+static int
+tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
+			      const struct tegra_xusb_padctl_group *group)
+{
+	unsigned int i;
+
+	for (i = 0; i < group->num_pins; i++) {
+		const struct tegra_xusb_padctl_lane *lane;
+		unsigned int func;
+		u32 value;
+
+		lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
+		if (!lane) {
+			error("tegra-xusb-padctl: no lane for pin %s",
+			      group->pins[i]);
+			continue;
+		}
+
+		func = tegra_xusb_padctl_lane_find_function(padctl, lane,
+							    group->func);
+		if (func < 0) {
+			error("tegra-xusb-padctl: function %s invalid for lane %s: %d",
+			      group->func, lane->name, func);
+			continue;
+		}
+
+		value = padctl_readl(padctl, lane->offset);
+
+		/* set pin function */
+		value &= ~(lane->mask << lane->shift);
+		value |= func << lane->shift;
+
+		/*
+		 * Set IDDQ if supported on the lane and specified in the
+		 * configuration.
+		 */
+		if (lane->iddq > 0 && group->iddq >= 0) {
+			if (group->iddq != 0)
+				value &= ~(1 << lane->iddq);
+			else
+				value |= 1 << lane->iddq;
+		}
+
+		padctl_writel(padctl, value, lane->offset);
+	}
+
+	return 0;
+}
+
+static int
+tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
+			       struct tegra_xusb_padctl_config *config)
+{
+	unsigned int i;
+
+	for (i = 0; i < config->num_groups; i++) {
+		const struct tegra_xusb_padctl_group *group;
+		int err;
+
+		group = &config->groups[i];
+
+		err = tegra_xusb_padctl_group_apply(padctl, group);
+		if (err < 0) {
+			error("tegra-xusb-padctl: failed to apply group %s: %d",
+			      group->name, err);
+			continue;
+		}
+	}
+
+	return 0;
+}
+
+static int
+tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
+				  struct tegra_xusb_padctl_config *config,
+				  const void *fdt, int node)
+{
+	int subnode;
+
+	config->name = fdt_get_name(fdt, node, NULL);
+
+	fdt_for_each_subnode(fdt, subnode, node) {
+		struct tegra_xusb_padctl_group *group;
+		int err;
+
+		group = &config->groups[config->num_groups];
+
+		err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
+						       subnode);
+		if (err < 0) {
+			error("tegra-xusb-padctl: failed to parse group %s",
+			      group->name);
+			return err;
+		}
+
+		config->num_groups++;
+	}
+
+	return 0;
+}
+
+static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
+				      const void *fdt, int node)
+{
+	int subnode, err;
+
+	err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
+	if (err < 0) {
+		error("tegra-xusb-padctl: registers not found");
+		return err;
+	}
+
+	fdt_for_each_subnode(fdt, subnode, node) {
+		struct tegra_xusb_padctl_config *config = &padctl->config;
+
+		err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
+							subnode);
+		if (err < 0) {
+			error("tegra-xusb-padctl: failed to parse entry %s: %d",
+			      config->name, err);
+			continue;
+		}
+	}
+
+	return 0;
+}
+
+static int process_nodes(const void *fdt, int nodes[], unsigned int count)
+{
+	unsigned int i;
+
+	for (i = 0; i < count; i++) {
+		enum fdt_compat_id id;
+		int err;
+
+		if (!fdtdec_get_is_enabled(fdt, nodes[i]))
+			continue;
+
+		id = fdtdec_lookup(fdt, nodes[i]);
+		switch (id) {
+		case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
+			break;
+
+		default:
+			error("tegra-xusb-padctl: unsupported compatible: %s",
+			      fdtdec_get_compatible(id));
+			continue;
+		}
+
+		padctl->num_lanes = ARRAY_SIZE(tegra124_lanes);
+		padctl->lanes = tegra124_lanes;
+
+		padctl->num_functions = ARRAY_SIZE(tegra124_functions);
+		padctl->functions = tegra124_functions;
+
+		err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
+		if (err < 0) {
+			error("tegra-xusb-padctl: failed to parse DT: %d",
+			      err);
+			continue;
+		}
+
+		/* deassert XUSB padctl reset */
+		reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
+
+		err = tegra_xusb_padctl_config_apply(padctl, &padctl->config);
+		if (err < 0) {
+			error("tegra-xusb-padctl: failed to apply pinmux: %d",
+			      err);
+			continue;
+		}
+
+		/* only a single instance is supported */
+		break;
+	}
+
+	return 0;
+}
+
+struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
+{
+	struct tegra_xusb_phy *phy = NULL;
+
+	switch (type) {
+	case TEGRA_XUSB_PADCTL_PCIE:
+		phy = &padctl->phys[0];
+		phy->padctl = padctl;
+		break;
+
+	case TEGRA_XUSB_PADCTL_SATA:
+		phy = &padctl->phys[1];
+		phy->padctl = padctl;
+		break;
+	}
+
+	return phy;
+}
+
+int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
+{
+	if (phy && phy->ops && phy->ops->prepare)
+		return phy->ops->prepare(phy);
+
+	return phy ? -ENOSYS : -EINVAL;
+}
+
+int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
+{
+	if (phy && phy->ops && phy->ops->enable)
+		return phy->ops->enable(phy);
+
+	return phy ? -ENOSYS : -EINVAL;
+}
+
+int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
+{
+	if (phy && phy->ops && phy->ops->disable)
+		return phy->ops->disable(phy);
+
+	return phy ? -ENOSYS : -EINVAL;
+}
+
+int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
+{
+	if (phy && phy->ops && phy->ops->unprepare)
+		return phy->ops->unprepare(phy);
+
+	return phy ? -ENOSYS : -EINVAL;
+}
+
+void tegra_xusb_padctl_init(const void *fdt)
+{
+	int count, nodes[1];
+
+	count = fdtdec_find_aliases_for_id(fdt, "padctl",
+					   COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
+					   nodes, ARRAY_SIZE(nodes));
+	if (process_nodes(fdt, nodes, count))
+		return;
+}

arch/arm/cpu/tegra20-common/clock.c

@@ -7,6 +7,7 @@
 /* Tegra20 Clock control functions */
 
 #include <common.h>
+#include <errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/tegra.h>
@@ -332,7 +333,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	/* 0x48 */
 	NONE(AFI),
 	NONE(CORESIGHT),
-	NONE(RESERVED74),
+	NONE(PCIEXCLK),
 	NONE(AVPUCQ),
 	NONE(RESERVED76),
 	NONE(RESERVED77),
@@ -494,7 +495,7 @@ enum periph_id clk_id_to_periph_id(int clk_id)
 	case PERIPH_ID_RESERVED30:
 	case PERIPH_ID_RESERVED35:
 	case PERIPH_ID_RESERVED56:
-	case PERIPH_ID_RESERVED74:
+	case PERIPH_ID_PCIEXCLK:
 	case PERIPH_ID_RESERVED76:
 	case PERIPH_ID_RESERVED77:
 	case PERIPH_ID_RESERVED78:
@@ -548,3 +549,139 @@ void clock_early_init(void)
 void arch_timer_init(void)
 {
 }
+
+#define PMC_SATA_PWRGT 0x1ac
+#define  PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
+#define  PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
+
+#define PLLE_SS_CNTL 0x68
+#define  PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
+#define  PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
+#define  PLLE_SS_CNTL_SSCBYP (1 << 12)
+#define  PLLE_SS_CNTL_INTERP_RESET (1 << 11)
+#define  PLLE_SS_CNTL_BYPASS_SS (1 << 10)
+#define  PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
+
+#define PLLE_BASE 0x0e8
+#define  PLLE_BASE_ENABLE_CML (1 << 31)
+#define  PLLE_BASE_ENABLE (1 << 30)
+#define  PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
+#define  PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
+#define  PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
+#define  PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
+
+#define PLLE_MISC 0x0ec
+#define  PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
+#define  PLLE_MISC_PLL_READY (1 << 15)
+#define  PLLE_MISC_LOCK (1 << 11)
+#define  PLLE_MISC_LOCK_ENABLE (1 << 9)
+#define  PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
+
+static int tegra_plle_train(void)
+{
+	unsigned int timeout = 2000;
+	unsigned long value;
+
+	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+	value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
+	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+	value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
+	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+	value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
+	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+	do {
+		value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+		if (value & PLLE_MISC_PLL_READY)
+			break;
+
+		udelay(100);
+	} while (--timeout);
+
+	if (timeout == 0) {
+		error("timeout waiting for PLLE to become ready");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+int tegra_plle_enable(void)
+{
+	unsigned int timeout = 1000;
+	u32 value;
+	int err;
+
+	/* disable PLLE clock */
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+	value &= ~PLLE_BASE_ENABLE_CML;
+	value &= ~PLLE_BASE_ENABLE;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+	/* clear lock enable and setup field */
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+	value &= ~PLLE_MISC_LOCK_ENABLE;
+	value &= ~PLLE_MISC_SETUP_BASE(0xffff);
+	value &= ~PLLE_MISC_SETUP_EXT(0x3);
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+	if ((value & PLLE_MISC_PLL_READY) == 0) {
+		err = tegra_plle_train();
+		if (err < 0) {
+			error("failed to train PLLE: %d", err);
+			return err;
+		}
+	}
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+	value |= PLLE_MISC_SETUP_BASE(0x7);
+	value |= PLLE_MISC_LOCK_ENABLE;
+	value |= PLLE_MISC_SETUP_EXT(0);
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+	value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
+		 PLLE_SS_CNTL_BYPASS_SS;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+	value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+	do {
+		value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+		if (value & PLLE_MISC_LOCK)
+			break;
+
+		udelay(2);
+	} while (--timeout);
+
+	if (timeout == 0) {
+		error("timeout waiting for PLLE to lock");
+		return -ETIMEDOUT;
+	}
+
+	udelay(50);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+	value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
+	value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
+
+	value &= ~PLLE_SS_CNTL_SSCINC(0xff);
+	value |= PLLE_SS_CNTL_SSCINC(0x01);
+
+	value &= ~PLLE_SS_CNTL_SSCBYP;
+	value &= ~PLLE_SS_CNTL_INTERP_RESET;
+	value &= ~PLLE_SS_CNTL_BYPASS_SS;
+
+	value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
+	value |= PLLE_SS_CNTL_SSCMAX(0x24);
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+	return 0;
+}

arch/arm/cpu/tegra30-common/clock.c

@@ -17,6 +17,7 @@
 /* Tegra30 Clock control functions */
 
 #include <common.h>
+#include <errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/tegra.h>
@@ -563,6 +564,7 @@ enum periph_id clk_id_to_periph_id(int clk_id)
 	case PERIPH_ID_RESERVED43:
 	case PERIPH_ID_RESERVED45:
 	case PERIPH_ID_RESERVED56:
+	case PERIPH_ID_PCIEXCLK:
 	case PERIPH_ID_RESERVED76:
 	case PERIPH_ID_RESERVED77:
 	case PERIPH_ID_RESERVED78:
@@ -587,3 +589,156 @@ void clock_early_init(void)
 void arch_timer_init(void)
 {
 }
+
+#define PMC_SATA_PWRGT 0x1ac
+#define  PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
+#define  PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
+
+#define PLLE_SS_CNTL 0x68
+#define  PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
+#define  PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
+#define  PLLE_SS_CNTL_SSCBYP (1 << 12)
+#define  PLLE_SS_CNTL_INTERP_RESET (1 << 11)
+#define  PLLE_SS_CNTL_BYPASS_SS (1 << 10)
+#define  PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
+
+#define PLLE_BASE 0x0e8
+#define  PLLE_BASE_ENABLE_CML (1 << 31)
+#define  PLLE_BASE_ENABLE (1 << 30)
+#define  PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
+#define  PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
+#define  PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
+#define  PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
+
+#define PLLE_MISC 0x0ec
+#define  PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
+#define  PLLE_MISC_PLL_READY (1 << 15)
+#define  PLLE_MISC_LOCK (1 << 11)
+#define  PLLE_MISC_LOCK_ENABLE (1 << 9)
+#define  PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
+
+static int tegra_plle_train(void)
+{
+	unsigned int timeout = 2000;
+	unsigned long value;
+
+	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+	value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
+	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+	value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
+	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+	value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
+	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
+
+	do {
+		value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+		if (value & PLLE_MISC_PLL_READY)
+			break;
+
+		udelay(100);
+	} while (--timeout);
+
+	if (timeout == 0) {
+		error("timeout waiting for PLLE to become ready");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+int tegra_plle_enable(void)
+{
+	unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
+	u32 value;
+	int err;
+
+	/* disable PLLE clock */
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+	value &= ~PLLE_BASE_ENABLE_CML;
+	value &= ~PLLE_BASE_ENABLE;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+	/* clear lock enable and setup field */
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+	value &= ~PLLE_MISC_LOCK_ENABLE;
+	value &= ~PLLE_MISC_SETUP_BASE(0xffff);
+	value &= ~PLLE_MISC_SETUP_EXT(0x3);
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+	if ((value & PLLE_MISC_PLL_READY) == 0) {
+		err = tegra_plle_train();
+		if (err < 0) {
+			error("failed to train PLLE: %d", err);
+			return err;
+		}
+	}
+
+	/* configure PLLE */
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+	value &= ~PLLE_BASE_PLDIV_CML(0x0f);
+	value |= PLLE_BASE_PLDIV_CML(cpcon);
+
+	value &= ~PLLE_BASE_PLDIV(0x3f);
+	value |= PLLE_BASE_PLDIV(p);
+
+	value &= ~PLLE_BASE_NDIV(0xff);
+	value |= PLLE_BASE_NDIV(n);
+
+	value &= ~PLLE_BASE_MDIV(0xff);
+	value |= PLLE_BASE_MDIV(m);
+
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+	value |= PLLE_MISC_SETUP_BASE(0x7);
+	value |= PLLE_MISC_LOCK_ENABLE;
+	value |= PLLE_MISC_SETUP_EXT(0);
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+	value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
+		 PLLE_SS_CNTL_BYPASS_SS;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
+	value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
+
+	do {
+		value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
+		if (value & PLLE_MISC_LOCK)
+			break;
+
+		udelay(2);
+	} while (--timeout);
+
+	if (timeout == 0) {
+		error("timeout waiting for PLLE to lock");
+		return -ETIMEDOUT;
+	}
+
+	udelay(50);
+
+	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+	value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
+	value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
+
+	value &= ~PLLE_SS_CNTL_SSCINC(0xff);
+	value |= PLLE_SS_CNTL_SSCINC(0x01);
+
+	value &= ~PLLE_SS_CNTL_SSCBYP;
+	value &= ~PLLE_SS_CNTL_INTERP_RESET;
+	value &= ~PLLE_SS_CNTL_BYPASS_SS;
+
+	value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
+	value |= PLLE_SS_CNTL_SSCMAX(0x24);
+	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
+
+	return 0;
+}

arch/arm/dts/Makefile

@@ -13,7 +13,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-smdk5250.dtb \
 	exynos5420-smdk5420.dtb \
 	exynos5420-peach-pit.dtb \
-	exynos5800-peach-pi.dtb
+	exynos5800-peach-pi.dtb \
+	exynos5422-odroidxu3.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \

arch/arm/dts/exynos5250-snow.dts

@@ -64,7 +64,7 @@
 	spi@131b0000 {
 		spi-max-frequency = <1000000>;
 		spi-deactivate-delay = <100>;
-		cros-ec@0 {
+		cros_ec: cros-ec@0 {
 			reg = <0>;
 			compatible = "google,cros-ec";
 			spi-max-frequency = <5000000>;
@@ -151,61 +151,6 @@
 		samsung,dc-value	= <25>;
 	};
 
-	cros-ec-keyb {
-		compatible = "google,cros-ec-keyb";
-		google,key-rows = <8>;
-		google,key-columns = <13>;
-		google,repeat-delay-ms = <240>;
-		google,repeat-rate-ms = <30>;
-		google,ghost-filter;
-		/*
-		 * Keymap entries take the form of 0xRRCCKKKK where
-		 * RR=Row CC=Column KKKK=Key Code
-		 * The values below are for a US keyboard layout and
-		 * are taken from the Linux driver. Note that the
-		 * 102ND key is not used for US keyboards.
-		 */
-		linux,keymap = <
-			/* CAPSLCK F1         B          F10     */
-			0x0001003a 0x0002003b 0x00030030 0x00040044
-			/* N       =          R_ALT      ESC     */
-			0x00060031 0x0008000d 0x000a0064 0x01010001
-			/* F4      G          F7         H       */
-			0x0102003e 0x01030022 0x01040041 0x01060023
-			/* '       F9         BKSPACE    L_CTRL  */
-			0x01080028 0x01090043 0x010b000e 0x0200001d
-			/* TAB     F3         T          F6      */
-			0x0201000f 0x0202003d 0x02030014 0x02040040
-			/* ]       Y          102ND      [       */
-			0x0205001b 0x02060015 0x02070056 0x0208001a
-			/* F8      GRAVE      F2         5       */
-			0x02090042 0x03010029 0x0302003c 0x03030006
-			/* F5      6          -          \       */
-			0x0304003f 0x03060007 0x0308000c 0x030b002b
-			/* R_CTRL  A          D          F       */
-			0x04000061 0x0401001e 0x04020020 0x04030021
-			/* S       K          J          ;       */
-			0x0404001f 0x04050025 0x04060024 0x04080027
-			/* L       ENTER      Z          C       */
-			0x04090026 0x040b001c 0x0501002c 0x0502002e
-			/* V       X          ,          M       */
-			0x0503002f 0x0504002d 0x05050033 0x05060032
-			/* L_SHIFT /          .          SPACE   */
-			0x0507002a 0x05080035 0x05090034 0x050B0039
-			/* 1       3          4          2       */
-			0x06010002 0x06020004 0x06030005 0x06040003
-			/* 8       7          0          9       */
-			0x06050009 0x06060008 0x0608000b 0x0609000a
-			/* L_ALT   DOWN       RIGHT      Q       */
-			0x060a0038 0x060b006c 0x060c006a 0x07010010
-			/* E       R          W          I       */
-			0x07020012 0x07030013 0x07040011 0x07050017
-			/* U       R_SHIFT    P          O       */
-			0x07060016 0x07070036 0x07080019 0x07090018
-			/* UP      LEFT    */
-			0x070b0067 0x070c0069>;
-	};
-
 	fimd@14400000 {
 		samsung,vl-freq = <60>;
 		samsung,vl-col = <1366>;
@@ -250,3 +195,5 @@
 	};
 
 };
+
+#include "cros-ec-keyboard.dtsi"

arch/arm/dts/exynos5420-peach-pit.dts

@@ -28,61 +28,6 @@
 		pmic = "/i2c@12ca0000";
 	};
 
-	cros-ec-keyb {
-		compatible = "google,cros-ec-keyb";
-		google,key-rows = <8>;
-		google,key-columns = <13>;
-		google,repeat-delay-ms = <240>;
-		google,repeat-rate-ms = <30>;
-		google,ghost-filter;
-		/*
-		 * Keymap entries take the form of 0xRRCCKKKK where
-		 * RR=Row CC=Column KKKK=Key Code
-		 * The values below are for a US keyboard layout and
-		 * are taken from the Linux driver. Note that the
-		 * 102ND key is not used for US keyboards.
-		 */
-		linux,keymap = <
-			/* CAPSLCK F1         B          F10     */
-			0x0001003a 0x0002003b 0x00030030 0x00040044
-			/* N       =          R_ALT      ESC     */
-			0x00060031 0x0008000d 0x000a0064 0x01010001
-			/* F4      G          F7         H       */
-			0x0102003e 0x01030022 0x01040041 0x01060023
-			/* '       F9         BKSPACE    L_CTRL  */
-			0x01080028 0x01090043 0x010b000e 0x0200001d
-			/* TAB     F3         T          F6      */
-			0x0201000f 0x0202003d 0x02030014 0x02040040
-			/* ]       Y          102ND      [       */
-			0x0205001b 0x02060015 0x02070056 0x0208001a
-			/* F8      GRAVE      F2         5       */
-			0x02090042 0x03010029 0x0302003c 0x03030006
-			/* F5      6          -          \       */
-			0x0304003f 0x03060007 0x0308000c 0x030b002b
-			/* R_CTRL  A          D          F       */
-			0x04000061 0x0401001e 0x04020020 0x04030021
-			/* S       K          J          ;       */
-			0x0404001f 0x04050025 0x04060024 0x04080027
-			/* L       ENTER      Z          C       */
-			0x04090026 0x040b001c 0x0501002c 0x0502002e
-			/* V       X          ,          M       */
-			0x0503002f 0x0504002d 0x05050033 0x05060032
-			/* L_SHIFT /          .          SPACE   */
-			0x0507002a 0x05080035 0x05090034 0x050B0039
-			/* 1       3          4          2       */
-			0x06010002 0x06020004 0x06030005 0x06040003
-			/* 8       7          0          9       */
-			0x06050009 0x06060008 0x0608000b 0x0609000a
-			/* L_ALT   DOWN       RIGHT      Q       */
-			0x060a0038 0x060b006c 0x060c006a 0x07010010
-			/* E       R          W          I       */
-			0x07020012 0x07030013 0x07040011 0x07050017
-			/* U       R_SHIFT    P          O       */
-			0x07060016 0x07070036 0x07080019 0x07090018
-			/* UP      LEFT    */
-			0x070b0067 0x070c0069>;
-	};
-
 	dmc {
 		mem-manuf = "samsung";
 		mem-type = "ddr3";
@@ -157,7 +102,7 @@
 	spi@12d40000 { /* spi2 */
 		spi-max-frequency = <4000000>;
 		spi-deactivate-delay = <200>;
-		cros-ec@0 {
+		cros_ec: cros-ec@0 {
 			reg = <0>;
 			compatible = "google,cros-ec";
 			spi-half-duplex;
@@ -211,3 +156,5 @@
 		samsung,dual-lcd-enabled = <0>;
 	};
 };
+
+#include "cros-ec-keyboard.dtsi"

arch/arm/dts/exynos5422-odroidxu3.dts

@@ -0,0 +1,49 @@
+/*
+ * Odroid XU3 device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "exynos54xx.dtsi"
+
+/ {
+	model = "Odroid XU3 based on EXYNOS5422";
+	compatible = "samsung,odroidxu3", "samsung,exynos5";
+
+	aliases {
+		serial0 = "/serial@12C00000";
+		console = "/serial@12C20000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg =  <0x40000000 0x10000000
+			0x50000000 0x10000000
+			0x60000000 0x10000000
+			0x70000000 0x10000000
+			0x80000000 0x10000000
+			0x90000000 0x10000000
+			0xa0000000 0x10000000
+			0xb0000000 0xea00000>;
+	};
+
+	ehci@12110000 {
+		samsung,vbus-gpio = <&gpio 0x66 0>; /* X26 */
+	};
+
+	serial@12C20000 {
+		status="okay";
+	};
+
+	mmc@12200000 {
+		fifoth_val = <0x201f0020>;
+	};
+
+	mmc@12220000 {
+		fifoth_val = <0x201f0020>;
+	};
+};

arch/arm/dts/exynos5800-peach-pi.dts

@@ -63,11 +63,6 @@
 	              reg = <0x20>;
 	              compatible = "maxim,max98090-codec";
 	       };
-
-	        edp-lvds-bridge@48 {
-	                compatible = "parade,ps8625";
-	                reg = <0x48>;
-	        };
 	};
 
         sound@3830000 {
@@ -101,7 +96,7 @@
 	spi@12d40000 { /* spi2 */
 		spi-max-frequency = <4000000>;
 		spi-deactivate-delay = <200>;
-		cros-ec@0 {
+		cros_ec: cros-ec@0 {
 			reg = <0>;
 			compatible = "google,cros-ec";
 			spi-half-duplex;
@@ -155,3 +150,5 @@
 		samsung,dual-lcd-enabled = <0>;
 	};
 };
+
+#include "cros-ec-keyboard.dtsi"

arch/arm/dts/socfpga.dtsi

@@ -637,19 +637,19 @@
 			interrupts = <0 151 4>;
 			clocks = <&qspi_clk>;
 			ext-decoder = <0>;  /* external decoder */
-			num-chipselect = <4>;
+			num-cs = <4>;
 			fifo-depth = <128>;
 			bus-num = <2>;
 			status = "disabled";
 		};
 
 		spi0: spi@fff00000 {
-			compatible = "snps,dw-spi-mmio";
+			compatible = "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xfff00000 0x1000>;
 			interrupts = <0 154 4>;
-			num-chipselect = <4>;
+			num-cs = <4>;
 			bus-num = <0>;
 			tx-dma-channel = <&pdma 16>;
 			rx-dma-channel = <&pdma 17>;
@@ -658,12 +658,12 @@
 		};
 
 		spi1: spi@fff01000 {
-			compatible = "snps,dw-spi-mmio";
+			compatible = "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xfff01000 0x1000>;
 			interrupts = <0 156 4>;
-			num-chipselect = <4>;
+			num-cs = <4>;
 			bus-num = <1>;
 			tx-dma-channel = <&pdma 20>;
 			rx-dma-channel = <&pdma 21>;

arch/arm/dts/tegra124-jetson-tk1.dts

@@ -29,6 +29,26 @@
 		reg = <0x80000000 0x80000000>;
 	};
 
+	pcie-controller@01003000 {
+		status = "okay";
+
+		avddio-pex-supply = <&vdd_1v05_run>;
+		dvddio-pex-supply = <&vdd_1v05_run>;
+		avdd-pex-pll-supply = <&vdd_1v05_run>;
+		hvdd-pex-supply = <&vdd_3v3_lp0>;
+		hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
+		vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
+		avdd-pll-erefe-supply = <&avdd_1v05_run>;
+
+		pci@1,0 {
+			status = "okay";
+		};
+
+		pci@2,0 {
+			status = "okay";
+		};
+	};
+
 	i2c@7000c000 {
 		status = "okay";
 		clock-frequency = <100000>;
@@ -49,9 +69,195 @@
 		clock-frequency = <100000>;
 	};
 
+	/* Expansion PWR_I2C_*, on-board components */
 	i2c@7000d000 {
 		status = "okay";
 		clock-frequency = <400000>;
+
+		pmic: pmic@40 {
+			compatible = "ams,as3722";
+			reg = <0x40>;
+			interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+			ams,system-power-controller;
+
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&as3722_default>;
+
+			as3722_default: pinmux {
+				gpio0 {
+					pins = "gpio0";
+					function = "gpio";
+					bias-pull-down;
+				};
+
+				gpio1_2_4_7 {
+					pins = "gpio1", "gpio2", "gpio4", "gpio7";
+					function = "gpio";
+					bias-pull-up;
+				};
+
+				gpio3_5_6 {
+					pins = "gpio3", "gpio5", "gpio6";
+					bias-high-impedance;
+				};
+			};
+
+			regulators {
+				vsup-sd2-supply = <&vdd_5v0_sys>;
+				vsup-sd3-supply = <&vdd_5v0_sys>;
+				vsup-sd4-supply = <&vdd_5v0_sys>;
+				vsup-sd5-supply = <&vdd_5v0_sys>;
+				vin-ldo0-supply = <&vdd_1v35_lp0>;
+				vin-ldo1-6-supply = <&vdd_3v3_run>;
+				vin-ldo2-5-7-supply = <&vddio_1v8>;
+				vin-ldo3-4-supply = <&vdd_3v3_sys>;
+				vin-ldo9-10-supply = <&vdd_5v0_sys>;
+				vin-ldo11-supply = <&vdd_3v3_run>;
+
+				sd0 {
+					regulator-name = "+VDD_CPU_AP";
+					regulator-min-microvolt = <700000>;
+					regulator-max-microvolt = <1400000>;
+					regulator-min-microamp = <3500000>;
+					regulator-max-microamp = <3500000>;
+					regulator-always-on;
+					regulator-boot-on;
+					ams,ext-control = <2>;
+				};
+
+				sd1 {
+					regulator-name = "+VDD_CORE";
+					regulator-min-microvolt = <700000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-min-microamp = <2500000>;
+					regulator-max-microamp = <2500000>;
+					regulator-always-on;
+					regulator-boot-on;
+					ams,ext-control = <1>;
+				};
+
+				vdd_1v35_lp0: sd2 {
+					regulator-name = "+1.35V_LP0(sd2)";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				sd3 {
+					regulator-name = "+1.35V_LP0(sd3)";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				vdd_1v05_run: sd4 {
+					regulator-name = "+1.05V_RUN";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				vddio_1v8: sd5 {
+					regulator-name = "+1.8V_VDDIO";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				vdd_gpu: sd6 {
+					regulator-name = "+VDD_GPU_AP";
+					regulator-min-microvolt = <650000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-min-microamp = <3500000>;
+					regulator-max-microamp = <3500000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				avdd_1v05_run: ldo0 {
+					regulator-name = "+1.05V_RUN_AVDD";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+					regulator-boot-on;
+					regulator-always-on;
+					ams,ext-control = <1>;
+				};
+
+				ldo1 {
+					regulator-name = "+1.8V_RUN_CAM";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo2 {
+					regulator-name = "+1.2V_GEN_AVDD";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo3 {
+					regulator-name = "+1.05V_LP0_VDD_RTC";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-boot-on;
+					regulator-always-on;
+					ams,enable-tracking;
+				};
+
+				ldo4 {
+					regulator-name = "+2.8V_RUN_CAM";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo5 {
+					regulator-name = "+1.2V_RUN_CAM_FRONT";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				vddio_sdmmc3: ldo6 {
+					regulator-name = "+VDDIO_SDMMC3";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				ldo7 {
+					regulator-name = "+1.05V_RUN_CAM_REAR";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				ldo9 {
+					regulator-name = "+3.3V_RUN_TOUCH";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo10 {
+					regulator-name = "+2.8V_RUN_CAM_AF";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo11 {
+					regulator-name = "+1.8V_RUN_VPP_FUSE";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+			};
+		};
 	};
 
 	i2c@7000d100 {
@@ -69,6 +275,32 @@
 		spi-max-frequency = <25000000>;
 	};
 
+	padctl@7009f000 {
+		pinctrl-0 = <&padctl_default>;
+		pinctrl-names = "default";
+
+		padctl_default: pinmux {
+			usb3 {
+				nvidia,lanes = "pcie-0", "pcie-1";
+				nvidia,function = "usb3";
+				nvidia,iddq = <0>;
+			};
+
+			pcie {
+				nvidia,lanes = "pcie-2", "pcie-3",
+					       "pcie-4";
+				nvidia,function = "pcie";
+				nvidia,iddq = <0>;
+			};
+
+			sata {
+				nvidia,lanes = "sata-0";
+				nvidia,function = "sata";
+				nvidia,iddq = <0>;
+			};
+		};
+	};
+
 	sdhci@700b0400 {
 		status = "okay";
 		cd-gpios = <&gpio 170 1>; /* gpio PV2 */
@@ -91,4 +323,145 @@
 		status = "okay";
 		nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
 	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_mux: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "+VDD_MUX";
+			regulator-min-microvolt = <12000000>;
+			regulator-max-microvolt = <12000000>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+
+		vdd_5v0_sys: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "+5V_SYS";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+			regulator-boot-on;
+			vin-supply = <&vdd_mux>;
+		};
+
+		vdd_3v3_sys: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "+3.3V_SYS";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			vin-supply = <&vdd_mux>;
+		};
+
+		vdd_3v3_run: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "+3.3V_RUN";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_3v3_sys>;
+		};
+
+		vdd_3v3_hdmi: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			vin-supply = <&vdd_3v3_run>;
+		};
+
+		vdd_usb1_vbus: regulator@7 {
+			compatible = "regulator-fixed";
+			reg = <7>;
+			regulator-name = "+USB0_VBUS_SW";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+
+		vdd_usb3_vbus: regulator@8 {
+			compatible = "regulator-fixed";
+			reg = <8>;
+			regulator-name = "+5V_USB_HS";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+
+		vdd_3v3_lp0: regulator@10 {
+			compatible = "regulator-fixed";
+			reg = <10>;
+			regulator-name = "+3.3V_LP0";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_3v3_sys>;
+		};
+
+		vdd_hdmi_pll: regulator@11 {
+			compatible = "regulator-fixed";
+			reg = <11>;
+			regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1050000>;
+			gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+			vin-supply = <&vdd_1v05_run>;
+		};
+
+		vdd_5v0_hdmi: regulator@12 {
+			compatible = "regulator-fixed";
+			reg = <12>;
+			regulator-name = "+5V_HDMI_CON";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+
+		/* Molex power connector */
+		vdd_5v0_sata: regulator@13 {
+			compatible = "regulator-fixed";
+			reg = <13>;
+			regulator-name = "+5V_SATA";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_5v0_sys>;
+		};
+
+		vdd_12v0_sata: regulator@14 {
+			compatible = "regulator-fixed";
+			reg = <14>;
+			regulator-name = "+12V_SATA";
+			regulator-min-microvolt = <12000000>;
+			regulator-max-microvolt = <12000000>;
+			gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_mux>;
+		};
+	};
 };

arch/arm/dts/tegra124.dtsi

@@ -2,11 +2,91 @@
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 
 #include "skeleton.dtsi"
 
 / {
 	compatible = "nvidia,tegra124";
+	interrupt-parent = <&gic>;
+
+	pcie-controller@01003000 {
+		compatible = "nvidia,tegra124-pcie";
+		device_type = "pci";
+		reg = <0x01003000 0x00000800   /* PADS registers */
+		       0x01003800 0x00000800   /* AFI registers */
+		       0x02000000 0x10000000>; /* configuration space */
+		reg-names = "pads", "afi", "cs";
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+		interrupt-names = "intr", "msi";
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+		bus-range = <0x00 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000   /* port 0 configuration space */
+			  0x82000000 0 0x01001000 0x01001000 0 0x00001000   /* port 1 configuration space */
+			  0x81000000 0 0x0        0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
+			  0x82000000 0 0x13000000 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
+			  0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
+
+		clocks = <&tegra_car TEGRA124_CLK_PCIE>,
+			 <&tegra_car TEGRA124_CLK_AFI>,
+			 <&tegra_car TEGRA124_CLK_PLL_E>,
+			 <&tegra_car TEGRA124_CLK_CML0>;
+		clock-names = "pex", "afi", "pll_e", "cml";
+		resets = <&tegra_car 70>,
+			 <&tegra_car 72>,
+			 <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
+		status = "disabled";
+
+		phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
+		phy-names = "pcie";
+
+		pci@1,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
+			reg = <0x000800 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <2>;
+		};
+
+		pci@2,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
+			reg = <0x001000 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <1>;
+		};
+	};
+
+	gic: interrupt-controller@50041000 {
+		compatible = "arm,cortex-a15-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x50041000 0x1000>,
+		      <0x50042000 0x2000>,
+		      <0x50044000 0x2000>,
+		      <0x50046000 0x2000>;
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
 
 	tegra_car: clock@60006000 {
 		compatible = "nvidia,tegra124-car";
@@ -269,6 +349,15 @@
 		clocks = <&tegra_car 105>;
 	};
 
+	padctl: padctl@7009f000 {
+		compatible = "nvidia,tegra124-xusb-padctl";
+		reg = <0x7009f000 0x1000>;
+		resets = <&tegra_car 142>;
+		reset-names = "padctl";
+
+		#phy-cells = <1>;
+	};
+
 	sdhci@700b0000 {
 		compatible = "nvidia,tegra124-sdhci";
 		reg = <0x700b0000 0x200>;

arch/arm/dts/tegra20-trimslice.dts

@@ -47,6 +47,20 @@
 		status = "disabled";
 	};
 
+	pcie-controller@80003000 {
+		status = "okay";
+
+		avdd-pex-supply = <&pci_vdd_reg>;
+		vdd-pex-supply = <&pci_vdd_reg>;
+		avdd-pex-pll-supply = <&pci_vdd_reg>;
+		avdd-plle-supply = <&pci_vdd_reg>;
+		vddio-pex-clk-supply = <&pci_clk_reg>;
+
+		pci@1,0 {
+			status = "okay";
+		};
+	};
+
 	usb@c5000000 {
 		nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
 	};
@@ -66,4 +80,59 @@
 		wp-gpios = <&gpio 122 0>; /* gpio PP2 */
 		bus-width = <4>;
 	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		hdmi_vdd_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "avdd_hdmi";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		hdmi_pll_reg: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "avdd_hdmi_pll";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		vbus_reg: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "usb1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+
+		pci_clk_reg: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "pci_clk";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		pci_vdd_reg: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "pci_vdd";
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1050000>;
+			regulator-always-on;
+		};
+	};
+
 };

arch/arm/dts/tegra20.dtsi

@@ -332,6 +332,65 @@
 		reg = <0x7000f400 0x200>;
 	};
 
+	pcie-controller@80003000 {
+		compatible = "nvidia,tegra20-pcie";
+		device_type = "pci";
+		reg = <0x80003000 0x00000800   /* PADS registers */
+		       0x80003800 0x00000200   /* AFI registers */
+		       0x90000000 0x10000000>; /* configuration space */
+		reg-names = "pads", "afi", "cs";
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
+			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+		interrupt-names = "intr", "msi";
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+		bus-range = <0x00 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
+			  0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
+			  0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
+			  0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
+			  0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
+
+		clocks = <&tegra_car TEGRA20_CLK_PEX>,
+			 <&tegra_car TEGRA20_CLK_AFI>,
+			 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
+			 <&tegra_car TEGRA20_CLK_PLL_E>;
+		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		status = "disabled";
+
+		pci@1,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
+			reg = <0x000800 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <2>;
+		};
+
+		pci@2,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
+			reg = <0x001000 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <2>;
+		};
+	};
+
 	usb@c5000000 {
 		compatible = "nvidia,tegra20-ehci", "usb-ehci";
 		reg = <0xc5000000 0x4000>;

arch/arm/dts/tegra30-beaver.dts

@@ -28,6 +28,33 @@
 		reg = <0x80000000 0x7ff00000>;
 	};
 
+	pcie-controller@00003000 {
+		status = "okay";
+
+		avdd-pexa-supply = <&ldo1_reg>;
+		vdd-pexa-supply = <&ldo1_reg>;
+		avdd-pexb-supply = <&ldo1_reg>;
+		vdd-pexb-supply = <&ldo1_reg>;
+		avdd-pex-pll-supply = <&ldo1_reg>;
+		avdd-plle-supply = <&ldo1_reg>;
+		vddio-pex-ctl-supply = <&sys_3v3_reg>;
+		hvdd-pex-supply = <&sys_3v3_pexs_reg>;
+
+		pci@1,0 {
+			status = "okay";
+			nvidia,num-lanes = <2>;
+		};
+
+		pci@2,0 {
+			nvidia,num-lanes = <2>;
+		};
+
+		pci@3,0 {
+			status = "okay";
+			nvidia,num-lanes = <2>;
+		};
+	};
+
 	i2c@7000c000 {
 		status = "okay";
 		clock-frequency = <100000>;
@@ -51,6 +78,110 @@
 	i2c@7000d000 {
 		status = "okay";
 		clock-frequency = <100000>;
+
+		pmic: tps65911@2d {
+			compatible = "ti,tps65911";
+			reg = <0x2d>;
+
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			vcc1-supply = <&vdd_5v_in_reg>;
+			vcc2-supply = <&vdd_5v_in_reg>;
+			vcc3-supply = <&vio_reg>;
+			vcc4-supply = <&vdd_5v_in_reg>;
+			vcc5-supply = <&vdd_5v_in_reg>;
+			vcc6-supply = <&vdd2_reg>;
+			vcc7-supply = <&vdd_5v_in_reg>;
+			vccio-supply = <&vdd_5v_in_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				vdd1_reg: vdd1 {
+					regulator-name = "vddio_ddr_1v2";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				vdd2_reg: vdd2 {
+					regulator-name = "vdd_1v5_gen";
+					regulator-min-microvolt = <1500000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+				};
+
+				vddctrl_reg: vddctrl {
+					regulator-name = "vdd_cpu,vdd_sys";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				vio_reg: vio {
+					regulator-name = "vdd_1v8_gen";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo1_reg: ldo1 {
+					regulator-name = "vdd_pexa,vdd_pexb";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				ldo2_reg: ldo2 {
+					regulator-name = "vdd_sata,avdd_plle";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				/* LDO3 is not connected to anything */
+
+				ldo4_reg: ldo4 {
+					regulator-name = "vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				ldo5_reg: ldo5 {
+					regulator-name = "vddio_sdmmc,avdd_vdac";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo6_reg: ldo6 {
+					regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				ldo7_reg: ldo7 {
+					regulator-name = "vdd_pllm,x,u,a_p_c_s";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				ldo8_reg: ldo8 {
+					regulator-name = "vdd_ddr_hs";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+			};
+		};
 	};
 
 	spi@7000da00 {
@@ -86,4 +217,118 @@
 		nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
 		status = "okay";
 	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v_in_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v_in";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		chargepump_5v_reg: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "chargepump_5v";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-boot-on;
+			regulator-always-on;
+			enable-active-high;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		ddr_reg: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "vdd_ddr";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+			vin-supply = <&vdd_5v_in_reg>;
+		};
+
+		vdd_5v_sata_reg: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "vdd_5v_sata";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&vdd_5v_in_reg>;
+		};
+
+		usb1_vbus_reg: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "usb1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v_in_reg>;
+		};
+
+		usb3_vbus_reg: regulator@5 {
+			compatible = "regulator-fixed";
+			reg = <5>;
+			regulator-name = "usb3_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v_in_reg>;
+		};
+
+		sys_3v3_reg: regulator@6 {
+			compatible = "regulator-fixed";
+			reg = <6>;
+			regulator-name = "sys_3v3,vdd_3v3_alw";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+			vin-supply = <&vdd_5v_in_reg>;
+		};
+
+		sys_3v3_pexs_reg: regulator@7 {
+			compatible = "regulator-fixed";
+			reg = <7>;
+			regulator-name = "sys_3v3_pexs";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&sys_3v3_reg>;
+		};
+
+		vdd_5v0_hdmi: regulator@8 {
+			compatible = "regulator-fixed";
+			reg = <8>;
+			regulator-name = "+VDD_5V_HDMI";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+			regulator-boot-on;
+			vin-supply = <&sys_3v3_reg>;
+		};
+	};
 };

arch/arm/dts/tegra30-cardhu.dts

@@ -27,6 +27,31 @@
 		reg = <0x80000000 0x40000000>;
 	};
 
+	pcie-controller@00003000 {
+		status = "okay";
+
+		/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
+		avdd-pexb-supply = <&ldo1_reg>;
+		vdd-pexb-supply = <&ldo1_reg>;
+		avdd-pex-pll-supply = <&ldo1_reg>;
+		hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
+		vddio-pex-ctl-supply = <&sys_3v3_reg>;
+		avdd-plle-supply = <&ldo2_reg>;
+
+		pci@1,0 {
+			nvidia,num-lanes = <4>;
+		};
+
+		pci@2,0 {
+			nvidia,num-lanes = <1>;
+		};
+
+		pci@3,0 {
+			status = "okay";
+			nvidia,num-lanes = <1>;
+		};
+	};
+
 	i2c@7000c000 {
 		status = "okay";
 		clock-frequency = <100000>;
@@ -50,6 +75,107 @@
 	i2c@7000d000 {
 		status = "okay";
 		clock-frequency = <100000>;
+
+		pmic: tps65911@2d {
+			compatible = "ti,tps65911";
+			reg = <0x2d>;
+
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			vcc1-supply = <&vdd_ac_bat_reg>;
+			vcc2-supply = <&vdd_ac_bat_reg>;
+			vcc3-supply = <&vio_reg>;
+			vcc4-supply = <&vdd_5v0_reg>;
+			vcc5-supply = <&vdd_ac_bat_reg>;
+			vcc6-supply = <&vdd2_reg>;
+			vcc7-supply = <&vdd_ac_bat_reg>;
+			vccio-supply = <&vdd_ac_bat_reg>;
+
+			regulators {
+				vdd1_reg: vdd1 {
+					regulator-name = "vddio_ddr_1v2";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				vdd2_reg: vdd2 {
+					regulator-name = "vdd_1v5_gen";
+					regulator-min-microvolt = <1500000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+				};
+
+				vddctrl_reg: vddctrl {
+					regulator-name = "vdd_cpu,vdd_sys";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				vio_reg: vio {
+					regulator-name = "vdd_1v8_gen";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo1_reg: ldo1 {
+					regulator-name = "vdd_pexa,vdd_pexb";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				ldo2_reg: ldo2 {
+					regulator-name = "vdd_sata,avdd_plle";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				/* LDO3 is not connected to anything */
+
+				ldo4_reg: ldo4 {
+					regulator-name = "vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				ldo5_reg: ldo5 {
+					regulator-name = "vddio_sdmmc,avdd_vdac";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo6_reg: ldo6 {
+					regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				ldo7_reg: ldo7 {
+					regulator-name = "vdd_pllm,x,u,a_p_c_s";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				ldo8_reg: ldo8 {
+					regulator-name = "vdd_ddr_hs";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+			};
+		};
 	};
 
 	spi@7000da00 {
@@ -74,4 +200,240 @@
 		nvidia,vbus-gpio = <&gpio 236 0>;	/* PDD4 */
 		status = "okay";
 	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_ac_bat_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_ac_bat";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		cam_1v8_reg: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "cam_1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&vio_reg>;
+		};
+
+		cp_5v_reg: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "cp_5v";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-boot-on;
+			regulator-always-on;
+			enable-active-high;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		emmc_3v3_reg: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "emmc_3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&sys_3v3_reg>;
+		};
+
+		modem_3v3_reg: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "modem_3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
+		};
+
+		pex_hvdd_3v3_reg: regulator@5 {
+			compatible = "regulator-fixed";
+			reg = <5>;
+			regulator-name = "pex_hvdd_3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&sys_3v3_reg>;
+		};
+
+		vdd_cam1_ldo_reg: regulator@6 {
+			compatible = "regulator-fixed";
+			reg = <6>;
+			regulator-name = "vdd_cam1_ldo";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&sys_3v3_reg>;
+		};
+
+		vdd_cam2_ldo_reg: regulator@7 {
+			compatible = "regulator-fixed";
+			reg = <7>;
+			regulator-name = "vdd_cam2_ldo";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&sys_3v3_reg>;
+		};
+
+		vdd_cam3_ldo_reg: regulator@8 {
+			compatible = "regulator-fixed";
+			reg = <8>;
+			regulator-name = "vdd_cam3_ldo";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&sys_3v3_reg>;
+		};
+
+		vdd_com_reg: regulator@9 {
+			compatible = "regulator-fixed";
+			reg = <9>;
+			regulator-name = "vdd_com";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&sys_3v3_reg>;
+		};
+
+		vdd_fuse_3v3_reg: regulator@10 {
+			compatible = "regulator-fixed";
+			reg = <10>;
+			regulator-name = "vdd_fuse_3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&sys_3v3_reg>;
+		};
+
+		vdd_pnl1_reg: regulator@11 {
+			compatible = "regulator-fixed";
+			reg = <11>;
+			regulator-name = "vdd_pnl1";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
+			vin-supply = <&sys_3v3_reg>;
+		};
+
+		vdd_vid_reg: regulator@12 {
+			compatible = "regulator-fixed";
+			reg = <12>;
+			regulator-name = "vddio_vid";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v0_reg>;
+		};
+
+		ddr_reg: regulator@100 {
+			compatible = "regulator-fixed";
+			regulator-name = "ddr";
+			reg = <100>;
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+		};
+
+		sys_3v3_reg: regulator@101 {
+			compatible = "regulator-fixed";
+			reg = <101>;
+			regulator-name = "sys_3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+		};
+
+		usb1_vbus_reg: regulator@102 {
+			compatible = "regulator-fixed";
+			reg = <102>;
+			regulator-name = "usb1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v0_reg>;
+		};
+
+		usb3_vbus_reg: regulator@103 {
+			compatible = "regulator-fixed";
+			reg = <103>;
+			regulator-name = "usb3_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
+			gpio-open-drain;
+			vin-supply = <&vdd_5v0_reg>;
+		};
+
+		vdd_5v0_reg: regulator@104 {
+			compatible = "regulator-fixed";
+			reg = <104>;
+			regulator-name = "5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
+		};
+
+		vdd_bl_reg: regulator@105 {
+			compatible = "regulator-fixed";
+			reg = <105>;
+			regulator-name = "vdd_bl";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
+		};
+
+		vdd_bl2_reg: regulator@106 {
+			compatible = "regulator-fixed";
+			reg = <106>;
+			regulator-name = "vdd_bl2";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+			regulator-boot-on;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
+		};
+	};
 };

arch/arm/dts/tegra30-colibri.dts

@@ -27,8 +27,10 @@
 		reg = <0x80000000 0x40000000>;
 	};
 
-	/* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
-	   board) */
+	/*
+	 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
+	 * board)
+	 */
 	i2c@7000c000 {
 		status = "okay";
 		clock-frequency = <100000>;
@@ -44,8 +46,10 @@
 		clock-frequency = <100000>;
 	};
 
-	/* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
-	   touch screen controller */
+	/*
+	 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+	 * touch screen controller
+	 */
 	i2c@7000d000 {
 		status = "okay";
 		clock-frequency = <100000>;

arch/arm/dts/tegra30.dtsi

@@ -6,6 +6,89 @@
 
 / {
 	compatible = "nvidia,tegra30";
+	interrupt-parent = <&intc>;
+
+	intc: interrupt-controller@50041000 {
+		compatible = "arm,cortex-a9-gic";
+		reg = <0x50041000 0x1000
+		       0x50040100 0x0100>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
+	pcie-controller@00003000 {
+		compatible = "nvidia,tegra30-pcie";
+		device_type = "pci";
+		reg = <0x00003000 0x00000800   /* PADS registers */
+		       0x00003800 0x00000200   /* AFI registers */
+		       0x10000000 0x10000000>; /* configuration space */
+		reg-names = "pads", "afi", "cs";
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
+		              GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+		interrupt-names = "intr", "msi";
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+		bus-range = <0x00 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
+			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
+			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
+			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
+			  0x82000000 0 0x20000000 0x20000000 0 0x10000000   /* non-prefetchable memory */
+			  0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
+
+		clocks = <&tegra_car TEGRA30_CLK_PCIE>,
+			 <&tegra_car TEGRA30_CLK_AFI>,
+			 <&tegra_car TEGRA30_CLK_PCIEX>,
+			 <&tegra_car TEGRA30_CLK_PLL_E>,
+			 <&tegra_car TEGRA30_CLK_CML0>;
+		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+		status = "disabled";
+
+		pci@1,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
+			reg = <0x000800 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <2>;
+		};
+
+		pci@2,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
+			reg = <0x001000 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <2>;
+		};
+
+		pci@3,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
+			reg = <0x001800 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <2>;
+		};
+	};
 
 	tegra_car: clock {
 		compatible = "nvidia,tegra30-car";

arch/arm/imx-common/i2c-mxv7.c

@@ -73,26 +73,21 @@ static void * const i2c_bases[] = {
 int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
 	      struct i2c_pads_info *p)
 {
-	char *name1, *name2;
+	char name[9];
 	int ret;
 
 	if (i2c_index >= ARRAY_SIZE(i2c_bases))
 		return -EINVAL;
 
-	name1 = malloc(9);
-	name2 = malloc(9);
-	if (!name1 || !name2)
-		return -ENOMEM;
-
-	sprintf(name1, "i2c_sda%d", i2c_index);
-	sprintf(name2, "i2c_scl%d", i2c_index);
-	ret = gpio_request(p->sda.gp, name1);
+	snprintf(name, sizeof(name), "i2c_sda%01d", i2c_index);
+	ret = gpio_request(p->sda.gp, name);
 	if (ret)
-		goto err_req1;
+		return ret;
 
-	ret = gpio_request(p->scl.gp, name2);
+	snprintf(name, sizeof(name), "i2c_scl%01d", i2c_index);
+	ret = gpio_request(p->scl.gp, name);
 	if (ret)
-		goto err_req2;
+		goto err_req;
 
 	/* Enable i2c clock */
 	ret = enable_i2c_clk(1, i2c_index);
@@ -112,11 +107,8 @@ int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
 err_idle:
 err_clk:
 	gpio_free(p->scl.gp);
-err_req2:
+err_req:
 	gpio_free(p->sda.gp);
-err_req1:
-	free(name1);
-	free(name2);
 
 	return ret;
 }

arch/arm/imx-common/spl.c

@@ -68,8 +68,10 @@ u32 spl_boot_mode(void)
 	/* for MMC return either RAW or FAT mode */
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
-#ifdef CONFIG_SPL_FAT_SUPPORT
+#if defined(CONFIG_SPL_FAT_SUPPORT)
 		return MMCSD_MODE_FS;
+#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
+		return MMCSD_MODE_EMMCBOOT;
 #else
 		return MMCSD_MODE_RAW;
 #endif

arch/arm/include/asm/arch-exynos/system.h

@@ -41,7 +41,4 @@ void set_usbhost_mode(unsigned int mode);
 void set_system_display_ctrl(void);
 int exynos_lcd_early_init(const void *blob);
 
-/* Initialize the Parade dP<->LVDS bridge if present */
-int parade_init(const void *blob);
-
 #endif	/* _EXYNOS4_SYSTEM_H */

arch/arm/include/asm/arch-keystone/hardware.h

@@ -144,6 +144,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
 #define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
 #define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+#define KS2_DEVCFG			(KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
 
 /* PSC */
 #define KS2_PSC_BASE			0x02350000

arch/arm/include/asm/arch-mx6/clock.h

@@ -67,5 +67,6 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
+void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
 #endif /* __ASM_ARCH_CLOCK_H */

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -92,10 +92,10 @@
 #define AIPS3_END_ADDR			0x022FFFFF
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF
-#define QSPI1_ARB_BASE_ADDR             0x60000000
-#define QSPI1_ARB_END_ADDR              0x6FFFFFFF
-#define QSPI2_ARB_BASE_ADDR             0x70000000
-#define QSPI2_ARB_END_ADDR              0x7FFFFFFF
+#define QSPI0_AMBA_BASE                0x60000000
+#define QSPI0_AMBA_END                 0x6FFFFFFF
+#define QSPI1_AMBA_BASE                0x70000000
+#define QSPI1_AMBA_END                 0x7FFFFFFF
 #else
 #define SATA_ARB_BASE_ADDR              0x02200000
 #define SATA_ARB_END_ADDR               0x02203FFF
@@ -262,8 +262,8 @@
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
 #ifdef CONFIG_MX6SX
 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define QSPI2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)

arch/arm/include/asm/arch-omap4/sys_proto.h

@@ -22,6 +22,9 @@ extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
 extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
 extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
 extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
+extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2;
+extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2;
+extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2;
 struct omap_sysinfo {
 	char *board_string;
 };

arch/arm/include/asm/arch-tegra/powergate.h

@@ -0,0 +1,38 @@
+#ifndef _TEGRA_POWERGATE_H_
+#define _TEGRA_POWERGATE_H_
+
+#include <asm/arch/clock.h>
+
+enum tegra_powergate {
+	TEGRA_POWERGATE_CPU,
+	TEGRA_POWERGATE_3D,
+	TEGRA_POWERGATE_VENC,
+	TEGRA_POWERGATE_PCIE,
+	TEGRA_POWERGATE_VDEC,
+	TEGRA_POWERGATE_L2,
+	TEGRA_POWERGATE_MPE,
+	TEGRA_POWERGATE_HEG,
+	TEGRA_POWERGATE_SATA,
+	TEGRA_POWERGATE_CPU1,
+	TEGRA_POWERGATE_CPU2,
+	TEGRA_POWERGATE_CPU3,
+	TEGRA_POWERGATE_CELP,
+	TEGRA_POWERGATE_3D1,
+	TEGRA_POWERGATE_CPU0,
+	TEGRA_POWERGATE_C0NC,
+	TEGRA_POWERGATE_C1NC,
+	TEGRA_POWERGATE_SOR,
+	TEGRA_POWERGATE_DIS,
+	TEGRA_POWERGATE_DISB,
+	TEGRA_POWERGATE_XUSBA,
+	TEGRA_POWERGATE_XUSBB,
+	TEGRA_POWERGATE_XUSBC,
+	TEGRA_POWERGATE_VIC,
+	TEGRA_POWERGATE_IRAM,
+};
+
+int tegra_powergate_sequence_power_up(enum tegra_powergate id,
+				      enum periph_id periph);
+int tegra_powergate_power_off(enum tegra_powergate id);
+
+#endif

arch/arm/include/asm/arch-tegra/xusb-padctl.h

@@ -0,0 +1,24 @@
+#ifndef _TEGRA_XUSB_PADCTL_H_
+#define _TEGRA_XUSB_PADCTL_H_
+
+struct tegra_xusb_phy;
+
+/**
+ * tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY
+ * @type: the type of PHY to obtain
+ *
+ * The type of PHY varies between SoC generations. Typically there are XUSB,
+ * PCIe and SATA PHYs, though not all generations support all of them. The
+ * value of type can usually be directly parsed from a device tree.
+ *
+ * Return: a pointer to the PHY or NULL if no such PHY exists
+ */
+struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
+
+void tegra_xusb_padctl_init(const void *fdt);
+int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy);
+
+#endif

arch/arm/include/asm/arch-tegra114/powergate.h

@@ -0,0 +1,6 @@
+#ifndef _TEGRA114_POWERGATE_H_
+#define _TEGRA114_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA114_POWERGATE_H_ */

arch/arm/include/asm/arch-tegra124/clock.h

@@ -16,4 +16,6 @@
 #define OSC_FREQ_SHIFT          28
 #define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
 
+int tegra_plle_enable(void);
+
 #endif	/* _TEGRA124_CLOCK_H_ */

arch/arm/include/asm/arch-tegra124/powergate.h

@@ -0,0 +1,6 @@
+#ifndef _TEGRA124_POWERGATE_H_
+#define _TEGRA124_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA124_POWERGATE_H_ */

arch/arm/include/asm/arch-tegra20/clock-tables.h

@@ -131,7 +131,7 @@ enum periph_id {
 	/* 72 */
 	PERIPH_ID_AFI,
 	PERIPH_ID_CORESIGHT,
-	PERIPH_ID_RESERVED74,
+	PERIPH_ID_PCIEXCLK,
 	PERIPH_ID_AVPUCQ,
 	PERIPH_ID_RESERVED76,
 	PERIPH_ID_RESERVED77,

arch/arm/include/asm/arch-tegra20/clock.h

@@ -15,4 +15,6 @@
 #define OSC_FREQ_SHIFT          30
 #define OSC_FREQ_MASK           (3U << OSC_FREQ_SHIFT)
 
+int tegra_plle_enable(void);
+
 #endif	/* _TEGRA20_CLOCK_H */

arch/arm/include/asm/arch-tegra20/powergate.h

@@ -0,0 +1,6 @@
+#ifndef _TEGRA20_POWERGATE_H_
+#define _TEGRA20_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA20_POWERGATE_H_ */

arch/arm/include/asm/arch-tegra30/clock.h

@@ -25,4 +25,6 @@
 #define OSC_FREQ_SHIFT          28
 #define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
 
+int tegra_plle_enable(void);
+
 #endif	/* _TEGRA30_CLOCK_H_ */

arch/arm/include/asm/arch-tegra30/powergate.h

@@ -0,0 +1,6 @@
+#ifndef _TEGRA30_POWERGATE_H_
+#define _TEGRA30_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA30_POWERGATE_H_ */

arch/arm/include/asm/arch-uniphier/ddrphy-regs.h

@@ -0,0 +1,172 @@
+/*
+ * UniPhier DDR PHY registers
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_REGS_H
+#define ARCH_DDRPHY_REGS_H
+
+#include <linux/compiler.h>
+
+#ifndef __ASSEMBLY__
+
+struct ddrphy {
+	u32 ridr;		/* Revision Identification Register */
+	u32 pir;		/* PHY Initialixation Register */
+	u32 pgcr[2];		/* PHY General Configuration Register */
+	u32 pgsr[2];		/* PHY General Status Register */
+	u32 pllcr;		/* PLL Control Register */
+	u32 ptr[5];		/* PHY Timing Register */
+	u32 acmdlr;		/* AC Master Delay Line Register */
+	u32 acbdlr;		/* AC Bit Delay Line Register */
+	u32 aciocr;		/* AC I/O Configuration Register */
+	u32 dxccr;		/* DATX8 Common Configuration Register */
+	u32 dsgcr;		/* DDR System General Configuration Register */
+	u32 dcr;		/* DRAM Configuration Register */
+	u32 dtpr[3];		/* DRAM Timing Parameters Register */
+	u32 mr0;		/* Mode Register 0 */
+	u32 mr1;		/* Mode Register 1 */
+	u32 mr2;		/* Mode Register 2 */
+	u32 mr3;		/* Mode Register 3 */
+	u32 odtcr;		/* ODT Configuration Register */
+	u32 dtcr;		/* Data Training Configuration Register */
+	u32 dtar[4];		/* Data Training Address Register */
+	u32 dtdr[2];		/* Data Training Data Register */
+	u32 dtedr[2];		/* Data Training Eye Data Register */
+	u32 rsv0[13];		/* Reserved */
+	u32 dcuar;		/* DCU Address Register */
+	u32 dcudr;		/* DCU Data Register */
+	u32 dcurr;		/* DCU Run Register */
+	u32 dculr;		/* DCU Loop Register */
+	u32 dcugcr;		/* DCU General Configuration Register */
+	u32 dcutpr;		/* DCU Timing Parameters Register */
+	u32 dcusr[2];		/* DCU Status Register */
+	u32 rsv1[8];		/* Reserved */
+	u32 bistrr;		/* BIST Run Register */
+	u32 bistwcr;		/* BIST Word Count Register */
+	u32 bistmskr[3];	/* BIST Mask Register */
+	u32 bistlsr;		/* BIST LFSR Sed Register */
+	u32 bistar[3];		/* BIST Address Register */
+	u32 bistudpr;		/* BIST User Data Pattern Register */
+	u32 bistgsr;		/* BIST General Status Register */
+	u32 bistwer;		/* BIST Word Error Register */
+	u32 bistber[4];		/* BIST Bit Error Register */
+	u32 bistwcsr;		/* BIST Word Count Status Register */
+	u32 bistfwr[3];		/* BIST Fail Word Register */
+	u32 rsv2[10];		/* Reserved */
+	u32 gpr[2];		/* General Purpose Register */
+	struct ddrphy_zq {	/* ZQ */
+		u32 cr[2];	/* Impedance Control Register */
+		u32 sr[2];	/* Impedance Status Register */
+	} zq[4];
+	struct ddrphy_datx8 {	/* DATX8 */
+		u32 gcr;	/* General Configuration Register */
+		u32 gsr[2];	/* General Status Register */
+		u32 bdlr[5];	/* Bit Delay Line Register */
+		u32 lcdlr[3];	/* Local Calibrated Delay Line Register */
+		u32 mdlr;	/* Master Delay Line Register */
+		u32 gtr;	/* General Timing Register */
+		u32 rsv[3];	/* Reserved */
+	} dx[9];
+} __packed;
+
+#endif /* __ASSEMBLY__ */
+
+#define PIR_INIT		(1 <<  0)	/* Initialization Trigger */
+#define PIR_ZCAL		(1 <<  1)	/* Impedance Calibration */
+#define PIR_PLLINIT		(1 <<  4)	/* PLL Initialization */
+#define PIR_DCAL		(1 <<  5)	/* DDL Calibration */
+#define PIR_PHYRST		(1 <<  6)	/* PHY Reset */
+#define PIR_DRAMRST		(1 <<  7)	/* DRAM Reset */
+#define PIR_DRAMINIT		(1 <<  8)	/* DRAM Initialization */
+#define PIR_WL			(1 <<  9)	/* Write Leveling */
+#define PIR_QSGATE		(1 << 10)	/* Read DQS Gate Training */
+#define PIR_WLADJ		(1 << 11)	/* Write Leveling Adjust */
+#define PIR_RDDSKW		(1 << 12)	/* Read Data Bit Deskew */
+#define PIR_WRDSKW		(1 << 13)	/* Write Data Bit Deskew */
+#define PIR_RDEYE		(1 << 14)	/* Read Data Eye Training */
+#define PIR_WREYE		(1 << 15)	/* Write Data Eye Training */
+#define PIR_LOCKBYP		(1 << 28)	/* PLL Lock Bypass */
+#define PIR_DCALBYP		(1 << 29)	/* DDL Calibration Bypass */
+#define PIR_ZCALBYP		(1 << 30)	/* Impedance Calib Bypass */
+#define PIR_INITBYP		(1 << 31)	/* Initialization Bypass */
+
+#define PGSR0_IDONE		(1 <<  0)	/* Initialization Done */
+#define PGSR0_PLDONE		(1 <<  1)	/* PLL Lock Done */
+#define PGSR0_DCDONE		(1 <<  2)	/* DDL Calibration Done */
+#define PGSR0_ZCDONE		(1 <<  3)	/* Impedance Calibration Done */
+#define PGSR0_DIDONE		(1 <<  4)	/* DRAM Initialization Done */
+#define PGSR0_WLDONE		(1 <<  5)	/* Write Leveling Done */
+#define PGSR0_QSGDONE		(1 <<  6)	/* DQS Gate Training Done */
+#define PGSR0_WLADONE		(1 <<  7)	/* Write Leveling Adjust Done */
+#define PGSR0_RDDONE		(1 <<  8)	/* Read Bit Deskew Done */
+#define PGSR0_WDDONE		(1 <<  9)	/* Write Bit Deskew Done */
+#define PGSR0_REDONE		(1 << 10)	/* Read Eye Training Done */
+#define PGSR0_WEDONE		(1 << 11)	/* Write Eye Training Done */
+#define PGSR0_IERR		(1 << 16)	/* Initialization Error */
+#define PGSR0_PLERR		(1 << 17)	/* PLL Lock Error */
+#define PGSR0_DCERR		(1 << 18)	/* DDL Calibration Error */
+#define PGSR0_ZCERR		(1 << 19)	/* Impedance Calib Error */
+#define PGSR0_DIERR		(1 << 20)	/* DRAM Initialization Error */
+#define PGSR0_WLERR		(1 << 21)	/* Write Leveling Error */
+#define PGSR0_QSGERR		(1 << 22)	/* DQS Gate Training Error */
+#define PGSR0_WLAERR		(1 << 23)	/* Write Leveling Adj Error */
+#define PGSR0_RDERR		(1 << 24)	/* Read Bit Deskew Error */
+#define PGSR0_WDERR		(1 << 25)	/* Write Bit Deskew Error */
+#define PGSR0_REERR		(1 << 26)	/* Read Eye Training Error */
+#define PGSR0_WEERR		(1 << 27)	/* Write Eye Training Error */
+#define PGSR0_DTERR_SHIFT	28		/* Data Training Error Status*/
+#define PGSR0_DTERR		(7 << (PGSR0_DTERR_SHIFT))
+#define PGSR0_APLOCK		(1 << 31)	/* AC PLL Lock */
+
+#define DXCCR_DQSRES_OPEN	(0 << 5)
+#define DXCCR_DQSRES_688_OHM	(1 << 5)
+#define DXCCR_DQSRES_611_OHM	(2 << 5)
+#define DXCCR_DQSRES_550_OHM	(3 << 5)
+#define DXCCR_DQSRES_500_OHM	(4 << 5)
+#define DXCCR_DQSRES_458_OHM	(5 << 5)
+#define DXCCR_DQSRES_393_OHM	(6 << 5)
+#define DXCCR_DQSRES_344_OHM	(7 << 5)
+
+#define DXCCR_DQSNRES_OPEN	(0 << 9)
+#define DXCCR_DQSNRES_688_OHM	(1 << 9)
+#define DXCCR_DQSNRES_611_OHM	(2 << 9)
+#define DXCCR_DQSNRES_550_OHM	(3 << 9)
+#define DXCCR_DQSNRES_500_OHM	(4 << 9)
+#define DXCCR_DQSNRES_458_OHM	(5 << 9)
+#define DXCCR_DQSNRES_393_OHM	(6 << 9)
+#define DXCCR_DQSNRES_344_OHM	(7 << 9)
+
+#define DTCR_DTRANK_SHIFT	4		/* Data Training Rank */
+#define DTCR_DTRANK_MASK	(0x3 << (DTCR_DTRANK_SHIFT))
+#define DTCR_DTMPR		(1 << 6)	/* Data Training using MPR */
+#define DTCR_RNKEN_SHIFT	24		/* Rank Enable */
+#define DTCR_RNKEN_MASK		(0xf << (DTCR_RNKEN_SHIFT))
+
+#define DXGCR_WLRKEN_SHIFT	26		/* Write Level Rank Enable */
+#define DXGCR_WLRKEN_MASK	(0xf << (DXGCR_WLRKEN_SHIFT))
+
+/* SoC-specific parameters */
+#define NR_DATX8_PER_DDRPHY	2
+
+#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define NR_DDRPHY_PER_CH		1
+#else
+#define NR_DDRPHY_PER_CH		2
+#endif
+
+#define NR_DDRCH		2
+
+#define DDRPHY_BASE(ch, phy)	(0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
+
+#ifndef __ASSEMBLY__
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
+int ddrphy_training(struct ddrphy __iomem *phy);
+#endif
+
+#endif /* ARCH_DDRPHY_REGS_H */

arch/arm/include/asm/arch-uniphier/debug-uart.S

@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/serial_reg.h>
+
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
+
+#define BAUDRATE		115200
+#define DIV_ROUND(x, d)		(((x) + ((d) / 2)) / (d))
+#define DIVISOR			DIV_ROUND(UART_CLK, 16 * BAUDRATE)
+
+	.macro		init_debug_uart, ra, rb, rc
+	addruart	\ra, \rb, \rc
+	mov		\rb, #UART_LCR_WLEN8
+	strb		\rb, [\ra, #0x11]
+	ldr		\rb, =DIVISOR
+	str		\rb, [\ra, #0x24]
+	.endm

arch/arm/include/asm/arch-uniphier/sbc-regs.h

@@ -95,6 +95,7 @@
 #define SBCTRL1_ADMULTIPLX_MEM_VALUE	0x03005500
 #define SBCTRL2_ADMULTIPLX_MEM_VALUE	0x14000010
 
+#define PC0CTRL				0x598000c0
 #define ROM_BOOT_ROMRSV2		0x59801208
 
 #ifndef __ASSEMBLY__

arch/arm/include/asm/armv7.h

@@ -80,6 +80,7 @@ void v7_outer_cache_inval_range(u32 start, u32 end);
 
 int armv7_init_nonsec(void);
 int armv7_update_dt(void *fdt);
+bool armv7_boot_nonsec(void);
 
 /* defined in assembly file */
 unsigned int _nonsec_init(void);

arch/arm/include/asm/assembler.h

@@ -14,12 +14,14 @@
  *  assembler source.
  */
 
+#include <config.h>
+
 /*
  * Endian independent macros for shifting bytes within registers.
  */
 #ifndef __ARMEB__
-#define pull		lsr
-#define push		lsl
+#define lspull		lsr
+#define lspush		lsl
 #define get_byte_0	lsl #0
 #define get_byte_1	lsr #8
 #define get_byte_2	lsr #16
@@ -29,8 +31,8 @@
 #define put_byte_2	lsl #16
 #define put_byte_3	lsl #24
 #else
-#define pull		lsl
-#define push		lsr
+#define lspull		lsl
+#define lspush		lsr
 #define get_byte_0	lsr #24
 #define get_byte_1	lsr #16
 #define get_byte_2	lsr #8
@@ -54,7 +56,28 @@
 #define PLD(code...)
 #endif
 
+	.irp	c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
+	.macro	ret\c, reg
+#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__)
+	mov\c	pc, \reg
+#else
+	.ifeqs	"\reg", "lr"
+	bx\c	\reg
+	.else
+	mov\c	pc, \reg
+	.endif
+#endif
+	.endm
+	.endr
+
 /*
- * Cache alligned
+ * Cache aligned, used for optimized memcpy/memset
+ * In the kernel this is only enabled for Feroceon CPU's...
+ * We disable it especially for Thumb builds since those instructions
+ * are not made in a Thumb ready way...
  */
+#ifdef CONFIG_SYS_THUMB_BUILD
+#define CALGN(code...)
+#else
 #define CALGN(code...) code
+#endif

arch/arm/include/asm/system.h

@@ -212,6 +212,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  */
 void mmu_page_table_flush(unsigned long start, unsigned long stop);
 
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+void noncached_init(void);
+phys_addr_t noncached_alloc(size_t size, size_t align);
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
 #endif /* __ASSEMBLY__ */
 
 #define arch_align_stack(x) (x)

arch/arm/lib/bootm.c

@@ -238,7 +238,7 @@ static void boot_prep_linux(bootm_headers_t *images)
 }
 
 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
-static bool boot_nonsec(void)
+bool armv7_boot_nonsec(void)
 {
 	char *s = getenv("bootm_boot_mode");
 #ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT
@@ -305,7 +305,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 
 	if (!fake) {
 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
-		if (boot_nonsec()) {
+		if (armv7_boot_nonsec()) {
 			armv7_init_nonsec();
 			secure_ram_addr(_do_nonsec_entry)(kernel_entry,
 							  0, machid, r2);

arch/arm/lib/cache.c

@@ -8,6 +8,7 @@
 /* for now: just dummy functions to satisfy the linker */
 
 #include <common.h>
+#include <malloc.h>
 
 __weak void flush_cache(unsigned long start, unsigned long size)
 {
@@ -49,3 +50,46 @@ __weak void enable_caches(void)
 {
 	puts("WARNING: Caches not enabled\n");
 }
+
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+/*
+ * Reserve one MMU section worth of address space below the malloc() area that
+ * will be mapped uncached.
+ */
+static unsigned long noncached_start;
+static unsigned long noncached_end;
+static unsigned long noncached_next;
+
+void noncached_init(void)
+{
+	phys_addr_t start, end;
+	size_t size;
+
+	end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
+	size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
+	start = end - size;
+
+	debug("mapping memory %pa-%pa non-cached\n", &start, &end);
+
+	noncached_start = start;
+	noncached_end = end;
+	noncached_next = start;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+	mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
+#endif
+}
+
+phys_addr_t noncached_alloc(size_t size, size_t align)
+{
+	phys_addr_t next = ALIGN(noncached_next, align);
+
+	if (next >= noncached_end || (noncached_end - next) < size)
+		return 0;
+
+	debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
+	noncached_next = next + size;
+
+	return next;
+}
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */

arch/arm/lib/memcpy.S

@@ -10,9 +10,14 @@
  *  published by the Free Software Foundation.
  */
 
+#include <linux/linkage.h>
 #include <asm/assembler.h>
 
+#ifdef CONFIG_SYS_THUMB_BUILD
+#define W(instr)	instr.w
+#else
 #define W(instr)	instr
+#endif
 
 #define LDR1W_SHIFT	0
 #define STR1W_SHIFT	0
@@ -30,7 +35,7 @@
 	.endm
 
 	.macro ldr1b ptr reg cond=al abort
-	ldr\cond\()b \reg, [\ptr], #1
+	ldrb\cond\() \reg, [\ptr], #1
 	.endm
 
 	.macro str1w ptr reg abort
@@ -42,7 +47,7 @@
 	.endm
 
 	.macro str1b ptr reg cond=al abort
-	str\cond\()b \reg, [\ptr], #1
+	strb\cond\() \reg, [\ptr], #1
 	.endm
 
 	.macro enter reg1 reg2
@@ -56,10 +61,12 @@
 	.text
 
 /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
-
-.globl memcpy
-memcpy:
-
+	.syntax unified
+#ifdef CONFIG_SYS_THUMB_BUILD
+	.thumb
+	.thumb_func
+#endif
+ENTRY(memcpy)
 		cmp	r0, r1
 		moveq	pc, lr
 
@@ -79,7 +86,7 @@ memcpy:
 
 	CALGN(	ands	ip, r0, #31		)
 	CALGN(	rsb	r3, ip, #32		)
-	CALGN(	sbcnes	r4, r3, r2		)  @ C is always set here
+	CALGN(	sbcsne	r4, r3, r2		)  @ C is always set here
 	CALGN(	bcs	2f			)
 	CALGN(	adr	r4, 6f			)
 	CALGN(	subs	r2, r2, r3		)  @ C gets set
@@ -178,7 +185,7 @@ memcpy:
 
 	CALGN(	ands	ip, r0, #31		)
 	CALGN(	rsb	ip, ip, #32		)
-	CALGN(	sbcnes	r4, ip, r2		)  @ C is always set here
+	CALGN(	sbcsne	r4, ip, r2		)  @ C is always set here
 	CALGN(	subcc	r2, r2, ip		)
 	CALGN(	bcc	15f			)
 
@@ -193,24 +200,24 @@ memcpy:
 
 12:	PLD(	pld	[r1, #124]		)
 13:		ldr4w	r1, r4, r5, r6, r7, abort=19f
-		mov	r3, lr, pull #\pull
+		mov	r3, lr, lspull #\pull
 		subs	r2, r2, #32
 		ldr4w	r1, r8, r9, ip, lr, abort=19f
-		orr	r3, r3, r4, push #\push
-		mov	r4, r4, pull #\pull
-		orr	r4, r4, r5, push #\push
-		mov	r5, r5, pull #\pull
-		orr	r5, r5, r6, push #\push
-		mov	r6, r6, pull #\pull
-		orr	r6, r6, r7, push #\push
-		mov	r7, r7, pull #\pull
-		orr	r7, r7, r8, push #\push
-		mov	r8, r8, pull #\pull
-		orr	r8, r8, r9, push #\push
-		mov	r9, r9, pull #\pull
-		orr	r9, r9, ip, push #\push
-		mov	ip, ip, pull #\pull
-		orr	ip, ip, lr, push #\push
+		orr	r3, r3, r4, lspush #\push
+		mov	r4, r4, lspull #\pull
+		orr	r4, r4, r5, lspush #\push
+		mov	r5, r5, lspull #\pull
+		orr	r5, r5, r6, lspush #\push
+		mov	r6, r6, lspull #\pull
+		orr	r6, r6, r7, lspush #\push
+		mov	r7, r7, lspull #\pull
+		orr	r7, r7, r8, lspush #\push
+		mov	r8, r8, lspull #\pull
+		orr	r8, r8, r9, lspush #\push
+		mov	r9, r9, lspull #\pull
+		orr	r9, r9, ip, lspush #\push
+		mov	ip, ip, lspull #\pull
+		orr	ip, ip, lr, lspush #\push
 		str8w	r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
 		bge	12b
 	PLD(	cmn	r2, #96			)
@@ -221,10 +228,10 @@ memcpy:
 14:		ands	ip, r2, #28
 		beq	16f
 
-15:		mov	r3, lr, pull #\pull
+15:		mov	r3, lr, lspull #\pull
 		ldr1w	r1, lr, abort=21f
 		subs	ip, ip, #4
-		orr	r3, r3, lr, push #\push
+		orr	r3, r3, lr, lspush #\push
 		str1w	r0, r3, abort=21f
 		bgt	15b
 	CALGN(	cmp	r2, #0			)
@@ -241,3 +248,24 @@ memcpy:
 17:		forward_copy_shift	pull=16	push=16
 
 18:		forward_copy_shift	pull=24	push=8
+
+
+/*
+ * Abort preamble and completion macros.
+ * If a fixup handler is required then those macros must surround it.
+ * It is assumed that the fixup code will handle the private part of
+ * the exit macro.
+ */
+
+	.macro	copy_abort_preamble
+19:	ldmfd	sp!, {r5 - r9}
+	b	21f
+20:	ldmfd	sp!, {r5 - r8}
+21:
+	.endm
+
+	.macro	copy_abort_end
+	ldmfd	sp!, {r4, pc}
+	.endm
+
+ENDPROC(memcpy)

arch/arm/lib/memset.S

@@ -9,32 +9,25 @@
  *
  *  ASM optimised string functions
  */
+#include <linux/linkage.h>
 #include <asm/assembler.h>
 
 	.text
 	.align	5
-	.word	0
 
-1:	subs	r2, r2, #4		@ 1 do we have enough
-	blt	5f			@ 1 bytes to align with?
-	cmp	r3, #2			@ 1
-	strltb	r1, [r0], #1		@ 1
-	strleb	r1, [r0], #1		@ 1
-	strb	r1, [r0], #1		@ 1
-	add	r2, r2, r3		@ 1 (r2 = r2 - (4 - r3))
-/*
- * The pointer is now aligned and the length is adjusted.  Try doing the
- * memset again.
- */
-
-.globl memset
-memset:
+	.syntax unified
+#ifdef CONFIG_SYS_THUMB_BUILD
+	.thumb
+	.thumb_func
+#endif
+ENTRY(memset)
 	ands	r3, r0, #3		@ 1 unaligned?
-	bne	1b			@ 1
+	mov	ip, r0			@ preserve r0 as return value
+	bne	6f			@ 1
 /*
- * we know that the pointer in r0 is aligned to a word boundary.
+ * we know that the pointer in ip is aligned to a word boundary.
  */
-	orr	r1, r1, r1, lsl #8
+1:	orr	r1, r1, r1, lsl #8
 	orr	r1, r1, r1, lsl #16
 	mov	r3, r1
 	cmp	r2, #16
@@ -43,29 +36,28 @@ memset:
 #if ! CALGN(1)+0
 
 /*
- * We need an extra register for this loop - save the return address and
- * use the LR
+ * We need 2 extra registers for this loop - use r8 and the LR
  */
-	str	lr, [sp, #-4]!
-	mov	ip, r1
+	stmfd	sp!, {r8, lr}
+	mov	r8, r1
 	mov	lr, r1
 
 2:	subs	r2, r2, #64
-	stmgeia	r0!, {r1, r3, ip, lr}	@ 64 bytes at a time.
-	stmgeia	r0!, {r1, r3, ip, lr}
-	stmgeia	r0!, {r1, r3, ip, lr}
-	stmgeia	r0!, {r1, r3, ip, lr}
+	stmiage	ip!, {r1, r3, r8, lr}	@ 64 bytes at a time.
+	stmiage	ip!, {r1, r3, r8, lr}
+	stmiage	ip!, {r1, r3, r8, lr}
+	stmiage	ip!, {r1, r3, r8, lr}
 	bgt	2b
-	ldmeqfd	sp!, {pc}		@ Now <64 bytes to go.
+	ldmfdeq	sp!, {r8, pc}		@ Now <64 bytes to go.
 /*
  * No need to correct the count; we're only testing bits from now on
  */
 	tst	r2, #32
-	stmneia	r0!, {r1, r3, ip, lr}
-	stmneia	r0!, {r1, r3, ip, lr}
+	stmiane	ip!, {r1, r3, r8, lr}
+	stmiane	ip!, {r1, r3, r8, lr}
 	tst	r2, #16
-	stmneia	r0!, {r1, r3, ip, lr}
-	ldr	lr, [sp], #4
+	stmiane	ip!, {r1, r3, r8, lr}
+	ldmfd	sp!, {r8, lr}
 
 #else
 
@@ -74,53 +66,63 @@ memset:
  * whole cache lines at once.
  */
 
-	stmfd	sp!, {r4-r7, lr}
+	stmfd	sp!, {r4-r8, lr}
 	mov	r4, r1
 	mov	r5, r1
 	mov	r6, r1
 	mov	r7, r1
-	mov	ip, r1
+	mov	r8, r1
 	mov	lr, r1
 
 	cmp	r2, #96
-	tstgt	r0, #31
+	tstgt	ip, #31
 	ble	3f
 
-	and	ip, r0, #31
-	rsb	ip, ip, #32
-	sub	r2, r2, ip
-	movs	ip, ip, lsl #(32 - 4)
-	stmcsia	r0!, {r4, r5, r6, r7}
-	stmmiia	r0!, {r4, r5}
-	tst	ip, #(1 << 30)
-	mov	ip, r1
-	strne	r1, [r0], #4
+	and	r8, ip, #31
+	rsb	r8, r8, #32
+	sub	r2, r2, r8
+	movs	r8, r8, lsl #(32 - 4)
+	stmiacs	ip!, {r4, r5, r6, r7}
+	stmiami	ip!, {r4, r5}
+	tst	r8, #(1 << 30)
+	mov	r8, r1
+	strne	r1, [ip], #4
 
 3:	subs	r2, r2, #64
-	stmgeia	r0!, {r1, r3-r7, ip, lr}
-	stmgeia	r0!, {r1, r3-r7, ip, lr}
+	stmiage	ip!, {r1, r3-r8, lr}
+	stmiage	ip!, {r1, r3-r8, lr}
 	bgt	3b
-	ldmeqfd	sp!, {r4-r7, pc}
+	ldmfdeq	sp!, {r4-r8, pc}
 
 	tst	r2, #32
-	stmneia	r0!, {r1, r3-r7, ip, lr}
+	stmiane	ip!, {r1, r3-r8, lr}
 	tst	r2, #16
-	stmneia	r0!, {r4-r7}
-	ldmfd	sp!, {r4-r7, lr}
+	stmiane	ip!, {r4-r7}
+	ldmfd	sp!, {r4-r8, lr}
 
 #endif
 
 4:	tst	r2, #8
-	stmneia	r0!, {r1, r3}
+	stmiane	ip!, {r1, r3}
 	tst	r2, #4
-	strne	r1, [r0], #4
+	strne	r1, [ip], #4
 /*
  * When we get here, we've got less than 4 bytes to zero.  We
  * may have an unaligned pointer as well.
  */
 5:	tst	r2, #2
-	strneb	r1, [r0], #1
-	strneb	r1, [r0], #1
+	strbne	r1, [ip], #1
+	strbne	r1, [ip], #1
 	tst	r2, #1
-	strneb	r1, [r0], #1
-	mov	pc, lr
+	strbne	r1, [ip], #1
+	ret	lr
+
+6:	subs	r2, r2, #4		@ 1 do we have enough
+	blt	5b			@ 1 bytes to align with?
+	cmp	r3, #2			@ 1
+	strblt	r1, [ip], #1		@ 1
+	strble	r1, [ip], #1		@ 1
+	strb	r1, [ip], #1		@ 1
+	add	r2, r2, r3		@ 1 (r2 = r2 - (4 - r3))
+	b	1b
+ENDPROC(memset)

arch/powerpc/Kconfig

@@ -19,9 +19,6 @@ config 5xx
 config MPC5xxx
 	bool "MPC5xxx"
 
-config MPC824X
-	bool "MPC824X"
-
 config MPC8260
 	bool "MPC8260"
 
@@ -46,7 +43,6 @@ source "arch/powerpc/cpu/74xx_7xx/Kconfig"
 source "arch/powerpc/cpu/mpc512x/Kconfig"
 source "arch/powerpc/cpu/mpc5xx/Kconfig"
 source "arch/powerpc/cpu/mpc5xxx/Kconfig"
-source "arch/powerpc/cpu/mpc824x/Kconfig"
 source "arch/powerpc/cpu/mpc8260/Kconfig"
 source "arch/powerpc/cpu/mpc83xx/Kconfig"
 source "arch/powerpc/cpu/mpc85xx/Kconfig"

arch/powerpc/cpu/mpc5xxx/Kconfig

@@ -83,15 +83,6 @@ config TARGET_O3DNT
 config TARGET_DIGSY_MTC
 	bool "Support digsy_mtc"
 
-config TARGET_HMI1001
-	bool "Support hmi1001"
-
-config TARGET_MUCMC52
-	bool "Support mucmc52"
-
-config TARGET_UC101
-	bool "Support uc101"
-
 config TARGET_PCM030
 	bool "Support pcm030"
 
@@ -124,9 +115,6 @@ source "board/inka4x0/Kconfig"
 source "board/intercontrol/digsy_mtc/Kconfig"
 source "board/ipek01/Kconfig"
 source "board/jupiter/Kconfig"
-source "board/manroland/hmi1001/Kconfig"
-source "board/manroland/mucmc52/Kconfig"
-source "board/manroland/uc101/Kconfig"
 source "board/motionpro/Kconfig"
 source "board/munices/Kconfig"
 source "board/phytec/pcm030/Kconfig"

arch/powerpc/cpu/mpc5xxx/ide.c

@@ -41,19 +41,11 @@ int ide_preinit (void)
 	/* All sample codes do that... */
 	*(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
 
-#if defined(CONFIG_UC101)
-	/* Configure and reset host */
-	*(vu_long *) MPC5XXX_ATA_HOST_CONFIG =
-		MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
-	udelay (10);
-	*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0;
-#else
 	/* Configure and reset host */
 	*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
 		MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
 	udelay (10);
 	*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
-#endif
 
 	/* Disable prefetch on Commbus */
 	psdma->PtdCntrl |= 1;

arch/powerpc/cpu/mpc824x/Kconfig

@@ -1,48 +0,0 @@
-menu "mpc824x CPU"
-	depends on MPC824X
-
-config SYS_CPU
-	default "mpc824x"
-
-choice
-	prompt "Target select"
-
-config TARGET_A3000
-	bool "Support A3000"
-
-config TARGET_CPC45
-	bool "Support CPC45"
-
-config TARGET_CU824
-	bool "Support CU824"
-
-config TARGET_EXALION
-	bool "Support eXalion"
-
-config TARGET_MUSENKI
-	bool "Support MUSENKI"
-
-config TARGET_MVBLUE
-	bool "Support MVBLUE"
-
-config TARGET_SANDPOINT8240
-	bool "Support Sandpoint8240"
-
-config TARGET_SANDPOINT8245
-	bool "Support Sandpoint8245"
-
-config TARGET_UTX8245
-	bool "Support utx8245"
-
-endchoice
-
-source "board/a3000/Kconfig"
-source "board/cpc45/Kconfig"
-source "board/cu824/Kconfig"
-source "board/eXalion/Kconfig"
-source "board/musenki/Kconfig"
-source "board/mvblue/Kconfig"
-source "board/sandpoint/Kconfig"
-source "board/utx8245/Kconfig"
-
-endmenu

arch/powerpc/cpu/mpc824x/Makefile

@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y	= start.o
-obj-y	= traps.o cpu.o cpu_init.o interrupts.o speed.o \
-	  drivers/epic/epic1.o drivers/i2c/i2c.o pci.o
-obj-y += ../mpc8260/bedbug_603e.o

arch/powerpc/cpu/mpc824x/config.mk

@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mstring -mcpu=603e -msoft-float

arch/powerpc/cpu/mpc824x/cpu.c

@@ -1,262 +0,0 @@
-/*
- * (C) Copyright 2000 - 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <mpc824x.h>
-#include <common.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkcpu (void)
-{
-	unsigned int pvr = get_pvr ();
-	unsigned int version = pvr >> 16;
-	unsigned char revision;
-	ulong clock = gd->cpu_clk;
-	char buf[32];
-
-	puts ("CPU:   ");
-
-	switch (version) {
-	case CPU_TYPE_8240:
-		puts ("MPC8240");
-		break;
-
-	case CPU_TYPE_8245:
-		puts ("MPC8245");
-		break;
-
-	default:
-		return -1;		/*not valid for this source */
-	}
-
-	CONFIG_READ_BYTE (REVID, revision);
-
-	if (revision) {
-		printf (" Revision %d.%d",
-			(revision & 0xf0) >> 4,
-			(revision & 0x0f));
-	} else {
-		return -1;		/* no valid CPU revision info */
-	}
-
-	printf(" at %s MHz: ", strmhz(buf, clock));
-
-	print_size(checkicache(), " I-Cache ");
-	print_size(checkdcache(), " D-Cache\n");
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-/* L1 i-cache                                                                */
-
-int checkicache (void)
-{
-	 /*TODO*/
-	 return 128 * 4 * 32;
-};
-
-/* ------------------------------------------------------------------------- */
-/* L1 d-cache                                                                */
-
-int checkdcache (void)
-{
-	 /*TODO*/
-	 return 128 * 4 * 32;
-
-};
-
-/*------------------------------------------------------------------- */
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong msr, addr;
-
-	/* Interrupts and MMU off */
-	__asm__ ("mtspr    81, 0");
-
-	/* Interrupts and MMU off */
-	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
-
-	msr &= ~0x1030;
-	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
-
-	/*
-	 * Trying to execute the next instruction at a non-existing address
-	 * should cause a machine check, resulting in reset
-	 */
-#ifdef CONFIG_SYS_RESET_ADDRESS
-	addr = CONFIG_SYS_RESET_ADDRESS;
-#else
-	/*
-	 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
-	 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
-	 * address. Better pick an address known to be invalid on
-	 * your system and assign it to CONFIG_SYS_RESET_ADDRESS.
-	 * "(ulong)-1" used to be a good choice for many systems...
-	 */
-	addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
-#endif
-	((void (*)(void)) addr) ();
-	return 1;
-
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Get timebase clock frequency (like cpu_clk in Hz)
- * This is the sys_logic_clk (memory bus) divided by 4
- */
-unsigned long get_tbclk (void)
-{
-	return ((get_bus_freq (0) + 2L) / 4L);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * The MPC824x has an integrated PCI controller known as the MPC107.
- * The following are MPC107 Bridge Controller and PCI Support functions
- *
- */
-
-/*
- *  This procedure reads a 32-bit address MPC107 register, and returns
- *  a 32 bit value.  It swaps the address to little endian before
- *  writing it to config address, and swaps the value to big endian
- *  before returning to the caller.
- */
-unsigned int mpc824x_mpc107_getreg (unsigned int regNum)
-{
-	unsigned int temp;
-
-	/* swap the addr. to little endian */
-	*(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum);
-	temp = *(volatile unsigned int *) CHRP_REG_DATA;
-	return PCISWAP (temp);		/* swap the data upon return */
-}
-
-/*
- *  This procedure writes a 32-bit address MPC107 register.  It swaps
- *  the address to little endian before writing it to config address.
- */
-
-void mpc824x_mpc107_setreg (unsigned int regNum, unsigned int regVal)
-{
-	/* swap the addr. to little endian */
-	*(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum);
-	*(volatile unsigned int *) CHRP_REG_DATA = PCISWAP (regVal);
-	return;
-}
-
-
-/*
- *  Write a byte (8 bits) to a memory location.
- */
-void mpc824x_mpc107_write8 (unsigned int addr, unsigned char data)
-{
-	*(unsigned char *) addr = data;
-	__asm__ ("sync");
-}
-
-/*
- *  Write a word (16 bits) to a memory location after the value
- *  has been byte swapped (big to little endian or vice versa)
- */
-
-void mpc824x_mpc107_write16 (unsigned int address, unsigned short data)
-{
-	*(volatile unsigned short *) address = BYTE_SWAP_16_BIT (data);
-	__asm__ ("sync");
-}
-
-/*
- *  Write a long word (32 bits) to a memory location after the value
- *  has been byte swapped (big to little endian or vice versa)
- */
-
-void mpc824x_mpc107_write32 (unsigned int address, unsigned int data)
-{
-	*(volatile unsigned int *) address = LONGSWAP (data);
-	__asm__ ("sync");
-}
-
-/*
- *  Read a byte (8 bits) from a memory location.
- */
-unsigned char mpc824x_mpc107_read8 (unsigned int addr)
-{
-	return *(volatile unsigned char *) addr;
-}
-
-
-/*
- *  Read a word (16 bits) from a memory location, and byte swap the
- *  value before returning to the caller.
- */
-unsigned short mpc824x_mpc107_read16 (unsigned int address)
-{
-	unsigned short retVal;
-
-	retVal = BYTE_SWAP_16_BIT (*(unsigned short *) address);
-	return retVal;
-}
-
-
-/*
- *  Read a long word (32 bits) from a memory location, and byte
- *  swap the value before returning to the caller.
- */
-unsigned int mpc824x_mpc107_read32 (unsigned int address)
-{
-	unsigned int retVal;
-
-	retVal = LONGSWAP (*(unsigned int *) address);
-	return (retVal);
-}
-
-
-/*
- *  Read a register in the Embedded Utilities Memory Block address
- *  space.
- *  Input: regNum - register number + utility base address.  Example,
- *         the base address of EPIC is 0x40000, the register number
- *	   being passed is 0x40000+the address of the target register.
- *	   (See epic.h for register addresses).
- *  Output:  The 32 bit little endian value of the register.
- */
-
-unsigned int mpc824x_eummbar_read (unsigned int regNum)
-{
-	unsigned int temp;
-
-	temp = *(volatile unsigned int *) (EUMBBAR_VAL + regNum);
-	temp = PCISWAP (temp);
-	return temp;
-}
-
-
-/*
- *  Write a value to a register in the Embedded Utilities Memory
- *  Block address space.
- *  Input: regNum - register number + utility base address.  Example,
- *                  the base address of EPIC is 0x40000, the register
- *	            number is 0x40000+the address of the target register.
- *	            (See epic.h for register addresses).
- *         regVal - value to be written to the register.
- */
-
-void mpc824x_eummbar_write (unsigned int regNum, unsigned int regVal)
-{
-	*(volatile unsigned int *) (EUMBBAR_VAL + regNum) = PCISWAP (regVal);
-	return;
-}
-
-/* ------------------------------------------------------------------------- */

arch/powerpc/cpu/mpc824x/cpu_init.c

@@ -1,311 +0,0 @@
-/*
- * (C) Copyright 2000
- * Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <mpc824x.h>
-
-#ifndef CONFIG_SYS_BANK0_ROW
-#define CONFIG_SYS_BANK0_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK1_ROW
-#define CONFIG_SYS_BANK1_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK2_ROW
-#define CONFIG_SYS_BANK2_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK3_ROW
-#define CONFIG_SYS_BANK3_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK4_ROW
-#define CONFIG_SYS_BANK4_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK5_ROW
-#define CONFIG_SYS_BANK5_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK6_ROW
-#define CONFIG_SYS_BANK6_ROW 0
-#endif
-#ifndef CONFIG_SYS_BANK7_ROW
-#define CONFIG_SYS_BANK7_ROW 0
-#endif
-#ifndef CONFIG_SYS_DBUS_SIZE2
-#define CONFIG_SYS_DBUS_SIZE2 0
-#endif
-
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- */
-void
-cpu_init_f (void)
-{
-    register unsigned long val;
-    CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
-/*    CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
-
-#if defined(CONFIG_MUSENKI)
-/* Why is this here, you ask?  Try, just try setting 0x8000
- * in PCIACR with CONFIG_WRITE_HALFWORD()
- * this one was a stumper, and we are annoyed
- */
-
-#define M_CONFIG_WRITE_HALFWORD( addr, data ) \
-	__asm__ __volatile__("		\
-		stw  %2,0(%0)\n		\
-		sync\n			\
-		sth  %3,2(%1)\n		\
-		sync\n			\
-		"			\
-		: /* no output */	\
-		: "r" (CONFIG_ADDR), "r" (CONFIG_DATA),			\
-		"r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16))	\
-	);
-
-	M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
-#endif
-
-	CONFIG_WRITE_BYTE(PCLSR, 0x8);	/* set PCI cache line size */
-	CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
-	/*
-	* Note that although this bit is cleared after a hard reset, it
-	* must be explicitly set and then cleared by software during
-	* initialization in order to guarantee correct operation of the
-	* DLL and the SDRAM_CLK[0:3] signals (if they are used).
-	*/
-	CONFIG_READ_BYTE (AMBOR, val);
-	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
-	CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
-	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
-#ifdef CONFIG_MPC8245
-	/* silicon bug 28 MPC8245 */
-	CONFIG_READ_BYTE(AMBOR,val);
-	CONFIG_WRITE_BYTE(AMBOR,val|0x1);
-
-#if 0
-	/*
-	 * The following bug only affects older (XPC8245) processors.
-	 * DMA transfers initiated by external devices get corrupted due
-	 * to a hardware scheduling problem.
-	 *
-	 * The effect is:
-	 * when transferring X words, the first 32 words are transferred
-	 * OK, the next 3 x 32 words are 'old' data (from previous DMA)
-	 * while the rest of the X words is xferred fine.
-	 *
-	 * Disabling 3 of the 4 32 word hardware buffers solves the problem
-	 * with no significant performance loss.
-	 */
-
-	CONFIG_READ_BYTE(PCMBCR,val);
-	/* in order not to corrupt data which is being read over the PCI bus
-	* with the PPC as slave, we need to reduce the number of PCMRBs to 1,
-	* 4.11 in the  processor user manual
-	* */
-
-#if 1
-	CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
-#else
-	CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
-	CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
-	/* default, 4 PCMRBs are used */
-#endif
-#endif
-#endif
-
-	CONFIG_READ_WORD(PICR1, val);
-#if defined(CONFIG_MPC8240)
-	CONFIG_WRITE_WORD( PICR1,
-		(val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
-		       PIRC1_MSK | PICR1_PROC_TYPE_603E |
-		       PICR1_FLASH_WR_EN | PICR1_MCP_EN |
-		       PICR1_CF_DPARK | PICR1_EN_PCS |
-		       PICR1_CF_APARK );
-#elif defined(CONFIG_MPC8245)
-	CONFIG_WRITE_WORD( PICR1,
-		(val & (PICR1_RCS0)) |
-		       PICR1_PROC_TYPE_603E |
-		       PICR1_FLASH_WR_EN | PICR1_MCP_EN |
-		       PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
-		       PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-	CONFIG_READ_WORD(PICR2, val);
-	val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
-	val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
-	CONFIG_WRITE_WORD(PICR2, val);
-
-	CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
-#ifndef CONFIG_SYS_RAMBOOT
-	CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) |
-				 (CONFIG_SYS_BANK0_ROW) |
-				 (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
-				 (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
-				 (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
-				 (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
-				 (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
-				 (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
-				 (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
-				 (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
-#endif
-
-#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
-	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT |
-				 CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT |
-				 CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
-#else
-	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
-#endif
-
-#if defined(CONFIG_MPC8240)
-	CONFIG_WRITE_WORD(MCCR3,
-		(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
-		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) |
-		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT));
-#elif defined(CONFIG_MPC8245)
-	CONFIG_WRITE_WORD(MCCR3,
-		(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
-		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-/* this is gross.  We think these should all be the same, and various boards
- *  should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
- *  its not set, we define it to zero in this file
- */
-#if defined(CONFIG_CU824)
-	CONFIG_WRITE_WORD(MCCR4,
-	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
-	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
-	MCCR4_BIT21 |
-	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
-	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
-	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
-		  CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
-	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
-	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
-#elif defined(CONFIG_MPC8240)
-	CONFIG_WRITE_WORD(MCCR4,
-	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
-	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
-	MCCR4_BIT21 |
-	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
-	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
-	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
-		  (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
-	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
-#elif defined(CONFIG_MPC8245)
-	CONFIG_READ_WORD(MCCR1, val);
-	val &= MCCR1_DBUS_SIZE0;    /* test for 64-bit mem bus */
-
-	CONFIG_WRITE_WORD(MCCR4,
-		(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
-		(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
-		(CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) |
-		(CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) |
-		(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
-		((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
-		(CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
-		(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
-		      (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT)  |
-		(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
-		(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-	CONFIG_WRITE_WORD(MSAR1,
-		( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
-		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
-		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
-		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
-	CONFIG_WRITE_WORD(EMSAR1,
-		( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
-		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
-		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
-		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
-	CONFIG_WRITE_WORD(MSAR2,
-		( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
-		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
-		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
-		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
-	CONFIG_WRITE_WORD(EMSAR2,
-		( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
-		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
-		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
-		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
-	CONFIG_WRITE_WORD(MEAR1,
-		( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
-		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
-		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
-		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
-	CONFIG_WRITE_WORD(EMEAR1,
-		( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
-		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
-		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
-		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
-	CONFIG_WRITE_WORD(MEAR2,
-		( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
-		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
-		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
-		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
-	CONFIG_WRITE_WORD(EMEAR2,
-		( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
-		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
-		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
-		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
-
-	CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
-#ifdef CONFIG_SYS_DLL_MAX_DELAY
-	CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY);	/* needed to make DLL lock */
-#endif
-#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
-	CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL);
-#endif
-#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
-	CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD);	/* change memory input */
-#endif /* setup & hold time */
-
-	CONFIG_WRITE_BYTE(MBER,
-		 CONFIG_SYS_BANK0_ENABLE |
-		(CONFIG_SYS_BANK1_ENABLE << 1) |
-		(CONFIG_SYS_BANK2_ENABLE << 2) |
-		(CONFIG_SYS_BANK3_ENABLE << 3) |
-		(CONFIG_SYS_BANK4_ENABLE << 4) |
-		(CONFIG_SYS_BANK5_ENABLE << 5) |
-		(CONFIG_SYS_BANK6_ENABLE << 6) |
-		(CONFIG_SYS_BANK7_ENABLE << 7));
-
-#ifdef CONFIG_SYS_PGMAX
-	CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
-#endif
-
-	/* ! Wait 200us before initialize other registers */
-	/*FIXME: write a decent udelay wait */
-	__asm__ __volatile__(
-		" mtctr	%0 \n \
-		0: bdnz	 0b\n"
-		:
-		: "r" (0x10000));
-
-	CONFIG_READ_WORD(MCCR1, val);
-	CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
-	__asm__ __volatile__("eieio");
-}
-
-/*
- * initialize higher level parts of CPU like time base and timers
- */
-int cpu_init_r (void)
-{
-	return (0);
-}