Prepare v2016.07

Signed-off-by: Tom Rini <trini@konsulko.com>

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

arch/arc/config.mk

@@ -43,11 +43,11 @@ PLATFORM_CPPFLAGS += -marcem
 endif
 
 ifdef CONFIG_CPU_ARCHS34
-PLATFORM_CPPFLAGS += -marchs
+PLATFORM_CPPFLAGS += -mcpu=archs
 endif
 
 ifdef CONFIG_CPU_ARCHS38
-PLATFORM_CPPFLAGS += -marchs
+PLATFORM_CPPFLAGS += -mcpu=archs
 endif
 
 PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2

arch/arc/include/asm/global_data.h

@@ -7,9 +7,11 @@
 #ifndef	__ASM_ARC_GLOBAL_DATA_H
 #define __ASM_ARC_GLOBAL_DATA_H
 
+#ifndef __ASSEMBLY__
 /* Architecture-specific global data */
 struct arch_global_data {
 };
+#endif /* __ASSEMBLY__ */
 
 #include <asm-generic/global_data.h>
 

arch/arm/cpu/armv8/start.S

@@ -81,6 +81,14 @@ reset:
 	msr	cpacr_el1, x0			/* Enable FP/SIMD */
 0:
 
+	/* Enalbe SMPEN bit for coherency.
+	 * This register is not architectural but at the moment
+	 * this bit should be set for A53/A57/A72.
+	 */
+	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
+	orr     x0, x0, #0x40
+	msr     S3_1_c15_c2_1, x0
+
 	/* Apply ARM core specific erratas */
 	bl	apply_core_errata
 

arch/arm/dts/Makefile

@@ -234,7 +234,8 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
 dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-ga10h-v1.1.dtb \
 	sun8i-a33-q8-tablet.dtb \
-	sun8i-a33-sinlinx-sina33.dtb
+	sun8i-a33-sinlinx-sina33.dtb \
+	sun8i-r16-parrot.dtb
 dtb-$(CONFIG_MACH_SUN8I_A83T) += \
 	sun8i-a83t-allwinner-h8homlet-v2.dtb \
 	sun8i-a83t-cubietruck-plus.dtb \

arch/arm/dts/sun8i-r16-parrot.dts

@@ -0,0 +1,348 @@
+/*
+ * Copyright 2016 Quentin Schulz
+ *
+ * Quentin Schulz <quentin.schulz@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Allwinner R16 EVB (Parrot)";
+	compatible = "allwinner,parrot", "allwinner,sun8i-a33";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins_parrot>;
+
+		led1 {
+			label = "parrot:led1:usr";
+			gpio = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
+		};
+
+		led2 {
+			label = "parrot:led2:usr";
+			gpio = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
+		};
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
+	};
+
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "okay";
+
+	/* FIXME: An as-yet-unknown accelerometer is connected to this i2c bus. */
+};
+
+&lradc {
+	vref-supply = <&reg_aldo3>;
+	status = "okay";
+
+	button@0 {
+		label = "V+";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <190000>;
+	};
+
+	button@1 {
+		label = "V-";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <390000>;
+	};
+
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_parrot>;
+	vmmc-supply = <&reg_dcdc1>;
+	cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+	bus-width = <4>;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_parrot>;
+	vmmc-supply = <&reg_aldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&mmc2_8bit_pins {
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&pio {
+	mmc0_cd_pin_parrot: mmc0_cd_pin@0 {
+		allwinner,pins = "PD14";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	led_pins_parrot: led_pins@0 {
+		allwinner,pins = "PE16", "PE17";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	usb0_id_det: usb0_id_detect_pin@0 {
+		allwinner,pins = "PD10";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	usb1_vbus_pin_parrot: usb1_vbus_pin@0 {
+		allwinner,pins = "PD12";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&r_pio {
+	wifi_reset_pin_parrot: wifi_reset_pin@0 {
+		allwinner,pins = "PL6";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp22x: pmic@3a3 {
+		compatible = "x-powers,axp223";
+		reg = <0x3a3>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		drivevbus-supply = <&reg_vcc5v0>;
+		x-powers,drive-vbus-en;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2350000>;
+	regulator-max-microvolt = <2650000>;
+	regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+	/*
+	 * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered.
+	 * Remove next line once it is possible to sync two regulators.
+	 */
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi0";
+};
+
+&reg_dldo2 {
+	/*
+	 * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered.
+	 * Remove next line once it is possible to sync two regulators.
+	 */
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi1";
+};
+
+&reg_dldo3 {
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0-csi";
+};
+
+&reg_drivevbus {
+	regulator-name = "usb0-vbus";
+	status = "okay";
+};
+
+&reg_eldo1 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-1v2-hsic";
+};
+
+&reg_eldo2 {
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-dsp";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "eldo3";
+};
+
+&reg_usb1_vbus {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_vbus_pin_parrot>;
+	gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_det>;
+	usb0_vbus-supply = <&reg_drivevbus>;
+	usb0_id_det-gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10 */
+	usb0_vbus_power-supply = <&usb_power_supply>;
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+};

arch/arm/dts/tegra20-harmony.dts

@@ -1,5 +1,6 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
@@ -11,6 +12,9 @@
 	};
 
 	aliases {
+		rtc0 = "/i2c@7000d000/tps6586x@34";
+		rtc1 = "/rtc@7000e000";
+		serial0 = &uartd;
 		usb0 = "/usb@c5008000";
 		usb1 = "/usb@c5004000";
 		sdhci0 = "/sdhci@c8000600";
@@ -27,15 +31,295 @@
 			status = "okay";
 			rgb {
 				status = "okay";
-				nvidia,panel = <&lcd_panel>;
+
+				nvidia,panel = <&panel>;
+
+				display-timings {
+					timing@0 {
+						/* Seaboard has 1366x768 */
+						clock-frequency = <42430000>;
+						hactive = <1024>;
+						vactive = <600>;
+						hback-porch = <138>;
+						hfront-porch = <34>;
+						hsync-len = <136>;
+						vback-porch = <21>;
+						vfront-porch = <4>;
+						vsync-len = <4>;
+					};
+				};
+			};
+		};
+
+		hdmi@54280000 {
+			status = "okay";
+
+			hdmi-supply = <&vdd_5v0_hdmi>;
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pinmux@70000014 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+					"spia", "spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			dta {
+				nvidia,pins = "dta", "dtd";
+				nvidia,function = "sdio2";
+			};
+			dtb {
+				nvidia,pins = "dtb", "dtc", "dte";
+				nvidia,function = "rsvd1";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint", "pta";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uarta";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+					"ld3", "ld4", "ld5", "ld6", "ld7",
+					"ld8", "ld9", "ld10", "ld11", "ld12",
+					"ld13", "ld14", "ld15", "ld16", "ld17",
+					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
+					"lhs", "lm0", "lm1", "lpp", "lpw0",
+					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
+					"lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc", "spdi", "spdo", "uac";
+				nvidia,function = "rsvd2";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+					"cdev1", "cdev2", "dap1", "dtb", "gma",
+					"gmb", "gmc", "gmd", "gme", "gpu7",
+					"gpv", "i2cp", "pta", "rm", "slxa",
+					"slxk", "spia", "spib", "uac";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			};
+			conf_csus {
+				nvidia,pins = "csus", "spid", "spif";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+					"dtc", "dte", "dtf", "gpu", "sdio1",
+					"slxc", "slxd", "spdi", "spdo", "spig",
+					"uda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_ddc {
+				nvidia,pins = "ddc", "dta", "dtd", "kbca",
+					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+					"sdc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
+					"lvp0", "owc", "sdb";
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_irrx {
+				nvidia,pins = "irrx", "irtx", "sdd", "spic",
+					"spie", "spih", "uaa", "uab", "uad",
+					"uca", "ucb";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+					"lvs", "pmc";
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 			};
 		};
 	};
 
+	i2s@70002800 {
+		status = "okay";
+	};
+
 	serial@70006300 {
+		status = "okay";
 		clock-frequency = < 216000000 >;
 	};
 
+	pwm: pwm@7000a000 {
+		status = "okay";
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		wm8903: wm8903@1a {
+			compatible = "wlf,wm8903";
+			reg = <0x1a>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			micdet-cfg = <0>;
+			micdet-delay = <100>;
+			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+		};
+	};
+
 	nand-controller@70008000 {
 		nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
 		nvidia,width = <8>;
@@ -46,15 +330,319 @@
 		};
 	};
 
+	hdmi_ddc: i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: tps6586x@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				sys_reg: sys {
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				sm0 {
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				sm1 {
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: sm2 {
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				pci_clk_reg: ldo0 {
+					regulator-name = "vdd_ldo0,vddio_pex_clk";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				ldo1 {
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				ldo2 {
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				ldo3 {
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo4 {
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5 {
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo6 {
+					regulator-name = "vdd_ldo6,avdd_vdac";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				hdmi_vdd_reg: ldo7 {
+					regulator-name = "vdd_ldo7,avdd_hdmi";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: ldo8 {
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo9 {
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo_rtc {
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor@4c {
+			compatible = "adi,adt7461";
+			reg = <0x4c>;
+		};
+	};
+
+	kbc@7000e200 {
+		status = "okay";
+		nvidia,debounce-delay-ms = <2>;
+		nvidia,repeat-delay-ms = <160>;
+		nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+		nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
+				MATRIX_KEY(0x00, 0x03, KEY_S)
+				MATRIX_KEY(0x00, 0x04, KEY_A)
+				MATRIX_KEY(0x00, 0x05, KEY_Z)
+				MATRIX_KEY(0x00, 0x07, KEY_FN)
+				MATRIX_KEY(0x01, 0x07, KEY_MENU)
+				MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
+				MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
+				MATRIX_KEY(0x03, 0x00, KEY_5)
+				MATRIX_KEY(0x03, 0x01, KEY_4)
+				MATRIX_KEY(0x03, 0x02, KEY_R)
+				MATRIX_KEY(0x03, 0x03, KEY_E)
+				MATRIX_KEY(0x03, 0x04, KEY_F)
+				MATRIX_KEY(0x03, 0x05, KEY_D)
+				MATRIX_KEY(0x03, 0x06, KEY_X)
+				MATRIX_KEY(0x04, 0x00, KEY_7)
+				MATRIX_KEY(0x04, 0x01, KEY_6)
+				MATRIX_KEY(0x04, 0x02, KEY_T)
+				MATRIX_KEY(0x04, 0x03, KEY_H)
+				MATRIX_KEY(0x04, 0x04, KEY_G)
+				MATRIX_KEY(0x04, 0x05, KEY_V)
+				MATRIX_KEY(0x04, 0x06, KEY_C)
+				MATRIX_KEY(0x04, 0x07, KEY_SPACE)
+				MATRIX_KEY(0x05, 0x00, KEY_9)
+				MATRIX_KEY(0x05, 0x01, KEY_8)
+				MATRIX_KEY(0x05, 0x02, KEY_U)
+				MATRIX_KEY(0x05, 0x03, KEY_Y)
+				MATRIX_KEY(0x05, 0x04, KEY_J)
+				MATRIX_KEY(0x05, 0x05, KEY_N)
+				MATRIX_KEY(0x05, 0x06, KEY_B)
+				MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
+				MATRIX_KEY(0x06, 0x00, KEY_MINUS)
+				MATRIX_KEY(0x06, 0x01, KEY_0)
+				MATRIX_KEY(0x06, 0x02, KEY_O)
+				MATRIX_KEY(0x06, 0x03, KEY_I)
+				MATRIX_KEY(0x06, 0x04, KEY_L)
+				MATRIX_KEY(0x06, 0x05, KEY_K)
+				MATRIX_KEY(0x06, 0x06, KEY_COMMA)
+				MATRIX_KEY(0x06, 0x07, KEY_M)
+				MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
+				MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
+				MATRIX_KEY(0x07, 0x03, KEY_ENTER)
+				MATRIX_KEY(0x07, 0x07, KEY_MENU)
+				MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
+				MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
+				MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
+				MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
+				MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
+				MATRIX_KEY(0x0B, 0x01, KEY_P)
+				MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
+				MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
+				MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
+				MATRIX_KEY(0x0B, 0x05, KEY_DOT)
+				MATRIX_KEY(0x0C, 0x00, KEY_F10)
+				MATRIX_KEY(0x0C, 0x01, KEY_F9)
+				MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
+				MATRIX_KEY(0x0C, 0x03, KEY_3)
+				MATRIX_KEY(0x0C, 0x04, KEY_2)
+				MATRIX_KEY(0x0C, 0x05, KEY_UP)
+				MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
+				MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
+				MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
+				MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
+				MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
+				MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
+				MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
+				MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
+				MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
+				MATRIX_KEY(0x0E, 0x00, KEY_F11)
+				MATRIX_KEY(0x0E, 0x01, KEY_F12)
+				MATRIX_KEY(0x0E, 0x02, KEY_F8)
+				MATRIX_KEY(0x0E, 0x03, KEY_Q)
+				MATRIX_KEY(0x0E, 0x04, KEY_F4)
+				MATRIX_KEY(0x0E, 0x05, KEY_F3)
+				MATRIX_KEY(0x0E, 0x06, KEY_1)
+				MATRIX_KEY(0x0E, 0x07, KEY_F7)
+				MATRIX_KEY(0x0F, 0x00, KEY_ESC)
+				MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
+				MATRIX_KEY(0x0F, 0x02, KEY_F5)
+				MATRIX_KEY(0x0F, 0x03, KEY_TAB)
+				MATRIX_KEY(0x0F, 0x04, KEY_F1)
+				MATRIX_KEY(0x0F, 0x05, KEY_F2)
+				MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
+				MATRIX_KEY(0x0F, 0x07, KEY_F6)
+				MATRIX_KEY(0x14, 0x00, KEY_KP7)
+				MATRIX_KEY(0x15, 0x00, KEY_KP9)
+				MATRIX_KEY(0x15, 0x01, KEY_KP8)
+				MATRIX_KEY(0x15, 0x02, KEY_KP4)
+				MATRIX_KEY(0x15, 0x04, KEY_KP1)
+				MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
+				MATRIX_KEY(0x16, 0x02, KEY_KP6)
+				MATRIX_KEY(0x16, 0x03, KEY_KP5)
+				MATRIX_KEY(0x16, 0x04, KEY_KP3)
+				MATRIX_KEY(0x16, 0x05, KEY_KP2)
+				MATRIX_KEY(0x16, 0x07, KEY_KP0)
+				MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
+				MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
+				MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
+				MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
+				MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
+				MATRIX_KEY(0x1D, 0x03, KEY_HOME)
+				MATRIX_KEY(0x1D, 0x04, KEY_END)
+				MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
+				MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
+				MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
+				MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
+				MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
+				MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
+				MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
+	};
+
+	pmc@7000e400 {
+		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <5000>;
+		nvidia,cpu-pwr-off-time = <5000>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <3875>;
+		nvidia,sys-clock-req-active-high;
+	};
+
+	pcie-controller@80003000 {
+		status = "okay";
+
+		avdd-pex-supply = <&pci_vdd_reg>;
+		vdd-pex-supply = <&pci_vdd_reg>;
+		avdd-pex-pll-supply = <&pci_vdd_reg>;
+		avdd-plle-supply = <&pci_vdd_reg>;
+		vddio-pex-clk-supply = <&pci_clk_reg>;
+
+		pci@1,0 {
+			status = "okay";
+		};
+
+		pci@2,0 {
+			status = "okay";
+		};
+	};
+
+	usb@c5000000 {
+		status = "okay";
+	};
+
+	usb-phy@c5000000 {
+		status = "okay";
+	};
+
 	usb@c5004000 {
-		statuc = "okay";
+		status = "okay";
 		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
 	};
 
+	usb-phy@c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
+	};
+
 	usb@c5008000 {
 		status = "okay";
 	};
 
+	usb-phy@c5008000 {
+		status = "okay";
+	};
+
 	sdhci@c8000200 {
 		status = "okay";
 		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -71,6 +659,17 @@
 		bus-width = <8>;
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+
+		enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+		power-supply = <&vdd_bl_reg>;
+		pwms = <&pwm 0 5000000>;
+
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+	};
+
 	clocks {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -84,32 +683,130 @@
 		};
 	};
 
-	pwm: pwm@7000a000 {
-		status = "okay";
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			gpio-key,wakeup;
+		};
 	};
 
-	lcd_panel: panel {
-		clock = <42430000>;
-		xres = <1024>;
-		yres = <600>;
-		left-margin = <138>;
-		right-margin = <34>;
-		hsync-len = <136>;
-		lower-margin = <4>;
-		upper-margin = <21>;
-		vsync-len = <4>;
-		hsync-active-high;
-		vsyncx-active-high;
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 0 0>;
-		nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,panel-timings = <0 0 200 0 0>;
+	panel: panel {
+		compatible = "auo,b101aw03", "simple-panel";
+
+		power-supply = <&vdd_pnl_reg>;
+		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+
+		backlight = <&backlight>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vdd_1v5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "vdd_1v2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		pci_vdd_reg: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "vdd_1v05";
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1050000>;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_pnl_reg: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "vdd_pnl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_bl_reg: regulator@5 {
+			compatible = "regulator-fixed";
+			reg = <5>;
+			regulator-name = "vdd_bl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_5v0_hdmi: regulator@6 {
+			compatible = "regulator-fixed";
+			reg = <6>;
+			regulator-name = "VDDIO_HDMI";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_5v0_reg>;
+		};
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-wm8903-harmony",
+			     "nvidia,tegra-audio-wm8903";
+		nvidia,model = "NVIDIA Tegra Harmony";
+
+		nvidia,audio-routing =
+			"Headphone Jack", "HPOUTR",
+			"Headphone Jack", "HPOUTL",
+			"Int Spk", "ROP",
+			"Int Spk", "RON",
+			"Int Spk", "LOP",
+			"Int Spk", "LON",
+			"Mic Jack", "MICBIAS",
+			"IN1L", "Mic Jack";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&wm8903>;
+
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+			GPIO_ACTIVE_HIGH>;
+
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
+		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };

arch/arm/dts/tegra20-ventana.dts

@@ -1,5 +1,6 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
@@ -11,6 +12,9 @@
 	};
 
 	aliases {
+		rtc0 = "/i2c@7000d000/tps6586x@34";
+		rtc1 = "/rtc@7000e000";
+		serial0 = &uartd;
 		usb0 = "/usb@c5008000";
 		sdhci0 = "/sdhci@c8000600";
 		sdhci1 = "/sdhci@c8000400";
@@ -26,19 +30,557 @@
 			status = "okay";
 			rgb {
 				status = "okay";
-				nvidia,panel = <&lcd_panel>;
+
+				nvidia,panel = <&panel>;
+
+				display-timings {
+					timing@0 {
+						/* Seaboard has 1366x768 */
+						clock-frequency = <70600000>;
+						hactive = <1366>;
+						vactive = <768>;
+						hback-porch = <58>;
+						hfront-porch = <58>;
+						hsync-len = <58>;
+						vback-porch = <4>;
+						vfront-porch = <4>;
+						vsync-len = <4>;
+						hsync-active = <1>;
+					};
+				};
+			};
+		};
+
+		hdmi@54280000 {
+			status = "okay";
+
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pinmux@70000014 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "spia",
+					"spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp", "lm1";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+				nvidia,function = "vi";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gmd {
+				nvidia,pins = "gmd";
+				nvidia,function = "sflash";
+			};
+			gpu {
+				nvidia,pins = "gpu";
+				nvidia,function = "pwm";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uartb";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+					"lsdi", "lvp0";
+				nvidia,function = "rsvd4";
+			};
+			ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lpp", "lpw0",
+					"lpw2", "lsc0", "lsc1", "lsck", "lsda",
+					"lspi", "lvp1", "lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc", "spdi", "spdo", "uac";
+				nvidia,function = "rsvd2";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd", "slxc";
+				nvidia,function = "sdio3";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxd {
+				nvidia,pins = "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd",
+					"cdev1", "cdev2", "dap1", "dap2",
+					"dap4", "ddc", "dtf", "gma", "gmc",
+					"gme", "gpu", "gpu7", "i2cp", "irrx",
+					"irtx", "pta", "rm", "sdc", "sdd",
+					"slxc", "slxd", "slxk", "spdi", "spdo",
+					"uac", "uad", "uca", "ucb", "uda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_ate {
+				nvidia,pins = "ate", "csus", "dap3", "gmd",
+					"gpv", "owc", "spia", "spib", "spic",
+					"spid", "spie", "spig";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "gmb", "slxa", "spih";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_dte {
+				nvidia,pins = "dte", "spif";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsck", "lsda", "lsdi", "lvp0";
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf", "sdio1", "uaa", "uab";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
+					"lvp1", "lvs", "pmc", "sdb";
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+			};
+			drive_sdio1 {
+				nvidia,pins = "drive_sdio1";
+				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+				nvidia,pull-down-strength = <31>;
+				nvidia,pull-up-strength = <31>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+			};
+		};
+
+		state_i2cmux_ddc: pinmux_i2cmux_ddc {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+			};
+		};
+
+		state_i2cmux_pta: pinmux_i2cmux_pta {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "i2c2";
+			};
+		};
+
+		state_i2cmux_idle: pinmux_i2cmux_idle {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
 			};
 		};
 	};
 
+	i2s@70002800 {
+		status = "okay";
+	};
+
 	serial@70006300 {
-		clock-frequency = < 216000000 >;
+		status = "okay";
+		clock-frequency = < 216000000 >;	};
+
+	pwm: pwm@7000a000 {
+		status = "okay";
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		wm8903: wm8903@1a {
+			compatible = "wlf,wm8903";
+			reg = <0x1a>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			micdet-cfg = <0>;
+			micdet-delay = <100>;
+			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+		};
+
+		/* ALS and proximity sensor */
+		isl29018@44 {
+			compatible = "isil,isl29018";
+			reg = <0x44>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2cmux {
+		compatible = "i2c-mux-pinctrl";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c-parent = <&{/i2c@7000c400}>;
+
+		pinctrl-names = "ddc", "pta", "idle";
+		pinctrl-0 = <&state_i2cmux_ddc>;
+		pinctrl-1 = <&state_i2cmux_pta>;
+		pinctrl-2 = <&state_i2cmux_idle>;
+
+		hdmi_ddc: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		lvds_ddc: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: tps6586x@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				sys_reg: sys {
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				sm0 {
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				sm1 {
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: sm2 {
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				ldo1 {
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				ldo2 {
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				ldo3 {
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo4 {
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5 {
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo6 {
+					regulator-name = "vdd_ldo6,avdd_vdac";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				hdmi_vdd_reg: ldo7 {
+					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: ldo8 {
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo9 {
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo_rtc {
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor@4c {
+			compatible = "onnn,nct1008";
+			reg = <0x4c>;
+		};
+	};
+
+	pmc@7000e400 {
+		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <2000>;
+		nvidia,cpu-pwr-off-time = <100>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <458>;
+		nvidia,sys-clock-req-active-high;
+	};
+
+	usb@c5000000 {
+		status = "okay";
+	};
+
+	usb-phy@c5000000 {
+		status = "okay";
+	};
+
+	usb@c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
+	};
+
+	usb-phy@c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb@c5008000 {
 		status = "okay";
 	};
 
+	usb-phy@c5008000 {
+		status = "okay";
+	};
+
+	sdhci@c8000000 {
+		status = "okay";
+		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+		bus-width = <4>;
+		keep-power-in-suspend;
+	};
+
 	sdhci@c8000400 {
 		status = "okay";
 		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -50,6 +592,18 @@
 	sdhci@c8000600 {
 		status = "okay";
 		bus-width = <8>;
+		non-removable;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+
+		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+		power-supply = <&vdd_bl_reg>;
+		pwms = <&pwm 2 5000000>;
+
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
 	};
 
 	clocks {
@@ -65,32 +619,109 @@
 		};
 	};
 
-	pwm: pwm@7000a000 {
-		status = "okay";
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			gpio-key,wakeup;
+		};
 	};
 
-	lcd_panel: panel {
-		clock = <72072000>;
-		xres = <1366>;
-		yres = <768>;
-		left-margin = <58>;
-		right-margin = <58>;
-		hsync-len = <58>;
-		lower-margin = <4>;
-		upper-margin = <4>;
-		vsync-len = <4>;
-		hsync-active-high;
-		vsync-active-high;
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 2 0>;
-		nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,panel-timings = <0 0 200 0 0>;
+	panel: panel {
+		compatible = "chunghwa,claa101wa01a", "simple-panel";
+
+		power-supply = <&vdd_pnl_reg>;
+		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+
+		backlight = <&backlight>;
+		ddc-i2c-bus = <&lvds_ddc>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vdd_1v5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "vdd_1v2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_pnl_reg: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "vdd_pnl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_bl_reg: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "vdd_bl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-wm8903-ventana",
+			     "nvidia,tegra-audio-wm8903";
+		nvidia,model = "NVIDIA Tegra Ventana";
+
+		nvidia,audio-routing =
+			"Headphone Jack", "HPOUTR",
+			"Headphone Jack", "HPOUTL",
+			"Int Spk", "ROP",
+			"Int Spk", "RON",
+			"Int Spk", "LOP",
+			"Int Spk", "LON",
+			"Mic Jack", "MICBIAS",
+			"IN1L", "Mic Jack";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&wm8903>;
+
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+			GPIO_ACTIVE_HIGH>;
+
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
+		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };

arch/arm/include/asm/arch-sunxi/spl.h

@@ -20,6 +20,8 @@
 
 /* The low 8-bits of the 'boot_media' field in the SPL header */
 #define SUNXI_BOOTED_FROM_MMC0	0
+#define SUNXI_BOOTED_FROM_NAND	1
+#define SUNXI_BOOTED_FROM_MMC2	2
 #define SUNXI_BOOTED_FROM_SPI	3
 
 /* boot head definition from sun4i boot code */

arch/arm/include/asm/setjmp.h

@@ -43,6 +43,7 @@ static inline int setjmp(jmp_buf jmp)
 #else
 	asm volatile(
 #ifdef CONFIG_SYS_THUMB_BUILD
+		".align 2\n"
 		"adr r0, jmp_target\n"
 		"add r0, r0, $1\n"
 #else
@@ -52,7 +53,8 @@ static inline int setjmp(jmp_buf jmp)
 		"mov r2, sp\n"
 		"stm r1!, {r0, r2, r4, r5, r6, r7}\n"
 		"b 2f\n"
-		"jmp_target: "
+		".align 2\n"
+		"jmp_target: \n"
 		"mov %0, #1\n"
 		"2:\n"
 		: "+l" (r)

arch/powerpc/cpu/mpc85xx/Makefile

@@ -26,7 +26,9 @@ else
 
 obj-$(CONFIG_MP)	+= release.o
 
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
+endif
 obj-$(CONFIG_CPM2)	+= commproc.o
 
 obj-$(CONFIG_CPM2)	+= ether_fcc.o

board/sunxi/MAINTAINERS

@@ -202,6 +202,11 @@ M:	Siarhei Siamashka <siarhei.siamashka@gmail.com>
 S:	Maintained
 F:	configs/MSI_Primo81_defconfig
 
+R16 EVB PARROT BOARD
+M:	Quentin Schulz <quentin.schulz@free-electrons.com>
+S:	Maintained
+F:	configs/parrot_r16_defconfig
+
 SINLINX SINA31s BOARD
 M:	Chen-Yu Tsai <wens@csie.org>
 S:	Maintained

board/sunxi/README.pine64

@@ -0,0 +1,98 @@
+Pine64 board README
+====================
+
+The Pine64(+) is a single board computer equipped with an AArch64 capable ARMv8
+compliant Allwinner A64 SoC.
+This chip has ARM Cortex A-53 cores and thus can run both in AArch32
+(compatible to 32-bit ARMv7) and AArch64 modes. Upon reset the SoC starts
+in AArch32 mode and executes 32-bit code from the Boot ROM (BROM).
+This has some implications on U-Boot.
+
+Quick start
+============
+- Get hold of a boot0.img file (see below for more details).
+- Get the boot0img tool source from the tools directory in [1] and compile
+  that on your host.
+- Build U-Boot:
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make pine64_plus_defconfig
+$ make
+- You also need a compiled ARM Trusted Firmware (ATF) binary. Checkout the
+  "allwinner" branch from the github repository [2] and build it:
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make PLAT=sun50iw1p1 DEBUG=1 bl31
+  The resulting binary is build/sun50iw1p1/debug/bl31.bin.
+
+Now put an empty (or disposable) micro SD card in your card reader and learn
+its device file name, replacing /dev/sd<x> below with the result (that could
+be /dev/mmcblk<x> as well):
+
+$ ./boot0img --device /dev/sd<x> -e -u u-boot.bin -B boot0.img \
+	-d trampoline64:0x44000 -s bl31.bin -a 0x44008 -p 100
+(either copying the respective files to the working directory or specifying
+the paths directly)
+
+This will create a new partition table (with a 100 MB FAT boot partition),
+copies boot0.img, ATF and U-Boot to the proper locations on the SD card and
+will fill in the magic Allwinner header to be recognized by boot0.
+Prefix the above call with "sudo" if you don't have write access to the
+uSD card. You can also use "-o output.img" instead of "--device /dev/sd<x>"
+to create an image file and "dd" that to the uSD card.
+Omitting the "-p" option will skip the partition table.
+
+Now put this uSD card in the board and power it on. You should be greeted by
+the U-Boot prompt.
+
+
+Main U-Boot
+============
+The main U-Boot proper is a real 64-bit ARMv8 port and runs entirely in the
+64-bit AArch64 mode. It can load any AArch64 code, EFI applications or arm64
+Linux kernel images (often named "Image") using the booti command.
+Launching 32-bit code and kernels is technically possible, though not without
+drawbacks (or hacks to avoid them) and currently not implemented.
+
+SPL support
+============
+The main task of the SPL support is to bring up the DRAM controller and make
+DRAM actually accessible. At the moment there is no documentation or source
+code available which would do this.
+There are currently two ways to overcome this situation: using a tainted 32-bit
+SPL (involving some hacks and resulting in a non-redistributable binary, thus
+not described here) or using the Allwinner boot0 blob.
+
+boot0 method
+-------------
+boot0 is Allwiner's secondary program loader and it can be used as some kind
+of SPL replacement to get U-Boot up and running.
+The binary is a 32 KByte blob and contained on every Pine64 image distributed
+so far. It can be easily extracted from a micro SD card or an image file:
+# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4
+where /dev/sd<x> is the device name of the uSD card or the name of the image
+file. Apparently Allwinner allows re-distribution of this proprietary code
+as-is.
+For the time being this boot0 blob is the only redistributable way of making
+U-Boot work on the Pine64. Beside loading the various parts of the (original)
+firmware it also switches the core into AArch64 mode.
+The original boot0 code looks for U-Boot at a certain place on an uSD card
+(at 19096 KB), also it expects a header with magic bytes and a checksum.
+There is a tool called boot0img[1] which takes a boot0.bin image and a compiled
+U-Boot binary (plus other binaries) and will populate that header accordingly.
+To make space for the magic header, the pine64_plus_defconfig will make sure
+there is sufficient space at the beginning of the U-Boot binary.
+boot0img will also take care of putting the different binaries at the right
+places on the uSD card and works around unused, but mandatory parts by using
+trampoline code. See the output of "boot0img -h" for more information.
+boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead
+fetching it from just behind the boot0 binary (-B option).
+
+FEL boot
+=========
+FEL is the name of the Allwinner defined USB boot protocol built-in the
+mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely
+by using the USB-OTG interface and a host port on another computer.
+Since FEL boot does not work with boot0, it requires the libdram hack, which
+is not described here.
+
+[1] https://github.com/apritzel/pine64/
+[2] https://github.com/apritzel/arm-trusted-firmware.git

board/sunxi/board.c

@@ -529,7 +529,7 @@ void sunxi_board_init(void)
 #endif
 	printf("DRAM:");
 	ramsize = sunxi_dram_init();
-	printf(" %lu MiB\n", ramsize >> 20);
+	printf(" %d MiB\n", (int)(ramsize >> 20));
 	if (!ramsize)
 		hang();
 

cmd/usb.c

@@ -438,9 +438,11 @@ static void usb_show_subtree(struct usb_device *dev)
 	usb_show_tree_graph(dev, &preamble[0]);
 }
 
-void usb_show_tree(void)
-{
 #ifdef CONFIG_DM_USB
+typedef void (*usb_dev_func_t)(struct usb_device *udev);
+
+static void usb_for_each_root_dev(usb_dev_func_t func)
+{
 	struct udevice *bus;
 
 	for (uclass_find_first_device(UCLASS_USB, &bus);
@@ -455,9 +457,16 @@ void usb_show_tree(void)
 		device_find_first_child(bus, &dev);
 		if (dev && device_active(dev)) {
 			udev = dev_get_parent_priv(dev);
-			usb_show_subtree(udev);
+			func(udev);
 		}
 	}
+}
+#endif
+
+void usb_show_tree(void)
+{
+#ifdef CONFIG_DM_USB
+	usb_for_each_root_dev(usb_show_subtree);
 #else
 	struct usb_device *udev;
 	int i;
@@ -584,39 +593,20 @@ static void do_usb_start(void)
 }
 
 #ifdef CONFIG_DM_USB
-static void show_info(struct udevice *dev)
+static void usb_show_info(struct usb_device *udev)
 {
 	struct udevice *child;
-	struct usb_device *udev;
 
-	udev = dev_get_parent_priv(dev);
 	usb_display_desc(udev);
 	usb_display_config(udev);
-	for (device_find_first_child(dev, &child);
+	for (device_find_first_child(udev->dev, &child);
 	     child;
 	     device_find_next_child(&child)) {
-		if (device_active(child))
-			show_info(child);
-	}
-}
-
-static int usb_device_info(void)
-{
-	struct udevice *bus;
-
-	for (uclass_first_device(UCLASS_USB, &bus);
-	     bus;
-	     uclass_next_device(&bus)) {
-		struct udevice *hub;
-
-		device_find_first_child(bus, &hub);
-		if (device_get_uclass_id(hub) == UCLASS_USB_HUB &&
-		    device_active(hub)) {
-			show_info(hub);
+		if (device_active(child)) {
+			udev = dev_get_parent_priv(child);
+			usb_show_info(udev);
 		}
 	}
-
-	return 0;
 }
 #endif
 
@@ -672,7 +662,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (strncmp(argv[1], "inf", 3) == 0) {
 		if (argc == 2) {
 #ifdef CONFIG_DM_USB
-			usb_device_info();
+			usb_for_each_root_dev(usb_show_info);
 #else
 			int d;
 			for (d = 0; d < USB_MAX_DEVICE; d++) {

configs/colibri_t20_defconfig

@@ -23,6 +23,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -30,6 +32,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

configs/harmony_defconfig

@@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

configs/medcom-wide_defconfig

@@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

configs/parrot_r16_defconfig

@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_MACH_SUN8I=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+
+CONFIG_CMD_MMC=y
+CONFIG_MMC0_CD_PIN="PD14"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_MMC2_PINS="PC"
+
+CONFIG_DRAM_CLK=600
+CONFIG_DRAM_ZQ=15291
+CONFIG_ODT_EN=y
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN="PD12"
+
+CONFIG_AXP_GPIO=y
+CONFIG_USB0_ID_DET="PD10"
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010

configs/paz00_defconfig

@@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

configs/seaboard_defconfig

@@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

configs/tec_defconfig

@@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

configs/ventana_defconfig

@@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

doc/git-mailrc

@@ -76,7 +76,7 @@ alias tegra2         tegra
 alias ti             uboot, trini
 alias uniphier       uboot, masahiro
 alias zynq           uboot, monstr
-
+alias rockchip       uboot, sjg, Lin huang <hl@rock-chips.com>
 alias avr32          uboot, abiessmann
 
 alias bfin           uboot, vapier, sonic

drivers/mmc/msm_sdhci.c

@@ -136,7 +136,12 @@ static int msm_sdc_probe(struct udevice *dev)
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 
 	/* automatically detect max and min speed */
-	return add_sdhci(host, 0, 0);
+	ret =  add_sdhci(host, 0, 0);
+	if (ret)
+		return ret;
+	host->mmc->dev = dev;
+
+	return 0;
 }
 
 static int msm_sdc_remove(struct udevice *dev)

drivers/net/designware.c

@@ -80,7 +80,7 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 	return ret;
 }
 
-#if CONFIG_DM_ETH
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
 static int dw_mdio_reset(struct mii_dev *bus)
 {
 	struct udevice *dev = bus->priv;
@@ -126,7 +126,7 @@ static int dw_mdio_init(const char *name, void *priv)
 	bus->read = dw_mdio_read;
 	bus->write = dw_mdio_write;
 	snprintf(bus->name, sizeof(bus->name), "%s", name);
-#ifdef CONFIG_DM_ETH
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
 	bus->reset = dw_mdio_reset;
 #endif
 
@@ -690,11 +690,15 @@ static const struct eth_ops designware_eth_ops = {
 static int designware_eth_ofdata_to_platdata(struct udevice *dev)
 {
 	struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+#ifdef CONFIG_DM_GPIO
 	struct dw_eth_dev *priv = dev_get_priv(dev);
+#endif
 	struct eth_pdata *pdata = &dw_pdata->eth_pdata;
 	const char *phy_mode;
 	const fdt32_t *cell;
+#ifdef CONFIG_DM_GPIO
 	int reset_flags = GPIOD_IS_OUT;
+#endif
 	int ret = 0;
 
 	pdata->iobase = dev_get_addr(dev);
@@ -712,6 +716,7 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev)
 	if (cell)
 		pdata->max_speed = fdt32_to_cpu(*cell);
 
+#ifdef CONFIG_DM_GPIO
 	if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
 			    "snps,reset-active-low"))
 		reset_flags |= GPIOD_ACTIVE_LOW;
@@ -724,6 +729,7 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev)
 	} else if (ret == -ENOENT) {
 		ret = 0;
 	}
+#endif
 
 	return ret;
 }

drivers/net/designware.h

@@ -8,7 +8,9 @@
 #ifndef _DW_ETH_H
 #define _DW_ETH_H
 
-#include <asm/gpio.h>
+#ifdef CONFIG_DM_GPIO
+#include <asm-generic/gpio.h>
+#endif
 
 #define CONFIG_TX_DESCR_NUM	16
 #define CONFIG_RX_DESCR_NUM	16
@@ -234,7 +236,10 @@ struct dw_eth_dev {
 #ifndef CONFIG_DM_ETH
 	struct eth_device *dev;
 #endif
+#ifdef CONFIG_DM_GPIO
 	struct gpio_desc reset_gpio;
+#endif
+
 	struct phy_device *phydev;
 	struct mii_dev *bus;
 };

drivers/net/phy/aquantia.c

@@ -147,6 +147,32 @@ struct phy_driver aqr105_driver = {
 	.shutdown = &gen10g_shutdown,
 };
 
+struct phy_driver aqr106_driver = {
+	.name = "Aquantia AQR106",
+	.uid = 0x3a1b4d0,
+	.mask = 0xfffffff0,
+	.features = PHY_10G_FEATURES,
+	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+			MDIO_MMD_PHYXS | MDIO_MMD_AN |
+			MDIO_MMD_VEND1),
+	.config = &aquantia_config,
+	.startup = &aquantia_startup,
+	.shutdown = &gen10g_shutdown,
+};
+
+struct phy_driver aqr107_driver = {
+	.name = "Aquantia AQR107",
+	.uid = 0x3a1b4e0,
+	.mask = 0xfffffff0,
+	.features = PHY_10G_FEATURES,
+	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+			MDIO_MMD_PHYXS | MDIO_MMD_AN |
+			MDIO_MMD_VEND1),
+	.config = &aquantia_config,
+	.startup = &aquantia_startup,
+	.shutdown = &gen10g_shutdown,
+};
+
 struct phy_driver aqr405_driver = {
 	.name = "Aquantia AQR405",
 	.uid = 0x3a1b4b2,
@@ -165,6 +191,8 @@ int phy_aquantia_init(void)
 	phy_register(&aq1202_driver);
 	phy_register(&aq2104_driver);
 	phy_register(&aqr105_driver);
+	phy_register(&aqr106_driver);
+	phy_register(&aqr107_driver);
 	phy_register(&aqr405_driver);
 
 	return 0;

drivers/net/rtl8169.c

@@ -666,12 +666,12 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
 		puts("tx timeout/error\n");
 		printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 #endif
-		ret = 0;
+		ret = -ETIMEDOUT;
 	} else {
 #ifdef DEBUG_RTL8169_TX
 		puts("tx done\n");
 #endif
-		ret = length;
+		ret = 0;
 	}
 	/* Delay to make net console (nc) work properly */
 	udelay(20);

drivers/pci/pci_tegra.c

@@ -154,15 +154,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PADS_REFCLK_CFG_PREDI_SHIFT		8  /* 11:8 */
 #define PADS_REFCLK_CFG_DRVI_SHIFT		12 /* 15:12 */
 
-/* Default value provided by HW engineering is 0xfa5c */
-#define PADS_REFCLK_CFG_VALUE \
-	( \
-		(0x17 << PADS_REFCLK_CFG_TERM_SHIFT)   | \
-		(0    << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
-		(0xa  << PADS_REFCLK_CFG_PREDI_SHIFT)  | \
-		(0xf  << PADS_REFCLK_CFG_DRVI_SHIFT)     \
-	)
-
 #define RP_VEND_XP	0x00000F00
 #define  RP_VEND_XP_DL_UP	(1 << 30)
 
@@ -198,6 +189,8 @@ struct tegra_pcie_soc {
 	unsigned int num_ports;
 	unsigned long pads_pll_ctl;
 	unsigned long tx_ref_sel;
+	u32 pads_refclk_cfg0;
+	u32 pads_refclk_cfg1;
 	bool has_pex_clkreq_en;
 	bool has_pex_bias_ctrl;
 	bool has_cml_clk;
@@ -627,13 +620,6 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
 	value |= PADS_PLL_CTL_RST_B4SM;
 	pads_writel(pcie, value, soc->pads_pll_ctl);
 
-	/* configure the reference clock driver */
-	value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
-	pads_writel(pcie, value, PADS_REFCLK_CFG0);
-
-	if (soc->num_ports > 2)
-		pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
-
 	/* wait for the PLL to lock */
 	err = tegra_pcie_pll_wait(pcie, 500);
 	if (err < 0) {
@@ -827,20 +813,21 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
 
 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
 {
-	const struct tegra_pcie_soc *soc = port->pcie->soc;
+	struct tegra_pcie *pcie = port->pcie;
+	const struct tegra_pcie_soc *soc = pcie->soc;
 	unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
 	unsigned long value;
 
 	/* enable reference clock */
-	value = afi_readl(port->pcie, ctrl);
+	value = afi_readl(pcie, ctrl);
 	value |= AFI_PEX_CTRL_REFCLK_EN;
 
-	if (port->pcie->soc->has_pex_clkreq_en)
+	if (pcie->soc->has_pex_clkreq_en)
 		value |= AFI_PEX_CTRL_CLKREQ_EN;
 
 	value |= AFI_PEX_CTRL_OVERRIDE_EN;
 
-	afi_writel(port->pcie, value, ctrl);
+	afi_writel(pcie, value, ctrl);
 
 	tegra_pcie_port_reset(port);
 
@@ -849,6 +836,11 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
 		value |= RP_VEND_CTL2_PCA_ENABLE;
 		rp_writel(port, value, RP_VEND_CTL2);
 	}
+
+	/* configure the reference clock driver */
+	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
+	if (soc->num_ports > 2)
+		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
 }
 
 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
@@ -943,6 +935,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
 		.num_ports = 2,
 		.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
 		.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
+		.pads_refclk_cfg0 = 0xfa5cfa5c,
 		.has_pex_clkreq_en = false,
 		.has_pex_bias_ctrl = false,
 		.has_cml_clk = false,
@@ -952,6 +945,8 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
 		.num_ports = 3,
 		.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
 		.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+		.pads_refclk_cfg0 = 0xfa5cfa5c,
+		.pads_refclk_cfg1 = 0xfa5cfa5c,
 		.has_pex_clkreq_en = true,
 		.has_pex_bias_ctrl = true,
 		.has_cml_clk = true,
@@ -961,6 +956,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
 		.num_ports = 2,
 		.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
 		.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+		.pads_refclk_cfg0 = 0x44ac44ac,
 		.has_pex_clkreq_en = true,
 		.has_pex_bias_ctrl = true,
 		.has_cml_clk = true,
@@ -970,6 +966,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
 		.num_ports = 2,
 		.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
 		.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+		.pads_refclk_cfg0 = 0x90b890b8,
 		.has_pex_clkreq_en = true,
 		.has_pex_bias_ctrl = true,
 		.has_cml_clk = true,

drivers/usb/host/ehci-fsl.c

@@ -65,7 +65,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 		mdelay(5);
 	}
 	memset(current_usb_controller, '\0', 5);
-	snprintf(current_usb_controller, 4, "usb%d", index+1);
+	snprintf(current_usb_controller, sizeof(current_usb_controller),
+		 "usb%d", index+1);
 
 	switch (index) {
 	case 0:

drivers/usb/host/ehci-mx6.c

@@ -194,8 +194,9 @@ struct usbnc_regs {
 	u32 reserve1[10];
 	u32 phy_cfg1;
 	u32 phy_cfg2;
+	u32 reserve2;
 	u32 phy_status;
-	u32 reserve2[4];
+	u32 reserve3[4];
 	u32 adp_cfg1;
 	u32 adp_cfg2;
 	u32 adp_status;
@@ -207,8 +208,11 @@ static void usb_power_config(int index)
 			(0x10000 * index) + USBNC_OFFSET);
 	void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
 
-	/* Enable usb_otg_id detection */
-	setbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
+	/*
+	 * Clear the ACAENB to enable usb_otg_id detection,
+	 * otherwise it is the ACA detection enabled.
+	 */
+	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
 }
 
 int usb_phy_mode(int port)

drivers/video/rockchip/rk_hdmi.c

@@ -666,7 +666,7 @@ static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs)
 		if (hdmi_get_plug_in_status(regs))
 			return 0;
 		udelay(100);
-	} while (get_timer(start) < 30000);
+	} while (get_timer(start) < 300);
 
 	return -1;
 }

drivers/video/tegra.c

@@ -6,6 +6,7 @@
 #include <common.h>
 #include <dm.h>
 #include <fdtdec.h>
+#include <panel.h>
 #include <pwm.h>
 #include <video.h>
 #include <asm/system.h>
@@ -21,70 +22,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* These are the stages we go throuh in enabling the LCD */
-enum stage_t {
-	STAGE_START,
-	STAGE_PANEL_VDD,
-	STAGE_LVDS,
-	STAGE_BACKLIGHT_VDD,
-	STAGE_PWM,
-	STAGE_BACKLIGHT_EN,
-	STAGE_DONE,
-};
-
-#define FDT_LCD_TIMINGS	4
-
-enum {
-	FDT_LCD_TIMING_REF_TO_SYNC,
-	FDT_LCD_TIMING_SYNC_WIDTH,
-	FDT_LCD_TIMING_BACK_PORCH,
-	FDT_LCD_TIMING_FRONT_PORCH,
-
-	FDT_LCD_TIMING_COUNT,
-};
-
-enum lcd_cache_t {
-	FDT_LCD_CACHE_OFF		= 0,
-	FDT_LCD_CACHE_WRITE_THROUGH	= 1 << 0,
-	FDT_LCD_CACHE_WRITE_BACK	= 1 << 1,
-	FDT_LCD_CACHE_FLUSH		= 1 << 2,
-	FDT_LCD_CACHE_WRITE_BACK_FLUSH	= FDT_LCD_CACHE_WRITE_BACK |
-						FDT_LCD_CACHE_FLUSH,
-};
-
 /* Information about the display controller */
 struct tegra_lcd_priv {
-	enum stage_t stage;	/* Current stage we are at */
-	unsigned long timer_next; /* Time we can move onto next stage */
 	int width;			/* width in pixels */
 	int height;			/* height in pixels */
-
-	/*
-	 * log2 of number of bpp, in general, unless it bpp is 24 in which
-	 * case this field holds 24 also! This is a U-Boot thing.
-	 */
-	int log2_bpp;
+	enum video_log2_bpp log2_bpp;	/* colour depth */
+	struct display_timing timing;
+	struct udevice *panel;
 	struct disp_ctlr *disp;		/* Display controller to use */
 	fdt_addr_t frame_buffer;	/* Address of frame buffer */
 	unsigned pixel_clock;		/* Pixel clock in Hz */
-	uint horiz_timing[FDT_LCD_TIMING_COUNT];	/* Horizontal timing */
-	uint vert_timing[FDT_LCD_TIMING_COUNT];		/* Vertical timing */
-	struct udevice *pwm;
-	int pwm_channel;		/* PWM channel to use for backlight */
-	enum lcd_cache_t cache_type;
-
-	struct gpio_desc backlight_en;	/* GPIO for backlight enable */
-	struct gpio_desc lvds_shutdown;	/* GPIO for lvds shutdown */
-	struct gpio_desc backlight_vdd;	/* GPIO for backlight vdd */
-	struct gpio_desc panel_vdd;	/* GPIO for panel vdd */
-	/*
-	 * Panel required timings
-	 * Timing 1: delay between panel_vdd-rise and data-rise
-	 * Timing 2: delay between data-rise and backlight_vdd-rise
-	 * Timing 3: delay between backlight_vdd and pwm-rise
-	 * Timing 4: delay between pwm-rise and backlight_en-rise
-	 */
-	uint panel_timings[FDT_LCD_TIMINGS];
 };
 
 enum {
@@ -150,26 +97,23 @@ static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
 	writel(val, &dc->cmd.state_ctrl);
 }
 
-static void write_pair(struct tegra_lcd_priv *priv, int item, u32 *reg)
-{
-	writel(priv->horiz_timing[item] |
-			(priv->vert_timing[item] << 16), reg);
-}
-
 static int update_display_mode(struct dc_disp_reg *disp,
 			       struct tegra_lcd_priv *priv)
 {
+	struct display_timing *dt = &priv->timing;
 	unsigned long val;
 	unsigned long rate;
 	unsigned long div;
 
 	writel(0x0, &disp->disp_timing_opt);
-	write_pair(priv, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
-	write_pair(priv, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
-	write_pair(priv, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
-	write_pair(priv, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
 
-	writel(priv->width | (priv->height << 16), &disp->disp_active);
+	writel(1 | 1 << 16, &disp->ref_to_sync);
+	writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
+	writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
+	       &disp->back_porch);
+	writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
+	       &disp->front_porch);
+	writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
 
 	val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
 	val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
@@ -287,12 +231,11 @@ static int setup_window(struct disp_ctl_win *win,
 	win->stride = priv->width * (1 << priv->log2_bpp) / 8;
 	debug("%s: depth = %d\n", __func__, priv->log2_bpp);
 	switch (priv->log2_bpp) {
-	case 5:
-	case 24:
+	case VIDEO_BPP32:
 		win->fmt = COLOR_DEPTH_R8G8B8A8;
 		win->bpp = 32;
 		break;
-	case 4:
+	case VIDEO_BPP16:
 		win->fmt = COLOR_DEPTH_B5G6R5;
 		win->bpp = 16;
 		break;
@@ -305,18 +248,6 @@ static int setup_window(struct disp_ctl_win *win,
 	return 0;
 }
 
-static void debug_timing(const char *name, unsigned int timing[])
-{
-#ifdef DEBUG
-	int i;
-
-	debug("%s timing: ", name);
-	for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
-		debug("%d ", timing[i]);
-	debug("\n");
-#endif
-}
-
 /**
  * Register a new display based on device tree configuration.
  *
@@ -363,137 +294,35 @@ static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
 	return 0;
 }
 
-/**
- * Handle the next stage of device init
- */
-static int handle_stage(const void *blob, struct tegra_lcd_priv *priv)
-{
-	debug("%s: stage %d\n", __func__, priv->stage);
-
-	/* do the things for this stage */
-	switch (priv->stage) {
-	case STAGE_START:
-		/*
-		 * It is possible that the FDT has requested that the LCD be
-		 * disabled. We currently don't support this. It would require
-		 * changes to U-Boot LCD subsystem to have LCD support
-		 * compiled in but not used. An easier option might be to
-		 * still have a frame buffer, but leave the backlight off and
-		 * remove all mention of lcd in the stdout environment
-		 * variable.
-		 */
-
-		funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
-		break;
-	case STAGE_PANEL_VDD:
-		if (dm_gpio_is_valid(&priv->panel_vdd))
-			dm_gpio_set_value(&priv->panel_vdd, 1);
-		break;
-	case STAGE_LVDS:
-		if (dm_gpio_is_valid(&priv->lvds_shutdown))
-			dm_gpio_set_value(&priv->lvds_shutdown, 1);
-		break;
-	case STAGE_BACKLIGHT_VDD:
-		if (dm_gpio_is_valid(&priv->backlight_vdd))
-			dm_gpio_set_value(&priv->backlight_vdd, 1);
-		break;
-	case STAGE_PWM:
-		/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
-		pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
-		pinmux_tristate_disable(PMUX_PINGRP_GPU);
-
-		pwm_set_config(priv->pwm, priv->pwm_channel, 0xdf, 0xff);
-		pwm_set_enable(priv->pwm, priv->pwm_channel, true);
-		break;
-	case STAGE_BACKLIGHT_EN:
-		if (dm_gpio_is_valid(&priv->backlight_en))
-			dm_gpio_set_value(&priv->backlight_en, 1);
-		break;
-	case STAGE_DONE:
-		break;
-	}
-
-	/* set up timer for next stage */
-	priv->timer_next = timer_get_us();
-	if (priv->stage < FDT_LCD_TIMINGS)
-		priv->timer_next += priv->panel_timings[priv->stage] * 1000;
-
-	/* move to next stage */
-	priv->stage++;
-	return 0;
-}
-
-/**
- * Perform the next stage of the LCD init if it is time to do so.
- *
- * LCD init can be time-consuming because of the number of delays we need
- * while waiting for the backlight power supply, etc. This function can
- * be called at various times during U-Boot operation to advance the
- * initialization of the LCD to the next stage if sufficient time has
- * passed since the last stage. It keeps track of what stage it is up to
- * and the time that it is permitted to move to the next stage.
- *
- * The final call should have wait=1 to complete the init.
- *
- * @param blob	fdt blob containing LCD information
- * @param wait	1 to wait until all init is complete, and then return
- *		0 to return immediately, potentially doing nothing if it is
- *		not yet time for the next init.
- */
-static int tegra_lcd_check_next_stage(const void *blob,
-				      struct tegra_lcd_priv *priv, int wait)
-{
-	if (priv->stage == STAGE_DONE)
-		return 0;
-
-	do {
-		/* wait if we need to */
-		debug("%s: stage %d\n", __func__, priv->stage);
-		if (priv->stage != STAGE_START) {
-			int delay = priv->timer_next - timer_get_us();
-
-			if (delay > 0) {
-				if (wait)
-					udelay(delay);
-				else
-					return 0;
-			}
-		}
-
-		if (handle_stage(blob, priv))
-			return -1;
-	} while (wait && priv->stage != STAGE_DONE);
-	if (priv->stage == STAGE_DONE)
-		debug("%s: LCD init complete\n", __func__);
-
-	return 0;
-}
-
 static int tegra_lcd_probe(struct udevice *dev)
 {
 	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct tegra_lcd_priv *priv = dev_get_priv(dev);
 	const void *blob = gd->fdt_blob;
-	int type = DCACHE_OFF;
+	int ret;
 
 	/* Initialize the Tegra display controller */
+	funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
 	if (tegra_display_probe(blob, priv, (void *)plat->base)) {
 		printf("%s: Failed to probe display driver\n", __func__);
 		return -1;
 	}
 
-	tegra_lcd_check_next_stage(blob, priv, 1);
+	pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
+	pinmux_tristate_disable(PMUX_PINGRP_GPU);
 
-	/* Set up the LCD caching as requested */
-	if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
-		type = DCACHE_WRITETHROUGH;
-	else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
-		type = DCACHE_WRITEBACK;
-	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);
+	ret = panel_enable_backlight(priv->panel);
+	if (ret) {
+		debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
+		return ret;
+	}
+
+	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
+					DCACHE_WRITETHROUGH);
 
 	/* Enable flushing after LCD writes if requested */
-	video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);
+	video_set_flush_dcache(dev, true);
 
 	uc_priv->xsize = priv->width;
 	uc_priv->ysize = priv->height;
@@ -507,13 +336,11 @@ static int tegra_lcd_probe(struct udevice *dev)
 static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
 {
 	struct tegra_lcd_priv *priv = dev_get_priv(dev);
-	struct fdtdec_phandle_args args;
 	const void *blob = gd->fdt_blob;
+	struct display_timing *timing;
 	int node = dev->of_offset;
-	int front, back, ref;
 	int panel_node;
 	int rgb;
-	int bpp, bit;
 	int ret;
 
 	priv->disp = (struct disp_ctlr *)dev_get_addr(dev);
@@ -523,96 +350,40 @@ static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
 	}
 
 	rgb = fdt_subnode_offset(blob, node, "rgb");
+	if (rgb < 0) {
+		debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
+		      __func__, dev->name, rgb);
+		return -EINVAL;
+	}
 
+	ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
+	if (ret) {
+		debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
+		      __func__, dev->name, ret);
+		return -EINVAL;
+	}
+	timing = &priv->timing;
+	priv->width = timing->hactive.typ;
+	priv->height = timing->vactive.typ;
+	priv->pixel_clock = timing->pixelclock.typ;
+	priv->log2_bpp = VIDEO_BPP16;
+
+	/*
+	 * Sadly the panel phandle is in an rgb subnode so we cannot use
+	 * uclass_get_device_by_phandle().
+	 */
 	panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
 	if (panel_node < 0) {
 		debug("%s: Cannot find panel information\n", __func__);
 		return -EINVAL;
 	}
-
-	priv->width = fdtdec_get_int(blob, panel_node, "xres", -1);
-	priv->height = fdtdec_get_int(blob, panel_node, "yres", -1);
-	priv->pixel_clock = fdtdec_get_int(blob, panel_node, "clock", 0);
-	if (!priv->pixel_clock || priv->width == -1 || priv->height == -1) {
-		debug("%s: Pixel parameters missing\n", __func__);
-		return -EINVAL;
-	}
-
-	back = fdtdec_get_int(blob, panel_node, "left-margin", -1);
-	front = fdtdec_get_int(blob, panel_node, "right-margin", -1);
-	ref = fdtdec_get_int(blob, panel_node, "hsync-len", -1);
-	if ((back | front | ref) == -1) {
-		debug("%s: Horizontal parameters missing\n", __func__);
-		return -EINVAL;
-	}
-
-	/* Use a ref-to-sync of 1 always, and take this from the front porch */
-	priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
-	priv->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
-	priv->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
-	priv->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
-		priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
-	debug_timing("horiz", priv->horiz_timing);
-
-	back = fdtdec_get_int(blob, panel_node, "upper-margin", -1);
-	front = fdtdec_get_int(blob, panel_node, "lower-margin", -1);
-	ref = fdtdec_get_int(blob, panel_node, "vsync-len", -1);
-	if ((back | front | ref) == -1) {
-		debug("%s: Vertical parameters missing\n", __func__);
-		return -EINVAL;
-	}
-
-	priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
-	priv->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
-	priv->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
-	priv->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
-		priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
-	debug_timing("vert", priv->vert_timing);
-
-	bpp = fdtdec_get_int(blob, panel_node, "nvidia,bits-per-pixel", -1);
-	bit = ffs(bpp) - 1;
-	if (bpp == (1 << bit))
-		priv->log2_bpp = bit;
-	else
-		priv->log2_bpp = bpp;
-	if (bpp == -1) {
-		debug("%s: Pixel bpp parameters missing\n", __func__);
-		return -EINVAL;
-	}
-
-	if (fdtdec_parse_phandle_with_args(blob, panel_node, "nvidia,pwm",
-					   "#pwm-cells", 0, 0, &args)) {
-		debug("%s: Unable to decode PWM\n", __func__);
-		return -EINVAL;
-	}
-
-	ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
+	ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
+					     &priv->panel);
 	if (ret) {
-		debug("%s: Unable to find PWM\n", __func__);
-		return -EINVAL;
+		debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
+		      dev->name, ret);
+		return ret;
 	}
-	priv->pwm_channel = args.args[0];
-
-	priv->cache_type = fdtdec_get_int(blob, panel_node, "nvidia,cache-type",
-					  FDT_LCD_CACHE_WRITE_BACK_FLUSH);
-
-	/* These GPIOs are all optional */
-	gpio_request_by_name_nodev(blob, panel_node,
-				   "nvidia,backlight-enable-gpios", 0,
-				   &priv->backlight_en, GPIOD_IS_OUT);
-	gpio_request_by_name_nodev(blob, panel_node,
-				   "nvidia,lvds-shutdown-gpios", 0,
-				   &priv->lvds_shutdown, GPIOD_IS_OUT);
-	gpio_request_by_name_nodev(blob, panel_node,
-				   "nvidia,backlight-vdd-gpios", 0,
-				   &priv->backlight_vdd, GPIOD_IS_OUT);
-	gpio_request_by_name_nodev(blob, panel_node,
-				   "nvidia,panel-vdd-gpios", 0,
-				   &priv->panel_vdd, GPIOD_IS_OUT);
-
-	if (fdtdec_get_int_array(blob, panel_node, "nvidia,panel-timings",
-				 priv->panel_timings, FDT_LCD_TIMINGS))
-		return -EINVAL;
 
 	return 0;
 }

include/common.h

@@ -16,6 +16,7 @@ typedef volatile unsigned short vu_short;
 typedef volatile unsigned char	vu_char;
 
 #include <config.h>
+#include <errno.h>
 #include <asm-offsets.h>
 #include <linux/bitops.h>
 #include <linux/types.h>

include/configs/km/kmp204x-common.h

@@ -406,6 +406,7 @@ int get_scl(void);
 #endif
 
 #define __USB_PHY_TYPE	utmi
+#define CONFIG_USB_EHCI_FSL
 
 /*
  * Environment Configuration

include/configs/socfpga_common.h

@@ -346,7 +346,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #else
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	3
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	1
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x200 /* offset 512 sect (256k) */
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #endif

include/errno.h

@@ -1,4 +1,11 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
 #ifndef _ERRNO_H
+#define _ERRNO_H
 
 #include <asm-generic/errno.h>
 
@@ -8,5 +15,10 @@ extern int errno;
 
 #ifdef CONFIG_ERRNO_STR
 const char *errno_str(int errno);
+#else
+static inline const char *errno_str(int errno)
+{
+	return 0;
+}
 #endif
 #endif /* _ERRNO_H */

include/fdtdec.h

@@ -119,10 +119,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_EMC,	/* Tegra20 memory controller */
 	COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
 	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
-	COMPAT_NVIDIA_TEGRA20_PWM,	/* Tegra 2 PWM controller */
-	COMPAT_NVIDIA_TEGRA124_SOR,	/* Tegra 124 Serial Output Resource */
 	COMPAT_NVIDIA_TEGRA124_PMC,	/* Tegra 124 power mgmt controller */
-	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
 	COMPAT_NVIDIA_TEGRA186_SDMMC,	/* Tegra186 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA210_SDMMC,	/* Tegra210 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA124_SDMMC,	/* Tegra124 SDMMC controller */
@@ -146,7 +143,6 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS5_DP,	/* Exynos Display port controller */
 	COMPAT_SAMSUNG_EXYNOS_DWMMC,	/* Exynos DWMMC controller */
 	COMPAT_SAMSUNG_EXYNOS_MMC,	/* Exynos MMC controller */
-	COMPAT_SAMSUNG_EXYNOS_SERIAL,	/* Exynos UART */
 	COMPAT_MAXIM_MAX77686_PMIC,	/* MAX77686 PMIC */
 	COMPAT_GENERIC_SPI_FLASH,	/* Generic SPI Flash chip */
 	COMPAT_MAXIM_98095_CODEC,	/* MAX98095 Codec */

lib/fdtdec.c

@@ -26,10 +26,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
 	COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
 	COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
-	COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
-	COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
 	COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
-	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
 	COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
 	COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
 	COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
@@ -51,7 +48,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
 	COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
 	COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
-	COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
 	COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686"),
 	COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
 	COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),

lib/tiny-printf.c

@@ -13,11 +13,16 @@
 #include <stdarg.h>
 #include <serial.h>
 
-static char *bf;
-static char zs;
+/*
+ * This code in here may execute before the DRAM is initialised, so
+ * we should make sure that it doesn't touch BSS, which some boards
+ * put in DRAM.
+ */
+static char *bf __attribute__ ((section(".data")));
+static char zs __attribute__ ((section(".data")));
 
 /* Current position in sprintf() output string */
-static char *outstr;
+static char *outstr __attribute__ ((section(".data")));
 
 static void out(char c)
 {

net/nfs.c

@@ -132,7 +132,7 @@ static char *dirname(char *path)
 /**************************************************************************
 RPC_ADD_CREDENTIALS - Add RPC authentication/verifier entries
 **************************************************************************/
-static long *rpc_add_credentials(long *p)
+static uint32_t *rpc_add_credentials(uint32_t *p)
 {
 	int hl;
 	int hostnamelen;
@@ -241,7 +241,7 @@ static void nfs_mount_req(char *path)
 	pathlen = strlen(path);
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials((long *)p);
+	p = rpc_add_credentials(p);
 
 	*p++ = htonl(pathlen);
 	if (pathlen & 3)
@@ -268,7 +268,7 @@ static void nfs_umountall_req(void)
 		return;
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials((long *)p);
+	p = rpc_add_credentials(p);
 
 	len = (uint32_t *)p - (uint32_t *)&(data[0]);
 
@@ -289,7 +289,7 @@ static void nfs_readlink_req(void)
 	int len;
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials((long *)p);
+	p = rpc_add_credentials(p);
 
 	memcpy(p, filefh, NFS_FHSIZE);
 	p += (NFS_FHSIZE / 4);
@@ -312,7 +312,7 @@ static void nfs_lookup_req(char *fname)
 	fnamelen = strlen(fname);
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials((long *)p);
+	p = rpc_add_credentials(p);
 
 	memcpy(p, dirfh, NFS_FHSIZE);
 	p += (NFS_FHSIZE / 4);
@@ -337,7 +337,7 @@ static void nfs_read_req(int offset, int readlen)
 	int len;
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials((long *)p);
+	p = rpc_add_credentials(p);
 
 	memcpy(p, filefh, NFS_FHSIZE);
 	p += (NFS_FHSIZE / 4);

test/py/tests/test_hush_if_test.py

@@ -109,27 +109,27 @@ def exec_hush_if(u_boot_console, expr, result):
     response = u_boot_console.run_command(cmd)
     assert response.strip() == str(result).lower()
 
-@pytest.mark.buildconfigspec('sys_hush_parser')
+@pytest.mark.buildconfigspec('hush_parser')
 def test_hush_if_test_setup(u_boot_console):
     """Set up environment variables used during the "if" tests."""
 
     u_boot_console.run_command('setenv ut_var_nonexistent')
     u_boot_console.run_command('setenv ut_var_exists 1')
 
-@pytest.mark.buildconfigspec('sys_hush_parser')
+@pytest.mark.buildconfigspec('hush_parser')
 @pytest.mark.parametrize('expr,result', subtests)
 def test_hush_if_test(u_boot_console, expr, result):
     """Test a single "if test" condition."""
 
     exec_hush_if(u_boot_console, expr, result)
 
-@pytest.mark.buildconfigspec('sys_hush_parser')
+@pytest.mark.buildconfigspec('hush_parser')
 def test_hush_if_test_teardown(u_boot_console):
     """Clean up environment variables used during the "if" tests."""
 
     u_boot_console.run_command('setenv ut_var_exists')
 
-@pytest.mark.buildconfigspec('sys_hush_parser')
+@pytest.mark.buildconfigspec('hush_parser')
 # We might test this on real filesystems via UMS, DFU, 'save', etc.
 # Of those, only UMS currently allows file removal though.
 @pytest.mark.boardspec('sandbox')

test/py/tests/test_sandbox_exit.py

@@ -7,7 +7,7 @@ import pytest
 import signal
 
 @pytest.mark.boardspec('sandbox')
-@pytest.mark.buildconfigspec('reset')
+@pytest.mark.buildconfigspec('sysreset')
 def test_reset(u_boot_console):
     """Test that the "reset" command exits sandbox process."""
 

test/py/u_boot_spawn.py

@@ -38,6 +38,11 @@ class Spawn(object):
         self.before = ''
         self.after = ''
         self.timeout = None
+        # http://stackoverflow.com/questions/7857352/python-regex-to-match-vt100-escape-sequences
+        # Note that re.I doesn't seem to work with this regex (or perhaps the
+        # version of Python in Ubuntu 14.04), hence the inclusion of a-z inside
+        # [] instead.
+        self.re_vt100 = re.compile('(\x1b\[|\x9b)[^@-_a-z]*[@-_a-z]|\x1b[@-_a-z]')
 
         (self.pid, self.fd) = pty.fork()
         if self.pid == 0:
@@ -168,6 +173,10 @@ class Spawn(object):
                 if self.logfile_read:
                     self.logfile_read.write(c)
                 self.buf += c
+                # count=0 is supposed to be the default, which indicates
+                # unlimited substitutions, but in practice the version of
+                # Python in Ubuntu 14.04 appears to default to count=2!
+                self.buf = self.re_vt100.sub('', self.buf, count=1000000)
         finally:
             if self.logfile_read:
                 self.logfile_read.flush()

test/py/u_boot_utils.py

@@ -201,7 +201,7 @@ def find_ram_base(u_boot_console):
     with u_boot_console.log.section('find_ram_base'):
         response = u_boot_console.run_command('bdinfo')
         for l in response.split('\n'):
-            if '-> start' in l:
+            if '-> start' in l or 'memstart    =' in l:
                 ram_base = int(l.split('=')[1].strip(), 16)
                 break
         if ram_base is None:

tools/Makefile

@@ -76,8 +76,6 @@ dumpimage-mkimage-objs := aisimage.o \
 			lib/fdtdec.o \
 			fit_common.o \
 			fit_image.o \
-			gpimage.o \
-			gpimage-common.o \
 			common/image-fit.o \
 			image-host.o \
 			common/image.o \
@@ -100,6 +98,8 @@ dumpimage-mkimage-objs := aisimage.o \
 			zynqimage.o \
 			zynqmpimage.o \
 			$(LIBFDT_OBJS) \
+			gpimage.o \
+			gpimage-common.o \
 			$(RSA_OBJS-y)
 
 dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o