Prepare v2018.07

Signed-off-by: Tom Rini <trini@konsulko.com>

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2018
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

arch/arm/cpu/armv8/generic_timer.c

@@ -20,27 +20,70 @@ unsigned long get_tbclk(void)
 	return cntfrq;
 }
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
 /*
- * Generic timer implementation of timer_read_counter()
+ * FSL erratum A-008585 says that the ARM generic timer counter "has the
+ * potential to contain an erroneous value for a small number of core
+ * clock cycles every time the timer value changes".
+ * This sometimes leads to a consecutive counter read returning a lower
+ * value than the previous one, thus reporting the time to go backwards.
+ * The workaround is to read the counter twice and only return when the value
+ * was the same in both reads.
+ * Assumes that the CPU runs in much higher frequency than the timer.
  */
 unsigned long timer_read_counter(void)
 {
 	unsigned long cntpct;
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
-	/* This erratum number needs to be confirmed to match ARM document */
 	unsigned long temp;
-#endif
+
 	isb();
 	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
 	asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
 	while (temp != cntpct) {
 		asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
 		asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
 	}
-#endif
+
 	return cntpct;
 }
+#elif CONFIG_SUNXI_A64_TIMER_ERRATUM
+/*
+ * This erratum sometimes flips the lower 11 bits of the counter value
+ * to all 0's or all 1's, leading to jumps forwards or backwards.
+ * Backwards jumps might be interpreted all roll-overs and be treated as
+ * huge jumps forward.
+ * The workaround is to check whether the lower 11 bits of the counter are
+ * all 0 or all 1, then discard this value and read again.
+ * This occasionally discards valid values, but will catch all erroneous
+ * reads and fixes the problem reliably. Also this mostly requires only a
+ * single read, so does not have any significant overhead.
+ * The algorithm was conceived by Samuel Holland.
+ */
+unsigned long timer_read_counter(void)
+{
+	unsigned long cntpct;
+
+	isb();
+	do {
+		asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+	} while (((cntpct + 1) & GENMASK(10, 0)) <= 1);
+
+	return cntpct;
+}
+#else
+/*
+ * timer_read_counter() using the Arm Generic Timer (aka arch timer).
+ */
+unsigned long timer_read_counter(void)
+{
+	unsigned long cntpct;
+
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+
+	return cntpct;
+}
+#endif
 
 uint64_t get_ticks(void)
 {

arch/arm/dts/Makefile

@@ -357,6 +357,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
 	sun8i-a83t-tbs-a711.dts
 dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h2-plus-libretech-all-h3-cc.dtb \
+	sun8i-h2-plus-orangepi-r1.dtb \
 	sun8i-h2-plus-orangepi-zero.dtb \
 	sun8i-h3-bananapi-m2-plus.dtb \
 	sun8i-h3-libretech-all-h3-cc.dtb \
@@ -380,6 +381,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
 	sun50i-h5-libretech-all-h3-cc.dtb \
 	sun50i-h5-nanopi-neo2.dtb \
 	sun50i-h5-nanopi-neo-plus2.dtb \
+	sun50i-h5-orangepi-zero-plus.dtb \
 	sun50i-h5-orangepi-pc2.dtb \
 	sun50i-h5-orangepi-prime.dtb \
 	sun50i-h5-orangepi-zero-plus2.dtb

arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts

@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * Copyright (C) 2018 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR X11)
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Xunlong Orange Pi Zero Plus";
+	compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5";
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	aliases {
+		ethernet0 = &emac;
+		ethernet1 = &rtl8189ftv;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		pwr {
+			label = "orangepi:green:pwr";
+			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+			default-state = "on";
+		};
+
+		status {
+			label = "orangepi:red:status";
+			gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
+		};
+	};
+
+	reg_gmac_3v3: gmac-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "gmac-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		enable-active-high;
+		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_rgmii_pins>;
+	phy-supply = <&reg_gmac_3v3>;
+	phy-handle = <&ext_rgmii_phy>;
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&external_mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+	status = "okay";
+};
+
+&mmc1 {
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	/*
+	 * Explicitly define the sdio device, so that we can add an ethernet
+	 * alias for it (which e.g. makes u-boot set a mac-address).
+	 */
+	rtl8189ftv: sdio_wifi@1 {
+		reg = <1>;
+	};
+};
+
+/*
+&spi0  {
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "mxicy,mx25l1606e", "winbond,w25q128";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+	};
+};
+*/
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbphy {
+	/* USB Type-A ports' VBUS is always on */
+	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+	status = "okay";
+};

arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts

@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* Orange Pi R1 is based on Orange Pi Zero design */
+#include "sun8i-h2-plus-orangepi-zero.dts"
+
+/ {
+	model = "Xunlong Orange Pi R1";
+	compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus";
+
+	/delete-node/ reg_vcc_wifi;
+
+	/*
+	 * Ths pin of this regulator is the same with the Wi-Fi extra
+	 * regulator on the original Zero. However it's used for USB
+	 * Ethernet rather than the Wi-Fi now.
+	 */
+	reg_vcc_usb_eth: reg-vcc-usb-ethernet {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc-usb-ethernet";
+		enable-active-high;
+		gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+	};
+
+	aliases {
+		ethernet1 = &rtl8189etv;
+	};
+};
+
+/*
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "mxicy,mx25l12805d", "jedec,spi-nor";
+	};
+};
+*/
+
+&ohci1 {
+	/*
+	 * RTL8152B USB-Ethernet adapter is connected to USB1,
+	 * and it's a USB 2.0 device. So the OHCI1 controller
+	 * can be left disabled.
+	 */
+	status = "disabled";
+};
+
+&mmc1 {
+	vmmc-supply = <&reg_vcc3v3>;
+	vqmmc-supply = <&reg_vcc3v3>;
+
+	rtl8189etv: sdio_wifi@1 {
+		reg = <1>;
+	};
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_vcc_usb_eth>;
+};

arch/arm/mach-sunxi/Kconfig

@@ -84,6 +84,9 @@ config SUNXI_HIGH_SRAM
 	Chips using the latter setup are supposed to select this option to
 	adjust the addresses accordingly.
 
+config SUNXI_A64_TIMER_ERRATUM
+	bool
+
 # Note only one of these may be selected at a time! But hidden choices are
 # not supported by Kconfig
 config SUNXI_GEN_SUN4I
@@ -270,6 +273,7 @@ config MACH_SUN50I
 	select SUNXI_DRAM_DW_32BIT
 	select FIT
 	select SPL_LOAD_FIT
+	select SUNXI_A64_TIMER_ERRATUM
 
 config MACH_SUN50I_H5
 	bool "sun50i (Allwinner H5)"

board/sunxi/MAINTAINERS

@@ -340,6 +340,11 @@ M:	Icenowy Zheng <icenowy@aosc.xyz>
 S:	Maintained
 F:	configs/orangepi_zero_defconfig
 
+ORANGEPI ZERO PLUS BOARD
+M:	Hauke Mehrtens <hauke@hauke-m.de>
+S:	Maintained
+F:	configs/orangepi_zero_plus_defconfig
+
 ORANGEPI ZERO PLUS 2 BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
@@ -355,6 +360,11 @@ M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	configs/orangepi_prime_defconfig
 
+ORANGEPI R1 BOARD
+M:	Hauke Mehrtens <hauke@hauke-m.de>
+S:	Maintained
+F:	configs/orangepi_r1_defconfig
+
 PINE64 BOARDS
 M:	Andre Przywara <andre.przywara@arm.com>
 S:	Maintained

configs/nyan-big_defconfig

@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TEGRA=y
-CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_TEXT_BASE=0x81000100
 CONFIG_DEBUG_UART_BASE=0x70006000
 CONFIG_DEBUG_UART_CLOCK=408000000
 CONFIG_TEGRA124=y

configs/orangepi_r1_defconfig

@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO_DE2 is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_zero_plus_defconfig

@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881977
+CONFIG_MMC0_CD_PIN="PH13"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

doc/README.chromium

@@ -43,26 +43,13 @@ https://git.collabora.com/cgit/user/tomeu/u-boot.git/commit/?h=nyan-big
 https://lists.denx.de/pipermail/u-boot/2017-May/289491.html
 https://github.com/chromeos-nvidia-androidtv/gnu-linux-on-acer-chromebook-13#copy-data-to-the-sd-card
 
-1. Patch U-Boot
-
-Open include/configs/tegra124-common.h
-
-Change:
-
-#define CONFIG_SYS_TEXT_BASE	0x80110000
-
-to:
-
-#define CONFIG_SYS_TEXT_BASE	0x81000100
-
-
-2. Build U-Boot
+1. Build U-Boot
 
    mkdir b
    make -j8 O=b/nyan-big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all
 
 
-3. Select a .its file
+2. Select a .its file
 
 Select something from doc/chromium which matches your board, or create your
 own.
@@ -72,7 +59,7 @@ used by U-Boot. This is because the Chromebook expects to pass it to the
 kernel, and crashes if it is not present.
 
 
-4. Build and sign an image
+3. Build and sign an image
 
    ./b/nyan-big/tools/mkimage -f doc/chromium/nyan-big.its u-boot-chromium.fit
    echo test >dummy.txt
@@ -82,7 +69,7 @@ kernel, and crashes if it is not present.
 	--bootloader dummy.txt --pack u-boot.kpart
 
 
-5. Prepare an SD card
+4. Prepare an SD card
 
    DISK=/dev/sdc   # Replace with your actual SD card device
    sudo cgpt create $DISK
@@ -91,12 +78,12 @@ kernel, and crashes if it is not present.
    sudo gdisk $DISK   # Enter command 'w' to write a protective MBR to the disk
 
 
-6. Write U-Boot to the SD card
+5. Write U-Boot to the SD card
 
    sudo dd if=u-boot.kpart of=/dev/sdc1; sync
 
 
-7. Start it up
+6. Start it up
 
 Reboot the device in dev mode. Make sure that you have USB booting enabled. To
 do this, login as root (via Ctrl-Alt-forward_arrow) and type
@@ -115,7 +102,7 @@ mode screen. It should show something like the following on the display:
    Tegra124 (Nyan-big) #
 
 
-8. Known problems
+7. Known problems
 
 On the serial console the word MMC is chopped at the start of the line:
 

drivers/usb/host/dwc2.c

@@ -1314,6 +1314,7 @@ struct dm_usb_ops dwc2_usb_ops = {
 
 static const struct udevice_id dwc2_usb_ids[] = {
 	{ .compatible = "brcm,bcm2835-usb" },
+	{ .compatible = "brcm,bcm2708-usb" },
 	{ .compatible = "snps,dwc2" },
 	{ }
 };

drivers/usb/host/ohci-sunxi.c

@@ -44,6 +44,8 @@ struct ohci_sunxi_priv {
 	const struct ohci_sunxi_cfg *cfg;
 };
 
+static fdt_addr_t last_ohci_addr = 0;
+
 static int ohci_usb_probe(struct udevice *dev)
 {
 	struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
@@ -53,6 +55,9 @@ static int ohci_usb_probe(struct udevice *dev)
 	u8 reg_mask = 0;
 	int phys, ret;
 
+	if ((fdt_addr_t)regs > last_ohci_addr)
+		last_ohci_addr = (fdt_addr_t)regs;
+
 	priv->cfg = (const struct ohci_sunxi_cfg *)dev_get_driver_data(dev);
 	priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	if (IS_ERR(priv->ccm))
@@ -114,6 +119,7 @@ no_phy:
 static int ohci_usb_remove(struct udevice *dev)
 {
 	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
+	fdt_addr_t base_addr = devfdt_get_addr(dev);
 	int ret;
 
 	if (generic_phy_valid(&priv->phy)) {
@@ -130,7 +136,18 @@ static int ohci_usb_remove(struct udevice *dev)
 
 	if (priv->cfg->has_reset)
 		clrbits_le32(priv->reset0_cfg, priv->ahb_gate_mask);
-	clrbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
+	/*
+	 * On the A64 CLK_USB_OHCI0 is the parent of CLK_USB_OHCI1, so
+	 * we have to wait with bringing down any clock until the last
+	 * OHCI controller is removed.
+	 */
+	if (!priv->cfg->extra_usb_gate_mask || base_addr == last_ohci_addr) {
+		u32 usb_gate_mask = priv->usb_gate_mask;
+
+		usb_gate_mask |= priv->cfg->extra_usb_gate_mask;
+		clrbits_le32(&priv->ccm->usb_clk_cfg, usb_gate_mask);
+	}
+
 	clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask);
 
 	return 0;

drivers/video/bcm2835.c

@@ -48,6 +48,7 @@ static int bcm2835_video_probe(struct udevice *dev)
 
 static const struct udevice_id bcm2835_video_ids[] = {
 	{ .compatible = "brcm,bcm2835-hdmi" },
+	{ .compatible = "brcm,bcm2708-fb" },
 	{ }
 };