Prepare v2019.01

Signed-off-by: Tom Rini <trini@konsulko.com>

.github/pull_request_template.md

@@ -0,0 +1,3 @@
+Please do not submit a Pull Request via github.  Our project makes use of
+mailing lists for patch submission and review.  For more details please
+see https://www.denx.de/wiki/U-Boot/Patches

Kconfig

@@ -251,6 +251,16 @@ config FIT
 
 if FIT
 
+config FIT_EXTERNAL_OFFSET
+	hex "Text Base"
+	default 0x0
+	help
+	  This specifies a data offset in fit image.
+	  The offset is from data payload offset to the beginning of
+	  fit image header. When specifies a offset, specific data
+	  could be put in the hole between data payload and fit image
+	  header, such as CSF data on i.MX platform.
+
 config FIT_ENABLE_SHA256_SUPPORT
 	bool "Support SHA256 checksum of FIT image contents"
 	default y

MAINTAINERS

@@ -123,7 +123,7 @@ F:	drivers/spi/bcmstb_spi.c
 ARM FREESCALE IMX
 M:	Stefano Babic <sbabic@denx.de>
 M:	Fabio Estevam <fabio.estevam@nxp.com>
-R:	NXP Linux Team <linux-imx@nxp.com>
+R:	NXP i.MX U-Boot Team <uboot-imx@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-imx.git
 F:	arch/arm/cpu/arm1136/mx*/
@@ -512,6 +512,24 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-mips.git
 F:	arch/mips/
 
+MIPS MSCC
+M:	Gregory CLEMENT <gregory.clement@bootlin.com>
+M:	Lars Povlsen <lars.povlsen@microchip.com>
+M:	Horatiu Vultur <horatiu.vultur@microchip.com>
+S:	Maintained
+F:	arch/mips/mach-mscc/
+F:	arch/mips/dts/luton*
+F:	arch/mips/dts/mscc*
+F:	arch/mips/dts/ocelot*
+F:	board/mscc/
+F:	configs/mscc*
+F:	include/configs/vcoreiii.h
+
+MIPS JZ4780
+M:	Ezequiel Garcia <ezequiel@collabora.com>
+S:	Maintained
+F:	arch/mips/mach-jz47xx/
+
 MMC
 M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2019
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -712,8 +712,8 @@ libs-y += drivers/usb/dwc3/
 libs-y += drivers/usb/common/
 libs-y += drivers/usb/emul/
 libs-y += drivers/usb/eth/
-libs-y += drivers/usb/gadget/
-libs-y += drivers/usb/gadget/udc/
+libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
+libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
 libs-y += drivers/usb/host/
 libs-y += drivers/usb/musb/
 libs-y += drivers/usb/musb-new/
@@ -893,7 +893,7 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
 	>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
 
 quiet_cmd_mkfitimage = MKIMAGE $@
-cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \
+cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\
 	>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
 
 quiet_cmd_cat = CAT     $@
@@ -938,7 +938,8 @@ ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
 	@echo >&2 "===================================================="
 endif
 endif
-ifeq ($(CONFIG_LIBATA)$(CONFIG_DM_SCSI)$(CONFIG_MVSATA_IDE),y)
+ifeq ($(CONFIG_LIBATA)$(CONFIG_MVSATA_IDE),y)
+ifneq ($(CONFIG_DM_SCSI),y)
 	@echo >&2 "===================== WARNING ======================"
 	@echo >&2 "This board does not use CONFIG_DM_SCSI. Please update"
 	@echo >&2 "the storage controller to use CONFIG_DM_SCSI before the v2019.07 release."
@@ -946,6 +947,27 @@ ifeq ($(CONFIG_LIBATA)$(CONFIG_DM_SCSI)$(CONFIG_MVSATA_IDE),y)
 	@echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
 	@echo >&2 "===================================================="
 endif
+endif
+ifeq ($(CONFIG_PCI),y)
+ifneq ($(CONFIG_DM_PCI),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM_PCI Please update"
+	@echo >&2 "the board to use CONFIG_DM_PCI before the v2019.07 release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+	@echo >&2 "===================================================="
+endif
+endif
+ifneq ($(CONFIG_LCD)$(CONFIG_VIDEO),)
+ifneq ($(CONFIG_DM_VIDEO),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM_VIDEO Please update"
+	@echo >&2 "the board to use CONFIG_DM_VIDEO before the v2019.07 release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+	@echo >&2 "===================================================="
+endif
+endif
 ifeq ($(CONFIG_OF_EMBED),y)
 	@echo >&2 "===================== WARNING ======================"
 	@echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
@@ -953,6 +975,27 @@ ifeq ($(CONFIG_OF_EMBED),y)
 	@echo >&2 "CONFIG_OF_SEPARATE for boards in mainline."
 	@echo >&2 "See doc/README.fdt-control for more info."
 	@echo >&2 "===================================================="
+endif
+ifeq ($(CONFIG_SPI),y)
+ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM_SPI. Please update"
+	@echo >&2 "the board before v2019.04 for no dm conversion"
+	@echo >&2 "and v2019.07 for partially dm converted drivers."
+	@echo >&2 "Failure to update can lead to driver/board removal"
+	@echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+	@echo >&2 "===================================================="
+endif
+endif
+ifeq ($(CONFIG_SPI_FLASH),y)
+ifneq ($(CONFIG_DM_SPI_FLASH)$(CONFIG_OF_CONTROL),yy)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM_SPI_FLASH. Please update"
+	@echo >&2 "the board to use CONFIG_SPI_FLASH before the v2019.07 release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+	@echo >&2 "===================================================="
+endif
 endif
 	@# Check that this build does not use CONFIG options that we do not
 	@# know about unless they are in Kconfig. All the existing CONFIG
@@ -1112,6 +1155,9 @@ U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
 else
 ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
 U_BOOT_ITS := u-boot.its
+ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
+U_BOOT_ITS_DEPS += u-boot-nodtb.bin
+endif
 ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
 U_BOOT_ITS_DEPS += u-boot
 endif
@@ -1207,6 +1253,11 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
 SPL: spl/u-boot-spl.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 
+ifeq ($(CONFIG_ARCH_IMX8M), y)
+flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
+	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+endif
+
 u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 

api/api_storage.c

@@ -99,6 +99,7 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
 {
 	struct blk_desc *dd;
 	int found = 0;
+	int found_last = 0;
 	int i = 0;
 
 	/* Wasn't configured for this type, return 0 directly */
@@ -111,9 +112,13 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
 			if (di->cookie ==
 			    (void *)blk_get_dev(specs[type].name, i)) {
 				i += 1;
+				found_last = 1;
 				break;
 			}
 		}
+
+		if (!found_last)
+			i = 0;
 	}
 
 	for (; i < specs[type].max_dev; i++) {

arch/arm/Kconfig

@@ -607,6 +607,7 @@ config ARCH_EXYNOS
 	select DM_SPI
 	select DM_SPI_FLASH
 	select SPI
+	imply SYS_THUMB_BUILD
 	imply CMD_DM
 	imply FAT_WRITE
 
@@ -694,7 +695,7 @@ config ARCH_IMX8
 	select DM
 	select OF_CONTROL
 
-config ARCH_MX8M
+config ARCH_IMX8M
 	bool "NXP i.MX8M platform"
 	select ARM64
 	select DM
@@ -874,7 +875,6 @@ config ARCH_SUNXI
 	imply PRE_CONSOLE_BUFFER
 	imply SPL_GPIO_SUPPORT
 	imply SPL_LIBCOMMON_SUPPORT
-	imply SPL_LIBDISK_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
 	imply SPL_MMC_SUPPORT if MMC
 	imply SPL_POWER_SUPPORT
@@ -1451,7 +1451,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig"
 
 source "arch/arm/mach-imx/imx8/Kconfig"
 
-source "arch/arm/mach-imx/mx8m/Kconfig"
+source "arch/arm/mach-imx/imx8m/Kconfig"
 
 source "arch/arm/mach-imx/mxs/Kconfig"
 

arch/arm/Makefile

@@ -103,11 +103,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m))
 libs-y += arch/arm/mach-imx/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
 libs-y += arch/arm/mach-imx/
 endif
 endif

arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2

@@ -8,3 +8,14 @@ Freescale LayerScape with Chassis Generation 2
 
 This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
 for example LS1043A.
+
+Watchdog support Overview
+-------------------
+Support watchdog driver for LSCH2. The driver is disabled in default.
+You can enable it by setting CONFIG_IMX_WATCHDOG.
+Use following config to set watchdog timeout, if this config is not defined,
+the default timeout value is 128s which is the maximum. Set 10 seconds for
+example:
+    #define CONFIG_WATCHDOG_TIMEOUT_MSECS 10000
+Set CONFIG_WATCHDOG_RESET_DISABLE to disable reset watchdog, so that the
+watchdog will not be fed in u-boot.

arch/arm/dts/Makefile

@@ -466,6 +466,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 
 dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
 
+dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
+
 dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a7795-h3ulcb-u-boot.dtb \
 	r8a7795-salvator-x-u-boot.dtb \

arch/arm/dts/fsl-imx8mq-evk.dts

@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x40000000 0x00020000;
+
+#include "fsl-imx8mq.dtsi"
+
+/ {
+	model = "Freescale i.MX8MQ EVK";
+	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+	chosen {
+		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		ledpwm2 {
+			label = "PWM2";
+			pwms = <&pwm2 0 50000>;
+			max-brightness = <255>;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx8mq-evk {
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
+				MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+				MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+				MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+				MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+				MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+				MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+				MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL	0x4000007f
+				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA	0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL	0x4000007f
+				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA	0x4000007f
+			>;
+		};
+
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x16
+			>;
+		};
+
+		pinctrl_qspi: qspigrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
+				MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
+				MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
+				MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
+				MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
+				MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
+
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x83
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc3
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc3
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc3
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc3
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc3
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc3
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc3
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc3
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc3
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x83
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x85
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc5
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc5
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc5
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc5
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc5
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc5
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc5
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc5
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc5
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x85
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x87
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc7
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc7
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc7
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc7
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc7
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc7
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc7
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc7
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc7
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x87
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
+				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x85
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc5
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc5
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc5
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc5
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc5
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x87
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc7
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc7
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc7
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc7
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc7
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
+				MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
+				MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
+				MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
+				MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+			>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,led-act-blind-workaround;
+			at803x,eee-disabled;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pfuze100@08 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3ab {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "disabled";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&lcdif {
+	status = "okay";
+	disp-dev = "mipi_dsi_northwest";
+	display = <&display0>;
+
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+			clock-frequency = <9200000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <8>;
+			hback-porch = <4>;
+			hsync-len = <41>;
+			vback-porch = <2>;
+			vfront-porch = <4>;
+			vsync-len = <10>;
+
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+
+	flash0: n25q256a@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};

arch/arm/dts/meson-axg-s400-u-boot.dtsi

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+/* wifi module */
+&sd_emmc_b {
+	status = "disabled";
+};
+
+/* emmc storage */
+&sd_emmc_c {
+	status = "okay";
+};

arch/arm/dts/omap5-u-boot.dtsi

@@ -12,6 +12,11 @@
 		tick-timer = &timer2;
 	};
 
+	aliases {
+		usb0 = &usb1;
+		usb1 = &usb2;
+	};
+
 	ocp {
 		u-boot,dm-spl;
 

arch/arm/dts/rk3399-puma.dtsi

@@ -172,10 +172,7 @@
 		regulator-max-microvolt = <1400000>;
 		regulator-always-on;
 		regulator-boot-on;
-
-		/* for rockchip boot on */
-		rockchip,pwm_id= <2>;
-		rockchip,pwm_voltage = <1000000>;
+		regulator-init-microvolt = <950000>;
 	};
 };
 

arch/arm/dts/socfpga_arria10.dtsi

@@ -660,6 +660,7 @@
 			fifo-depth = <0x400>;
 			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 			clock-names = "biu", "ciu";
+			resets = <&rst SDMMC_RESET>;
 			status = "disabled";
 		};
 

arch/arm/dts/uniphier-ld11.dtsi

@@ -116,6 +116,28 @@
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
 
+		spi0: spi@54006000 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006000 0x100>;
+			interrupts = <0 39 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi0>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
+		spi1: spi@54006100 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006100 0x100>;
+			interrupts = <0 216 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi1>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -432,6 +454,8 @@
 				 <&mio_clk 12>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 				 <&mio_rst 12>;
+			phy-names = "usb";
+			phys = <&usb_phy0>;
 			has-transaction-translator;
 		};
 
@@ -446,6 +470,8 @@
 				 <&mio_clk 13>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 				 <&mio_rst 13>;
+			phy-names = "usb";
+			phys = <&usb_phy1>;
 			has-transaction-translator;
 		};
 
@@ -460,6 +486,8 @@
 				 <&mio_clk 14>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 				 <&mio_rst 14>;
+			phy-names = "usb";
+			phys = <&usb_phy2>;
 			has-transaction-translator;
 		};
 
@@ -488,6 +516,27 @@
 			pinctrl: pinctrl {
 				compatible = "socionext,uniphier-ld11-pinctrl";
 			};
+
+			usb-phy {
+				compatible = "socionext,uniphier-ld11-usb2-phy";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				usb_phy0: phy@0 {
+					reg = <0>;
+					#phy-cells = <0>;
+				};
+
+				usb_phy1: phy@1 {
+					reg = <1>;
+					#phy-cells = <0>;
+				};
+
+				usb_phy2: phy@2 {
+					reg = <2>;
+					#phy-cells = <0>;
+				};
+			};
 		};
 
 		soc-glue@5f900000 {
@@ -571,7 +620,8 @@
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
-			clocks = <&sys_clk 2>;
+			clock-names = "nand", "nand_x", "ecc";
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 			resets = <&sys_rst 2>;
 		};
 	};

arch/arm/dts/uniphier-ld20-global.dts

@@ -145,6 +145,10 @@
 	};
 };
 
+&usb {
+	status = "okay";
+};
+
 &nand {
 	status = "okay";
 };

arch/arm/dts/uniphier-ld20-ref.dts

@@ -75,3 +75,7 @@
 		drive-strength = <9>;
 	};
 };
+
+&usb {
+	status = "okay";
+};

arch/arm/dts/uniphier-ld20.dtsi

@@ -224,6 +224,50 @@
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
 
+		spi0: spi@54006000 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006000 0x100>;
+			interrupts = <0 39 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi0>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
+		spi1: spi@54006100 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006100 0x100>;
+			interrupts = <0 216 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi1>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
+		spi2: spi@54006200 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006200 0x100>;
+			interrupts = <0 229 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi2>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
+		spi3: spi@54006300 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006300 0x100>;
+			interrupts = <0 230 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi3>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -567,6 +611,50 @@
 			efuse@200 {
 				compatible = "socionext,uniphier-efuse";
 				reg = <0x200 0x68>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				/* USB cells */
+				usb_rterm0: trim@54,4 {
+					reg = <0x54 1>;
+					bits = <4 2>;
+				};
+				usb_rterm1: trim@55,4 {
+					reg = <0x55 1>;
+					bits = <4 2>;
+				};
+				usb_rterm2: trim@58,4 {
+					reg = <0x58 1>;
+					bits = <4 2>;
+				};
+				usb_rterm3: trim@59,4 {
+					reg = <0x59 1>;
+					bits = <4 2>;
+				};
+				usb_sel_t0: trim@54,0 {
+					reg = <0x54 1>;
+					bits = <0 4>;
+				};
+				usb_sel_t1: trim@55,0 {
+					reg = <0x55 1>;
+					bits = <0 4>;
+				};
+				usb_sel_t2: trim@58,0 {
+					reg = <0x58 1>;
+					bits = <0 4>;
+				};
+				usb_sel_t3: trim@59,0 {
+					reg = <0x59 1>;
+					bits = <0 4>;
+				};
+				usb_hs_i0: trim@56,0 {
+					reg = <0x56 1>;
+					bits = <0 4>;
+				};
+				usb_hs_i2: trim@5a,0 {
+					reg = <0x5a 1>;
+					bits = <0 4>;
+				};
 			};
 		};
 
@@ -634,6 +722,157 @@
 			};
 		};
 
+		_usb: usb@65a00000 {
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+			status = "disabled";
+			reg = <0x65a00000 0xcd00>;
+			interrupt-names = "host";
+			interrupts = <0 134 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
+				    <&pinctrl_usb2>, <&pinctrl_usb3>;
+			clock-names = "ref", "bus_early", "suspend";
+			clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
+			resets = <&usb_rst 15>;
+			phys = <&usb_hsphy0>, <&usb_hsphy1>,
+			       <&usb_hsphy2>, <&usb_hsphy3>,
+			       <&usb_ssphy0>, <&usb_ssphy1>;
+			dr_mode = "host";
+		};
+
+		usb-glue@65b00000 {
+			compatible = "socionext,uniphier-ld20-dwc3-glue",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x65b00000 0x400>;
+
+			usb_rst: reset@0 {
+				compatible = "socionext,uniphier-ld20-usb3-reset";
+				reg = <0x0 0x4>;
+				#reset-cells = <1>;
+				clock-names = "link";
+				clocks = <&sys_clk 14>;
+				reset-names = "link";
+				resets = <&sys_rst 14>;
+			};
+
+			usb_vbus0: regulator@100 {
+				compatible = "socionext,uniphier-ld20-usb3-regulator";
+				reg = <0x100 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 14>;
+				reset-names = "link";
+				resets = <&sys_rst 14>;
+			};
+
+			usb_vbus1: regulator@110 {
+				compatible = "socionext,uniphier-ld20-usb3-regulator";
+				reg = <0x110 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 14>;
+				reset-names = "link";
+				resets = <&sys_rst 14>;
+			};
+
+			usb_vbus2: regulator@120 {
+				compatible = "socionext,uniphier-ld20-usb3-regulator";
+				reg = <0x120 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 14>;
+				reset-names = "link";
+				resets = <&sys_rst 14>;
+			};
+
+			usb_vbus3: regulator@130 {
+				compatible = "socionext,uniphier-ld20-usb3-regulator";
+				reg = <0x130 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 14>;
+				reset-names = "link";
+				resets = <&sys_rst 14>;
+			};
+
+			usb_hsphy0: hs-phy@200 {
+				compatible = "socionext,uniphier-ld20-usb3-hsphy";
+				reg = <0x200 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 14>, <&sys_clk 16>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 14>, <&sys_rst 16>;
+				vbus-supply = <&usb_vbus0>;
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
+				nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
+					      <&usb_hs_i0>;
+			};
+
+			usb_hsphy1: hs-phy@210 {
+				compatible = "socionext,uniphier-ld20-usb3-hsphy";
+				reg = <0x210 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 14>, <&sys_clk 16>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 14>, <&sys_rst 16>;
+				vbus-supply = <&usb_vbus1>;
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
+				nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
+					      <&usb_hs_i0>;
+			};
+
+			usb_hsphy2: hs-phy@220 {
+				compatible = "socionext,uniphier-ld20-usb3-hsphy";
+				reg = <0x220 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 14>, <&sys_clk 17>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 14>, <&sys_rst 17>;
+				vbus-supply = <&usb_vbus2>;
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
+				nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
+					      <&usb_hs_i2>;
+			};
+
+			usb_hsphy3: hs-phy@230 {
+				compatible = "socionext,uniphier-ld20-usb3-hsphy";
+				reg = <0x230 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 14>, <&sys_clk 17>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 14>, <&sys_rst 17>;
+				vbus-supply = <&usb_vbus3>;
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
+				nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
+					      <&usb_hs_i2>;
+			};
+
+			usb_ssphy0: ss-phy@300 {
+				compatible = "socionext,uniphier-ld20-usb3-ssphy";
+				reg = <0x300 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 14>, <&sys_clk 18>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 14>, <&sys_rst 18>;
+				vbus-supply = <&usb_vbus0>;
+			};
+
+			usb_ssphy1: ss-phy@310 {
+				compatible = "socionext,uniphier-ld20-usb3-ssphy";
+				reg = <0x310 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 14>, <&sys_clk 19>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 14>, <&sys_rst 19>;
+				vbus-supply = <&usb_vbus1>;
+			};
+		};
+
+		/* FIXME: U-Boot own node */
 		usb: usb@65b00000 {
 			compatible = "socionext,uniphier-ld20-dwc3";
 			reg = <0x65b00000 0x1000>;
@@ -660,7 +899,8 @@
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
-			clocks = <&sys_clk 2>;
+			clock-names = "nand", "nand_x", "ecc";
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 			resets = <&sys_rst 2>;
 		};
 	};

arch/arm/dts/uniphier-ld4.dtsi

@@ -63,6 +63,17 @@
 			cache-level = <2>;
 		};
 
+		spi: spi@54006000 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006000 0x100>;
+			interrupts = <0 39 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi0>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -381,7 +392,8 @@
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand2cs>;
-			clocks = <&sys_clk 2>;
+			clock-names = "nand", "nand_x", "ecc";
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 			resets = <&sys_rst 2>;
 		};
 	};

arch/arm/dts/uniphier-pinctrl.dtsi

@@ -131,6 +131,26 @@
 		function = "sd1";
 	};
 
+	pinctrl_spi0: spi0 {
+		groups = "spi0";
+		function = "spi0";
+	};
+
+	pinctrl_spi1: spi1 {
+		groups = "spi1";
+		function = "spi1";
+	};
+
+	pinctrl_spi2: spi2 {
+		groups = "spi2";
+		function = "spi2";
+	};
+
+	pinctrl_spi3: spi3 {
+		groups = "spi3";
+		function = "spi3";
+	};
+
 	pinctrl_system_bus: system-bus {
 		groups = "system_bus", "system_bus_cs1";
 		function = "system_bus";

arch/arm/dts/uniphier-pro4-ace.dts

@@ -73,11 +73,11 @@
 	status = "okay";
 };
 
-&usb0 {
+&usb2 {
 	status = "okay";
 };
 
-&usb1 {
+&usb3 {
 	status = "okay";
 };
 
@@ -92,10 +92,10 @@
 	};
 };
 
-&usb2 {
+&usb0 {
 	status = "okay";
 };
 
-&usb3 {
+&usb1 {
 	status = "okay";
 };

arch/arm/dts/uniphier-pro4-sanji.dts

@@ -68,11 +68,11 @@
 	status = "okay";
 };
 
-&usb0 {
+&usb2 {
 	status = "okay";
 };
 
-&usb1 {
+&usb3 {
 	status = "okay";
 };
 
@@ -87,10 +87,10 @@
 	};
 };
 
-&usb2 {
+&usb0 {
 	status = "okay";
 };
 
-&usb3 {
+&usb1 {
 	status = "okay";
 };

arch/arm/dts/uniphier-pro4.dtsi

@@ -71,6 +71,17 @@
 			cache-level = <2>;
 		};
 
+		spi0: spi@54006000 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006000 0x100>;
+			interrupts = <0 39 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi0>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -317,6 +328,8 @@
 				 <&mio_clk 12>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 				 <&mio_rst 12>;
+			phy-names = "usb";
+			phys = <&usb_phy0>;
 			has-transaction-translator;
 		};
 
@@ -331,6 +344,8 @@
 				 <&mio_clk 13>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 				 <&mio_rst 13>;
+			phy-names = "usb";
+			phys = <&usb_phy1>;
 			has-transaction-translator;
 		};
 
@@ -342,6 +357,34 @@
 			pinctrl: pinctrl {
 				compatible = "socionext,uniphier-pro4-pinctrl";
 			};
+
+			usb-phy {
+				compatible = "socionext,uniphier-pro4-usb2-phy";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				usb_phy0: phy@0 {
+					reg = <0>;
+					#phy-cells = <0>;
+				};
+
+				usb_phy1: phy@1 {
+					reg = <1>;
+					#phy-cells = <0>;
+				};
+
+				usb_phy2: phy@2 {
+					reg = <2>;
+					#phy-cells = <0>;
+					vbus-supply = <&usb0_vbus>;
+				};
+
+				usb_phy3: phy@3 {
+					reg = <3>;
+					#phy-cells = <0>;
+					vbus-supply = <&usb1_vbus>;
+				};
+			};
 		};
 
 		soc-glue@5f900000 {
@@ -434,6 +477,60 @@
 			};
 		};
 
+		_usb0: usb@65a00000 {
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+			status = "disabled";
+			reg = <0x65a00000 0xcd00>;
+			interrupt-names = "host", "peripheral";
+			interrupts = <0 134 4>, <0 135 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			clock-names = "ref", "bus_early", "suspend";
+			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+			resets = <&usb0_rst 4>;
+			phys = <&usb_phy2>, <&usb0_ssphy>;
+			dr_mode = "host";
+		};
+
+		usb-glue@65b00000 {
+			compatible = "socionext,uniphier-pro4-dwc3-glue",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x65b00000 0x100>;
+
+			usb0_vbus: regulator@0 {
+				compatible = "socionext,uniphier-pro4-usb3-regulator";
+				reg = <0 0x10>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 14>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 14>;
+			};
+
+			usb0_ssphy: ss-phy@10 {
+				compatible = "socionext,uniphier-pro4-usb3-ssphy";
+				reg = <0x10 0x10>;
+				#phy-cells = <0>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 14>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 14>;
+				vbus-supply = <&usb0_vbus>;
+			};
+
+			usb0_rst: reset@40 {
+				compatible = "socionext,uniphier-pro4-usb3-reset";
+				reg = <0x40 0x4>;
+				#reset-cells = <1>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 14>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 14>;
+			};
+		};
+
+		/* FIXME: U-Boot own node */
 		usb0: usb@65b00000 {
 			compatible = "socionext,uniphier-pro4-dwc3";
 			status = "disabled";
@@ -452,6 +549,49 @@
 			};
 		};
 
+		_usb1: usb@65c00000 {
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+			status = "disabled";
+			reg = <0x65c00000 0xcd00>;
+			interrupt-names = "host", "peripheral";
+			interrupts = <0 137 4>, <0 138 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			clock-names = "ref", "bus_early", "suspend";
+			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+			resets = <&usb1_rst 4>;
+			phys = <&usb_phy3>;
+			dr_mode = "host";
+		};
+
+		usb-glue@65d00000 {
+			compatible = "socionext,uniphier-pro4-dwc3-glue",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x65d00000 0x100>;
+
+			usb1_vbus: regulator@0 {
+				compatible = "socionext,uniphier-pro4-usb3-regulator";
+				reg = <0 0x10>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 15>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 15>;
+			};
+
+			usb1_rst: reset@40 {
+				compatible = "socionext,uniphier-pro4-usb3-reset";
+				reg = <0x40 0x4>;
+				#reset-cells = <1>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 15>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 15>;
+			};
+		};
+
+		/* FIXME: U-Boot own node */
 		usb1: usb@65d00000 {
 			compatible = "socionext,uniphier-pro4-dwc3";
 			status = "disabled";
@@ -478,7 +618,8 @@
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
-			clocks = <&sys_clk 2>;
+			clock-names = "nand", "nand_x", "ecc";
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 			resets = <&sys_rst 2>;
 		};
 	};

arch/arm/dts/uniphier-pro5.dtsi

@@ -156,6 +156,28 @@
 			cache-level = <3>;
 		};
 
+		spi0: spi@54006000 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006000 0x100>;
+			interrupts = <0 39 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi0>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
+		spi1: spi@54006100 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006100 0x100>;
+			interrupts = <0 216 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi1>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -475,7 +497,8 @@
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand2cs>;
-			clocks = <&sys_clk 2>;
+			clock-names = "nand", "nand_x", "ecc";
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 			resets = <&sys_rst 2>;
 		};
 

arch/arm/dts/uniphier-pxs2.dtsi

@@ -167,6 +167,28 @@
 			cache-level = <2>;
 		};
 
+		spi0: spi@54006000 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006000 0x100>;
+			interrupts = <0 39 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi0>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
+		spi1: spi@54006100 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006100 0x100>;
+			interrupts = <0 216 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi1>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -557,6 +579,103 @@
 			};
 		};
 
+		_usb0: usb@65a00000 {
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+			status = "disabled";
+			reg = <0x65a00000 0xcd00>;
+			interrupt-names = "host", "peripheral";
+			interrupts = <0 134 4>, <0 135 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+			clock-names = "ref", "bus_early", "suspend";
+			clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
+			resets = <&usb0_rst 15>;
+			phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
+			       <&usb0_ssphy0>, <&usb0_ssphy1>;
+			dr_mode = "host";
+		};
+
+		usb-glue@65b00000 {
+			compatible = "socionext,uniphier-pxs2-dwc3-glue",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x65b00000 0x400>;
+
+			usb0_rst: reset@0 {
+				compatible = "socionext,uniphier-pxs2-usb3-reset";
+				reg = <0x0 0x4>;
+				#reset-cells = <1>;
+				clock-names = "link";
+				clocks = <&sys_clk 14>;
+				reset-names = "link";
+				resets = <&sys_rst 14>;
+			};
+
+			usb0_vbus0: regulator@100 {
+				compatible = "socionext,uniphier-pxs2-usb3-regulator";
+				reg = <0x100 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 14>;
+				reset-names = "link";
+				resets = <&sys_rst 14>;
+			};
+
+			usb0_vbus1: regulator@110 {
+				compatible = "socionext,uniphier-pxs2-usb3-regulator";
+				reg = <0x110 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 14>;
+				reset-names = "link";
+				resets = <&sys_rst 14>;
+			};
+
+			usb0_hsphy0: hs-phy@200 {
+				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+				reg = <0x200 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 14>, <&sys_clk 16>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 14>, <&sys_rst 16>;
+				vbus-supply = <&usb0_vbus0>;
+			};
+
+			usb0_hsphy1: hs-phy@210 {
+				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+				reg = <0x210 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 14>, <&sys_clk 16>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 14>, <&sys_rst 16>;
+				vbus-supply = <&usb0_vbus1>;
+			};
+
+			usb0_ssphy0: ss-phy@300 {
+				compatible = "socionext,uniphier-pxs2-usb3-ssphy";
+				reg = <0x300 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 14>, <&sys_clk 17>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 14>, <&sys_rst 17>;
+				vbus-supply = <&usb0_vbus0>;
+			};
+
+			usb0_ssphy1: ss-phy@310 {
+				compatible = "socionext,uniphier-pxs2-usb3-ssphy";
+				reg = <0x310 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 14>, <&sys_clk 18>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 14>, <&sys_rst 18>;
+				vbus-supply = <&usb0_vbus1>;
+			};
+		};
+
+		/* FIXME: U-Boot own node */
 		usb0: usb@65b00000 {
 			compatible = "socionext,uniphier-pxs2-dwc3";
 			status = "disabled";
@@ -575,6 +694,91 @@
 			};
 		};
 
+		_usb1: usb@65c00000 {
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+			status = "disabled";
+			reg = <0x65c00000 0xcd00>;
+			interrupt-names = "host", "peripheral";
+			interrupts = <0 137 4>, <0 138 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+			clock-names = "ref", "bus_early", "suspend";
+			clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
+			resets = <&usb1_rst 15>;
+			phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
+			dr_mode = "host";
+		};
+
+		usb-glue@65d00000 {
+			compatible = "socionext,uniphier-pxs2-dwc3-glue",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x65d00000 0x400>;
+
+			usb1_rst: reset@0 {
+				compatible = "socionext,uniphier-pxs2-usb3-reset";
+				reg = <0x0 0x4>;
+				#reset-cells = <1>;
+				clock-names = "link";
+				clocks = <&sys_clk 15>;
+				reset-names = "link";
+				resets = <&sys_rst 15>;
+			};
+
+			usb1_vbus0: regulator@100 {
+				compatible = "socionext,uniphier-pxs2-usb3-regulator";
+				reg = <0x100 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 15>;
+				reset-names = "link";
+				resets = <&sys_rst 15>;
+			};
+
+			usb1_vbus1: regulator@110 {
+				compatible = "socionext,uniphier-pxs2-usb3-regulator";
+				reg = <0x110 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 15>;
+				reset-names = "link";
+				resets = <&sys_rst 15>;
+			};
+
+			usb1_hsphy0: hs-phy@200 {
+				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+				reg = <0x200 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 15>, <&sys_clk 20>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 15>, <&sys_rst 20>;
+				vbus-supply = <&usb1_vbus0>;
+			};
+
+			usb1_hsphy1: hs-phy@210 {
+				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+				reg = <0x210 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 15>, <&sys_clk 20>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 15>, <&sys_rst 20>;
+				vbus-supply = <&usb1_vbus1>;
+			};
+
+			usb1_ssphy0: ss-phy@300 {
+				compatible = "socionext,uniphier-pxs2-usb3-ssphy";
+				reg = <0x300 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 15>, <&sys_clk 21>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 15>, <&sys_rst 21>;
+				vbus-supply = <&usb1_vbus0>;
+			};
+		};
+
+		/* FIXME: U-Boot own node */
 		usb1: usb@65d00000 {
 			compatible = "socionext,uniphier-pxs2-dwc3";
 			status = "disabled";
@@ -601,7 +805,8 @@
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand2cs>;
-			clocks = <&sys_clk 2>;
+			clock-names = "nand", "nand_x", "ecc";
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 			resets = <&sys_rst 2>;
 		};
 	};

arch/arm/dts/uniphier-pxs3.dtsi

@@ -144,6 +144,28 @@
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
 
+		spi0: spi@54006000 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006000 0x100>;
+			interrupts = <0 39 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi0>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
+		spi1: spi@54006100 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006100 0x100>;
+			interrupts = <0 216 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi1>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -384,6 +406,50 @@
 			efuse@200 {
 				compatible = "socionext,uniphier-efuse";
 				reg = <0x200 0x68>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				/* USB cells */
+				usb_rterm0: trim@54,4 {
+					reg = <0x54 1>;
+					bits = <4 2>;
+				};
+				usb_rterm1: trim@55,4 {
+					reg = <0x55 1>;
+					bits = <4 2>;
+				};
+				usb_rterm2: trim@58,4 {
+					reg = <0x58 1>;
+					bits = <4 2>;
+				};
+				usb_rterm3: trim@59,4 {
+					reg = <0x59 1>;
+					bits = <4 2>;
+				};
+				usb_sel_t0: trim@54,0 {
+					reg = <0x54 1>;
+					bits = <0 4>;
+				};
+				usb_sel_t1: trim@55,0 {
+					reg = <0x55 1>;
+					bits = <0 4>;
+				};
+				usb_sel_t2: trim@58,0 {
+					reg = <0x58 1>;
+					bits = <0 4>;
+				};
+				usb_sel_t3: trim@59,0 {
+					reg = <0x59 1>;
+					bits = <0 4>;
+				};
+				usb_hs_i0: trim@56,0 {
+					reg = <0x56 1>;
+					bits = <0 4>;
+				};
+				usb_hs_i2: trim@5a,0 {
+					reg = <0x5a 1>;
+					bits = <0 4>;
+				};
 			};
 		};
 
@@ -465,6 +531,109 @@
 			};
 		};
 
+		_usb0: usb@65a00000 {
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+			status = "disabled";
+			reg = <0x65a00000 0xcd00>;
+			interrupt-names = "host", "peripheral";
+			interrupts = <0 134 4>, <0 135 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+			clock-names = "ref", "bus_early", "suspend";
+			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+			resets = <&usb0_rst 15>;
+			phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
+			       <&usb0_ssphy0>, <&usb0_ssphy1>;
+			dr_mode = "host";
+		};
+
+		usb-glue@65b00000 {
+			compatible = "socionext,uniphier-pxs3-dwc3-glue",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x65b00000 0x400>;
+
+			usb0_rst: reset@0 {
+				compatible = "socionext,uniphier-pxs3-usb3-reset";
+				reg = <0x0 0x4>;
+				#reset-cells = <1>;
+				clock-names = "link";
+				clocks = <&sys_clk 12>;
+				reset-names = "link";
+				resets = <&sys_rst 12>;
+			};
+
+			usb0_vbus0: regulator@100 {
+				compatible = "socionext,uniphier-pxs3-usb3-regulator";
+				reg = <0x100 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 12>;
+				reset-names = "link";
+				resets = <&sys_rst 12>;
+			};
+
+			usb0_vbus1: regulator@110 {
+				compatible = "socionext,uniphier-pxs3-usb3-regulator";
+				reg = <0x110 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 12>;
+				reset-names = "link";
+				resets = <&sys_rst 12>;
+			};
+
+			usb0_hsphy0: hs-phy@200 {
+				compatible = "socionext,uniphier-pxs3-usb3-hsphy";
+				reg = <0x200 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 12>, <&sys_clk 16>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 12>, <&sys_rst 16>;
+				vbus-supply = <&usb0_vbus0>;
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
+				nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
+					      <&usb_hs_i0>;
+			};
+
+			usb0_hsphy1: hs-phy@210 {
+				compatible = "socionext,uniphier-pxs3-usb3-hsphy";
+				reg = <0x210 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 12>, <&sys_clk 16>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 12>, <&sys_rst 16>;
+				vbus-supply = <&usb0_vbus1>;
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
+				nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
+					      <&usb_hs_i0>;
+			};
+
+			usb0_ssphy0: ss-phy@300 {
+				compatible = "socionext,uniphier-pxs3-usb3-ssphy";
+				reg = <0x300 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 12>, <&sys_clk 17>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 12>, <&sys_rst 17>;
+				vbus-supply = <&usb0_vbus0>;
+			};
+
+			usb0_ssphy1: ss-phy@310 {
+				compatible = "socionext,uniphier-pxs3-usb3-ssphy";
+				reg = <0x310 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy";
+				clocks = <&sys_clk 12>, <&sys_clk 18>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 12>, <&sys_rst 18>;
+				vbus-supply = <&usb0_vbus1>;
+			};
+		};
+
+		/* FIXME: U-Boot own node */
 		usb0: usb@65b00000 {
 			compatible = "socionext,uniphier-pxs3-dwc3";
 			status = "disabled";
@@ -483,6 +652,101 @@
 			};
 		};
 
+		_usb1: usb@65c00000 {
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+			status = "disabled";
+			reg = <0x65c00000 0xcd00>;
+			interrupt-names = "host", "peripheral";
+			interrupts = <0 137 4>, <0 138 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+			clock-names = "ref", "bus_early", "suspend";
+			clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
+			resets = <&usb1_rst 15>;
+			phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
+			       <&usb1_ssphy0>;
+			dr_mode = "host";
+		};
+
+		usb-glue@65d00000 {
+			compatible = "socionext,uniphier-pxs3-dwc3-glue",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x65d00000 0x400>;
+
+			usb1_rst: reset@0 {
+				compatible = "socionext,uniphier-pxs3-usb3-reset";
+				reg = <0x0 0x4>;
+				#reset-cells = <1>;
+				clock-names = "link";
+				clocks = <&sys_clk 13>;
+				reset-names = "link";
+				resets = <&sys_rst 13>;
+			};
+
+			usb1_vbus0: regulator@100 {
+				compatible = "socionext,uniphier-pxs3-usb3-regulator";
+				reg = <0x100 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 13>;
+				reset-names = "link";
+				resets = <&sys_rst 13>;
+			};
+
+			usb1_vbus1: regulator@110 {
+				compatible = "socionext,uniphier-pxs3-usb3-regulator";
+				reg = <0x110 0x10>;
+				clock-names = "link";
+				clocks = <&sys_clk 13>;
+				reset-names = "link";
+				resets = <&sys_rst 13>;
+			};
+
+			usb1_hsphy0: hs-phy@200 {
+				compatible = "socionext,uniphier-pxs3-usb3-hsphy";
+				reg = <0x200 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy", "phy-ext";
+				clocks = <&sys_clk 13>, <&sys_clk 20>,
+					 <&sys_clk 14>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 13>, <&sys_rst 20>;
+				vbus-supply = <&usb1_vbus0>;
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
+				nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
+					      <&usb_hs_i2>;
+			};
+
+			usb1_hsphy1: hs-phy@210 {
+				compatible = "socionext,uniphier-pxs3-usb3-hsphy";
+				reg = <0x210 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy", "phy-ext";
+				clocks = <&sys_clk 13>, <&sys_clk 20>,
+					 <&sys_clk 14>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 13>, <&sys_rst 20>;
+				vbus-supply = <&usb1_vbus1>;
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
+				nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
+					      <&usb_hs_i2>;
+			};
+
+			usb1_ssphy0: ss-phy@300 {
+				compatible = "socionext,uniphier-pxs3-usb3-ssphy";
+				reg = <0x300 0x10>;
+				#phy-cells = <0>;
+				clock-names = "link", "phy", "phy-ext";
+				clocks = <&sys_clk 13>, <&sys_clk 21>,
+					 <&sys_clk 14>;
+				reset-names = "link", "phy";
+				resets = <&sys_rst 13>, <&sys_rst 21>;
+				vbus-supply = <&usb1_vbus0>;
+			};
+		};
+
+		/* FIXME: U-Boot own node */
 		usb1: usb@65d00000 {
 			compatible = "socionext,uniphier-pxs3-dwc3";
 			status = "disabled";
@@ -509,7 +773,8 @@
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand>;
-			clocks = <&sys_clk 2>;
+			clock-names = "nand", "nand_x", "ecc";
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 			resets = <&sys_rst 2>;
 		};
 	};

arch/arm/dts/uniphier-sld8.dtsi

@@ -63,6 +63,17 @@
 			cache-level = <2>;
 		};
 
+		spi: spi@54006000 {
+			compatible = "socionext,uniphier-scssi";
+			status = "disabled";
+			reg = <0x54006000 0x100>;
+			interrupts = <0 39 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi0>;
+			clocks = <&peri_clk 11>;
+			resets = <&peri_rst 11>;
+		};
+
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -385,7 +396,8 @@
 			interrupts = <0 65 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_nand2cs>;
-			clocks = <&sys_clk 2>;
+			clock-names = "nand", "nand_x", "ecc";
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 			resets = <&sys_rst 2>;
 		};
 	};

arch/arm/dts/vf.dtsi

@@ -89,6 +89,12 @@
 				status = "disabled";
 			};
 
+			iomuxc: iomuxc@40048000 {
+				compatible = "fsl,vf610-iomuxc";
+				reg = <0x40048000 0x1000>;
+				fsl,mux_mask = <0x700000>;
+			};
+
 			gpio0: gpio@40049000 {
 				compatible = "fsl,vf610-gpio";
 				reg = <0x400ff000 0x40>;

arch/arm/dts/vf610-pinfunc.h

@@ -0,0 +1,810 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_VF610_PINFUNC_H
+#define __DTS_VF610_PINFUNC_H
+
+/*
+ * The pin function ID for VF610 is a tuple of:
+ * <mux_reg input_reg mux_mode input_val>
+ */
+
+#define ALT0	0x0
+#define ALT1	0x1
+#define ALT2	0x2
+#define ALT3	0x3
+#define ALT4	0x4
+#define ALT5	0x5
+#define ALT6	0x6
+#define ALT7	0x7
+
+
+#define VF610_PAD_PTA6__GPIO_0			0x000 0x000 ALT0 0x0
+#define VF610_PAD_PTA6__RMII_CLKOUT		0x000 0x000 ALT1 0x0
+#define VF610_PAD_PTA6__RMII_CLKIN		0x000 0x2F0 ALT2 0x0
+#define VF610_PAD_PTA6__DCU1_TCON11		0x000 0x000 ALT4 0x0
+#define VF610_PAD_PTA6__DCU1_R2			0x000 0x000 ALT7 0x0
+#define VF610_PAD_PTA8__GPIO_1			0x004 0x000 ALT0 0x0
+#define VF610_PAD_PTA8__TCLK			0x004 0x000 ALT1 0x0
+#define VF610_PAD_PTA8__DCU0_R0			0x004 0x000 ALT4 0x0
+#define VF610_PAD_PTA8__MLB_CLK			0x004 0x354 ALT7 0x0
+#define VF610_PAD_PTA9__GPIO_2			0x008 0x000 ALT0 0x0
+#define VF610_PAD_PTA9__TDI			0x008 0x000 ALT1 0x0
+#define VF610_PAD_PTA9__RMII_CLKOUT		0x008 0x000 ALT2 0x0
+#define VF610_PAD_PTA9__RMII_CLKIN		0x008 0x2F0 ALT3 0x1
+#define VF610_PAD_PTA9__DCU0_R1			0x008 0x000 ALT4 0x0
+#define VF610_PAD_PTA9__WDOG_B			0x008 0x000 ALT6 0x0
+#define VF610_PAD_PTA10__GPIO_3			0x00C 0x000 ALT0 0x0
+#define VF610_PAD_PTA10__TDO			0x00C 0x000 ALT1 0x0
+#define VF610_PAD_PTA10__EXT_AUDIO_MCLK		0x00C 0x2EC ALT2 0x0
+#define VF610_PAD_PTA10__DCU0_G0		0x00C 0x000 ALT4 0x0
+#define VF610_PAD_PTA10__ENET_TS_CLKIN		0x00C 0x2F4 ALT6 0x0
+#define VF610_PAD_PTA10__MLB_SIGNAL		0x00C 0x35C ALT7 0x0
+#define VF610_PAD_PTA11__GPIO_4			0x010 0x000 ALT0 0x0
+#define VF610_PAD_PTA11__TMS			0x010 0x000 ALT1 0x0
+#define VF610_PAD_PTA11__DCU0_G1		0x010 0x000 ALT4 0x0
+#define VF610_PAD_PTA11__MLB_DATA		0x010 0x358 ALT7 0x0
+#define VF610_PAD_PTA12__GPIO_5			0x014 0x000 ALT0 0x0
+#define VF610_PAD_PTA12__TRACECK		0x014 0x000 ALT1 0x0
+#define VF610_PAD_PTA12__EXT_AUDIO_MCLK		0x014 0x2EC ALT2 0x1
+#define VF610_PAD_PTA12__VIU_DATA13		0x014 0x000 ALT6 0x0
+#define VF610_PAD_PTA12__I2C0_SCL		0x014 0x33C ALT7 0x0
+#define VF610_PAD_PTA16__GPIO_6			0x018 0x000 ALT0 0x0
+#define VF610_PAD_PTA16__TRACED0		0x018 0x000 ALT1 0x0
+#define VF610_PAD_PTA16__USB0_VBUS_EN		0x018 0x000 ALT2 0x0
+#define VF610_PAD_PTA16__ADC1_SE0		0x018 0x000 ALT3 0x0
+#define VF610_PAD_PTA16__LCD29			0x018 0x000 ALT4 0x0
+#define VF610_PAD_PTA16__SAI2_TX_BCLK		0x018 0x370 ALT5 0x0
+#define VF610_PAD_PTA16__VIU_DATA14		0x018 0x000 ALT6 0x0
+#define VF610_PAD_PTA16__I2C0_SDA		0x018 0x340 ALT7 0x0
+#define VF610_PAD_PTA17__GPIO_7			0x01C 0x000 ALT0 0x0
+#define VF610_PAD_PTA17__TRACED1		0x01C 0x000 ALT1 0x0
+#define VF610_PAD_PTA17__USB0_VBUS_OC		0x01C 0x000 ALT2 0x0
+#define VF610_PAD_PTA17__ADC1_SE1		0x01C 0x000 ALT3 0x0
+#define VF610_PAD_PTA17__LCD30			0x01C 0x000 ALT4 0x0
+#define VF610_PAD_PTA17__USB0_SOF_PULSE		0x01C 0x000 ALT5 0x0
+#define VF610_PAD_PTA17__VIU_DATA15		0x01C 0x000 ALT6 0x0
+#define VF610_PAD_PTA17__I2C1_SCL		0x01C 0x344 ALT7 0x0
+#define VF610_PAD_PTA18__GPIO_8			0x020 0x000 ALT0 0x0
+#define VF610_PAD_PTA18__TRACED2		0x020 0x000 ALT1 0x0
+#define VF610_PAD_PTA18__ADC0_SE0		0x020 0x000 ALT2 0x0
+#define VF610_PAD_PTA18__FTM1_QD_PHA		0x020 0x334 ALT3 0x0
+#define VF610_PAD_PTA18__LCD31			0x020 0x000 ALT4 0x0
+#define VF610_PAD_PTA18__SAI2_TX_DATA		0x020 0x000 ALT5 0x0
+#define VF610_PAD_PTA18__VIU_DATA16		0x020 0x000 ALT6 0x0
+#define VF610_PAD_PTA18__I2C1_SDA		0x020 0x348 ALT7 0x0
+#define VF610_PAD_PTA19__GPIO_9			0x024 0x000 ALT0 0x0
+#define VF610_PAD_PTA19__TRACED3		0x024 0x000 ALT1 0x0
+#define VF610_PAD_PTA19__ADC0_SE1		0x024 0x000 ALT2 0x0
+#define VF610_PAD_PTA19__FTM1_QD_PHB		0x024 0x338 ALT3 0x0
+#define VF610_PAD_PTA19__LCD32			0x024 0x000 ALT4 0x0
+#define VF610_PAD_PTA19__SAI2_TX_SYNC		0x024 0x000 ALT5 0x0
+#define VF610_PAD_PTA19__VIU_DATA17		0x024 0x000 ALT6 0x0
+#define VF610_PAD_PTA19__QSPI1_A_QSCK		0x024 0x374 ALT7 0x0
+#define VF610_PAD_PTA20__GPIO_10		0x028 0x000 ALT0 0x0
+#define VF610_PAD_PTA20__TRACED4		0x028 0x000 ALT1 0x0
+#define VF610_PAD_PTA20__LCD33			0x028 0x000 ALT4 0x0
+#define VF610_PAD_PTA20__UART3_TX		0x028 0x394 ALT6 0x0
+#define VF610_PAD_PTA20__DCU1_HSYNC		0x028 0x000 ALT7 0x0
+#define VF610_PAD_PTA21__GPIO_11		0x02C 0x000 ALT0 0x0
+#define VF610_PAD_PTA21__TRACED5		0x02C 0x000 ALT1 0x0
+#define VF610_PAD_PTA21__SAI2_RX_BCLK		0x02C 0x364 ALT5 0x0
+#define VF610_PAD_PTA21__UART3_RX		0x02C 0x390 ALT6 0x0
+#define VF610_PAD_PTA21__DCU1_VSYNC		0x02C 0x000 ALT7 0x0
+#define VF610_PAD_PTA22__GPIO_12		0x030 0x000 ALT0 0x0
+#define VF610_PAD_PTA22__TRACED6		0x030 0x000 ALT1 0x0
+#define VF610_PAD_PTA22__SAI2_RX_DATA		0x030 0x368 ALT5 0x0
+#define VF610_PAD_PTA22__I2C2_SCL		0x030 0x34C ALT6 0x0
+#define VF610_PAD_PTA22__DCU1_TAG		0x030 0x000 ALT7 0x0
+#define VF610_PAD_PTA23__GPIO_13		0x034 0x000 ALT0 0x0
+#define VF610_PAD_PTA23__TRACED7		0x034 0x000 ALT1 0x0
+#define VF610_PAD_PTA23__SAI2_RX_SYNC		0x034 0x36C ALT5 0x0
+#define VF610_PAD_PTA23__I2C2_SDA		0x034 0x350 ALT6 0x0
+#define VF610_PAD_PTA23__DCU1_DE		0x034 0x000 ALT7 0x0
+#define VF610_PAD_PTA24__GPIO_14		0x038 0x000 ALT0 0x0
+#define VF610_PAD_PTA24__TRACED8		0x038 0x000 ALT1 0x0
+#define VF610_PAD_PTA24__USB1_VBUS_EN		0x038 0x000 ALT2 0x0
+#define VF610_PAD_PTA24__ESDHC1_CLK		0x038 0x000 ALT5 0x0
+#define VF610_PAD_PTA24__DCU1_TCON4		0x038 0x000 ALT6 0x0
+#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL	0x038 0x000 ALT7 0x0
+#define VF610_PAD_PTA25__GPIO_15		0x03C 0x000 ALT0 0x0
+#define VF610_PAD_PTA25__TRACED9		0x03C 0x000 ALT1 0x0
+#define VF610_PAD_PTA25__USB1_VBUS_OC		0x03C 0x000 ALT2 0x0
+#define VF610_PAD_PTA25__ESDHC1_CMD		0x03C 0x000 ALT5 0x0
+#define VF610_PAD_PTA25__DCU1_TCON5		0x03C 0x000 ALT6 0x0
+#define VF610_PAD_PTA26__GPIO_16		0x040 0x000 ALT0 0x0
+#define VF610_PAD_PTA26__TRACED10		0x040 0x000 ALT1 0x0
+#define VF610_PAD_PTA26__SAI3_TX_BCLK		0x040 0x000 ALT2 0x0
+#define VF610_PAD_PTA26__ESDHC1_DAT0		0x040 0x000 ALT5 0x0
+#define VF610_PAD_PTA26__DCU1_TCON6		0x040 0x000 ALT6 0x0
+#define VF610_PAD_PTA27__GPIO_17		0x044 0x000 ALT0 0x0
+#define VF610_PAD_PTA27__TRACED11		0x044 0x000 ALT1 0x0
+#define VF610_PAD_PTA27__SAI3_RX_BCLK		0x044 0x000 ALT2 0x0
+#define VF610_PAD_PTA27__ESDHC1_DAT1		0x044 0x000 ALT5 0x0
+#define VF610_PAD_PTA27__DCU1_TCON7		0x044 0x000 ALT6 0x0
+#define VF610_PAD_PTA28__GPIO_18		0x048 0x000 ALT0 0x0
+#define VF610_PAD_PTA28__TRACED12		0x048 0x000 ALT1 0x0
+#define VF610_PAD_PTA28__SAI3_RX_DATA		0x048 0x000 ALT2 0x0
+#define VF610_PAD_PTA28__ENET1_1588_TMR0	0x048 0x000 ALT3 0x0
+#define VF610_PAD_PTA28__UART4_TX		0x048 0x000 ALT4 0x0
+#define VF610_PAD_PTA28__ESDHC1_DATA2		0x048 0x000 ALT5 0x0
+#define VF610_PAD_PTA28__DCU1_TCON8		0x048 0x000 ALT6 0x0
+#define VF610_PAD_PTA29__GPIO_19		0x04C 0x000 ALT0 0x0
+#define VF610_PAD_PTA29__TRACED13		0x04C 0x000 ALT1 0x0
+#define VF610_PAD_PTA29__SAI3_TX_DATA		0x04C 0x000 ALT2 0x0
+#define VF610_PAD_PTA29__ENET1_1588_TMR1	0x04C 0x000 ALT3 0x0
+#define VF610_PAD_PTA29__UART4_RX		0x04C 0x000 ALT4 0x0
+#define VF610_PAD_PTA29__ESDHC1_DAT3		0x04C 0x000 ALT5 0x0
+#define VF610_PAD_PTA29__DCU1_TCON9		0x04C 0x000 ALT6 0x0
+#define VF610_PAD_PTA30__GPIO_20		0x050 0x000 ALT0 0x0
+#define VF610_PAD_PTA30__TRACED14		0x050 0x000 ALT1 0x0
+#define VF610_PAD_PTA30__SAI3_RX_SYNC		0x050 0x000 ALT2 0x0
+#define VF610_PAD_PTA30__ENET1_1588_TMR2	0x050 0x000 ALT3 0x0
+#define VF610_PAD_PTA30__UART4_RTS		0x050 0x000 ALT4 0x0
+#define VF610_PAD_PTA30__I2C3_SCL		0x050 0x000 ALT5 0x0
+#define VF610_PAD_PTA30__UART3_TX		0x050 0x394 ALT7 0x1
+#define VF610_PAD_PTA31__GPIO_21		0x054 0x000 ALT0 0x0
+#define VF610_PAD_PTA31__TRACED15		0x054 0x000 ALT1 0x0
+#define VF610_PAD_PTA31__SAI3_TX_SYNC		0x054 0x000 ALT2 0x0
+#define VF610_PAD_PTA31__ENET1_1588_TMR3	0x054 0x000 ALT3 0x0
+#define VF610_PAD_PTA31__UART4_CTS		0x054 0x000 ALT4 0x0
+#define VF610_PAD_PTA31__I2C3_SDA		0x054 0x000 ALT5 0x0
+#define VF610_PAD_PTA31__UART3_RX		0x054 0x390 ALT7 0x1
+#define VF610_PAD_PTB0__GPIO_22			0x058 0x000 ALT0 0x0
+#define VF610_PAD_PTB0__FTM0_CH0		0x058 0x000 ALT1 0x0
+#define VF610_PAD_PTB0__ADC0_SE2		0x058 0x000 ALT2 0x0
+#define VF610_PAD_PTB0__TRACE_CTL		0x058 0x000 ALT3 0x0
+#define VF610_PAD_PTB0__LCD34			0x058 0x000 ALT4 0x0
+#define VF610_PAD_PTB0__SAI2_RX_BCLK		0x058 0x364 ALT5 0x1
+#define VF610_PAD_PTB0__VIU_DATA18		0x058 0x000 ALT6 0x0
+#define VF610_PAD_PTB0__QSPI1_A_QPCS0		0x058 0x000 ALT7 0x0
+#define VF610_PAD_PTB1__GPIO_23			0x05C 0x000 ALT0 0x0
+#define VF610_PAD_PTB1__FTM0_CH1		0x05C 0x000 ALT1 0x0
+#define VF610_PAD_PTB1__ADC0_SE3		0x05C 0x000 ALT2 0x0
+#define VF610_PAD_PTB1__SRC_RCON30		0x05C 0x000 ALT3 0x0
+#define VF610_PAD_PTB1__LCD35			0x05C 0x000 ALT4 0x0
+#define VF610_PAD_PTB1__SAI2_RX_DATA		0x05C 0x368 ALT5 0x1
+#define VF610_PAD_PTB1__VIU_DATA19		0x05C 0x000 ALT6 0x0
+#define VF610_PAD_PTB1__QSPI1_A_DATA3		0x05C 0x000 ALT7 0x0
+#define VF610_PAD_PTB2__GPIO_24			0x060 0x000 ALT0 0x0
+#define VF610_PAD_PTB2__FTM0_CH2		0x060 0x000 ALT1 0x0
+#define VF610_PAD_PTB2__ADC1_SE2		0x060 0x000 ALT2 0x0
+#define VF610_PAD_PTB2__SRC_RCON31		0x060 0x000 ALT3 0x0
+#define VF610_PAD_PTB2__LCD36			0x060 0x000 ALT4 0x0
+#define VF610_PAD_PTB2__SAI2_RX_SYNC		0x060 0x36C ALT5 0x1
+#define VF610_PAD_PTB2__VIDEO_IN0_DATA20	0x060 0x000 ALT6 0x0
+#define VF610_PAD_PTB2__QSPI1_A_DATA2		0x060 0x000 ALT7 0x0
+#define VF610_PAD_PTB3__GPIO_25			0x064 0x000 ALT0 0x0
+#define VF610_PAD_PTB3__FTM0_CH3		0x064 0x000 ALT1 0x0
+#define VF610_PAD_PTB3__ADC1_SE3		0x064 0x000 ALT2 0x0
+#define VF610_PAD_PTB3__PDB_EXTRIG		0x064 0x000 ALT3 0x0
+#define VF610_PAD_PTB3__LCD37			0x064 0x000 ALT4 0x0
+#define VF610_PAD_PTB3__VIU_DATA21		0x064 0x000 ALT6 0x0
+#define VF610_PAD_PTB3__QSPI1_A_DATA1		0x064 0x000 ALT7 0x0
+#define VF610_PAD_PTB4__GPIO_26			0x068 0x000 ALT0 0x0
+#define VF610_PAD_PTB4__FTM0_CH4		0x068 0x000 ALT1 0x0
+#define VF610_PAD_PTB4__UART1_TX		0x068 0x380 ALT2 0x0
+#define VF610_PAD_PTB4__ADC0_SE4		0x068 0x000 ALT3 0x0
+#define VF610_PAD_PTB4__LCD38			0x068 0x000 ALT4 0x0
+#define VF610_PAD_PTB4__VIU_FID			0x068 0x3A8 ALT5 0x0
+#define VF610_PAD_PTB4__VIU_DATA22		0x068 0x000 ALT6 0x0
+#define VF610_PAD_PTB4__QSPI1_A_DATA0		0x068 0x000 ALT7 0x0
+#define VF610_PAD_PTB5__GPIO_27			0x06C 0x000 ALT0 0x0
+#define VF610_PAD_PTB5__FTM0_CH5		0x06C 0x000 ALT1 0x0
+#define VF610_PAD_PTB5__UART1_RX		0x06C 0x37C ALT2 0x0
+#define VF610_PAD_PTB5__ADC1_SE4		0x06C 0x000 ALT3 0x0
+#define VF610_PAD_PTB5__LCD39			0x06C 0x000 ALT4 0x0
+#define VF610_PAD_PTB5__VIU_DE			0x06C 0x3A4 ALT5 0x0
+#define VF610_PAD_PTB5__QSPI1_A_DQS		0x06C 0x000 ALT7 0x0
+#define VF610_PAD_PTB6__GPIO_28			0x070 0x000 ALT0 0x0
+#define VF610_PAD_PTB6__FTM0_CH6		0x070 0x000 ALT1 0x0
+#define VF610_PAD_PTB6__UART1_RTS		0x070 0x000 ALT2 0x0
+#define VF610_PAD_PTB6__QSPI0_QPCS1_A		0x070 0x000 ALT3 0x0
+#define VF610_PAD_PTB6__LCD_LCD40		0x070 0x000 ALT4 0x0
+#define VF610_PAD_PTB6__FB_CLKOUT		0x070 0x000 ALT5 0x0
+#define VF610_PAD_PTB6__VIU_HSYNC		0x070 0x000 ALT6 0x0
+#define VF610_PAD_PTB6__UART2_TX		0x070 0x38C ALT7 0x0
+#define VF610_PAD_PTB7__GPIO_29			0x074 0x000 ALT0 0x0
+#define VF610_PAD_PTB7__FTM0_CH7		0x074 0x000 ALT1 0x0
+#define VF610_PAD_PTB7__UART1_CTS		0x074 0x378 ALT2 0x0
+#define VF610_PAD_PTB7__QSPI0_B_QPCS1		0x074 0x000 ALT3 0x0
+#define VF610_PAD_PTB7__LCD41			0x074 0x000 ALT4 0x0
+#define VF610_PAD_PTB7__VIU_VSYNC		0x074 0x000 ALT6 0x0
+#define VF610_PAD_PTB7__UART2_RX		0x074 0x388 ALT7 0x0
+#define VF610_PAD_PTB8__GPIO_30			0x078 0x000 ALT0 0x0
+#define VF610_PAD_PTB8__FTM1_CH0		0x078 0x32C ALT1 0x0
+#define VF610_PAD_PTB8__FTM1_QD_PHA		0x078 0x334 ALT3 0x1
+#define VF610_PAD_PTB8__VIU_DE			0x078 0x3A4 ALT5 0x1
+#define VF610_PAD_PTB8__DCU1_R6			0x078 0x000 ALT7 0x0
+#define VF610_PAD_PTB9__GPIO_31			0x07C 0x000 ALT0 0x0
+#define VF610_PAD_PTB9__FTM1_CH1		0x07C 0x330 ALT1 0x0
+#define VF610_PAD_PTB9__FTM1_QD_PHB		0x07C 0x338 ALT3 0x1
+#define VF610_PAD_PTB9__DCU1_R7			0x07C 0x000 ALT7 0x0
+#define VF610_PAD_PTB10__GPIO_32		0x080 0x000 ALT0 0x0
+#define VF610_PAD_PTB10__UART0_TX		0x080 0x000 ALT1 0x0
+#define VF610_PAD_PTB10__DCU0_TCON4		0x080 0x000 ALT4 0x0
+#define VF610_PAD_PTB10__VIU_DE			0x080 0x3A4 ALT5 0x2
+#define VF610_PAD_PTB10__CKO1			0x080 0x000 ALT6 0x0
+#define VF610_PAD_PTB10__ENET_TS_CLKIN		0x080 0x2F4 ALT7 0x1
+#define VF610_PAD_PTB11__GPIO_33		0x084 0x000 ALT0 0x0
+#define VF610_PAD_PTB11__UART0_RX		0x084 0x000 ALT1 0x0
+#define VF610_PAD_PTB11__DCU0_TCON5		0x084 0x000 ALT4 0x0
+#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B	0x084 0x000 ALT5 0x0
+#define VF610_PAD_PTB11__CKO2			0x084 0x000 ALT6 0x0
+#define VF610_PAD_PTB11_ENET0_1588_TMR0		0x084 0x304 ALT7 0x0
+#define VF610_PAD_PTB12__GPIO_34		0x088 0x000 ALT0 0x0
+#define VF610_PAD_PTB12__UART0_RTS		0x088 0x000 ALT1 0x0
+#define VF610_PAD_PTB12__DSPI0_CS5		0x088 0x000 ALT3 0x0
+#define VF610_PAD_PTB12__DCU0_TCON6		0x088 0x000 ALT4 0x0
+#define VF610_PAD_PTB12__FB_AD1			0x088 0x000 ALT5 0x0
+#define VF610_PAD_PTB12__NMI			0x088 0x000 ALT6 0x0
+#define VF610_PAD_PTB12__ENET0_1588_TMR1	0x088 0x308 ALT7 0x0
+#define VF610_PAD_PTB13__GPIO_35		0x08C 0x000 ALT0 0x0
+#define VF610_PAD_PTB13__UART0_CTS		0x08C 0x000 ALT1 0x0
+#define VF610_PAD_PTB13__DSPI0_CS4		0x08C 0x000 ALT3 0x0
+#define VF610_PAD_PTB13__DCU0_TCON7		0x08C 0x000 ALT4 0x0
+#define VF610_PAD_PTB13__FB_AD0			0x08C 0x000 ALT5 0x0
+#define VF610_PAD_PTB13__TRACE_CTL		0x08C 0x000 ALT6 0x0
+#define VF610_PAD_PTB14__GPIO_36		0x090 0x000 ALT0 0x0
+#define VF610_PAD_PTB14__CAN0_RX		0x090 0x000 ALT1 0x0
+#define VF610_PAD_PTB14__I2C0_SCL		0x090 0x33C ALT2 0x1
+#define VF610_PAD_PTB14__DCU0_TCON8		0x090 0x000 ALT4 0x0
+#define VF610_PAD_PTB14__DCU1_PCLK		0x090 0x000 ALT7 0x0
+#define VF610_PAD_PTB15__GPIO_37		0x094 0x000 ALT0 0x0
+#define VF610_PAD_PTB15__CAN0_TX		0x094 0x000 ALT1 0x0
+#define VF610_PAD_PTB15__I2C0_SDA		0x094 0x340 ALT2 0x1
+#define VF610_PAD_PTB15__DCU0_TCON9		0x094 0x000 ALT4 0x0
+#define VF610_PAD_PTB15__VIU_PIX_CLK		0x094 0x3AC ALT7 0x0
+#define VF610_PAD_PTB16__GPIO_38		0x098 0x000 ALT0 0x0
+#define VF610_PAD_PTB16__CAN1_RX		0x098 0x000 ALT1 0x0
+#define VF610_PAD_PTB16__I2C1_SCL		0x098 0x344 ALT2 0x1
+#define VF610_PAD_PTB16__DCU0_TCON10		0x098 0x000 ALT4 0x0
+#define VF610_PAD_PTB17__GPIO_39		0x09C 0x000 ALT0 0x0
+#define VF610_PAD_PTB17__CAN1_TX		0x09C 0x000 ALT1 0x0
+#define VF610_PAD_PTB17__I2C1_SDA		0x09C 0x348 ALT2 0x1
+#define VF610_PAD_PTB17__DCU0_TCON11		0x09C 0x000 ALT4 0x0
+#define VF610_PAD_PTB18__GPIO_40		0x0A0 0x000 ALT0 0x0
+#define VF610_PAD_PTB18__DSPI0_CS1		0x0A0 0x000 ALT1 0x0
+#define VF610_PAD_PTB18__EXT_AUDIO_MCLK		0x0A0 0x2EC ALT2 0x2
+#define VF610_PAD_PTB18__VIU_DATA9		0x0A0 0x000 ALT6 0x0
+#define VF610_PAD_PTB19__GPIO_41		0x0A4 0x000 ALT0 0x0
+#define VF610_PAD_PTB19__DSPI0_CS0		0x0A4 0x000 ALT1 0x0
+#define VF610_PAD_PTB19__VIU_DATA10		0x0A4 0x000 ALT6 0x0
+#define VF610_PAD_PTB20__GPIO_42		0x0A8 0x000 ALT0 0x0
+#define VF610_PAD_PTB20__DSPI0_SIN		0x0A8 0x000 ALT1 0x0
+#define VF610_PAD_PTB20__LCD42			0x0A8 0x000 ALT4 0x0
+#define VF610_PAD_PTB20__VIU_DATA11		0x0A8 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__GPIO_43		0x0AC 0x000 ALT0 0x0
+#define VF610_PAD_PTB21__DSPI0_SOUT		0x0AC 0x000 ALT1 0x0
+#define VF610_PAD_PTB21__LCD43			0x0AC 0x000 ALT4 0x0
+#define VF610_PAD_PTB21__VIU_DATA12		0x0AC 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__DCU1_PCLK		0x0AC 0x000 ALT7 0x0
+#define VF610_PAD_PTB22__GPIO_44		0x0B0 0x000 ALT0 0x0
+#define VF610_PAD_PTB22__DSPI0_SCK		0x0B0 0x000 ALT1 0x0
+#define VF610_PAD_PTB22__VLCD			0x0B0 0x000 ALT4 0x0
+#define VF610_PAD_PTB22__VIU_FID		0x0B0 0x3A8 ALT5 0x1
+#define VF610_PAD_PTC0__GPIO_45			0x0B4 0x000 ALT0 0x0
+#define VF610_PAD_PTC0__ENET_RMII0_MDC		0x0B4 0x000 ALT1 0x0
+#define VF610_PAD_PTC0__FTM1_CH0		0x0B4 0x32C ALT2 0x1
+#define VF610_PAD_PTC0__DSPI0_CS3		0x0B4 0x000 ALT3 0x0
+#define VF610_PAD_PTC0__ESAI_SCKT		0x0B4 0x310 ALT4 0x0
+#define VF610_PAD_PTC0__ESDHC0_CLK		0x0B4 0x000 ALT5 0x0
+#define VF610_PAD_PTC0__VIU_DATA0		0x0B4 0x000 ALT6 0x0
+#define VF610_PAD_PTC0__SRC_RCON18		0x0B4 0x398 ALT7 0x0
+#define VF610_PAD_PTC1__GPIO_46			0x0B8 0x000 ALT0 0x0
+#define VF610_PAD_PTC1__ENET_RMII0_MDIO		0x0B8 0x000 ALT1 0x0
+#define VF610_PAD_PTC1__FTM1_CH1		0x0B8 0x330 ALT2 0x1
+#define VF610_PAD_PTC1__DSPI0_CS2		0x0B8 0x000 ALT3 0x0
+#define VF610_PAD_PTC1__ESAI_FST		0x0B8 0x30C ALT4 0x0
+#define VF610_PAD_PTC1__ESDHC0_CMD		0x0B8 0x000 ALT5 0x0
+#define VF610_PAD_PTC1__VIU_DATA1		0x0B8 0x000 ALT6 0x0
+#define VF610_PAD_PTC1__SRC_RCON19		0x0B8 0x39C ALT7 0x0
+#define VF610_PAD_PTC2__GPIO_47			0x0BC 0x000 ALT0 0x0
+#define VF610_PAD_PTC2__ENET_RMII0_CRS		0x0BC 0x000 ALT1 0x0
+#define VF610_PAD_PTC2__UART1_TX		0x0BC 0x380 ALT2 0x1
+#define VF610_PAD_PTC2__ESAI_SDO0		0x0BC 0x314 ALT4 0x0
+#define VF610_PAD_PTC2__ESDHC0_DAT0		0x0BC 0x000 ALT5 0x0
+#define VF610_PAD_PTC2__VIU_DATA2		0x0BC 0x000 ALT6 0x0
+#define VF610_PAD_PTC2__SRC_RCON20		0x0BC 0x3A0 ALT7 0x0
+#define VF610_PAD_PTC3__GPIO_48			0x0C0 0x000 ALT0 0x0
+#define VF610_PAD_PTC3__ENET_RMII0_RXD1		0x0C0 0x000 ALT1 0x0
+#define VF610_PAD_PTC3__UART1_RX		0x0C0 0x37C ALT2 0x1
+#define VF610_PAD_PTC3__ESAI_SDO1		0x0C0 0x318 ALT4 0x0
+#define VF610_PAD_PTC3__ESDHC0_DAT1		0x0C0 0x000 ALT5 0x0
+#define VF610_PAD_PTC3__VIU_DATA3		0x0C0 0x000 ALT6 0x0
+#define VF610_PAD_PTC3__DCU0_R0			0x0C0 0x000 ALT7 0x0
+#define VF610_PAD_PTC4__GPIO_49			0x0C4 0x000 ALT0 0x0
+#define VF610_PAD_PTC4__ENET_RMII0_RXD0		0x0C4 0x000 ALT1 0x0
+#define VF610_PAD_PTC4__UART1_RTS		0x0C4 0x000 ALT2 0x0
+#define VF610_PAD_PTC4__DSPI1_CS1		0x0C4 0x000 ALT3 0x0
+#define VF610_PAD_PTC4__ESAI_SDO2		0x0C4 0x31C ALT4 0x0
+#define VF610_PAD_PTC4__ESDHC0_DAT2		0x0C4 0x000 ALT5 0x0
+#define VF610_PAD_PTC4__VIU_DATA4		0x0C4 0x000 ALT6 0x0
+#define VF610_PAD_PTC4__DCU0_R1			0x0C4 0x000 ALT7 0x0
+#define VF610_PAD_PTC5__GPIO_50			0x0C8 0x000 ALT0 0x0
+#define VF610_PAD_PTC5__ENET_RMII0_RXER		0x0C8 0x000 ALT1 0x0
+#define VF610_PAD_PTC5__UART1_CTS		0x0C8 0x378 ALT2 0x1
+#define VF610_PAD_PTC5__DSPI1_CS0		0x0C8 0x300 ALT3 0x0
+#define VF610_PAD_PTC5__ESAI_SDO3		0x0C8 0x320 ALT4 0x0
+#define VF610_PAD_PTC5__ESDHC0_DAT3		0x0C8 0x000 ALT5 0x0
+#define VF610_PAD_PTC5__VIU_DATA5		0x0C8 0x000 ALT6 0x0
+#define VF610_PAD_PTC5__DCU0_G0			0x0C8 0x000 ALT7 0x0
+#define VF610_PAD_PTC6__GPIO_51			0x0CC 0x000 ALT0 0x0
+#define VF610_PAD_PTC6__ENET_RMII0_TXD1		0x0CC 0x000 ALT1 0x0
+#define VF610_PAD_PTC6__DSPI1_SIN		0x0CC 0x2FC ALT3 0x0
+#define VF610_PAD_PTC6__ESAI_SDI0		0x0CC 0x328 ALT4 0x0
+#define VF610_PAD_PTC6__ESDHC0_WP		0x0CC 0x000 ALT5 0x0
+#define VF610_PAD_PTC6__VIU_DATA6		0x0CC 0x000 ALT6 0x0
+#define VF610_PAD_PTC6__DCU0_G1			0x0CC 0x000 ALT7 0x0
+#define VF610_PAD_PTC7__GPIO_52			0x0D0 0x000 ALT0 0x0
+#define VF610_PAD_PTC7__ENET_RMII0_TXD0		0x0D0 0x000 ALT1 0x0
+#define VF610_PAD_PTC7__DSPI1_SOUT		0x0D0 0x000 ALT3 0x0
+#define VF610_PAD_PTC7__ESAI_SDI1		0x0D0 0x324 ALT4 0x0
+#define VF610_PAD_PTC7__VIU_DATA7		0x0D0 0x000 ALT6 0x0
+#define VF610_PAD_PTC7__DCU0_B0			0x0D0 0x000 ALT7 0x0
+#define VF610_PAD_PTC8__GPIO_53			0x0D4 0x000 ALT0 0x0
+#define VF610_PAD_PTC8__ENET_RMII0_TXEN		0x0D4 0x000 ALT1 0x0
+#define VF610_PAD_PTC8__DSPI1_SCK		0x0D4 0x2F8 ALT3 0x0
+#define VF610_PAD_PTC8__VIU_DATA8		0x0D4 0x000 ALT6 0x0
+#define VF610_PAD_PTC8__DCU0_B1			0x0D4 0x000 ALT7 0x0
+#define VF610_PAD_PTC9__GPIO_54			0x0D8 0x000 ALT0 0x0
+#define VF610_PAD_PTC9__ENET_RMII1_MDC		0x0D8 0x000 ALT1 0x0
+#define VF610_PAD_PTC9__ESAI_SCKT		0x0D8 0x310 ALT3 0x1
+#define VF610_PAD_PTC9__MLB_CLK			0x0D8 0x354 ALT6 0x1
+#define VF610_PAD_PTC9__DEBUG_OUT0		0x0D8 0x000 ALT7 0x0
+#define VF610_PAD_PTC10__GPIO_55		0x0DC 0x000 ALT0 0x0
+#define VF610_PAD_PTC10__ENET_RMII1_MDIO	0x0DC 0x000 ALT1 0x0
+#define VF610_PAD_PTC10__ESAI_FST		0x0DC 0x30C ALT3 0x1
+#define VF610_PAD_PTC10__MLB_SIGNAL		0x0DC 0x35C ALT6 0x1
+#define VF610_PAD_PTC10__DEBUG_OUT1		0x0DC 0x000 ALT7 0x0
+#define VF610_PAD_PTC11__GPIO_56		0x0E0 0x000 ALT0 0x0
+#define VF610_PAD_PTC11__ENET_RMII1_CRS		0x0E0 0x000 ALT1 0x0
+#define VF610_PAD_PTC11__ESAI_SDO0		0x0E0 0x314 ALT3 0x1
+#define VF610_PAD_PTC11__MLB_DATA		0x0E0 0x358 ALT6 0x1
+#define VF610_PAD_PTC11__DEBUG_OUT		0x0E0 0x000 ALT7 0x0
+#define VF610_PAD_PTC12__GPIO_57		0x0E4 0x000 ALT0 0x0
+#define VF610_PAD_PTC12__ENET_RMII1_RXD1	0x0E4 0x000 ALT1 0x0
+#define VF610_PAD_PTC12__ESAI_SDO1		0x0E4 0x318 ALT3 0x1
+#define VF610_PAD_PTC12__SAI2_TX_BCLK		0x0E4 0x370 ALT5 0x1
+#define VF610_PAD_PTC12__DEBUG_OUT3		0x0E4 0x000 ALT7 0x0
+#define VF610_PAD_PTC13__GPIO_58		0x0E8 0x000 ALT0 0x0
+#define VF610_PAD_PTC13__ENET_RMII1_RXD0	0x0E8 0x000 ALT1 0x0
+#define VF610_PAD_PTC13__ESAI_SDO2		0x0E8 0x31C ALT3 0x1
+#define VF610_PAD_PTC13__SAI2_RX_BCLK		0x0E8 0x364 ALT5 0x2
+#define VF610_PAD_PTC13__DEBUG_OUT4		0x0E8 0x000 ALT7 0x0
+#define VF610_PAD_PTC14__GPIO_59		0x0EC 0x000 ALT0 0x0
+#define VF610_PAD_PTC14__ENET_RMII1_RXER	0x0EC 0x000 ALT1 0x0
+#define VF610_PAD_PTC14__ESAI_SDO3		0x0EC 0x320 ALT3 0x1
+#define VF610_PAD_PTC14__UART5_TX		0x0EC 0x000 ALT4 0x0
+#define VF610_PAD_PTC14__SAI2_RX_DATA		0x0EC 0x368 ALT5 0x2
+#define VF610_PAD_PTC14__ADC0_SE6		0x0EC 0x000 ALT6 0x0
+#define VF610_PAD_PTC14__DEBUG_OUT5		0x0EC 0x000 ALT7 0x0
+#define VF610_PAD_PTC15__GPIO_60		0x0F0 0x000 ALT0 0x0
+#define VF610_PAD_PTC15__ENET_RMII1_TXD1	0x0F0 0x000 ALT1 0x0
+#define VF610_PAD_PTC15__ESAI_SDI0		0x0F0 0x328 ALT3 0x1
+#define VF610_PAD_PTC15__UART5_RX		0x0F0 0x000 ALT4 0x0
+#define VF610_PAD_PTC15__SAI2_TX_DATA		0x0F0 0x000 ALT5 0x0
+#define VF610_PAD_PTC15__ADC0_SE7		0x0F0 0x000 ALT6 0x0
+#define VF610_PAD_PTC15__DEBUG_OUT6		0x0F0 0x000 ALT7 0x0
+#define VF610_PAD_PTC16__GPIO_61		0x0F4 0x000 ALT0 0x0
+#define VF610_PAD_PTC16__ENET_RMII1_TXD0	0x0F4 0x000 ALT1 0x0
+#define VF610_PAD_PTC16__ESAI_SDI1		0x0F4 0x324 ALT3 0x1
+#define VF610_PAD_PTC16__UART5_RTS		0x0F4 0x000 ALT4 0x0
+#define VF610_PAD_PTC16__SAI2_RX_SYNC		0x0F4 0x36C ALT5 0x2
+#define VF610_PAD_PTC16__ADC1_SE6		0x0F4 0x000 ALT6 0x0
+#define VF610_PAD_PTC16__DEBUG_OUT7		0x0F4 0x000 ALT7 0x0
+#define VF610_PAD_PTC17__GPIO_62		0x0F8 0x000 ALT0 0x0
+#define VF610_PAD_PTC17__ENET_RMII1_TXEN	0x0F8 0x000 ALT1 0x0
+#define VF610_PAD_PTC17__ADC1_SE7		0x0F8 0x000 ALT3 0x0
+#define VF610_PAD_PTC17__UART5_CTS		0x0F8 0x000 ALT4 0x0
+#define VF610_PAD_PTC17__SAI2_TX_SYNC		0x0F8 0x374 ALT5 0x1
+#define VF610_PAD_PTC17__USB1_SOF_PULSE		0x0F8 0x000 ALT6 0x0
+#define VF610_PAD_PTC17__DEBUG_OUT8		0x0F8 0x000 ALT7 0x0
+#define VF610_PAD_PTD31__GPIO_63		0x0FC 0x000 ALT0 0x0
+#define VF610_PAD_PTD31__FB_AD31		0x0FC 0x000 ALT1 0x0
+#define VF610_PAD_PTD31__NF_IO15		0x0FC 0x000 ALT2 0x0
+#define VF610_PAD_PTD31__FTM3_CH0		0x0FC 0x000 ALT4 0x0
+#define VF610_PAD_PTD31__DSPI2_CS1		0x0FC 0x000 ALT5 0x0
+#define VF610_PAD_PTD31__DEBUG_OUT9		0x0FC 0x000 ALT7 0x0
+#define VF610_PAD_PTD30__GPIO_64		0x100 0x000 ALT0 0x0
+#define VF610_PAD_PTD30__FB_AD30		0x100 0x000 ALT1 0x0
+#define VF610_PAD_PTD30__NF_IO14		0x100 0x000 ALT2 0x0
+#define VF610_PAD_PTD30__FTM3_CH1		0x100 0x000 ALT4 0x0
+#define VF610_PAD_PTD30__DSPI2_CS0		0x100 0x000 ALT5 0x0
+#define VF610_PAD_PTD30__DEBUG_OUT10		0x100 0x000 ALT7 0x0
+#define VF610_PAD_PTD29__GPIO_65		0x104 0x000 ALT0 0x0
+#define VF610_PAD_PTD29__FB_AD29		0x104 0x000 ALT1 0x0
+#define VF610_PAD_PTD29__NF_IO13		0x104 0x000 ALT2 0x0
+#define VF610_PAD_PTD29__FTM3_CH2		0x104 0x000 ALT4 0x0
+#define VF610_PAD_PTD29__DSPI2_SIN		0x104 0x000 ALT5 0x0
+#define VF610_PAD_PTD29__DEBUG_OUT11		0x104 0x000 ALT7 0x0
+#define VF610_PAD_PTD28__GPIO_66	 	0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__FB_AD28		0x108 0x000 ALT1 0x0
+#define VF610_PAD_PTD28__NF_IO12		0x108 0x000 ALT2 0x0
+#define VF610_PAD_PTD28__I2C2_SCL		0x108 0x34C ALT3 0x1
+#define VF610_PAD_PTD28__FTM3_CH3		0x108 0x000 ALT4 0x0
+#define VF610_PAD_PTD28__DSPI2_SOUT		0x108 0x000 ALT5 0x0
+#define VF610_PAD_PTD28__DEBUG_OUT12		0x108 0x000 ALT7 0x0
+#define VF610_PAD_PTD27__GPIO_67		0x10C 0x000 ALT0 0x0
+#define VF610_PAD_PTD27__FB_AD27		0x10C 0x000 ALT1 0x0
+#define VF610_PAD_PTD27__NF_IO11		0x10C 0x000 ALT2 0x0
+#define VF610_PAD_PTD27__I2C2_SDA		0x10C 0x350 ALT3 0x1
+#define VF610_PAD_PTD27__FTM3_CH4		0x10C 0x000 ALT4 0x0
+#define VF610_PAD_PTD27__DSPI2_SCK		0x10C 0x000 ALT5 0x0
+#define VF610_PAD_PTD27__DEBUG_OUT13		0x10C 0x000 ALT7 0x0
+#define VF610_PAD_PTD26__GPIO_68		0x110 0x000 ALT0 0x0
+#define VF610_PAD_PTD26__FB_AD26		0x110 0x000 ALT1 0x0
+#define VF610_PAD_PTD26__NF_IO10		0x110 0x000 ALT2 0x0
+#define VF610_PAD_PTD26__FTM3_CH5		0x110 0x000 ALT4 0x0
+#define VF610_PAD_PTD26__ESDHC1_WP		0x110 0x000 ALT5 0x0
+#define VF610_PAD_PTD26__DEBUG_OUT14		0x110 0x000 ALT7 0x0
+#define VF610_PAD_PTD25__GPIO_69		0x114 0x000 ALT0 0x0
+#define VF610_PAD_PTD25__FB_AD25		0x114 0x000 ALT1 0x0
+#define VF610_PAD_PTD25__NF_IO9			0x114 0x000 ALT2 0x0
+#define VF610_PAD_PTD25__FTM3_CH6		0x114 0x000 ALT4 0x0
+#define VF610_PAD_PTD25__DEBUG_OUT15		0x114 0x000 ALT7 0x0
+#define VF610_PAD_PTD24__GPIO_70		0x118 0x000 ALT0 0x0
+#define VF610_PAD_PTD24__FB_AD24		0x118 0x000 ALT1 0x0
+#define VF610_PAD_PTD24__NF_IO8			0x118 0x000 ALT2 0x0
+#define VF610_PAD_PTD24__FTM3_CH7		0x118 0x000 ALT4 0x0
+#define VF610_PAD_PTD24__DEBUG_OUT16		0x118 0x000 ALT7 0x0
+#define VF610_PAD_PTD23__GPIO_71		0x11C 0x000 ALT0 0x0
+#define VF610_PAD_PTD23__FB_AD23		0x11C 0x000 ALT1 0x0
+#define VF610_PAD_PTD23__NF_IO7			0x11C 0x000 ALT2 0x0
+#define VF610_PAD_PTD23__FTM2_CH0		0x11C 0x000 ALT3 0x0
+#define VF610_PAD_PTD23__ENET0_1588_TMR0	0x11C 0x304 ALT4 0x1
+#define VF610_PAD_PTD23__ESDHC0_DAT4		0x11C 0x000 ALT5 0x0
+#define VF610_PAD_PTD23__UART2_TX		0x11C 0x38C ALT6 0x1
+#define VF610_PAD_PTD23__DCU1_R3		0x11C 0x000 ALT7 0x0
+#define VF610_PAD_PTD22__GPIO_72		0x120 0x000 ALT0 0x0
+#define VF610_PAD_PTD22__FB_AD22		0x120 0x000 ALT1 0x0
+#define VF610_PAD_PTD22__NF_IO6			0x120 0x000 ALT2 0x0
+#define VF610_PAD_PTD22__FTM2_CH1		0x120 0x000 ALT3 0x0
+#define VF610_PAD_PTD22__ENET0_1588_TMR1	0x120 0x308 ALT4 0x1
+#define VF610_PAD_PTD22__ESDHC0_DAT5		0x120 0x000 ALT5 0x0
+#define VF610_PAD_PTD22__UART2_RX		0x120 0x388 ALT6 0x1
+#define VF610_PAD_PTD22__DCU1_R4		0x120 0x000 ALT7 0x0
+#define VF610_PAD_PTD21__GPIO_73		0x124 0x000 ALT0 0x0
+#define VF610_PAD_PTD21__FB_AD21		0x124 0x000 ALT1 0x0
+#define VF610_PAD_PTD21__NF_IO5			0x124 0x000 ALT2 0x0
+#define VF610_PAD_PTD21__ENET0_1588_TMR2	0x124 0x000 ALT4 0x0
+#define VF610_PAD_PTD21__ESDHC0_DAT6		0x124 0x000 ALT5 0x0
+#define VF610_PAD_PTD21__UART2_RTS		0x124 0x000 ALT6 0x0
+#define VF610_PAD_PTD21__DCU1_R5		0x124 0x000 ALT7 0x0
+#define VF610_PAD_PTD20__GPIO_74		0x128 0x000 ALT0 0x0
+#define VF610_PAD_PTD20__FB_AD20		0x128 0x000 ALT1 0x0
+#define VF610_PAD_PTD20__NF_IO4			0x128 0x000 ALT2 0x0
+#define VF610_PAD_PTD20__ENET0_1588_TMR3	0x128 0x000 ALT4 0x0
+#define VF610_PAD_PTD20__ESDHC0_DAT7		0x128 0x000 ALT5 0x0
+#define VF610_PAD_PTD20__UART2_CTS		0x128 0x384 ALT6 0x0
+#define VF610_PAD_PTD20__DCU1_R0		0x128 0x000 ALT7 0x0
+#define VF610_PAD_PTD19__GPIO_75		0x12C 0x000 ALT0 0x0
+#define VF610_PAD_PTD19__FB_AD19		0x12C 0x000 ALT1 0x0
+#define VF610_PAD_PTD19__NF_IO3			0x12C 0x000 ALT2 0x0
+#define VF610_PAD_PTD19__ESAI_SCKR		0x12C 0x000 ALT3 0x0
+#define VF610_PAD_PTD19__I2C0_SCL		0x12C 0x33C ALT4 0x2
+#define VF610_PAD_PTD19__FTM2_QD_PHA		0x12C 0x000 ALT5 0x0
+#define VF610_PAD_PTD19__DCU1_R1		0x12C 0x000 ALT7 0x0
+#define VF610_PAD_PTD18__GPIO_76		0x130 0x000 ALT0 0x0
+#define VF610_PAD_PTD18__FB_AD18		0x130 0x000 ALT1 0x0
+#define VF610_PAD_PTD18__NF_IO2			0x130 0x000 ALT2 0x0
+#define VF610_PAD_PTD18__ESAI_FSR		0x130 0x000 ALT3 0x0
+#define VF610_PAD_PTD18__I2C0_SDA		0x130 0x340 ALT4 0x2
+#define VF610_PAD_PTD18__FTM2_QD_PHB		0x130 0x000 ALT5 0x0
+#define VF610_PAD_PTD18__DCU1_G0		0x130 0x000 ALT7 0x0
+#define VF610_PAD_PTD17__GPIO_77		0x134 0x000 ALT0 0x0
+#define VF610_PAD_PTD17__FB_AD17		0x134 0x000 ALT1 0x0
+#define VF610_PAD_PTD17__NF_IO1			0x134 0x000 ALT2 0x0
+#define VF610_PAD_PTD17__ESAI_HCKR		0x134 0x000 ALT3 0x0
+#define VF610_PAD_PTD17__I2C1_SCL		0x134 0x344 ALT4 0x2
+#define VF610_PAD_PTD17__DCU1_G1		0x134 0x000 ALT7 0x0
+#define VF610_PAD_PTD16__GPIO_78		0x138 0x000 ALT0 0x0
+#define VF610_PAD_PTD16__FB_AD16		0x138 0x000 ALT1 0x0
+#define VF610_PAD_PTD16__NF_IO0			0x138 0x000 ALT2 0x0
+#define VF610_PAD_PTD16__ESAI_HCKT		0x138 0x000 ALT3 0x0
+#define VF610_PAD_PTD16__I2C1_SDA		0x138 0x348 ALT4 0x2
+#define VF610_PAD_PTD16__DCU1_G2		0x138 0x000 ALT7 0x0
+#define VF610_PAD_PTD0__GPIO_79			0x13C 0x000 ALT0 0x0
+#define VF610_PAD_PTD0__QSPI0_A_QSCK		0x13C 0x000 ALT1 0x0
+#define VF610_PAD_PTD0__UART2_TX		0x13C 0x38C ALT2 0x2
+#define VF610_PAD_PTD0__FB_AD15			0x13C 0x000 ALT4 0x0
+#define VF610_PAD_PTD0__SPDIF_EXTCLK		0x13C 0x000 ALT5 0x0
+#define VF610_PAD_PTD0__DEBUG_OUT17		0x13C 0x000 ALT7 0x0
+#define VF610_PAD_PTD1__GPIO_80			0x140 0x000 ALT0 0x0
+#define VF610_PAD_PTD1__QSPI0_A_CS0		0x140 0x000 ALT1 0x0
+#define VF610_PAD_PTD1__UART2_RX		0x140 0x388 ALT2 0x2
+#define VF610_PAD_PTD1__FB_AD14			0x140 0x000 ALT4 0x0
+#define VF610_PAD_PTD1__SPDIF_IN1		0x140 0x000 ALT5 0x0
+#define VF610_PAD_PTD1__DEBUG_OUT18		0x140 0x000 ALT7 0x0
+#define VF610_PAD_PTD2__GPIO_81			0x144 0x000 ALT0 0x0
+#define VF610_PAD_PTD2__QSPI0_A_DATA3		0x144 0x000 ALT1 0x0
+#define VF610_PAD_PTD2__UART2_RTS		0x144 0x000 ALT2 0x0
+#define VF610_PAD_PTD2__DSPI1_CS3		0x144 0x000 ALT3 0x0
+#define VF610_PAD_PTD2__FB_AD13			0x144 0x000 ALT4 0x0
+#define VF610_PAD_PTD2__SPDIF_OUT1		0x144 0x000 ALT5 0x0
+#define VF610_PAD_PTD2__DEBUG_OUT19		0x144 0x000 ALT7 0x0
+#define VF610_PAD_PTD3__GPIO_82			0x148 0x000 ALT0 0x0
+#define VF610_PAD_PTD3__QSPI0_A_DATA2		0x148 0x000 ALT1 0x0
+#define VF610_PAD_PTD3__UART2_CTS		0x148 0x384 ALT2 0x1
+#define VF610_PAD_PTD3__DSPI1_CS2		0x148 0x000 ALT3 0x0
+#define VF610_PAD_PTD3__FB_AD12			0x148 0x000 ALT4 0x0
+#define VF610_PAD_PTD3__SPDIF_PLOCK		0x148 0x000 ALT5 0x0
+#define VF610_PAD_PTD3__DEBUG_OUT20		0x148 0x000 ALT7 0x0
+#define VF610_PAD_PTD4__GPIO_83			0x14C 0x000 ALT0 0x0
+#define VF610_PAD_PTD4__QSPI0_A_DATA1		0x14C 0x000 ALT1 0x0
+#define VF610_PAD_PTD4__DSPI1_CS1		0x14C 0x000 ALT3 0x0
+#define VF610_PAD_PTD4__FB_AD11			0x14C 0x000 ALT4 0x0
+#define VF610_PAD_PTD4__SPDIF_SRCLK		0x14C 0x000 ALT5 0x0
+#define VF610_PAD_PTD4__DEBUG_OUT21		0x14C 0x000 ALT7 0x0
+#define VF610_PAD_PTD5__GPIO_84			0x150 0x000 ALT0 0x0
+#define VF610_PAD_PTD5__QSPI0_A_DATA0		0x150 0x000 ALT1 0x0
+#define VF610_PAD_PTD5__DSPI1_CS0		0x150 0x300 ALT3 0x1
+#define VF610_PAD_PTD5__FB_AD10			0x150 0x000 ALT4 0x0
+#define VF610_PAD_PTD5__DEBUG_OUT22		0x150 0x000 ALT7 0x0
+#define VF610_PAD_PTD6__GPIO_85			0x154 0x000 ALT0 0x0
+#define VF610_PAD_PTD6__QSPI1_A_DQS		0x154 0x000 ALT1 0x0
+#define VF610_PAD_PTD6__DSPI1_SIN		0x154 0x2FC ALT3 0x1
+#define VF610_PAD_PTD6__FB_AD9			0x154 0x000 ALT4 0x0
+#define VF610_PAD_PTD6__DEBUG_OUT23		0x154 0x000 ALT7 0x0
+#define VF610_PAD_PTD7__GPIO_86			0x158 0x000 ALT0 0x0
+#define VF610_PAD_PTD7__QSPI0_B_QSCK		0x158 0x000 ALT1 0x0
+#define VF610_PAD_PTD7__DSPI1_SOUT		0x158 0x000 ALT3 0x0
+#define VF610_PAD_PTD7__FB_AD8			0x158 0x000 ALT4 0x0
+#define VF610_PAD_PTD7__DEBUG_OUT24		0x158 0x000 ALT7 0x0
+#define VF610_PAD_PTD8__GPIO_87			0x15C 0x000 ALT0 0x0
+#define VF610_PAD_PTD8__QSPI0_B_CS0		0x15C 0x000 ALT1 0x0
+#define VF610_PAD_PTD8__FB_CLKOUT		0x15C 0x000 ALT2 0x0
+#define VF610_PAD_PTD8__DSPI1_SCK		0x15C 0x2F8 ALT3 0x1
+#define VF610_PAD_PTD8__FB_AD7			0x15C 0x000 ALT4 0x0
+#define VF610_PAD_PTD8__DEBUG_OUT25		0x15C 0x000 ALT7 0x0
+#define VF610_PAD_PTD9__GPIO_88			0x160 0x000 ALT0 0x0
+#define VF610_PAD_PTD9__QSPI0_B_DATA3		0x160 0x000 ALT1 0x0
+#define VF610_PAD_PTD9__DSPI3_CS1		0x160 0x000 ALT2 0x0
+#define VF610_PAD_PTD9__FB_AD6			0x160 0x000 ALT4 0x0
+#define VF610_PAD_PTD9__SAI1_TX_SYNC		0x160 0x360 ALT6 0x0
+#define VF610_PAD_PTD9__DCU1_B0			0x160 0x000 ALT7 0x0
+#define VF610_PAD_PTD10__GPIO_89		0x164 0x000 ALT0 0x0
+#define VF610_PAD_PTD10__QSPI0_B_DATA2		0x164 0x000 ALT1 0x0
+#define VF610_PAD_PTD10__DSPI3_CS0		0x164 0x000 ALT2 0x0
+#define VF610_PAD_PTD10__FB_AD5			0x164 0x000 ALT4 0x0
+#define VF610_PAD_PTD10__DCU1_B1		0x164 0x000 ALT7 0x0
+#define VF610_PAD_PTD11__GPIO_90		0x168 0x000 ALT0 0x0
+#define VF610_PAD_PTD11__QSPI0_B_DATA1		0x168 0x000 ALT1 0x0
+#define VF610_PAD_PTD11__DSPI3_SIN		0x168 0x000 ALT2 0x0
+#define VF610_PAD_PTD11__FB_AD4			0x168 0x000 ALT4 0x0
+#define VF610_PAD_PTD11__DEBUG_OUT26		0x168 0x000 ALT7 0x0
+#define VF610_PAD_PTD12__GPIO_91		0x16C 0x000 ALT0 0x0
+#define VF610_PAD_PTD12__QSPI0_B_DATA0		0x16C 0x000 ALT1 0x0
+#define VF610_PAD_PTD12__DSPI3_SOUT		0x16C 0x000 ALT2 0x0
+#define VF610_PAD_PTD12__FB_AD3			0x16C 0x000 ALT4 0x0
+#define VF610_PAD_PTD12__DEBUG_OUT27		0x16C 0x000 ALT7 0x0
+#define VF610_PAD_PTD13__GPIO_92		0x170 0x000 ALT0 0x0
+#define VF610_PAD_PTD13__QSPI0_B_DQS		0x170 0x000 ALT1 0x0
+#define VF610_PAD_PTD13__DSPI3_SCK		0x170 0x000 ALT2 0x0
+#define VF610_PAD_PTD13__FB_AD2			0x170 0x000 ALT4 0x0
+#define VF610_PAD_PTD13__DEBUG_OUT28		0x170 0x000 ALT7 0x0
+#define VF610_PAD_PTB23__GPIO_93		0x174 0x000 ALT0 0x0
+#define VF610_PAD_PTB23__SAI0_TX_BCLK		0x174 0x000 ALT1 0x0
+#define VF610_PAD_PTB23__UART1_TX		0x174 0x380 ALT2 0x2
+#define VF610_PAD_PTB23__SRC_RCON18		0x174 0x398 ALT3 0x1
+#define VF610_PAD_PTB23__FB_MUXED_ALE		0x174 0x000 ALT4 0x0
+#define VF610_PAD_PTB23__FB_TS_B		0x174 0x000 ALT5 0x0
+#define VF610_PAD_PTB23__UART3_RTS		0x174 0x000 ALT6 0x0
+#define VF610_PAD_PTB23__DCU1_G3		0x174 0x000 ALT7 0x0
+#define VF610_PAD_PTB24__GPIO_94		0x178 0x000 ALT0 0x0
+#define VF610_PAD_PTB24__SAI0_RX_BCLK		0x178 0x000 ALT1 0x0
+#define VF610_PAD_PTB24__UART1_RX		0x178 0x37C ALT2 0x2
+#define VF610_PAD_PTB24__SRC_RCON19		0x178 0x39C ALT3 0x1
+#define VF610_PAD_PTB24__FB_MUXED_TSIZ0		0x178 0x000 ALT4 0x0
+#define VF610_PAD_PTB24__NF_WE_B		0x178 0x000 ALT5 0x0
+#define VF610_PAD_PTB24__UART3_CTS		0x178 0x000 ALT6 0x0
+#define VF610_PAD_PTB24__DCU1_G4		0x178 0x000 ALT7 0x0
+#define VF610_PAD_PTB25__GPIO_95		0x17C 0x000 ALT0 0x0
+#define VF610_PAD_PTB25__SAI0_RX_DATA		0x17C 0x000 ALT1 0x0
+#define VF610_PAD_PTB25__UART1_RTS		0x17C 0x000 ALT2 0x0
+#define VF610_PAD_PTB25__SRC_RCON20		0x17C 0x3A0 ALT3 0x1
+#define VF610_PAD_PTB25__FB_CS1_B		0x17C 0x000 ALT4 0x0
+#define VF610_PAD_PTB25__NF_CE0_B		0x17C 0x000 ALT5 0x0
+#define VF610_PAD_PTB25__DCU1_G5		0x17C 0x000 ALT7 0x0
+#define VF610_PAD_PTB26__GPIO_96		0x180 0x000 ALT0 0x0
+#define VF610_PAD_PTB26__SAI0_TX_DATA		0x180 0x000 ALT1 0x0
+#define VF610_PAD_PTB26__UART1_CTS		0x180 0x378 ALT2 0x2
+#define VF610_PAD_PTB26__SRC_RCON21		0x180 0x000 ALT3 0x0
+#define VF610_PAD_PTB26__FB_CS0_B		0x180 0x000 ALT4 0x0
+#define VF610_PAD_PTB26__NF_CE1_B		0x180 0x000 ALT5 0x0
+#define VF610_PAD_PTB26__DCU1_G6		0x180 0x000 ALT7 0x0
+#define VF610_PAD_PTB27__GPIO_97		0x184 0x000 ALT0 0x0
+#define VF610_PAD_PTB27__SAI0_RX_SYNC		0x184 0x000 ALT1 0x0
+#define VF610_PAD_PTB27__SRC_RCON22		0x184 0x000 ALT3 0x0
+#define VF610_PAD_PTB27__FB_OE_B		0x184 0x000 ALT4 0x0
+#define VF610_PAD_PTB27__FB_MUXED_TBST_B	0x184 0x000 ALT5 0x0
+#define VF610_PAD_PTB27__NF_RE_B		0x184 0x000 ALT6 0x0
+#define VF610_PAD_PTB27__DCU1_G7		0x184 0x000 ALT7 0x0
+#define VF610_PAD_PTB28__GPIO_98		0x188 0x000 ALT0 0x0
+#define VF610_PAD_PTB28__SAI0_TX_SYNC		0x188 0x000 ALT1 0x0
+#define VF610_PAD_PTB28__SRC_RCON23		0x188 0x000 ALT3 0x0
+#define VF610_PAD_PTB28__FB_RW_B		0x188 0x000 ALT4 0x0
+#define VF610_PAD_PTB28__DCU1_B6		0x188 0x000 ALT7 0x0
+#define VF610_PAD_PTC26__GPIO_99		0x18C 0x000 ALT0 0x0
+#define VF610_PAD_PTC26__SAI1_TX_BCLK		0x18C 0x000 ALT1 0x0
+#define VF610_PAD_PTC26__DSPI0_CS5		0x18C 0x000 ALT2 0x0
+#define VF610_PAD_PTC26__SRC_RCON24		0x18C 0x000 ALT3 0x0
+#define VF610_PAD_PTC26__FB_TA_B		0x18C 0x000 ALT4 0x0
+#define VF610_PAD_PTC26__NF_RB_B		0x18C 0x000 ALT5 0x0
+#define VF610_PAD_PTC26__DCU1_B7		0x18C 0x000 ALT7 0x0
+#define VF610_PAD_PTC27__GPIO_100		0x190 0x000 ALT0 0x0
+#define VF610_PAD_PTC27__SAI1_RX_BCLK		0x190 0x000 ALT1 0x0
+#define VF610_PAD_PTC27__DSPI0_CS4		0x190 0x000 ALT2 0x0
+#define VF610_PAD_PTC27__SRC_RCON25		0x190 0x000 ALT3 0x0
+#define VF610_PAD_PTC27__FB_BE3_B		0x190 0x000 ALT4 0x0
+#define VF610_PAD_PTC27__FB_CS3_B		0x190 0x000 ALT5 0x0
+#define VF610_PAD_PTC27__NF_ALE			0x190 0x000 ALT6 0x0
+#define VF610_PAD_PTC27__DCU1_B2		0x190 0x000 ALT7 0x0
+#define VF610_PAD_PTC28__GPIO_101		0x194 0x000 ALT0 0x0
+#define VF610_PAD_PTC28__SAI1_RX_DATA		0x194 0x000 ALT1 0x0
+#define VF610_PAD_PTC28__DSPI0_CS3		0x194 0x000 ALT2 0x0
+#define VF610_PAD_PTC28__SRC_RCON26		0x194 0x000 ALT3 0x0
+#define VF610_PAD_PTC28__FB_BE2_B		0x194 0x000 ALT4 0x0
+#define VF610_PAD_PTC28__FB_CS2_B		0x194 0x000 ALT5 0x0
+#define VF610_PAD_PTC28__NF_CLE			0x194 0x000 ALT6 0x0
+#define VF610_PAD_PTC28__DCU1_B3		0x194 0x000 ALT7 0x0
+#define VF610_PAD_PTC29__GPIO_102		0x198 0x000 ALT0 0x0
+#define VF610_PAD_PTC29__SAI1_TX_DATA		0x198 0x000 ALT1 0x0
+#define VF610_PAD_PTC29__DSPI0_CS2		0x198 0x000 ALT2 0x0
+#define VF610_PAD_PTC29__SRC_RCON27		0x198 0x000 ALT3 0x0
+#define VF610_PAD_PTC29__FB_BE1_B		0x198 0x000 ALT4 0x0
+#define VF610_PAD_PTC29__FB_MUXED_TSIZE1	0x198 0x000 ALT5 0x0
+#define VF610_PAD_PTC29__DCU1_B4		0x198 0x000 ALT7 0x0
+#define VF610_PAD_PTC30__GPIO_103		0x19C 0x000 ALT0 0x0
+#define VF610_PAD_PTC30__SAI1_RX_SYNC		0x19C 0x000 ALT1 0x0
+#define VF610_PAD_PTC30__DSPI1_CS2		0x19C 0x000 ALT2 0x0
+#define VF610_PAD_PTC30__SRC_RCON28		0x19C 0x000 ALT3 0x0
+#define VF610_PAD_PTC30__FB_MUXED_BE0_B		0x19C 0x000 ALT4 0x0
+#define VF610_PAD_PTC30__FB_TSIZ0		0x19C 0x000 ALT5 0x0
+#define VF610_PAD_PTC30__ADC0_SE5		0x19C 0x000 ALT6 0x0
+#define VF610_PAD_PTC30__DCU1_B5		0x19C 0x000 ALT7 0x0
+#define VF610_PAD_PTC31__GPIO_104		0x1A0 0x000 ALT0 0x0
+#define VF610_PAD_PTC31__SAI1_TX_SYNC		0x1A0 0x360 ALT1 0x1
+#define VF610_PAD_PTC31__SRC_RCON29		0x1A0 0x000 ALT3 0x0
+#define VF610_PAD_PTC31__ADC1_SE5		0x1A0 0x000 ALT6 0x0
+#define VF610_PAD_PTC31__DCU1_B6		0x1A0 0x000 ALT7 0x0
+#define VF610_PAD_PTE0__GPIO_105		0x1A4 0x000 ALT0 0x0
+#define VF610_PAD_PTE0__DCU0_HSYNC		0x1A4 0x000 ALT1 0x0
+#define VF610_PAD_PTE0__SRC_BMODE1		0x1A4 0x000 ALT2 0x0
+#define VF610_PAD_PTE0__LCD0			0x1A4 0x000 ALT4 0x0
+#define VF610_PAD_PTE0__DEBUG_OUT29		0x1A4 0x000 ALT7 0x0
+#define VF610_PAD_PTE1__GPIO_106		0x1A8 0x000 ALT0 0x0
+#define VF610_PAD_PTE1__DCU0_VSYNC		0x1A8 0x000 ALT1 0x0
+#define VF610_PAD_PTE1__SRC_BMODE0		0x1A8 0x000 ALT2 0x0
+#define VF610_PAD_PTE1__LCD1			0x1A8 0x000 ALT4 0x0
+#define VF610_PAD_PTE1__DEBUG_OUT30		0x1A8 0x000 ALT7 0x0
+#define VF610_PAD_PTE2__GPIO_107		0x1AC 0x000 ALT0 0x0
+#define VF610_PAD_PTE2__DCU0_PCLK		0x1AC 0x000 ALT1 0x0
+#define VF610_PAD_PTE2__LCD2			0x1AC 0x000 ALT4 0x0
+#define VF610_PAD_PTE2__DEBUG_OUT31		0x1AC 0x000 ALT7 0x0
+#define VF610_PAD_PTE3__GPIO_108		0x1B0 0x000 ALT0 0x0
+#define VF610_PAD_PTE3__DCU0_TAG		0x1B0 0x000 ALT1 0x0
+#define VF610_PAD_PTE3__LCD3			0x1B0 0x000 ALT4 0x0
+#define VF610_PAD_PTE3__DEBUG_OUT32		0x1B0 0x000 ALT7 0x0
+#define VF610_PAD_PTE4__GPIO_109		0x1B4 0x000 ALT0 0x0
+#define VF610_PAD_PTE4__DCU0_DE			0x1B4 0x000 ALT1 0x0
+#define VF610_PAD_PTE4__LCD4			0x1B4 0x000 ALT4 0x0
+#define VF610_PAD_PTE4__DEBUG_OUT33		0x1B4 0x000 ALT7 0x0
+#define VF610_PAD_PTE5__GPIO_110		0x1B8 0x000 ALT0 0x0
+#define VF610_PAD_PTE5__DCU0_R0			0x1B8 0x000 ALT1 0x0
+#define VF610_PAD_PTE5__LCD5			0x1B8 0x000 ALT4 0x0
+#define VF610_PAD_PTE5__DEBUG_OUT34		0x1B8 0x000 ALT7 0x0
+#define VF610_PAD_PTE6__GPIO_111		0x1BC 0x000 ALT0 0x0
+#define VF610_PAD_PTE6__DCU0_R1			0x1BC 0x000 ALT1 0x0
+#define VF610_PAD_PTE6__LCD6			0x1BC 0x000 ALT4 0x0
+#define VF610_PAD_PTE6__DEBUG_OUT35		0x1BC 0x000 ALT7 0x0
+#define VF610_PAD_PTE7__GPIO_112		0x1C0 0x000 ALT0 0x0
+#define VF610_PAD_PTE7__DCU0_R2			0x1C0 0x000 ALT1 0x0
+#define VF610_PAD_PTE7__SRC_RCON0		0x1C0 0x000 ALT3 0x0
+#define VF610_PAD_PTE7__LCD7			0x1C0 0x000 ALT4 0x0
+#define VF610_PAD_PTE7__DEBUG_OUT36		0x1C0 0x000 ALT7 0x0
+#define VF610_PAD_PTE8__GPIO_113		0x1C4 0x000 ALT0 0x0
+#define VF610_PAD_PTE8__DCU0_R3			0x1C4 0x000 ALT1 0x0
+#define VF610_PAD_PTE8__SRC_RCON1		0x1C4 0x000 ALT3 0x0
+#define VF610_PAD_PTE8__LCD8			0x1C4 0x000 ALT4 0x0
+#define VF610_PAD_PTE8__DEBUG_OUT37		0x1C4 0x000 ALT7 0x0
+#define VF610_PAD_PTE9__GPIO_114		0x1C8 0x000 ALT0 0x0
+#define VF610_PAD_PTE9__DCU0_R4			0x1C8 0x000 ALT1 0x0
+#define VF610_PAD_PTE9__SRC_RCON2		0x1C8 0x000 ALT3 0x0
+#define VF610_PAD_PTE9__LCD9			0x1C8 0x000 ALT4 0x0
+#define VF610_PAD_PTE9__DEBUG_OUT38		0x1C8 0x000 ALT7 0x0
+#define VF610_PAD_PTE10__GPIO_115		0x1CC 0x000 ALT0 0x0
+#define VF610_PAD_PTE10__DCU0_R5		0x1CC 0x000 ALT1 0x0
+#define VF610_PAD_PTE10__SRC_RCON3		0x1CC 0x000 ALT3 0x0
+#define VF610_PAD_PTE10__LCD10			0x1CC 0x000 ALT4 0x0
+#define VF610_PAD_PTE10__DEBUG_OUT39		0x1CC 0x000 ALT7 0x0
+#define VF610_PAD_PTE11__GPIO_116		0x1D0 0x000 ALT0 0x0
+#define VF610_PAD_PTE11__DCU0_R6		0x1D0 0x000 ALT1 0x0
+#define VF610_PAD_PTE11__SRC_RCON4		0x1D0 0x000 ALT3 0x0
+#define VF610_PAD_PTE11__LCD11			0x1D0 0x000 ALT4 0x0
+#define VF610_PAD_PTE11__DEBUG_OUT40		0x1D0 0x000 ALT7 0x0
+#define VF610_PAD_PTE12__GPIO_117		0x1D4 0x000 ALT0 0x0
+#define VF610_PAD_PTE12__DCU0_R7		0x1D4 0x000 ALT1 0x0
+#define VF610_PAD_PTE12__DSPI1_CS3		0x1D4 0x000 ALT2 0x0
+#define VF610_PAD_PTE12__SRC_RCON5		0x1D4 0x000 ALT3 0x0
+#define VF610_PAD_PTE12__LCD12			0x1D4 0x000 ALT4 0x0
+#define VF610_PAD_PTE12__LPT_ALT0		0x1D4 0x000 ALT7 0x0
+#define VF610_PAD_PTE13__GPIO_118		0x1D8 0x000 ALT0 0x0
+#define VF610_PAD_PTE13__DCU0_G0		0x1D8 0x000 ALT1 0x0
+#define VF610_PAD_PTE13__LCD13			0x1D8 0x000 ALT4 0x0
+#define VF610_PAD_PTE13__DEBUG_OUT41		0x1D8 0x000 ALT7 0x0
+#define VF610_PAD_PTE14__GPIO_119		0x1DC 0x000 ALT0 0x0
+#define VF610_PAD_PTE14__DCU0_G1		0x1DC 0x000 ALT1 0x0
+#define VF610_PAD_PTE14__LCD14			0x1DC 0x000 ALT4 0x0
+#define VF610_PAD_PTE14__DEBUG_OUT42		0x1DC 0x000 ALT7 0x0
+#define VF610_PAD_PTE15__GPIO_120		0x1E0 0x000 ALT0 0x0
+#define VF610_PAD_PTE15__DCU0_G2		0x1E0 0x000 ALT1 0x0
+#define VF610_PAD_PTE15__SRC_RCON6		0x1E0 0x000 ALT3 0x0
+#define VF610_PAD_PTE15__LCD15			0x1E0 0x000 ALT4 0x0
+#define VF610_PAD_PTE15__DEBUG_OUT43		0x1E0 0x000 ALT7 0x0
+#define VF610_PAD_PTE16__GPIO_121		0x1E4 0x000 ALT0 0x0
+#define VF610_PAD_PTE16__DCU0_G3		0x1E4 0x000 ALT1 0x0
+#define VF610_PAD_PTE16__SRC_RCON7		0x1E4 0x000 ALT3 0x0
+#define VF610_PAD_PTE16__LCD16			0x1E4 0x000 ALT4 0x0
+#define VF610_PAD_PTE17__GPIO_122		0x1E8 0x000 ALT0 0x0
+#define VF610_PAD_PTE17__DCU0_G4		0x1E8 0x000 ALT1 0x0
+#define VF610_PAD_PTE17__SRC_RCON8		0x1E8 0x000 ALT3 0x0
+#define VF610_PAD_PTE17__LCD17			0x1E8 0x000 ALT4 0x0
+#define VF610_PAD_PTE18__GPIO_123		0x1EC 0x000 ALT0 0x0
+#define VF610_PAD_PTE18__DCU0_G5		0x1EC 0x000 ALT1 0x0
+#define VF610_PAD_PTE18__SRC_RCON9		0x1EC 0x000 ALT3 0x0
+#define VF610_PAD_PTE18__LCD18			0x1EC 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__GPIO_124		0x1F0 0x000 ALT0 0x0
+#define VF610_PAD_PTE19__DCU0_G6		0x1F0 0x000 ALT1 0x0
+#define VF610_PAD_PTE19__SRC_RCON10		0x1F0 0x000 ALT3 0x0
+#define VF610_PAD_PTE19__LCD19			0x1F0 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__I2C0_SCL		0x1F0 0x33C ALT5 0x3
+#define VF610_PAD_PTE20__GPIO_125		0x1F4 0x000 ALT0 0x0
+#define VF610_PAD_PTE20__DCU0_G7		0x1F4 0x000 ALT1 0x0
+#define VF610_PAD_PTE20__SRC_RCON11		0x1F4 0x000 ALT3 0x0
+#define VF610_PAD_PTE20__LCD20			0x1F4 0x000 ALT4 0x0
+#define VF610_PAD_PTE20__I2C0_SDA		0x1F4 0x340 ALT5 0x3
+#define VF610_PAD_PTE20__EWM_IN			0x1F4 0x000 ALT7 0x0
+#define VF610_PAD_PTE21__GPIO_126		0x1F8 0x000 ALT0 0x0
+#define VF610_PAD_PTE21__DCU0_B0		0x1F8 0x000 ALT1 0x0
+#define VF610_PAD_PTE21__LCD21			0x1F8 0x000 ALT4 0x0
+#define VF610_PAD_PTE22__GPIO_127		0x1FC 0x000 ALT0 0x0
+#define VF610_PAD_PTE22__DCU0_B1		0x1FC 0x000 ALT1 0x0
+#define VF610_PAD_PTE22__LCD22			0x1FC 0x000 ALT4 0x0
+#define VF610_PAD_PTE23__GPIO_128		0x200 0x000 ALT0 0x0
+#define VF610_PAD_PTE23__DCU0_B2		0x200 0x000 ALT1 0x0
+#define VF610_PAD_PTE23__SRC_RCON12		0x200 0x000 ALT3 0x0
+#define VF610_PAD_PTE23__LCD23			0x200 0x000 ALT4 0x0
+#define VF610_PAD_PTE24__GPIO_129		0x204 0x000 ALT0 0x0
+#define VF610_PAD_PTE24__DCU0_B3		0x204 0x000 ALT1 0x0
+#define VF610_PAD_PTE24__SRC_RCON13		0x204 0x000 ALT3 0x0
+#define VF610_PAD_PTE24__LCD24			0x204 0x000 ALT4 0x0
+#define VF610_PAD_PTE25__GPIO_130		0x208 0x000 ALT0 0x0
+#define VF610_PAD_PTE25__DCU0_B4		0x208 0x000 ALT1 0x0
+#define VF610_PAD_PTE25__SRC_RCON14		0x208 0x000 ALT3 0x0
+#define VF610_PAD_PTE25__LCD25			0x208 0x000 ALT4 0x0
+#define VF610_PAD_PTE26__GPIO_131		0x20C 0x000 ALT0 0x0
+#define VF610_PAD_PTE26__DCU0_B5		0x20C 0x000 ALT1 0x0
+#define VF610_PAD_PTE26__SRC_RCON15		0x20C 0x000 ALT3 0x0
+#define VF610_PAD_PTE26__LCD26			0x20C 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__GPIO_132		0x210 0x000 ALT0 0x0
+#define VF610_PAD_PTE27__DCU0_B6		0x210 0x000 ALT1 0x0
+#define VF610_PAD_PTE27__SRC_RCON16		0x210 0x000 ALT3 0x0
+#define VF610_PAD_PTE27__LCD27			0x210 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__I2C1_SCL		0x210 0x344 ALT5 0x3
+#define VF610_PAD_PTE28__GPIO_133		0x214 0x000 ALT0 0x0
+#define VF610_PAD_PTE28__DCU0_B7		0x214 0x000 ALT1 0x0
+#define VF610_PAD_PTE28__SRC_RCON17		0x214 0x000 ALT3 0x0
+#define VF610_PAD_PTE28__LCD28			0x214 0x000 ALT4 0x0
+#define VF610_PAD_PTE28__I2C1_SDA		0x214 0x348 ALT5 0x3
+#define VF610_PAD_PTE28__EWM_OUT		0x214 0x000 ALT7 0x0
+#define VF610_PAD_PTA7__GPIO_134		0x218 0x000 ALT0 0x0
+#define VF610_PAD_PTA7__VIU_PIX_CLK		0x218 0x3AC ALT1 0x1
+
+#endif

arch/arm/include/asm/arch-imx/cpu.h

@@ -24,7 +24,7 @@
 #define MXC_CPU_MX6QP		0x69
 #define MXC_CPU_MX7S		0x71 /* dummy ID */
 #define MXC_CPU_MX7D		0x72
-#define MXC_CPU_MX8MQ		0x82
+#define MXC_CPU_IMX8MQ		0x82
 #define MXC_CPU_IMX8QXP_A0	0x90 /* dummy ID */
 #define MXC_CPU_IMX8QXP		0x92 /* dummy ID */
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
@@ -32,7 +32,7 @@
 
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
-#define MXC_SOC_MX8M		0x80
+#define MXC_SOC_IMX8M		0x80
 #define MXC_SOC_IMX8		0x90 /* dummy */
 #define MXC_SOC_MX7ULP		0xE0 /* dummy */
 
@@ -41,6 +41,7 @@
 #define CHIP_REV_1_2            0x12
 #define CHIP_REV_1_5            0x15
 #define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_1            0x21
 #define CHIP_REV_2_5            0x25
 #define CHIP_REV_3_0            0x30
 

arch/arm/include/asm/arch-imx8m/clock.h

@@ -10,6 +10,8 @@
 
 #include <linux/bitops.h>
 
+#define MHZ(X)	((X) * 1000000UL)
+
 enum pll_clocks {
 	ANATOP_ARM_PLL,
 	ANATOP_GPU_PLL,
@@ -631,6 +633,26 @@ enum frac_pll_out_val {
 	FRAC_PLL_OUT_1600M,
 };
 
+#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k)			\
+	{								\
+		.clk		=	(_rate),			\
+		.alt_root_sel	=	(_m),				\
+		.alt_pre_div	=	(_p),				\
+		.apb_root_sel	=	(_s),				\
+		.apb_pre_div	=	(_k),				\
+	}
+
+struct dram_bypass_clk_setting {
+	ulong clk;
+	int alt_root_sel;
+	enum root_pre_div alt_pre_div;
+	int apb_root_sel;
+	enum root_pre_div apb_pre_div;
+};
+
+void dram_pll_init(ulong pll_val);
+void dram_enable_bypass(ulong clk_val);
+void dram_disable_bypass(void);
 u32 imx_get_fecclk(void);
 u32 imx_get_uartclk(void);
 int clock_init(void);

arch/arm/include/asm/arch-imx8m/crm_regs.h

@@ -3,7 +3,7 @@
  * Copyright 2017 NXP
  */
 
-#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
-#define _ASM_ARCH_MX8M_CRM_REGS_H
+#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H
+#define _ASM_ARCH_IMX8M_CRM_REGS_H
 /* Dummy header, some imx-common code needs this file */
 #endif

arch/arm/include/asm/arch-imx8m/ddr.h

@@ -0,0 +1,740 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8M_DDR_H
+#define __ASM_ARCH_IMX8M_DDR_H
+
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/arch/ddr.h>
+
+#define DDRC_DDR_SS_GPR0		0x3d000000
+#define DDRC_IPS_BASE_ADDR_0		0x3f400000
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X)	(0x3c000000 + (X * 0x2000000))
+#define DDRPHY_MEM(X)			(0x3c000000 + (X * 0x2000000) + 0x50000)
+
+struct ddrc_freq {
+	u32 res0[8];
+	u32 derateen;
+	u32 derateint;
+	u32 res1[10];
+	u32 rfshctl0;
+	u32 res2[4];
+	u32 rfshtmg;
+	u32 rfshtmg1;
+	u32 res3[28];
+	u32 init3;
+	u32 init4;
+	u32 res;
+	u32 init6;
+	u32 init7;
+	u32 res4[4];
+	u32 dramtmg0;
+	u32 dramtmg1;
+	u32 dramtmg2;
+	u32 dramtmg3;
+	u32 dramtmg4;
+	u32 dramtmg5;
+	u32 dramtmg6;
+	u32 dramtmg7;
+	u32 dramtmg8;
+	u32 dramtmg9;
+	u32 dramtmg10;
+	u32 dramtmg11;
+	u32 dramtmg12;
+	u32 dramtmg13;
+	u32 dramtmg14;
+	u32 dramtmg15;
+	u32 dramtmg16;
+	u32 dramtmg17;
+	u32 res5[10];
+	u32 mramtmg0;
+	u32 mramtmg1;
+	u32 mramtmg4;
+	u32 mramtmg9;
+	u32 zqctl0;
+	u32 res6[3];
+	u32 dfitmg0;
+	u32 dfitmg1;
+	u32 res7[7];
+	u32 dfitmg2;
+	u32 dfitmg3;
+	u32 res8[33];
+	u32 odtcfg;
+};
+
+struct imx8m_ddrc_regs {
+	u32 mstr;
+	u32 stat;
+	u32 mstr1;
+	u32 res1;
+	u32 mrctrl0;
+	u32 mrctrl1;
+	u32 mrstat;
+	u32 mrctrl2;
+	u32 derateen;
+	u32 derateint;
+	u32 mstr2;
+	u32 res2;
+	u32 pwrctl;
+	u32 pwrtmg;
+	u32 hwlpctl;
+	u32 hwffcctl;
+	u32 hwffcstat;
+	u32 res3[3];
+	u32 rfshctl0;
+	u32 rfshctl1;
+	u32 rfshctl2;
+	u32 rfshctl4;
+	u32 rfshctl3;
+	u32 rfshtmg;
+	u32 rfshtmg1;
+	u32 res4;
+	u32 ecccfg0;
+	u32 ecccfg1;
+	u32 eccstat;
+	u32 eccclr;
+	u32 eccerrcnt;
+	u32 ecccaddr0;
+	u32 ecccaddr1;
+	u32 ecccsyn0;
+	u32 ecccsyn1;
+	u32 ecccsyn2;
+	u32 eccbitmask0;
+	u32 eccbitmask1;
+	u32 eccbitmask2;
+	u32 eccuaddr0;
+	u32 eccuaddr1;
+	u32 eccusyn0;
+	u32 eccusyn1;
+	u32 eccusyn2;
+	u32 eccpoisonaddr0;
+	u32 eccpoisonaddr1;
+	u32 crcparctl0;
+	u32 crcparctl1;
+	u32 crcparctl2;
+	u32 crcparstat;
+	u32 init0;
+	u32 init1;
+	u32 init2;
+	u32 init3;
+	u32 init4;
+	u32 init5;
+	u32 init6;
+	u32 init7;
+	u32 dimmctl;
+	u32 rankctl;
+	u32 res5;
+	u32 chctl;
+	u32 dramtmg0;
+	u32 dramtmg1;
+	u32 dramtmg2;
+	u32 dramtmg3;
+	u32 dramtmg4;
+	u32 dramtmg5;
+	u32 dramtmg6;
+	u32 dramtmg7;
+	u32 dramtmg8;
+	u32 dramtmg9;
+	u32 dramtmg10;
+	u32 dramtmg11;
+	u32 dramtmg12;
+	u32 dramtmg13;
+	u32 dramtmg14;
+	u32 dramtmg15;
+	u32 dramtmg16;
+	u32 dramtmg17;
+	u32 res6[10];
+	u32 mramtmg0;
+	u32 mramtmg1;
+	u32 mramtmg4;
+	u32 mramtmg9;
+	u32 zqctl0;
+	u32 zqctl1;
+	u32 zqctl2;
+	u32 zqstat;
+	u32 dfitmg0;
+	u32 dfitmg1;
+	u32 dfilpcfg0;
+	u32 dfilpcfg1;
+	u32 dfiupd0;
+	u32 dfiupd1;
+	u32 dfiupd2;
+	u32 res7;
+	u32 dfimisc;
+	u32 dfitmg2;
+	u32 dfitmg3;
+	u32 dfistat;
+	u32 dbictl;
+	u32 dfiphymstr;
+	u32 res8[14];
+	u32 addrmap0;
+	u32 addrmap1;
+	u32 addrmap2;
+	u32 addrmap3;
+	u32 addrmap4;
+	u32 addrmap5;
+	u32 addrmap6;
+	u32 addrmap7;
+	u32 addrmap8;
+	u32 addrmap9;
+	u32 addrmap10;
+	u32 addrmap11;
+	u32 res9[4];
+	u32 odtcfg;
+	u32 odtmap;
+	u32 res10[2];
+	u32 sched;
+	u32 sched1;
+	u32 sched2;
+	u32 perfhpr1;
+	u32 res11;
+	u32 perflpr1;
+	u32 res12;
+	u32 perfwr1;
+	u32 res13[4];
+	u32 dqmap0;
+	u32 dqmap1;
+	u32 dqmap2;
+	u32 dqmap3;
+	u32 dqmap4;
+	u32 dqmap5;
+	u32 res14[26];
+	u32 dbg0;
+	u32 dbg1;
+	u32 dbgcam;
+	u32 dbgcmd;
+	u32 dbgstat;
+	u32 res15[3];
+	u32 swctl;
+	u32 swstat;
+	u32 res16[2];
+	u32 ocparcfg0;
+	u32 ocparcfg1;
+	u32 ocparcfg2;
+	u32 ocparcfg3;
+	u32 ocparstat0;
+	u32 ocparstat1;
+	u32 ocparwlog0;
+	u32 ocparwlog1;
+	u32 ocparwlog2;
+	u32 ocparawlog0;
+	u32 ocparawlog1;
+	u32 ocparrlog0;
+	u32 ocparrlog1;
+	u32 ocpararlog0;
+	u32 ocpararlog1;
+	u32 poisoncfg;
+	u32 poisonstat;
+	u32 adveccindex;
+	union  {
+		u32 adveccstat;
+		u32 eccapstat;
+	};
+	u32 eccpoisonpat0;
+	u32 eccpoisonpat1;
+	u32 eccpoisonpat2;
+	u32 res17[6];
+	u32 caparpoisonctl;
+	u32 caparpoisonstat;
+	u32 res18[2];
+	u32 dynbsmstat;
+	u32 res19[18];
+	u32 pstat;
+	u32 pccfg;
+	struct {
+		u32 pcfgr;
+		u32 pcfgw;
+		u32 pcfgc;
+		struct {
+			u32 pcfgidmaskch0;
+			u32 pcfidvaluech0;
+		} pcfgid[16];
+		u32 pctrl;
+		u32 pcfgqos0;
+		u32 pcfgqos1;
+		u32 pcfgwqos0;
+		u32 pcfgwqos1;
+		u32 res[4];
+	} pcfg[16];
+	struct {
+		u32 sarbase;
+		u32 sarsize;
+	} sar[4];
+	u32 sbrctl;
+	u32 sbrstat;
+	u32 sbrwdata0;
+	u32 sbrwdata1;
+	u32 pdch;
+	u32 res20[755];
+	/* umctl2_regs_dch1 */
+	u32 ch1_stat;
+	u32 res21[2];
+	u32 ch1_mrctrl0;
+	u32 ch1_mrctrl1;
+	u32 ch1_mrstat;
+	u32 ch1_mrctrl2;
+	u32 res22[4];
+	u32 ch1_pwrctl;
+	u32 ch1_pwrtmg;
+	u32 ch1_hwlpctl;
+	u32 res23[15];
+	u32 ch1_eccstat;
+	u32 ch1_eccclr;
+	u32 ch1_eccerrcnt;
+	u32 ch1_ecccaddr0;
+	u32 ch1_ecccaddr1;
+	u32 ch1_ecccsyn0;
+	u32 ch1_ecccsyn1;
+	u32 ch1_ecccsyn2;
+	u32 ch1_eccbitmask0;
+	u32 ch1_eccbitmask1;
+	u32 ch1_eccbitmask2;
+	u32 ch1_eccuaddr0;
+	u32 ch1_eccuaddr1;
+	u32 ch1_eccusyn0;
+	u32 ch1_eccusyn1;
+	u32 ch1_eccusyn2;
+	u32 res24[2];
+	u32 ch1_crcparctl0;
+	u32 res25[2];
+	u32 ch1_crcparstat;
+	u32 res26[46];
+	u32 ch1_zqctl2;
+	u32 ch1_zqstat;
+	u32 res27[11];
+	u32 ch1_dfistat;
+	u32 res28[33];
+	u32 ch1_odtmap;
+	u32 res29[47];
+	u32 ch1_dbg1;
+	u32 ch1_dbgcam;
+	u32 ch1_dbgcmd;
+	u32 ch1_dbgstat;
+	u32 res30[123];
+	/* umctl2_regs_freq1 */
+	struct ddrc_freq freq1;
+	u32 res31[109];
+	/* umctl2_regs_addrmap_alt */
+	u32 addrmap0_alt;
+	u32 addrmap1_alt;
+	u32 addrmap2_alt;
+	u32 addrmap3_alt;
+	u32 addrmap4_alt;
+	u32 addrmap5_alt;
+	u32 addrmap6_alt;
+	u32 addrmap7_alt;
+	u32 addrmap8_alt;
+	u32 addrmap9_alt;
+	u32 addrmap10_alt;
+	u32 addrmap11_alt;
+	u32 res32[758];
+	/* umctl2_regs_freq2 */
+	struct ddrc_freq freq2;
+	u32 res33[879];
+	/* umctl2_regs_freq3 */
+	struct ddrc_freq freq3;
+};
+
+struct imx8m_ddrphy_regs {
+	u32 reg[0xf0000];
+};
+
+/* PHY State */
+enum pstate {
+	PS0,
+	PS1,
+	PS2,
+	PS3,
+};
+
+enum msg_response {
+	TRAIN_SUCCESS = 0x7,
+	TRAIN_STREAM_START = 0x8,
+	TRAIN_FAIL = 0xff,
+};
+
+#define DDRC_MSTR(X)             (DDRC_IPS_BASE_ADDR(X) + 0x00)
+#define DDRC_STAT(X)             (DDRC_IPS_BASE_ADDR(X) + 0x04)
+#define DDRC_MSTR1(X)            (DDRC_IPS_BASE_ADDR(X) + 0x08)
+#define DDRC_MRCTRL0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x10)
+#define DDRC_MRCTRL1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x14)
+#define DDRC_MRSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x18)
+#define DDRC_MRCTRL2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1c)
+#define DDRC_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x20)
+#define DDRC_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x24)
+#define DDRC_MSTR2(X)            (DDRC_IPS_BASE_ADDR(X) + 0x28)
+#define DDRC_PWRCTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0x30)
+#define DDRC_PWRTMG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x34)
+#define DDRC_HWLPCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0x38)
+#define DDRC_HWFFCCTL(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3c)
+#define DDRC_HWFFCSTAT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x40)
+#define DDRC_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x50)
+#define DDRC_RFSHCTL1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x54)
+#define DDRC_RFSHCTL2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x58)
+#define DDRC_RFSHCTL3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x60)
+#define DDRC_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x64)
+#define DDRC_ECCCFG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x70)
+#define DDRC_ECCCFG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x74)
+#define DDRC_ECCSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x78)
+#define DDRC_ECCCLR(X)           (DDRC_IPS_BASE_ADDR(X) + 0x7c)
+#define DDRC_ECCERRCNT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x80)
+#define DDRC_ECCCADDR0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x84)
+#define DDRC_ECCCADDR1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x88)
+#define DDRC_ECCCSYN0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x8c)
+#define DDRC_ECCCSYN1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x90)
+#define DDRC_ECCCSYN2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x94)
+#define DDRC_ECCBITMASK0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x98)
+#define DDRC_ECCBITMASK1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x9c)
+#define DDRC_ECCBITMASK2(X)      (DDRC_IPS_BASE_ADDR(X) + 0xa0)
+#define DDRC_ECCUADDR0(X)        (DDRC_IPS_BASE_ADDR(X) + 0xa4)
+#define DDRC_ECCUADDR1(X)        (DDRC_IPS_BASE_ADDR(X) + 0xa8)
+#define DDRC_ECCUSYN0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xac)
+#define DDRC_ECCUSYN1(X)         (DDRC_IPS_BASE_ADDR(X) + 0xb0)
+#define DDRC_ECCUSYN2(X)         (DDRC_IPS_BASE_ADDR(X) + 0xb4)
+#define DDRC_ECCPOISONADDR0(X)   (DDRC_IPS_BASE_ADDR(X) + 0xb8)
+#define DDRC_ECCPOISONADDR1(X)   (DDRC_IPS_BASE_ADDR(X) + 0xbc)
+#define DDRC_CRCPARCTL0(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc0)
+#define DDRC_CRCPARCTL1(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc4)
+#define DDRC_CRCPARCTL2(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc8)
+#define DDRC_CRCPARSTAT(X)       (DDRC_IPS_BASE_ADDR(X) + 0xcc)
+#define DDRC_INIT0(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd0)
+#define DDRC_INIT1(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd4)
+#define DDRC_INIT2(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd8)
+#define DDRC_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0xdc)
+#define DDRC_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe0)
+#define DDRC_INIT5(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe4)
+#define DDRC_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe8)
+#define DDRC_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0xec)
+#define DDRC_DIMMCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf0)
+#define DDRC_RANKCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf4)
+#define DDRC_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x100)
+#define DDRC_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x104)
+#define DDRC_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x108)
+#define DDRC_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x10c)
+#define DDRC_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x110)
+#define DDRC_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x114)
+#define DDRC_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x118)
+#define DDRC_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x11c)
+#define DDRC_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x120)
+#define DDRC_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x124)
+#define DDRC_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x128)
+#define DDRC_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x12c)
+#define DDRC_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x130)
+#define DDRC_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x134)
+#define DDRC_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x138)
+#define DDRC_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x13C)
+#define DDRC_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x140)
+#define DDRC_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x144)
+#define DDRC_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x180)
+#define DDRC_ZQCTL1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x184)
+#define DDRC_ZQCTL2(X)           (DDRC_IPS_BASE_ADDR(X) + 0x188)
+#define DDRC_ZQSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x18c)
+#define DDRC_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x190)
+#define DDRC_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x194)
+#define DDRC_DFILPCFG0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x198)
+#define DDRC_DFILPCFG1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x19c)
+#define DDRC_DFIUPD0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
+#define DDRC_DFIUPD1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
+#define DDRC_DFIUPD2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
+#define DDRC_DFIMISC(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
+#define DDRC_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
+#define DDRC_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
+#define DDRC_DFISTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
+#define DDRC_DBICTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
+#define DDRC_DFIPHYMSTR(X)       (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
+#define DDRC_TRAINCTL0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
+#define DDRC_TRAINCTL1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
+#define DDRC_TRAINCTL2(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
+#define DDRC_TRAINSTAT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
+#define DDRC_ADDRMAP0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x200)
+#define DDRC_ADDRMAP1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x204)
+#define DDRC_ADDRMAP2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x208)
+#define DDRC_ADDRMAP3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x20c)
+#define DDRC_ADDRMAP4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x210)
+#define DDRC_ADDRMAP5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x214)
+#define DDRC_ADDRMAP6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x218)
+#define DDRC_ADDRMAP7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21c)
+#define DDRC_ADDRMAP8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x220)
+#define DDRC_ADDRMAP9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x224)
+#define DDRC_ADDRMAP10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x228)
+#define DDRC_ADDRMAP11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x22c)
+#define DDRC_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x240)
+#define DDRC_ODTMAP(X)           (DDRC_IPS_BASE_ADDR(X) + 0x244)
+#define DDRC_SCHED(X)            (DDRC_IPS_BASE_ADDR(X) + 0x250)
+#define DDRC_SCHED1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x254)
+#define DDRC_PERFHPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x25c)
+#define DDRC_PERFLPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x264)
+#define DDRC_PERFWR1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x26c)
+#define DDRC_PERFVPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x274)
+#define DDRC_PERFVPW1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x278)
+#define DDRC_DQMAP0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x280)
+#define DDRC_DQMAP1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x284)
+#define DDRC_DQMAP2(X)           (DDRC_IPS_BASE_ADDR(X) + 0x288)
+#define DDRC_DQMAP3(X)           (DDRC_IPS_BASE_ADDR(X) + 0x28c)
+#define DDRC_DQMAP4(X)           (DDRC_IPS_BASE_ADDR(X) + 0x290)
+#define DDRC_DQMAP5(X)           (DDRC_IPS_BASE_ADDR(X) + 0x294)
+#define DDRC_DBG0(X)             (DDRC_IPS_BASE_ADDR(X) + 0x300)
+#define DDRC_DBG1(X)             (DDRC_IPS_BASE_ADDR(X) + 0x304)
+#define DDRC_DBGCAM(X)           (DDRC_IPS_BASE_ADDR(X) + 0x308)
+#define DDRC_DBGCMD(X)           (DDRC_IPS_BASE_ADDR(X) + 0x30c)
+#define DDRC_DBGSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x310)
+#define DDRC_SWCTL(X)            (DDRC_IPS_BASE_ADDR(X) + 0x320)
+#define DDRC_SWSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x324)
+#define DDRC_OCPARCFG0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x330)
+#define DDRC_OCPARCFG1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x334)
+#define DDRC_OCPARCFG2(X)        (DDRC_IPS_BASE_ADDR(X) + 0x338)
+#define DDRC_OCPARCFG3(X)        (DDRC_IPS_BASE_ADDR(X) + 0x33c)
+#define DDRC_OCPARSTAT0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x340)
+#define DDRC_OCPARSTAT1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x344)
+#define DDRC_OCPARWLOG0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x348)
+#define DDRC_OCPARWLOG1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x34c)
+#define DDRC_OCPARWLOG2(X)       (DDRC_IPS_BASE_ADDR(X) + 0x350)
+#define DDRC_OCPARAWLOG0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x354)
+#define DDRC_OCPARAWLOG1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x358)
+#define DDRC_OCPARRLOG0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x35c)
+#define DDRC_OCPARRLOG1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x360)
+#define DDRC_OCPARARLOG0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x364)
+#define DDRC_OCPARARLOG1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x368)
+#define DDRC_POISONCFG(X)        (DDRC_IPS_BASE_ADDR(X) + 0x36C)
+#define DDRC_POISONSTAT(X)       (DDRC_IPS_BASE_ADDR(X) + 0x370)
+
+#define DDRC_PSTAT(X)            (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
+#define DDRC_PCCFG(X)            (DDRC_IPS_BASE_ADDR(X) + 0x400)
+#define DDRC_PCFGR_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x404)
+#define DDRC_PCFGR_1(X)          (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
+#define DDRC_PCFGR_2(X)          (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
+#define DDRC_PCFGR_3(X)          (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
+#define DDRC_PCFGW_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x408)
+#define DDRC_PCFGW_1(X)          (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
+#define DDRC_PCFGW_2(X)          (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
+#define DDRC_PCFGW_3(X)          (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
+#define DDRC_PCFGC_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x40c)
+#define DDRC_PCFGIDMASKCH(X)     (DDRC_IPS_BASE_ADDR(X) + 0x410)
+#define DDRC_PCFGIDVALUECH(X)    (DDRC_IPS_BASE_ADDR(X) + 0x414)
+#define DDRC_PCTRL_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490)
+#define DDRC_PCTRL_1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
+#define DDRC_PCTRL_2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
+#define DDRC_PCTRL_3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
+#define DDRC_PCFGQOS0_0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x494)
+#define DDRC_PCFGQOS1_0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x498)
+#define DDRC_PCFGWQOS0_0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x49c)
+#define DDRC_PCFGWQOS1_0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
+#define DDRC_SARBASE0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xf04)
+#define DDRC_SARSIZE0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xf08)
+#define DDRC_SBRCTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0xf24)
+#define DDRC_SBRSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf28)
+#define DDRC_SBRWDATA0(X)        (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
+#define DDRC_SBRWDATA1(X)        (DDRC_IPS_BASE_ADDR(X) + 0xf30)
+#define DDRC_PDCH(X)             (DDRC_IPS_BASE_ADDR(X) + 0xf34)
+
+#define DDRC_FREQ1_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2020)
+#define DDRC_FREQ1_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2024)
+#define DDRC_FREQ1_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2050)
+#define DDRC_FREQ1_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2064)
+#define DDRC_FREQ1_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
+#define DDRC_FREQ1_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
+#define DDRC_FREQ1_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
+#define DDRC_FREQ1_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
+#define DDRC_FREQ1_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2100)
+#define DDRC_FREQ1_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2104)
+#define DDRC_FREQ1_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2108)
+#define DDRC_FREQ1_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x210c)
+#define DDRC_FREQ1_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2110)
+#define DDRC_FREQ1_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2114)
+#define DDRC_FREQ1_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2118)
+#define DDRC_FREQ1_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x211c)
+#define DDRC_FREQ1_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2120)
+#define DDRC_FREQ1_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2124)
+#define DDRC_FREQ1_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2128)
+#define DDRC_FREQ1_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x212c)
+#define DDRC_FREQ1_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2130)
+#define DDRC_FREQ1_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2134)
+#define DDRC_FREQ1_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2138)
+#define DDRC_FREQ1_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x213C)
+#define DDRC_FREQ1_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2140)
+#define DDRC_FREQ1_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2144)
+#define DDRC_FREQ1_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x2180)
+#define DDRC_FREQ1_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_FREQ1_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_FREQ1_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_FREQ1_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_FREQ1_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+#define DDRC_FREQ2_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3020)
+#define DDRC_FREQ2_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3024)
+#define DDRC_FREQ2_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3050)
+#define DDRC_FREQ2_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3064)
+#define DDRC_FREQ2_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
+#define DDRC_FREQ2_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
+#define DDRC_FREQ2_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
+#define DDRC_FREQ2_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
+#define DDRC_FREQ2_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3100)
+#define DDRC_FREQ2_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3104)
+#define DDRC_FREQ2_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3108)
+#define DDRC_FREQ2_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x310c)
+#define DDRC_FREQ2_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3110)
+#define DDRC_FREQ2_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3114)
+#define DDRC_FREQ2_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3118)
+#define DDRC_FREQ2_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x311c)
+#define DDRC_FREQ2_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3120)
+#define DDRC_FREQ2_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3124)
+#define DDRC_FREQ2_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3128)
+#define DDRC_FREQ2_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x312c)
+#define DDRC_FREQ2_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3130)
+#define DDRC_FREQ2_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3134)
+#define DDRC_FREQ2_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3138)
+#define DDRC_FREQ2_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x313C)
+#define DDRC_FREQ2_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3140)
+#define DDRC_FREQ2_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3144)
+#define DDRC_FREQ2_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x3180)
+#define DDRC_FREQ2_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3190)
+#define DDRC_FREQ2_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3194)
+#define DDRC_FREQ2_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
+#define DDRC_FREQ2_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
+#define DDRC_FREQ2_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x3240)
+
+#define DDRC_FREQ3_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4020)
+#define DDRC_FREQ3_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4024)
+#define DDRC_FREQ3_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4050)
+#define DDRC_FREQ3_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4064)
+#define DDRC_FREQ3_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
+#define DDRC_FREQ3_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
+#define DDRC_FREQ3_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
+#define DDRC_FREQ3_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
+#define DDRC_FREQ3_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4100)
+#define DDRC_FREQ3_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4104)
+#define DDRC_FREQ3_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4108)
+#define DDRC_FREQ3_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x410c)
+#define DDRC_FREQ3_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4110)
+#define DDRC_FREQ3_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4114)
+#define DDRC_FREQ3_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4118)
+#define DDRC_FREQ3_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x411c)
+#define DDRC_FREQ3_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4120)
+#define DDRC_FREQ3_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4124)
+#define DDRC_FREQ3_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4128)
+#define DDRC_FREQ3_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x412c)
+#define DDRC_FREQ3_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4130)
+#define DDRC_FREQ3_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4134)
+#define DDRC_FREQ3_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4138)
+#define DDRC_FREQ3_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x413C)
+#define DDRC_FREQ3_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4140)
+
+#define DDRC_FREQ3_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x4180)
+#define DDRC_FREQ3_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4190)
+#define DDRC_FREQ3_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4194)
+#define DDRC_FREQ3_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
+#define DDRC_FREQ3_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
+#define DDRC_FREQ3_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x4240)
+#define DDRC_DFITMG0_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_DFITMG1_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_DFITMG2_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_DFITMG3_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_ODTCFG_SHADOW(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097)
+
+#define DRC_PERF_MON_BASE_ADDR(X)            (0x3d800000 + ((X) * 0x2000000))
+#define DRC_PERF_MON_CNT0_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
+#define DRC_PERF_MON_CNT1_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x4)
+#define DRC_PERF_MON_CNT2_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x8)
+#define DRC_PERF_MON_CNT3_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0xC)
+#define DRC_PERF_MON_CNT0_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x20)
+#define DRC_PERF_MON_CNT1_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x24)
+#define DRC_PERF_MON_CNT2_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x28)
+#define DRC_PERF_MON_CNT3_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x2C)
+#define DRC_PERF_MON_MRR0_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x40)
+#define DRC_PERF_MON_MRR1_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x44)
+#define DRC_PERF_MON_MRR2_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x48)
+#define DRC_PERF_MON_MRR3_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x4C)
+#define DRC_PERF_MON_MRR4_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x50)
+#define DRC_PERF_MON_MRR5_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x54)
+#define DRC_PERF_MON_MRR6_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x58)
+#define DRC_PERF_MON_MRR7_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x5C)
+#define DRC_PERF_MON_MRR8_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x60)
+#define DRC_PERF_MON_MRR9_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x64)
+#define DRC_PERF_MON_MRR10_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x68)
+#define DRC_PERF_MON_MRR11_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x6C)
+#define DRC_PERF_MON_MRR12_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x70)
+#define DRC_PERF_MON_MRR13_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x74)
+#define DRC_PERF_MON_MRR14_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x78)
+#define DRC_PERF_MON_MRR15_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x7C)
+
+/* user data type */
+enum fw_type {
+	FW_1D_IMAGE,
+	FW_2D_IMAGE,
+};
+
+struct dram_cfg_param {
+	unsigned int reg;
+	unsigned int val;
+};
+
+struct dram_fsp_msg {
+	unsigned int drate;
+	enum fw_type fw_type;
+	struct dram_cfg_param *fsp_cfg;
+	unsigned int fsp_cfg_num;
+};
+
+struct dram_timing_info {
+	/* umctl2 config */
+	struct dram_cfg_param *ddrc_cfg;
+	unsigned int ddrc_cfg_num;
+	/* ddrphy config */
+	struct dram_cfg_param *ddrphy_cfg;
+	unsigned int ddrphy_cfg_num;
+	/* ddr fsp train info */
+	struct dram_fsp_msg *fsp_msg;
+	unsigned int fsp_msg_num;
+	/* ddr phy trained CSR */
+	struct dram_cfg_param *ddrphy_trained_csr;
+	unsigned int ddrphy_trained_csr_num;
+	/* ddr phy PIE */
+	struct dram_cfg_param *ddrphy_pie;
+	unsigned int ddrphy_pie_num;
+	/* initialized drate table */
+	unsigned int fsp_table[4];
+};
+
+extern struct dram_timing_info dram_timing;
+
+void ddr_load_train_firmware(enum fw_type type);
+void ddr_init(struct dram_timing_info *timing_info);
+void ddr_cfg_phy(struct dram_timing_info *timing_info);
+void load_lpddr4_phy_pie(void);
+void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
+void dram_config_save(struct dram_timing_info *info, unsigned long base);
+
+/* utils function for ddr phy training */
+void wait_ddrphy_training_complete(void);
+void ddrphy_init_set_dfi_clk(unsigned int drate);
+void ddrphy_init_read_msg_block(enum fw_type type);
+
+static inline void reg32_write(unsigned long addr, u32 val)
+{
+	writel(val, addr);
+}
+
+static inline u32 reg32_read(unsigned long addr)
+{
+	return readl(addr);
+}
+
+static inline void reg32setbit(unsigned long addr, u32 bit)
+{
+	setbits_le32(addr, (1 << bit));
+}
+
+#define dwc_ddrphy_apb_wr(addr, data) \
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
+#define dwc_ddrphy_apb_rd(addr) \
+	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
+
+extern struct dram_cfg_param ddrphy_trained_csr[];
+extern uint32_t ddrphy_trained_csr_num;
+
+#endif

arch/arm/include/asm/arch-imx8m/gpio.h

@@ -3,8 +3,8 @@
  * Copyright 2017 NXP
  */
 
-#ifndef __ASM_ARCH_MX8M_GPIO_H
-#define __ASM_ARCH_MX8M_GPIO_H
+#ifndef __ASM_ARCH_IMX8M_GPIO_H
+#define __ASM_ARCH_IMX8M_GPIO_H
 
 #include <asm/mach-imx/gpio.h>
 

arch/arm/include/asm/arch-imx8m/imx-regs.h

@@ -3,8 +3,8 @@
  * Copyright 2017 NXP
  */
 
-#ifndef __ASM_ARCH_MX8M_REGS_H__
-#define __ASM_ARCH_MX8M_REGS_H__
+#ifndef __ASM_ARCH_IMX8M_REGS_H__
+#define __ASM_ARCH_IMX8M_REGS_H__
 
 #include <asm/mach-imx/regs-lcdif.h>
 

arch/arm/include/asm/arch-imx8m/imx8mq_pins.h

@@ -3,8 +3,8 @@
  * Copyright (C) 2017 NXP
  */
 
-#ifndef __ASM_ARCH_MX8MQ_PINS_H__
-#define __ASM_ARCH_MX8MQ_PINS_H__
+#ifndef __ASM_ARCH_IMX8MQ_PINS_H__
+#define __ASM_ARCH_IMX8MQ_PINS_H__
 
 #include <asm/mach-imx/iomux-v3.h>
 

arch/arm/include/asm/arch-imx8m/lpddr4_define.h

@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LPDDR4_DEFINE_H_
+#define __LPDDR4_DEFINE_H_
+
+#define LPDDR4_DVFS_DBI
+#define DDR_ONE_RANK
+/* #define LPDDR4_DBI_ON */
+#define DFI_BUG_WR
+#define M845S_4GBx2
+#define PRETRAIN
+
+/* DRAM MR setting */
+#ifdef LPDDR4_DBI_ON
+#define LPDDR4_MR3			0xf1
+#define LPDDR4_PHY_DMIPinPresent	0x1
+#else
+#define LPDDR4_MR3			0x31
+#define LPDDR4_PHY_DMIPinPresent	0x0
+#endif
+
+#ifdef DDR_ONE_RANK
+#define LPDDR4_CS			0x1
+#else
+#define LPDDR4_CS			0x3
+#endif
+
+/* PHY training feature */
+#define LPDDR4_HDT_CTL_2D		0xC8
+#define LPDDR4_HDT_CTL_3200_1D		0xC8
+#define LPDDR4_HDT_CTL_400_1D		0xC8
+#define LPDDR4_HDT_CTL_100_1D		0xC8
+
+/* 400/100 training seq */
+#define LPDDR4_TRAIN_SEQ_P2		0x121f
+#define LPDDR4_TRAIN_SEQ_P1		0x121f
+#define LPDDR4_TRAIN_SEQ_P0		0x121f
+#define LPDDR4_TRAIN_SEQ_100		0x121f
+#define LPDDR4_TRAIN_SEQ_400		0x121f
+
+/* 2D share & weight */
+#define LPDDR4_2D_WEIGHT		0x1f7f
+#define LPDDR4_2D_SHARE			1
+#define LPDDR4_CATRAIN_3200_1d		0
+#define LPDDR4_CATRAIN_400		0
+#define LPDDR4_CATRAIN_100		0
+#define LPDDR4_CATRAIN_3200_2d		0
+
+/* MRS parameter */
+/* for LPDDR4 Rtt */
+#define LPDDR4_RTT40			6
+#define LPDDR4_RTT48			5
+#define LPDDR4_RTT60			4
+#define LPDDR4_RTT80			3
+#define LPDDR4_RTT120			2
+#define LPDDR4_RTT240			1
+#define LPDDR4_RTT_DIS			0
+
+/* for LPDDR4 Ron */
+#define LPDDR4_RON34			7
+#define LPDDR4_RON40			6
+#define LPDDR4_RON48			5
+#define LPDDR4_RON60			4
+#define LPDDR4_RON80			3
+
+#define LPDDR4_PHY_ADDR_RON60		0x1
+#define LPDDR4_PHY_ADDR_RON40		0x3
+#define LPDDR4_PHY_ADDR_RON30		0x7
+#define LPDDR4_PHY_ADDR_RON24		0xf
+#define LPDDR4_PHY_ADDR_RON20		0x1f
+
+/* for read channel */
+#define LPDDR4_RON			LPDDR4_RON40
+#define LPDDR4_PHY_RTT			30
+#define LPDDR4_PHY_VREF_VALUE		17
+
+/* for write channel */
+#define LPDDR4_PHY_RON			30
+#define LPDDR4_PHY_ADDR_RON		LPDDR4_PHY_ADDR_RON40
+#define LPDDR4_RTT_DQ			LPDDR4_RTT40
+#define LPDDR4_RTT_CA			LPDDR4_RTT40
+#define LPDDR4_RTT_CA_BANK0		LPDDR4_RTT40
+#define LPDDR4_RTT_CA_BANK1		LPDDR4_RTT40
+#define LPDDR4_VREF_VALUE_CA		((1 << 6) | (0xd))
+#define LPDDR4_VREF_VALUE_DQ_RANK0	((1 << 6) | (0xd))
+#define LPDDR4_VREF_VALUE_DQ_RANK1	((1 << 6) | (0xd))
+#define LPDDR4_MR22_RANK0		((0 << 5) | (1 << 4) | (0 << 3) | \
+					(LPDDR4_RTT40))
+#define LPDDR4_MR22_RANK1		((1 << 5) | (1 << 4) | (1 << 3) | \
+					(LPDDR4_RTT40))
+
+#define LPDDR4_MR3_PU_CAL		1
+
+#endif /* __LPDDR4_DEFINE_H__ */

arch/arm/include/asm/arch-imx8m/sys_proto.h

@@ -3,8 +3,8 @@
  * Copyright (C) 2017 NXP
  */
 
-#ifndef __ARCH_MX8M_SYS_PROTO_H
-#define __ARCH_MX8M_SYS_PROTO_H
+#ifndef __ARCH_IMX8M_SYS_PROTO_H
+#define __ARCH_NMX8M_SYS_PROTO_H
 
 #include <asm/mach-imx/sys_proto.h>
 

arch/arm/include/asm/arch-mx8m/ddr.h

@@ -1,355 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2017 NXP
- */
-
-#ifndef __ASM_ARCH_MX8M_DDR_H
-#define __ASM_ARCH_MX8M_DDR_H
-
-#define DDRC_DDR_SS_GPR0		0x3d000000
-#define DDRC_IPS_BASE_ADDR_0		0x3f400000
-#define IP2APB_DDRPHY_IPS_BASE_ADDR(X)	(0x3c000000 + (X * 0x2000000))
-#define DDRPHY_MEM(X)			(0x3c000000 + (X * 0x2000000) + 0x50000)
-
-struct ddrc_freq {
-	u32 res0[8];
-	u32 derateen;
-	u32 derateint;
-	u32 res1[10];
-	u32 rfshctl0;
-	u32 res2[4];
-	u32 rfshtmg;
-	u32 rfshtmg1;
-	u32 res3[28];
-	u32 init3;
-	u32 init4;
-	u32 res;
-	u32 init6;
-	u32 init7;
-	u32 res4[4];
-	u32 dramtmg0;
-	u32 dramtmg1;
-	u32 dramtmg2;
-	u32 dramtmg3;
-	u32 dramtmg4;
-	u32 dramtmg5;
-	u32 dramtmg6;
-	u32 dramtmg7;
-	u32 dramtmg8;
-	u32 dramtmg9;
-	u32 dramtmg10;
-	u32 dramtmg11;
-	u32 dramtmg12;
-	u32 dramtmg13;
-	u32 dramtmg14;
-	u32 dramtmg15;
-	u32 dramtmg16;
-	u32 dramtmg17;
-	u32 res5[10];
-	u32 mramtmg0;
-	u32 mramtmg1;
-	u32 mramtmg4;
-	u32 mramtmg9;
-	u32 zqctl0;
-	u32 res6[3];
-	u32 dfitmg0;
-	u32 dfitmg1;
-	u32 res7[7];
-	u32 dfitmg2;
-	u32 dfitmg3;
-	u32 res8[33];
-	u32 odtcfg;
-};
-
-struct imx8m_ddrc_regs {
-	u32 mstr;
-	u32 stat;
-	u32 mstr1;
-	u32 res1;
-	u32 mrctrl0;
-	u32 mrctrl1;
-	u32 mrstat;
-	u32 mrctrl2;
-	u32 derateen;
-	u32 derateint;
-	u32 mstr2;
-	u32 res2;
-	u32 pwrctl;
-	u32 pwrtmg;
-	u32 hwlpctl;
-	u32 hwffcctl;
-	u32 hwffcstat;
-	u32 res3[3];
-	u32 rfshctl0;
-	u32 rfshctl1;
-	u32 rfshctl2;
-	u32 rfshctl4;
-	u32 rfshctl3;
-	u32 rfshtmg;
-	u32 rfshtmg1;
-	u32 res4;
-	u32 ecccfg0;
-	u32 ecccfg1;
-	u32 eccstat;
-	u32 eccclr;
-	u32 eccerrcnt;
-	u32 ecccaddr0;
-	u32 ecccaddr1;
-	u32 ecccsyn0;
-	u32 ecccsyn1;
-	u32 ecccsyn2;
-	u32 eccbitmask0;
-	u32 eccbitmask1;
-	u32 eccbitmask2;
-	u32 eccuaddr0;
-	u32 eccuaddr1;
-	u32 eccusyn0;
-	u32 eccusyn1;
-	u32 eccusyn2;
-	u32 eccpoisonaddr0;
-	u32 eccpoisonaddr1;
-	u32 crcparctl0;
-	u32 crcparctl1;
-	u32 crcparctl2;
-	u32 crcparstat;
-	u32 init0;
-	u32 init1;
-	u32 init2;
-	u32 init3;
-	u32 init4;
-	u32 init5;
-	u32 init6;
-	u32 init7;
-	u32 dimmctl;
-	u32 rankctl;
-	u32 res5;
-	u32 chctl;
-	u32 dramtmg0;
-	u32 dramtmg1;
-	u32 dramtmg2;
-	u32 dramtmg3;
-	u32 dramtmg4;
-	u32 dramtmg5;
-	u32 dramtmg6;
-	u32 dramtmg7;
-	u32 dramtmg8;
-	u32 dramtmg9;
-	u32 dramtmg10;
-	u32 dramtmg11;
-	u32 dramtmg12;
-	u32 dramtmg13;
-	u32 dramtmg14;
-	u32 dramtmg15;
-	u32 dramtmg16;
-	u32 dramtmg17;
-	u32 res6[10];
-	u32 mramtmg0;
-	u32 mramtmg1;
-	u32 mramtmg4;
-	u32 mramtmg9;
-	u32 zqctl0;
-	u32 zqctl1;
-	u32 zqctl2;
-	u32 zqstat;
-	u32 dfitmg0;
-	u32 dfitmg1;
-	u32 dfilpcfg0;
-	u32 dfilpcfg1;
-	u32 dfiupd0;
-	u32 dfiupd1;
-	u32 dfiupd2;
-	u32 res7;
-	u32 dfimisc;
-	u32 dfitmg2;
-	u32 dfitmg3;
-	u32 dfistat;
-	u32 dbictl;
-	u32 dfiphymstr;
-	u32 res8[14];
-	u32 addrmap0;
-	u32 addrmap1;
-	u32 addrmap2;
-	u32 addrmap3;
-	u32 addrmap4;
-	u32 addrmap5;
-	u32 addrmap6;
-	u32 addrmap7;
-	u32 addrmap8;
-	u32 addrmap9;
-	u32 addrmap10;
-	u32 addrmap11;
-	u32 res9[4];
-	u32 odtcfg;
-	u32 odtmap;
-	u32 res10[2];
-	u32 sched;
-	u32 sched1;
-	u32 sched2;
-	u32 perfhpr1;
-	u32 res11;
-	u32 perflpr1;
-	u32 res12;
-	u32 perfwr1;
-	u32 res13[4];
-	u32 dqmap0;
-	u32 dqmap1;
-	u32 dqmap2;
-	u32 dqmap3;
-	u32 dqmap4;
-	u32 dqmap5;
-	u32 res14[26];
-	u32 dbg0;
-	u32 dbg1;
-	u32 dbgcam;
-	u32 dbgcmd;
-	u32 dbgstat;
-	u32 res15[3];
-	u32 swctl;
-	u32 swstat;
-	u32 res16[2];
-	u32 ocparcfg0;
-	u32 ocparcfg1;
-	u32 ocparcfg2;
-	u32 ocparcfg3;
-	u32 ocparstat0;
-	u32 ocparstat1;
-	u32 ocparwlog0;
-	u32 ocparwlog1;
-	u32 ocparwlog2;
-	u32 ocparawlog0;
-	u32 ocparawlog1;
-	u32 ocparrlog0;
-	u32 ocparrlog1;
-	u32 ocpararlog0;
-	u32 ocpararlog1;
-	u32 poisoncfg;
-	u32 poisonstat;
-	u32 adveccindex;
-	union  {
-		u32 adveccstat;
-		u32 eccapstat;
-	};
-	u32 eccpoisonpat0;
-	u32 eccpoisonpat1;
-	u32 eccpoisonpat2;
-	u32 res17[6];
-	u32 caparpoisonctl;
-	u32 caparpoisonstat;
-	u32 res18[2];
-	u32 dynbsmstat;
-	u32 res19[18];
-	u32 pstat;
-	u32 pccfg;
-	struct {
-		u32 pcfgr;
-		u32 pcfgw;
-		u32 pcfgc;
-		struct {
-			u32 pcfgidmaskch0;
-			u32 pcfidvaluech0;
-		} pcfgid[16];
-		u32 pctrl;
-		u32 pcfgqos0;
-		u32 pcfgqos1;
-		u32 pcfgwqos0;
-		u32 pcfgwqos1;
-		u32 res[4];
-	} pcfg[16];
-	struct {
-		u32 sarbase;
-		u32 sarsize;
-	} sar[4];
-	u32 sbrctl;
-	u32 sbrstat;
-	u32 sbrwdata0;
-	u32 sbrwdata1;
-	u32 pdch;
-	u32 res20[755];
-	/* umctl2_regs_dch1 */
-	u32 ch1_stat;
-	u32 res21[2];
-	u32 ch1_mrctrl0;
-	u32 ch1_mrctrl1;
-	u32 ch1_mrstat;
-	u32 ch1_mrctrl2;
-	u32 res22[4];
-	u32 ch1_pwrctl;
-	u32 ch1_pwrtmg;
-	u32 ch1_hwlpctl;
-	u32 res23[15];
-	u32 ch1_eccstat;
-	u32 ch1_eccclr;
-	u32 ch1_eccerrcnt;
-	u32 ch1_ecccaddr0;
-	u32 ch1_ecccaddr1;
-	u32 ch1_ecccsyn0;
-	u32 ch1_ecccsyn1;
-	u32 ch1_ecccsyn2;
-	u32 ch1_eccbitmask0;
-	u32 ch1_eccbitmask1;
-	u32 ch1_eccbitmask2;
-	u32 ch1_eccuaddr0;
-	u32 ch1_eccuaddr1;
-	u32 ch1_eccusyn0;
-	u32 ch1_eccusyn1;
-	u32 ch1_eccusyn2;
-	u32 res24[2];
-	u32 ch1_crcparctl0;
-	u32 res25[2];
-	u32 ch1_crcparstat;
-	u32 res26[46];
-	u32 ch1_zqctl2;
-	u32 ch1_zqstat;
-	u32 res27[11];
-	u32 ch1_dfistat;
-	u32 res28[33];
-	u32 ch1_odtmap;
-	u32 res29[47];
-	u32 ch1_dbg1;
-	u32 ch1_dbgcam;
-	u32 ch1_dbgcmd;
-	u32 ch1_dbgstat;
-	u32 res30[123];
-	/* umctl2_regs_freq1 */
-	struct ddrc_freq freq1;
-	u32 res31[109];
-	/* umctl2_regs_addrmap_alt */
-	u32 addrmap0_alt;
-	u32 addrmap1_alt;
-	u32 addrmap2_alt;
-	u32 addrmap3_alt;
-	u32 addrmap4_alt;
-	u32 addrmap5_alt;
-	u32 addrmap6_alt;
-	u32 addrmap7_alt;
-	u32 addrmap8_alt;
-	u32 addrmap9_alt;
-	u32 addrmap10_alt;
-	u32 addrmap11_alt;
-	u32 res32[758];
-	/* umctl2_regs_freq2 */
-	struct ddrc_freq freq2;
-	u32 res33[879];
-	/* umctl2_regs_freq3 */
-	struct ddrc_freq freq3;
-};
-
-struct imx8m_ddrphy_regs {
-	u32 reg[0xf0000];
-};
-
-/* PHY State */
-enum pstate {
-	PS0,
-	PS1,
-	PS2,
-	PS3,
-};
-
-enum msg_response {
-	TRAIN_SUCCESS = 0x7,
-	TRAIN_STREAM_START = 0x8,
-	TRAIN_FAIL = 0xff,
-};
-
-#endif

arch/arm/include/asm/arch-vf610/imx-regs.h

@@ -200,7 +200,8 @@
 #define DDRMC_CR78_Q_FULLNESS(v)			(((v) & 0x7) << 24)
 #define DDRMC_CR78_BUR_ON_FLY_BIT(v)			((v) & 0xf)
 #define DDRMC_CR79_CTLUPD_AREF(v)			(((v) & 0x1) << 24)
-#define DDRMC_CR82_INT_MASK				0x10000000
+#define DDRMC_CR80_MC_INIT_COMPLETE			(1 << 8)
+#define DDRMC_CR82_INT_MASK				(1 << 28)
 #define DDRMC_CR87_ODT_WR_MAPCS0(v)			((v) << 24)
 #define DDRMC_CR87_ODT_RD_MAPCS0(v)			((v) << 16)
 #define DDRMC_CR88_TODTL_CMD(v)				(((v) & 0x1f) << 16)
@@ -239,7 +240,7 @@
 #define DDRMC_CR132_RDLAT_ADJ(v)			((v) & 0x3f)
 #define DDRMC_CR137_PHYCTL_DL(v)			(((v) & 0xf) << 16)
 #define DDRMC_CR138_PHY_WRLV_MXDL(v)			(((v) & 0xffff) << 16)
-#define DDRMC_CR138_PHYDRAM_CK_EN(v)			(((v) & 0x8) << 8)
+#define DDRMC_CR138_PHYDRAM_CK_EN(v)			(((v) & 0x7) << 8)
 #define DDRMC_CR139_PHY_WRLV_RESPLAT(v)			(((v) & 0xff) << 24)
 #define DDRMC_CR139_PHY_WRLV_LOAD(v)			(((v) & 0xff) << 16)
 #define DDRMC_CR139_PHY_WRLV_DLL(v)			(((v) & 0xff) << 8)

arch/arm/include/asm/arch-vf610/iomux-vf610.h

@@ -244,6 +244,8 @@ enum {
 	VF610_PAD_DDR_WE__DDR_WE_B		= IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_ODT1__DDR_ODT_0		= IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_ODT0__DDR_ODT_1		= IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1	= IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2	= IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 };
 
 #endif	/* __IOMUX_VF610_H__ */

arch/arm/include/asm/dma-mapping.h

@@ -13,7 +13,7 @@
 
 static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
 {
-	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN));
 	return (void *)*handle;
 }
 

arch/arm/include/asm/mach-imx/iomux-v3.h

@@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t;
 #define IOMUX_CONFIG_LPSR       0x20
 #define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
 				MUX_MODE_SHIFT)
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 #define PAD_CTL_DSE0		(0x0 << 0)
 #define PAD_CTL_DSE1		(0x1 << 0)
 #define PAD_CTL_DSE2		(0x2 << 0)

arch/arm/include/asm/mach-imx/regs-lcdif.h

@@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8M)
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
 #endif
 	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
@@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8M)
 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
 #endif
 	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
@@ -73,7 +73,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8M)
 	mxs_reg_32(hw_lcdif_thres)
 	mxs_reg_32(hw_lcdif_as_ctrl)
 	mxs_reg_32(hw_lcdif_as_buf)

arch/arm/include/asm/mach-imx/sys_proto.h

@@ -26,7 +26,7 @@
 
 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
-#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
+#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
@@ -42,6 +42,7 @@
 
 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
 
+#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
 
 #ifdef CONFIG_MX6

arch/arm/mach-exynos/include/mach/system.h

@@ -58,7 +58,7 @@ struct exynos5_sysreg {
 /* Move 0xd3 value to CPSR register to enable SVC mode */
 #define svc32_mode_en() __asm__ __volatile__				\
 			("@ I&F disable, Mode: 0x13 - SVC\n\t"		\
-			 "msr     cpsr_c, #0x13|0xC0\n\t" : : )
+			 "msr     cpsr_c, %0\n\t" : : "r"(0x13|0xC0))
 
 /* Set program counter with the given value */
 #define set_pc(x) __asm__ __volatile__ ("mov     pc, %0\n\t" : : "r"(x))

arch/arm/mach-imx/Makefile

@@ -5,12 +5,14 @@
 #
 # (C) Copyright 2011 Freescale Semiconductor, Inc.
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610))
 obj-y	= iomux-v3.o
 endif
 
-ifeq ($(SOC),$(filter $(SOC),mx8m))
+ifeq ($(SOC),$(filter $(SOC),imx8m))
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+endif
 obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
 obj-$(CONFIG_FEC_MXC) += mac.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
@@ -22,7 +24,7 @@ obj-y	+= cpu.o speed.o
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m))
 obj-y	+= misc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
@@ -104,7 +106,11 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%)
 ifeq ($(CONFIG_ARCH_IMX8), y)
 CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
 IMAGE_TYPE := imx8image
-DEPFILE_EXISTS := $(shell if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
+DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
+else ifeq ($(CONFIG_ARCH_IMX8M), y)
+IMAGE_TYPE := imx8mimage
+IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh
+DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi)
 else
 IMAGE_TYPE := imximage
 DEPFILE_EXISTS := 0
@@ -129,6 +135,26 @@ ifeq ($(DEPFILE_EXISTS),0)
 endif
 endif
 
+ifdef CONFIG_ARM64
+ifeq ($(CONFIG_ARCH_IMX8M), y)
+SPL:
+
+MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \
+		   -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
+flash.bin: MKIMAGEOUTPUT = flash.log
+
+spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
+ifeq ($(DEPFILE_EXISTS),0)
+	$(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1
+endif
+
+flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE
+ifeq ($(DEPFILE_EXISTS),0)
+	$(call if_changed,mkimage)
+endif
+endif
+
+else
 MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
 		   -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
 SPL: MKIMAGEOUTPUT = SPL.log
@@ -160,6 +186,7 @@ cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \
 
 spl/u-boot-nand-spl.imx: SPL FORCE
 	$(call if_changed,u-boot-nand-spl_imx)
+endif
 
 targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
 
@@ -169,5 +196,5 @@ obj-$(CONFIG_MX5) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
 obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
-obj-$(CONFIG_MX8M) += mx8m/
+obj-$(CONFIG_IMX8M) += imx8m/
 obj-$(CONFIG_ARCH_IMX8) += imx8/

arch/arm/mach-imx/cpu.c

@@ -62,7 +62,7 @@ static char *get_reset_cause(void)
 		return "WDOG4";
 	case 0x00200:
 		return "TEMPSENSE";
-#elif defined(CONFIG_MX8M)
+#elif defined(CONFIG_IMX8M)
 	case 0x00100:
 		return "WDOG2";
 	case 0x00200:
@@ -142,8 +142,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
-	case MXC_CPU_MX8MQ:
-		return "8MQ";	/* Quad-core version of the mx8m */
+	case MXC_CPU_IMX8MQ:
+		return "8MQ";	/* Quad-core version of the imx8m */
 	case MXC_CPU_MX7S:
 		return "7S";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
@@ -266,7 +266,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
+#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 u32 get_ahb_clk(void)
 {
 	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -300,7 +300,7 @@ void arch_preboot_os(void)
 #endif
 }
 
-#ifndef CONFIG_MX8M
+#ifndef CONFIG_IMX8M
 void set_chipselect_size(int const cs_size)
 {
 	unsigned int reg;
@@ -333,7 +333,7 @@ void set_chipselect_size(int const cs_size)
 }
 #endif
 
-#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
 /*
  * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  * defines a 2-bit SPEED_GRADING
@@ -409,7 +409,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 }
 #endif
 
-#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
 enum boot_device get_boot_device(void)
 {
 	struct bootrom_sw_info **p =
@@ -438,7 +438,7 @@ enum boot_device get_boot_device(void)
 	case BOOT_TYPE_SPINOR:
 		boot_dev = SPI_NOR_BOOT;
 		break;
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 	case BOOT_TYPE_USB:
 		boot_dev = USB_BOOT;
 		break;

arch/arm/mach-imx/ddrmc-vf610.c

@@ -61,6 +61,8 @@ void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
 		VF610_PAD_DDR_WE__DDR_WE_B,
 		VF610_PAD_DDR_ODT1__DDR_ODT_0,
 		VF610_PAD_DDR_ODT0__DDR_ODT_1,
+		VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
+		VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2,
 		VF610_PAD_DDR_RESETB,
 	};
 
@@ -188,7 +190,6 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 		   DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
 	writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
 		   DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
-	writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
 
 	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
 
@@ -231,6 +232,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 	/* all inits done, start the DDR controller */
 	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
 
-	while (!(readl(&ddrmr->cr[80]) && 0x100))
+	while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
 		udelay(10);
+	writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
 }

arch/arm/mach-imx/hab.c

@@ -6,6 +6,8 @@
 #include <common.h>
 #include <config.h>
 #include <fuse.h>
+#include <mapmem.h>
+#include <image.h>
 #include <asm/io.h>
 #include <asm/system.h>
 #include <asm/arch/clock.h>
@@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc,
 	return 0;
 }
 
+static ulong get_image_ivt_offset(ulong img_addr)
+{
+	const void *buf;
+
+	buf = map_sysmem(img_addr, 0);
+	switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+	case IMAGE_FORMAT_LEGACY:
+		return (image_get_image_size((image_header_t *)img_addr)
+			+ 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+#if IMAGE_ENABLE_FIT
+	case IMAGE_FORMAT_FIT:
+		return (fit_get_size(buf) + 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+	default:
+		return 0;
+	}
+}
+
 static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
 				 char * const argv[])
 {
 	ulong	addr, length, ivt_offset;
 	int	rcode = 0;
 
-	if (argc < 4)
+	if (argc < 3)
 		return CMD_RET_USAGE;
 
 	addr = simple_strtoul(argv[1], NULL, 16);
 	length = simple_strtoul(argv[2], NULL, 16);
-	ivt_offset = simple_strtoul(argv[3], NULL, 16);
+	if (argc == 3)
+		ivt_offset = get_image_ivt_offset(addr);
+	else
+		ivt_offset = simple_strtoul(argv[3], NULL, 16);
 
 	rcode = imx_hab_authenticate_image(addr, length, ivt_offset);
 	if (rcode == 0)

arch/arm/mach-imx/imx8/cpu.c

@@ -573,7 +573,7 @@ int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
 	if (size < 100)
 		return -ENOSPC;
 
-	snprintf(buf, size, "CPU:   Freescale i.MX8%s Rev%s %s at %u MHz\n",
+	snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n",
 		 plat->type, plat->rev, plat->name, plat->freq_mhz);
 
 	return 0;

arch/arm/mach-imx/imx8m/Kconfig

@@ -0,0 +1,23 @@
+if ARCH_IMX8M
+
+config IMX8M
+	bool
+	select ROM_UNIFIED_SECTIONS
+
+config SYS_SOC
+	default "imx8m"
+
+choice
+	prompt  "NXP i.MX8M board select"
+	optional
+
+config TARGET_IMX8MQ_EVK
+	bool "imx8mq_evk"
+	select IMX8M
+	select IMX8M_LPDDR4
+
+endchoice
+
+source "board/freescale/imx8mq_evk/Kconfig"
+
+endif

arch/arm/mach-imx/imx8m/clock.c

@@ -250,9 +250,9 @@ static u32 get_root_src_clk(enum clk_root_src root_src)
 	case OSC_25M_CLK:
 		return 25000000;
 	case OSC_27M_CLK:
-		return 25000000;
+		return 27000000;
 	case OSC_32K_CLK:
-		return 32000;
+		return 32768;
 	case ARM_PLL_CLK:
 		return decode_frac_pll(root_src);
 	case SYSTEM_PLL1_800M_CLK:
@@ -525,41 +525,127 @@ u32 imx_get_fecclk(void)
 	return get_root_clk(ENET_AXI_CLK_ROOT);
 }
 
-#ifdef CONFIG_SPL_BUILD
-void dram_pll_init(void)
+static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
+				CLK_ROOT_PRE_DIV2),
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
+				CLK_ROOT_PRE_DIV2),
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
+				CLK_ROOT_PRE_DIV2),
+};
+
+void dram_enable_bypass(ulong clk_val)
+{
+	int i;
+	struct dram_bypass_clk_setting *config;
+
+	for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
+		if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
+		printf("No matched freq table %lu\n", clk_val);
+		return;
+	}
+
+	config = &imx8mq_dram_bypass_tbl[i];
+
+	clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
+			     CLK_ROOT_PRE_DIV(config->alt_pre_div));
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
+			     CLK_ROOT_PRE_DIV(config->apb_pre_div));
+	clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1));
+}
+
+void dram_disable_bypass(void)
+{
+	clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(0));
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(4) |
+			     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
+}
+
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(ulong pll_val)
 {
-	struct src *src = (struct src *)SRC_BASE_ADDR;
-	void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
-	u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0;
 	u32 val;
-	int ret;
+	void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
+	void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
 
-	setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7));
-	setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5));
+	/* Bypass */
+	setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
+	setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
 
-	pwdn_mask = SSCG_PLL_PD_MASK;
-	pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
-	bypass1 = SSCG_PLL_BYPASS1_MASK;
-	bypass2 = SSCG_PLL_BYPASS2_MASK;
-
-	/* Enable DDR1 and DDR2 domain */
-	writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr);
-	writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr);
+	switch (pll_val) {
+	case MHZ(800):
+		val = readl(pll_cfg_reg2);
+		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+			 SSCG_PLL_REF_DIVR2_MASK);
+		val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
+		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
+		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+		val |= SSCG_PLL_REF_DIVR2_VAL(29);
+		writel(val, pll_cfg_reg2);
+		break;
+	case MHZ(600):
+		val = readl(pll_cfg_reg2);
+		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+			 SSCG_PLL_REF_DIVR2_MASK);
+		val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
+		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
+		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+		val |= SSCG_PLL_REF_DIVR2_VAL(29);
+		writel(val, pll_cfg_reg2);
+		break;
+	case MHZ(400):
+		val = readl(pll_cfg_reg2);
+		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+			 SSCG_PLL_REF_DIVR2_MASK);
+		val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
+		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
+		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+		val |= SSCG_PLL_REF_DIVR2_VAL(29);
+		writel(val, pll_cfg_reg2);
+		break;
+	case MHZ(167):
+		val = readl(pll_cfg_reg2);
+		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+			 SSCG_PLL_REF_DIVR2_MASK);
+		val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
+		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
+		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
+		val |= SSCG_PLL_REF_DIVR2_VAL(30);
+		writel(val, pll_cfg_reg2);
+		break;
+	default:
+		break;
+	}
 
 	/* Clear power down bit */
-	clrbits_le32(pll_control_reg, pwdn_mask);
+	clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
 	/* Eanble ARM_PLL/SYS_PLL  */
-	setbits_le32(pll_control_reg, pll_clke);
+	setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
 
 	/* Clear bypass */
-	clrbits_le32(pll_control_reg, bypass1);
+	clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
 	__udelay(100);
-	clrbits_le32(pll_control_reg, bypass2);
+	clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
 	/* Wait lock */
-	ret = readl_poll_timeout(pll_control_reg, val,
-				 val & SSCG_PLL_LOCK_MASK, 1);
-	if (ret)
-		printf("%s timeout\n", __func__);
+	while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
+		;
 }
 
 int frac_pll_init(u32 pll, enum frac_pll_out_val val)
@@ -730,7 +816,7 @@ int clock_init(void)
  * Dump some clockes.
  */
 #ifndef CONFIG_SPL_BUILD
-int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
 		       char * const argv[])
 {
 	u32 freq;
@@ -785,7 +871,7 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
 }
 
 U_BOOT_CMD(
-	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks,
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
 	"display clocks",
 	""
 );

arch/arm/mach-imx/imx8m/imximage.cfg

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define __ASSEMBLY__
+
+FIT
+BOOT_FROM	sd
+SIGNED_HDMI	signed_hdmi_imx8m.bin
+LOADER		spl/u-boot-spl-ddr.bin	0x7E1000
+SECOND_LOADER	u-boot.itb		0x40200000 0x60000
+
+DDR_FW lpddr4_pmu_train_1d_imem.bin
+DDR_FW lpddr4_pmu_train_1d_dmem.bin
+DDR_FW lpddr4_pmu_train_2d_imem.bin
+DDR_FW lpddr4_pmu_train_2d_dmem.bin

arch/arm/mach-imx/imx8m/soc.c

@@ -77,6 +77,22 @@ static struct mm_region imx8m_mem_map[] = {
 		.size = 0x100000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* CAAM */
+		.virt = 0x100000UL,
+		.phys = 0x100000UL,
+		.size = 0x8000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* TCM */
+		.virt = 0x7C0000UL,
+		.phys = 0x7C0000UL,
+		.size = 0x80000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
 		/* OCRAM */
 		.virt = 0x900000UL,

arch/arm/mach-imx/imx_bootaux.c

@@ -17,15 +17,15 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 	if (!boot_private_data)
 		return -EINVAL;
 
-	stack = *(ulong *)boot_private_data;
-	pc = *(ulong *)(boot_private_data + 4);
+	stack = *(u32 *)boot_private_data;
+	pc = *(u32 *)(boot_private_data + 4);
 
 	/* Set the stack and pc to M4 bootROM */
 	writel(stack, M4_BOOTROM_BASE_ADDR);
 	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
 
 	/* Enable M4 */
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 	call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
 #else
 	clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
@@ -37,7 +37,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 
 int arch_auxiliary_core_check_up(u32 core_id)
 {
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 	return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
 #else
 	unsigned int val;

arch/arm/mach-imx/mkimage_fit_atf.sh

@@ -0,0 +1,137 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for i.MX8MQ boards with
+# ARM Trusted Firmware and multiple device trees (given on the command line)
+#
+# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+
+[ -z "$BL31" ] && BL31="bl31.bin"
+[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
+[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000"
+
+if [ ! -f $BL31 ]; then
+	echo "ERROR: BL31 file $BL31 NOT found" >&2
+	exit 0
+else
+	echo "$BL31 size: " >&2
+	ls -lct $BL31 | awk '{print $5}' >&2
+fi
+
+BL32="tee.bin"
+
+if [ ! -f $BL32 ]; then
+	BL32=/dev/null
+else
+	echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
+	echo "$BL32 size: " >&2
+	ls -lct $BL32 | awk '{print $5}' >&2
+fi
+
+BL33="u-boot-nodtb.bin"
+
+if [ ! -f $BL33 ]; then
+	echo "ERROR: $BL33 file NOT found" >&2
+	exit 0
+else
+	echo "u-boot-nodtb.bin size: " >&2
+	ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2
+fi
+
+for dtname in $*
+do
+	echo "$dtname size: " >&2
+	ls -lct $dtname | awk '{print $5}' >&2
+done
+
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+	description = "Configuration to load ATF before U-Boot";
+
+	images {
+		uboot@1 {
+			description = "U-Boot (64-bit)";
+			data = /incbin/("$BL33");
+			type = "standalone";
+			arch = "arm64";
+			compression = "none";
+			load = <0x40200000>;
+		};
+		atf@1 {
+			description = "ARM Trusted Firmware";
+			data = /incbin/("$BL31");
+			type = "firmware";
+			arch = "arm64";
+			compression = "none";
+			load = <$ATF_LOAD_ADDR>;
+			entry = <$ATF_LOAD_ADDR>;
+		};
+__HEADER_EOF
+
+if [ -f $BL32 ]; then
+cat << __HEADER_EOF
+		tee@1 {
+			description = "TEE firmware";
+			data = /incbin/("$BL32");
+			type = "firmware";
+			arch = "arm64";
+			compression = "none";
+			load = <$TEE_LOAD_ADDR>;
+			entry = <$TEE_LOAD_ADDR>;
+		};
+__HEADER_EOF
+fi
+
+cnt=1
+for dtname in $*
+do
+	cat << __FDT_IMAGE_EOF
+		fdt@$cnt {
+			description = "$(basename $dtname .dtb)";
+			data = /incbin/("$dtname");
+			type = "flat_dt";
+			compression = "none";
+		};
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+	};
+	configurations {
+		default = "config@1";
+
+__CONF_HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+if [ -f $BL32 ]; then
+cat << __CONF_SECTION_EOF
+		config@$cnt {
+			description = "$(basename $dtname .dtb)";
+			firmware = "uboot@1";
+			loadables = "atf@1", "tee@1";
+			fdt = "fdt@$cnt";
+		};
+__CONF_SECTION_EOF
+else
+cat << __CONF_SECTION1_EOF
+		config@$cnt {
+			description = "$(basename $dtname .dtb)";
+			firmware = "uboot@1";
+			loadables = "atf@1";
+			fdt = "fdt@$cnt";
+		};
+__CONF_SECTION1_EOF
+fi
+cnt=$((cnt+1))
+done
+
+cat << __ITS_EOF
+	};
+};
+__ITS_EOF

arch/arm/mach-imx/mx6/Kconfig

@@ -182,6 +182,7 @@ config TARGET_DISPLAY5
 config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 	select BOARD_LATE_INIT
+	select SUPPORT_SPL
 
 config TARGET_GE_BX50V3
 	bool "General Electric Bx50v3"
@@ -262,7 +263,7 @@ config TARGET_MX6DL_MAMOJ
 	select SPL_PINCTRL if SPL
 	select SPL_SEPARATE_BSS if SPL
 	select SPL_SERIAL_SUPPORT if SPL
-	select SPL_USB_GADGET_SUPPORT if SPL
+	select SPL_USB_GADGET if SPL
 	select SPL_USB_HOST_SUPPORT if SPL
 	select SPL_USB_SDP_SUPPORT if SPL
 	select SPL_WATCHDOG_SUPPORT if SPL

arch/arm/mach-imx/mx8m/Kconfig

@@ -1,10 +0,0 @@
-if ARCH_MX8M
-
-config MX8M
-	bool
-	select ROM_UNIFIED_SECTIONS
-
-config SYS_SOC
-	default "mx8m"
-
-endif

arch/arm/mach-imx/spl.c

@@ -96,8 +96,8 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_NONE;
 }
 
-#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M)
-/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */
+#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
+/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
 u32 spl_boot_device(void)
 {
 #if defined(CONFIG_MX7)
@@ -126,6 +126,7 @@ u32 spl_boot_device(void)
 	enum boot_device boot_device_spl = get_boot_device();
 
 	switch (boot_device_spl) {
+#if defined(CONFIG_MX7)
 	case SD1_BOOT:
 	case MMC1_BOOT:
 	case SD2_BOOT:
@@ -133,6 +134,14 @@ u32 spl_boot_device(void)
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		return BOOT_DEVICE_MMC1;
+#elif defined(CONFIG_IMX8M)
+	case SD1_BOOT:
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC2;
+#endif
 	case NAND_BOOT:
 		return BOOT_DEVICE_NAND;
 	case SPI_NOR_BOOT:
@@ -143,9 +152,9 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_NONE;
 	}
 }
-#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
+#endif /* CONFIG_MX7 || CONFIG_IMX8M */
 
-#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
+#ifdef CONFIG_SPL_USB_GADGET
 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 {
 	put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM + 0xfff, &dev->idProduct);
@@ -220,14 +229,46 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 
 	debug("image entry point: 0x%lX\n", spl_image->entry_point);
 
-	/* HAB looks for the CSF at the end of the authenticated data therefore,
-	 * we need to subtract the size of the CSF from the actual filesize */
-	offset = spl_image->size - CONFIG_CSF_SIZE;
-	if (!imx_hab_authenticate_image(spl_image->load_addr,
-					offset + IVT_SIZE + CSF_PAD_SIZE,
-					offset)) {
+	if (spl_image->flags & SPL_FIT_FOUND) {
 		image_entry();
 	} else {
+		/*
+		 * HAB looks for the CSF at the end of the authenticated
+		 * data therefore, we need to subtract the size of the
+		 * CSF from the actual filesize
+		 */
+		offset = spl_image->size - CONFIG_CSF_SIZE;
+		if (!imx_hab_authenticate_image(spl_image->load_addr,
+						offset + IVT_SIZE +
+						CSF_PAD_SIZE, offset)) {
+			image_entry();
+		} else {
+			puts("spl: ERROR:  image authentication fail\n");
+			hang();
+		}
+	}
+}
+
+ulong board_spl_fit_size_align(ulong size)
+{
+	/*
+	 * HAB authenticate_image requests the IVT offset is
+	 * aligned to 0x1000
+	 */
+
+	size = ALIGN(size, 0x1000);
+	size += CONFIG_CSF_SIZE;
+
+	return size;
+}
+
+void board_spl_fit_post_load(ulong load_addr, size_t length)
+{
+	u32 offset = length - CONFIG_CSF_SIZE;
+
+	if (imx_hab_authenticate_image(load_addr,
+				       offset + IVT_SIZE + CSF_PAD_SIZE,
+				       offset)) {
 		puts("spl: ERROR:  image authentication unsuccessful\n");
 		hang();
 	}

arch/arm/mach-k3/config.mk

@@ -37,7 +37,7 @@ cmd_gencert = cat $(srctree)/tools/k3_x509template.txt | sed $(SED_OPTS) > u-boo
 ifeq ($(CONFIG_SYS_K3_KEY), "")
 KEY=u-boot-spl-eckey.pem
 else
-KEY=$(patsubst "%",%,$(CONFIG_SYS_K3_KEY))
+KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY))
 endif
 
 u-boot-spl-eckey.pem: FORCE

arch/arm/mach-mediatek/mt7629/lowlevel_init.S

@@ -5,6 +5,14 @@
 
 #include <linux/linkage.h>
 
+#define WAIT_CODE_SRAM_BASE	0x0010ff00
+
+#define SLAVE_JUMP_REG		0x10202034
+#define SLAVE1_MAGIC_REG	0x10202038
+#define SLAVE1_MAGIC_NUM	0x534c4131
+
+#define GIC_CPU_BASE		0x10320000
+
 ENTRY(lowlevel_init)
 
 #ifndef CONFIG_SPL_BUILD
@@ -28,6 +36,7 @@ ENTRY(lowlevel_init)
 	mrc	p15, 0, r0, c0, c0, 5
 	ands	r1, r0, #0x40000000
 	bne	go			@ Go if UP
+	/* read slave CPU number */
 	ands	r0, r0, #0x0f
 	beq	go			@ Go if core0 on primary core tile
 	b	secondary
@@ -37,14 +46,41 @@ go:
 	mov	pc, lr
 
 secondary:
-	/* read slave CPU number into r0 firstly */
-	mrc	p15, 0, r0, c0, c0, 5
-	and	r0, r0, #0x0f
+	/* enable GIC as cores will be waken up by IPI */
+	ldr	r2, =GIC_CPU_BASE
+	mov	r1, #0xf0
+	str	r1, [r2, #4]
+	mov	r1, #1
+	str	r1, [r2, #0]
+
+	ldr	r1, [r2]
+	orr	r1, #1
+	str	r1, [r2]
+
+	/* copy wait code into SRAM */
+	ldr	r0, =slave_cpu_wait
+	ldm	r0, {r1 - r8}		@ slave_cpu_wait has eight insns
+	ldr	r0, =WAIT_CODE_SRAM_BASE
+	stm	r0, {r1 - r8}
+
+	/* pass args to slave_cpu_wait */
+	ldr	r0, =SLAVE1_MAGIC_REG
+	ldr	r1, =SLAVE1_MAGIC_NUM
+
+	/* jump to wait code in SRAM */
+	ldr	pc, =WAIT_CODE_SRAM_BASE
 
-loop:
-	dsb
-	isb
-	wfi				@Zzz...
-	b	loop
 #endif
 ENDPROC(lowlevel_init)
+
+/* This function will be copied into SRAM */
+ENTRY(slave_cpu_wait)
+	wfi
+	ldr	r2, [r0]
+	cmp	r2, r1
+	bne	slave_cpu_wait
+	movw	r0, #:lower16:SLAVE_JUMP_REG
+	movt	r0, #:upper16:SLAVE_JUMP_REG
+	ldr	r1, [r0]
+	mov	pc, r1
+ENDPROC(slave_cpu_wait)

arch/arm/mach-mvebu/cpu.c

@@ -283,10 +283,8 @@ int print_cpuinfo(void)
  * and sets the correct windows sizes and base addresses accordingly.
  *
  * These values are set in the scratch registers by the Marvell
- * DDR3 training code, which is executed by the BootROM before the
- * main payload (U-Boot) is executed. This training code is currently
- * only available in the Marvell U-Boot version. It needs to be
- * ported to mainline U-Boot SPL at some point.
+ * DDR3 training code, which is executed by the SPL before the
+ * main payload (U-Boot) is executed.
  */
 static void update_sdram_window_sizes(void)
 {

arch/arm/mach-omap2/omap3/Kconfig

@@ -3,18 +3,23 @@ if OMAP34XX
 # We only enable the clocks for the GPIO banks that a given board requies.
 config OMAP3_GPIO_2
 	bool
+	default y if CMD_GPIO
 
 config OMAP3_GPIO_3
 	bool
+	default y if CMD_GPIO
 
 config OMAP3_GPIO_4
 	bool
+	default y if CMD_GPIO
 
 config OMAP3_GPIO_5
 	bool
+	default y if CMD_GPIO
 
 config OMAP3_GPIO_6
 	bool
+	default y if CMD_GPIO
 
 choice
 	prompt "OMAP3 board select"

arch/arm/mach-omap2/omap3/clock.c

@@ -750,23 +750,23 @@ void per_clocks_enable(void)
 	setbits_le32(&prcm_base->iclken_per, 0x00000800);
 #endif
 
-#if (CONFIG_IS_ENABLED(OMAP3_GPIO_2) || CONFIG_IS_ENABLED(CMD_GPIO))
+#if defined(CONFIG_OMAP3_GPIO_2)
 	setbits_le32(&prcm_base->fclken_per, 0x00002000);
 	setbits_le32(&prcm_base->iclken_per, 0x00002000);
 #endif
-#if (CONFIG_IS_ENABLED(OMAP3_GPIO_3) || CONFIG_IS_ENABLED(CMD_GPIO))
+#if defined(CONFIG_OMAP3_GPIO_3)
 	setbits_le32(&prcm_base->fclken_per, 0x00004000);
 	setbits_le32(&prcm_base->iclken_per, 0x00004000);
 #endif
-#if (CONFIG_IS_ENABLED(OMAP3_GPIO_4) || CONFIG_IS_ENABLED(CMD_GPIO))
+#if defined(CONFIG_OMAP3_GPIO_4)
 	setbits_le32(&prcm_base->fclken_per, 0x00008000);
 	setbits_le32(&prcm_base->iclken_per, 0x00008000);
 #endif
-#if (CONFIG_IS_ENABLED(OMAP3_GPIO_5) || CONFIG_IS_ENABLED(CMD_GPIO))
+#if defined(CONFIG_OMAP3_GPIO_5)
 	setbits_le32(&prcm_base->fclken_per, 0x00010000);
 	setbits_le32(&prcm_base->iclken_per, 0x00010000);
 #endif
-#if (CONFIG_IS_ENABLED(OMAP3_GPIO_6) || CONFIG_IS_ENABLED(CMD_GPIO))
+#if defined(CONFIG_OMAP3_GPIO_6)
 	setbits_le32(&prcm_base->fclken_per, 0x00020000);
 	setbits_le32(&prcm_base->iclken_per, 0x00020000);
 #endif

arch/arm/mach-rockchip/rk3036/sdram_rk3036.c

@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 /*
- * (C) Copyright 2015 Google, Inc
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
  */
 #include <common.h>
 #include <asm/io.h>

arch/arm/mach-rockchip/sdram_common.c

@@ -48,6 +48,24 @@ size_t rockchip_sdram_size(phys_addr_t reg)
 		      rank, col, bk, cs0_row, bw, row_3_4);
 	}
 
+	/*
+	 * This is workaround for issue we can't get correct size for 4GB ram
+	 * in 32bit system and available before we really need ram space
+	 * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
+	 * The size of 4GB is '0x1 00000000', and this value will be truncated
+	 * to 0 in 32bit system, and system can not get correct ram size.
+	 * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
+	 * and we are now setting SDRAM_MAX_SIZE as max available space for
+	 * ram in 4GB, so we can use this directly to workaround the issue.
+	 * TODO:
+	 *   1. update correct value for SDRAM_MAX_SIZE as what dram
+	 *   controller sees.
+	 *   2. update board_get_usable_ram_top() and dram_init_banksize()
+	 *   to reserve memory for peripheral space after previous update.
+	 */
+	if (size_mb > (SDRAM_MAX_SIZE >> 20))
+		size_mb = (SDRAM_MAX_SIZE >> 20);
+
 	return (size_t)size_mb << 20;
 }
 

arch/arm/mach-socfpga/Kconfig

@@ -35,6 +35,7 @@ config TARGET_SOCFPGA_STRATIX10
 	select ARMV8_MULTIENTRY
 	select ARMV8_SET_SMPEN
 	select ARMV8_SPIN_TABLE
+	select FPGA_STRATIX10
 
 choice
 	prompt "Altera SOCFPGA board select"

arch/arm/mach-socfpga/include/mach/mailbox_s10.h

@@ -107,6 +107,12 @@ enum ALT_SDM_MBOX_RESP_CODE {
 #define RECONFIG_STATUS_PIN_STATUS			2
 #define RECONFIG_STATUS_SOFTFUNC_STATUS			3
 
+/* Macros for specifying number of arguments in mailbox command */
+#define MBOX_NUM_ARGS(n, b)				(((n) & 0xFF) << (b))
+#define MBOX_DIRECT_COUNT(n)				MBOX_NUM_ARGS((n), 0)
+#define MBOX_ARG_DESC_COUNT(n)				MBOX_NUM_ARGS((n), 8)
+#define MBOX_RESP_DESC_COUNT(n)				MBOX_NUM_ARGS((n), 16)
+
 #define MBOX_CFGSTAT_STATE_IDLE				0x00000000
 #define MBOX_CFGSTAT_STATE_CONFIG			0x10000000
 #define MBOX_CFGSTAT_STATE_FAILACK			0x08000000
@@ -140,5 +146,6 @@ int mbox_qspi_open(void);
 #endif
 
 int mbox_reset_cold(void);
-
+int mbox_get_fpga_config_status(u32 cmd);
+int mbox_get_fpga_config_status_psci(u32 cmd);
 #endif /* _MAILBOX_S10_H_ */

arch/arm/mach-socfpga/include/mach/misc.h

@@ -18,9 +18,9 @@ struct bsel {
 extern struct bsel bsel_str[];
 
 #ifdef CONFIG_FPGA
-void socfpga_fpga_add(void);
+void socfpga_fpga_add(void *fpga_desc);
 #else
-static inline void socfpga_fpga_add(void) {}
+inline void socfpga_fpga_add(void *fpga_desc) {}
 #endif
 
 #ifdef CONFIG_TARGET_SOCFPGA_GEN5

arch/arm/mach-socfpga/mailbox_s10.c

@@ -342,6 +342,54 @@ int mbox_reset_cold(void)
 	return 0;
 }
 
+/* Accepted commands: CONFIG_STATUS or RECONFIG_STATUS */
+static __always_inline int mbox_get_fpga_config_status_common(u32 cmd)
+{
+	u32 reconfig_status_resp_len;
+	u32 reconfig_status_resp[RECONFIG_STATUS_RESPONSE_LEN];
+	int ret;
+
+	reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
+	ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd,
+				   MBOX_CMD_DIRECT, 0, NULL, 0,
+				   &reconfig_status_resp_len,
+				   reconfig_status_resp);
+
+	if (ret)
+		return ret;
+
+	/* Check for any error */
+	ret = reconfig_status_resp[RECONFIG_STATUS_STATE];
+	if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
+		return ret;
+
+	/* Make sure nStatus is not 0 */
+	ret = reconfig_status_resp[RECONFIG_STATUS_PIN_STATUS];
+	if (!(ret & RCF_PIN_STATUS_NSTATUS))
+		return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+
+	ret = reconfig_status_resp[RECONFIG_STATUS_SOFTFUNC_STATUS];
+	if (ret & RCF_SOFTFUNC_STATUS_SEU_ERROR)
+		return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+
+	if ((ret & RCF_SOFTFUNC_STATUS_CONF_DONE) &&
+	    (ret & RCF_SOFTFUNC_STATUS_INIT_DONE) &&
+	    !reconfig_status_resp[RECONFIG_STATUS_STATE])
+		return 0;	/* configuration success */
+
+	return MBOX_CFGSTAT_STATE_CONFIG;
+}
+
+int mbox_get_fpga_config_status(u32 cmd)
+{
+	return mbox_get_fpga_config_status_common(cmd);
+}
+
+int __secure mbox_get_fpga_config_status_psci(u32 cmd)
+{
+	return mbox_get_fpga_config_status_common(cmd);
+}
+
 int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
 		  u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
 {

arch/arm/mach-socfpga/misc.c

@@ -88,33 +88,11 @@ int overwrite_console(void)
 #endif
 
 #ifdef CONFIG_FPGA
-/*
- * FPGA programming support for SoC FPGA Cyclone V
- */
-static Altera_desc altera_fpga[] = {
-	{
-		/* Family */
-		Altera_SoCFPGA,
-		/* Interface type */
-		fast_passive_parallel,
-		/* No limitation as additional data will be ignored */
-		-1,
-		/* No device function table */
-		NULL,
-		/* Base interface address specified in driver */
-		NULL,
-		/* No cookie implementation */
-		0
-	},
-};
-
 /* add device descriptor to FPGA device table */
-void socfpga_fpga_add(void)
+void socfpga_fpga_add(void *fpga_desc)
 {
-	int i;
 	fpga_init();
-	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
-		fpga_add(fpga_altera, &altera_fpga[i]);
+	fpga_add(fpga_altera, fpga_desc);
 }
 #endif
 

arch/arm/mach-socfpga/misc_arria10.c

@@ -30,6 +30,27 @@
 
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * FPGA programming support for SoC FPGA Arria 10
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
 #if defined(CONFIG_SPL_BUILD)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -73,7 +94,7 @@ void socfpga_sdram_remap_zero(void)
 int arch_early_init_r(void)
 {
 	/* Add device descriptor to FPGA device table */
-	socfpga_fpga_add();
+	socfpga_fpga_add(&altera_fpga[0]);
 
 	return 0;
 }

arch/arm/mach-socfpga/misc_gen5.c

@@ -34,6 +34,26 @@ static struct nic301_registers *nic301_regs =
 static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
 /*
  * DesignWare Ethernet initialization
  */
@@ -221,7 +241,7 @@ int arch_early_init_r(void)
 	socfpga_sdram_remap_zero();
 
 	/* Add device descriptor to FPGA device table */
-	socfpga_fpga_add();
+	socfpga_fpga_add(&altera_fpga[0]);
 
 #ifdef CONFIG_DESIGNWARE_SPI
 	/* Get Designware SPI controller out of reset */

arch/arm/mach-socfpga/misc_s10.c

@@ -24,6 +24,26 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
+/*
+ * FPGA programming support for SoC FPGA Stratix 10
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Intel_FPGA_Stratix10,
+		/* Interface type */
+		secure_device_manager_mailbox,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
 /*
  * DesignWare Ethernet initialization
  */
@@ -125,6 +145,8 @@ int arch_misc_init(void)
 
 int arch_early_init_r(void)
 {
+	socfpga_fpga_add(&altera_fpga[0]);
+
 	return 0;
 }
 

arch/arm/mach-uniphier/board_late_init.c

@@ -66,20 +66,20 @@ int board_late_init(void)
 	switch (uniphier_boot_device_raw()) {
 	case BOOT_DEVICE_MMC1:
 		printf("eMMC Boot");
-		env_set("bootcmd", "run bootcmd_mmc0; run distro_bootcmd");
+		env_set("bootdev", "emmc");
 		break;
 	case BOOT_DEVICE_NAND:
 		printf("NAND Boot");
-		env_set("bootcmd", "run bootcmd_ubifs0; run distro_bootcmd");
+		env_set("bootdev", "nand");
 		nand_denali_wp_disable();
 		break;
 	case BOOT_DEVICE_NOR:
 		printf("NOR Boot");
-		env_set("bootcmd", "run tftpboot; run distro_bootcmd");
+		env_set("bootdev", "nor");
 		break;
 	case BOOT_DEVICE_USB:
 		printf("USB Boot");
-		env_set("bootcmd", "run bootcmd_usb0; run distro_bootcmd");
+		env_set("bootdev", "usb");
 		break;
 	default:
 		printf("Unknown");

arch/mips/Kconfig

@@ -59,6 +59,11 @@ config ARCH_ATH79
 	select OF_CONTROL
 	imply CMD_DM
 
+config ARCH_MSCC
+	bool "Support MSCC VCore-III"
+	select OF_CONTROL
+	select DM
+
 config ARCH_BMIPS
 	bool "Support BMIPS SoCs"
 	select CLK
@@ -79,7 +84,7 @@ config ARCH_MT7620
 	select DM_SERIAL
 	imply DM_SPI
 	imply DM_SPI_FLASH
-	select ARCH_MISC_INIT if WATCHDOG
+	select ARCH_MISC_INIT
 	select MIPS_TUNE_24KC
 	select OF_CONTROL
 	select ROM_EXCEPTION_VECTORS
@@ -88,6 +93,12 @@ config ARCH_MT7620
 	select SUPPORTS_LITTLE_ENDIAN
 	select SYSRESET
 
+config ARCH_JZ47XX
+	bool "Support Ingenic JZ47xx"
+	select SUPPORT_SPL
+	select OF_CONTROL
+	select DM
+
 config MACH_PIC32
 	bool "Support Microchip PIC32"
 	select DM
@@ -138,7 +149,9 @@ source "board/imgtec/xilfpga/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-mscc/Kconfig"
 source "arch/mips/mach-bmips/Kconfig"
+source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 source "arch/mips/mach-mt7620/Kconfig"
 

arch/mips/Makefile

@@ -13,8 +13,10 @@ libs-y += arch/mips/lib/
 
 machine-$(CONFIG_ARCH_ATH79) += ath79
 machine-$(CONFIG_ARCH_BMIPS) += bmips
+machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
 machine-$(CONFIG_MACH_PIC32) += pic32
 machine-$(CONFIG_ARCH_MT7620) += mt7620
+machine-$(CONFIG_ARCH_MSCC) += mscc
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 libs-y += $(machdirs)

arch/mips/cpu/cpu.c

@@ -28,16 +28,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 }
 #endif
 
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
-	write_c0_entrylo0(low0);
-	write_c0_pagemask(pagemask);
-	write_c0_entrylo1(low1);
-	write_c0_entryhi(hi);
-	write_c0_index(index);
-	tlb_write_indexed();
-}
-
 int arch_cpu_init(void)
 {
 	mips_cache_probe();

arch/mips/dts/Makefile

@@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 
 targets += $(dtb-y)
 

arch/mips/dts/ar933x.dtsi

@@ -3,7 +3,6 @@
  * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  */
 
-#include <dt-bindings/interrupt-controller/irq.h>
 #include "skeleton.dtsi"
 
 / {
@@ -68,7 +67,6 @@
 			uart0: uart@18020000 {
 				compatible = "qca,ar9330-uart";
 				reg = <0x18020000 0x20>;
-				interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
 
 				status = "disabled";
 			};
@@ -103,7 +101,6 @@
 		spi0: spi@1f000000 {
 			compatible = "qca,ar7100-spi";
 			reg = <0x1f000000 0x10>;
-			interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
 
 			status = "disabled";
 

arch/mips/dts/brcm,bcm6318.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/bcm6318-clock.h>
+#include <dt-bindings/dma/bcm6318-dma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/power-domain/bcm6318-power-domain.h>
 #include <dt-bindings/reset/bcm6318-reset.h>
@@ -54,6 +55,12 @@
 			reg = <0x10000004 0x4>;
 			#clock-cells = <1>;
 		};
+
+		ubus_clk: ubus-clk {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0x10000008 0x4>;
+			#clock-cells = <1>;
+		};
 	};
 
 	ubus {
@@ -182,5 +189,36 @@
 
 			status = "disabled";
 		};
+
+		enet: ethernet@10080000 {
+			compatible = "brcm,bcm6368-enet";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x10080000 0x8000>;
+			clocks = <&periph_clk BCM6318_CLK_ROBOSW250>,
+				 <&periph_clk BCM6318_CLK_ROBOSW025>,
+				 <&ubus_clk BCM6318_UCLK_ROBOSW>;
+			resets = <&periph_rst BCM6318_RST_ENETSW>,
+				 <&periph_rst BCM6318_RST_EPHY>;
+			dmas = <&iudma BCM6318_DMA_ENETSW_RX>,
+			       <&iudma BCM6318_DMA_ENETSW_TX>;
+			dma-names = "rx",
+				    "tx";
+			brcm,num-ports = <5>;
+
+			status = "disabled";
+		};
+
+		iudma: dma-controller@10088000 {
+			compatible = "brcm,bcm6368-iudma";
+			reg = <0x10088000 0x80>,
+			      <0x10088200 0x80>,
+			      <0x10088400 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+			#dma-cells = <1>;
+			dma-channels = <8>;
+		};
 	};
 };

arch/mips/dts/brcm,bcm63268.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/bcm63268-clock.h>
+#include <dt-bindings/dma/bcm63268-dma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/power-domain/bcm63268-power-domain.h>
 #include <dt-bindings/reset/bcm63268-reset.h>
@@ -217,5 +218,42 @@
 			reg = <0x10003000 0x894>;
 			u-boot,dm-pre-reloc;
 		};
+
+		iudma: dma-controller@1000d800 {
+			compatible = "brcm,bcm6368-iudma";
+			reg = <0x1000d800 0x80>,
+			      <0x1000da00 0x80>,
+			      <0x1000dc00 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+			#dma-cells = <1>;
+			dma-channels = <8>;
+		};
+
+		enet: ethernet@10700000 {
+			compatible = "brcm,bcm6368-enet";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x10700000 0x10000>;
+			clocks = <&periph_clk BCM63268_CLK_GMAC>,
+				 <&periph_clk BCM63268_CLK_ROBOSW>,
+				 <&periph_clk BCM63268_CLK_ROBOSW250>,
+				 <&timer_clk BCM63268_TCLK_EPHY1>,
+				 <&timer_clk BCM63268_TCLK_EPHY2>,
+				 <&timer_clk BCM63268_TCLK_EPHY3>,
+				 <&timer_clk BCM63268_TCLK_GPHY>;
+			resets = <&periph_rst BCM63268_RST_ENETSW>,
+				 <&periph_rst BCM63268_RST_EPHY>,
+				 <&periph_rst BCM63268_RST_GPHY>;
+			dmas = <&iudma BCM63268_DMA_ENETSW_RX>,
+			       <&iudma BCM63268_DMA_ENETSW_TX>;
+			dma-names = "rx",
+				    "tx";
+			brcm,rgmii-override;
+			brcm,rgmii-timing;
+
+			status = "disabled";
+		};
 	};
 };

arch/mips/dts/brcm,bcm6328.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/bcm6328-clock.h>
+#include <dt-bindings/dma/bcm6328-dma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/power-domain/bcm6328-power-domain.h>
 #include <dt-bindings/reset/bcm6328-reset.h>
@@ -187,5 +188,34 @@
 			reg = <0x10003000 0x864>;
 			u-boot,dm-pre-reloc;
 		};
+
+		iudma: dma-controller@1000d800 {
+			compatible = "brcm,bcm6368-iudma";
+			reg = <0x1000d800 0x80>,
+			      <0x1000da00 0x80>,
+			      <0x1000dc00 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+			#dma-cells = <1>;
+			dma-channels = <8>;
+		};
+
+		enet: ethernet@10e00000 {
+			compatible = "brcm,bcm6368-enet";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x10e00000 0x10000>;
+			clocks = <&periph_clk BCM6328_CLK_ROBOSW>;
+			resets = <&periph_rst BCM6328_RST_ENETSW>,
+				 <&periph_rst BCM6328_RST_EPHY>;
+			dmas = <&iudma BCM6328_DMA_ENETSW_RX>,
+			       <&iudma BCM6328_DMA_ENETSW_TX>;
+			dma-names = "rx",
+				    "tx";
+			brcm,num-ports = <5>;
+
+			status = "disabled";
+		};
 	};
 };

arch/mips/dts/brcm,bcm6338.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/bcm6338-clock.h>
+#include <dt-bindings/dma/bcm6338-dma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/reset/bcm6338-reset.h>
 #include "skeleton.dtsi"
@@ -130,5 +131,33 @@
 			reg = <0xfffe3100 0x38>;
 			u-boot,dm-pre-reloc;
 		};
+
+		iudma: dma-controller@fffe2400 {
+			compatible = "brcm,bcm6348-iudma";
+			reg = <0xfffe2400 0x1c>,
+			      <0xfffe2500 0x60>,
+			      <0xfffe2600 0x60>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+			#dma-cells = <1>;
+			dma-channels = <6>;
+			resets = <&periph_rst BCM6338_RST_DMAMEM>;
+		};
+
+		enet: ethernet@fffe2800 {
+			compatible = "brcm,bcm6348-enet";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfffe2800 0x2dc>;
+			clocks = <&periph_clk BCM6338_CLK_ENET>;
+			resets = <&periph_rst BCM6338_RST_ENET>;
+			dmas = <&iudma BCM6338_DMA_ENET_RX>,
+			       <&iudma BCM6338_DMA_ENET_TX>;
+			dma-names = "rx",
+				    "tx";
+
+			status = "disabled";
+		};
 	};
 };

arch/mips/dts/brcm,bcm6348.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/bcm6348-clock.h>
+#include <dt-bindings/dma/bcm6348-dma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/reset/bcm6348-reset.h>
 #include "skeleton.dtsi"
@@ -159,5 +160,46 @@
 			reg = <0xfffe2300 0x38>;
 			u-boot,dm-pre-reloc;
 		};
+
+		enet0: ethernet@fffe6000 {
+			compatible = "brcm,bcm6348-enet";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfffe6000 0x2dc>;
+			dmas = <&iudma BCM6348_DMA_ENET0_RX>,
+			       <&iudma BCM6348_DMA_ENET0_TX>;
+			dma-names = "rx",
+				    "tx";
+
+			status = "disabled";
+		};
+
+		enet1: ethernet@fffe6800 {
+			compatible = "brcm,bcm6348-enet";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfffe6800 0x2dc>;
+			dmas = <&iudma BCM6348_DMA_ENET1_RX>,
+			       <&iudma BCM6348_DMA_ENET1_TX>;
+			dma-names = "rx",
+				    "tx";
+
+			status = "disabled";
+		};
+
+		iudma: dma-controller@fffe7000 {
+			compatible = "brcm,bcm6348-iudma";
+			reg = <0xfffe7000 0x1c>,
+			      <0xfffe7100 0x40>,
+			      <0xfffe7200 0x40>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			clocks = <&periph_clk BCM6348_CLK_ENET>;
+			resets = <&periph_rst BCM6348_RST_ENET>,
+				 <&periph_rst BCM6348_RST_DMAMEM>;
+		};
 	};
 };

arch/mips/dts/brcm,bcm6358.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/bcm6358-clock.h>
+#include <dt-bindings/dma/bcm6358-dma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/reset/bcm6358-reset.h>
 #include "skeleton.dtsi"
@@ -190,5 +191,50 @@
 
 			status = "disabled";
 		};
+
+		enet0: ethernet@fffe4000 {
+			compatible = "brcm,bcm6348-enet";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfffe4000 0x2dc>;
+			clocks = <&periph_clk BCM6358_CLK_ENET0>;
+			dmas = <&iudma BCM6358_DMA_ENET0_RX>,
+			       <&iudma BCM6358_DMA_ENET0_TX>;
+			dma-names = "rx",
+				    "tx";
+
+			status = "disabled";
+		};
+
+		enet1: ethernet@fffe4800 {
+			compatible = "brcm,bcm6348-enet";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfffe4800 0x2dc>;
+			clocks = <&periph_clk BCM6358_CLK_ENET1>;
+			dmas = <&iudma BCM6358_DMA_ENET1_RX>,
+			       <&iudma BCM6358_DMA_ENET1_TX>;
+			dma-names = "rx",
+				    "tx";
+
+			status = "disabled";
+		};
+
+		iudma: dma-controller@fffe5000 {
+			compatible = "brcm,bcm6348-iudma";
+			reg = <0xfffe5000 0x24>,
+			      <0xfffe5100 0x80>,
+			      <0xfffe5200 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+			#dma-cells = <1>;
+			dma-channels = <8>;
+			clocks = <&periph_clk BCM6358_CLK_EMUSB>,
+				 <&periph_clk BCM6358_CLK_USBSU>,
+				 <&periph_clk BCM6358_CLK_EPHY>;
+			resets = <&periph_rst BCM6358_RST_ENET>,
+				 <&periph_rst BCM6358_RST_EPHY>;
+		};
 	};
 };

arch/mips/dts/brcm,bcm6362.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/bcm6362-clock.h>
+#include <dt-bindings/dma/bcm6362-dma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/power-domain/bcm6362-power-domain.h>
 #include <dt-bindings/reset/bcm6362-reset.h>
@@ -211,5 +212,36 @@
 			reg = <0x10003000 0x864>;
 			u-boot,dm-pre-reloc;
 		};
+
+		iudma: dma-controller@1000d800 {
+			compatible = "brcm,bcm6368-iudma";
+			reg = <0x1000d800 0x80>,
+			      <0x1000da00 0x80>,
+			      <0x1000dc00 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+			#dma-cells = <1>;
+			dma-channels = <8>;
+		};
+
+		enet: ethernet@10e00000 {
+			compatible = "brcm,bcm6368-enet";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x10e00000 0x10000>;
+			clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,
+				 <&periph_clk BCM6362_CLK_SWPKT_SAR>,
+				 <&periph_clk BCM6362_CLK_ROBOSW>;
+			resets = <&periph_rst BCM6362_RST_ENETSW>,
+				 <&periph_rst BCM6362_RST_EPHY>;
+			dmas = <&iudma BCM6362_DMA_ENETSW_RX>,
+			       <&iudma BCM6362_DMA_ENETSW_TX>;
+			dma-names = "rx",
+				    "tx";
+			brcm,num-ports = <6>;
+
+			status = "disabled";
+		};
 	};
 };

arch/mips/dts/brcm,bcm6368.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/bcm6368-clock.h>
+#include <dt-bindings/dma/bcm6368-dma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/reset/bcm6368-reset.h>
 #include "skeleton.dtsi"
@@ -192,5 +193,36 @@
 
 			status = "disabled";
 		};
+
+		iudma: dma-controller@10006800 {
+			compatible = "brcm,bcm6368-iudma";
+			reg = <0x10006800 0x80>,
+			      <0x10006a00 0x80>,
+			      <0x10006c00 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+			#dma-cells = <1>;
+			dma-channels = <8>;
+		};
+
+		enet: ethernet@10f00000 {
+			compatible = "brcm,bcm6368-enet";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x10f00000 0x10000>;
+			clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>,
+				 <&periph_clk BCM6368_CLK_SWPKT_SAR>,
+				 <&periph_clk BCM6368_CLK_ROBOSW>;
+			resets = <&periph_rst BCM6368_RST_SWITCH>,
+				 <&periph_rst BCM6368_RST_EPHY>;
+			dmas = <&iudma BCM6368_DMA_ENETSW_RX>,
+			       <&iudma BCM6368_DMA_ENETSW_TX>;
+			dma-names = "rx",
+				    "tx";
+			brcm,num-ports = <6>;
+
+			status = "disabled";
+		};
 	};
 };

arch/mips/dts/ci20.dts

@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+#include "jz4780.dtsi"
+
+/ {
+	compatible = "img,ci20", "ingenic,jz4780";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	chosen {
+		stdout-path = "serial4:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x10000000
+		       0x30000000 0x30000000>;
+	};
+};
+
+&ext {
+	clock-frequency = <48000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&nemc {
+	status = "okay";
+
+	nandc: nand-controller@1 {
+		compatible = "ingenic,jz4780-nand";
+		reg = <1 0 0x1000000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ingenic,bch-controller = <&bch>;
+
+		ingenic,nemc-tAS = <10>;
+		ingenic,nemc-tAH = <5>;
+		ingenic,nemc-tBP = <10>;
+		ingenic,nemc-tAW = <15>;
+		ingenic,nemc-tSTRV = <100>;
+
+		nand@1 {
+			reg = <1>;
+
+			nand-ecc-step-size = <1024>;
+			nand-ecc-strength = <24>;
+			nand-ecc-mode = "hw";
+			nand-on-flash-bbt;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <2>;
+				#size-cells = <2>;
+
+				partition@0 {
+					label = "u-boot-spl";
+					reg = <0x0 0x0 0x0 0x800000>;
+				};
+
+				partition@0x800000 {
+					label = "u-boot";
+					reg = <0x0 0x800000 0x0 0x200000>;
+				};
+
+				partition@0xa00000 {
+					label = "u-boot-env";
+					reg = <0x0 0xa00000 0x0 0x200000>;
+				};
+
+				partition@0xc00000 {
+					label = "boot";
+					reg = <0x0 0xc00000 0x0 0x4000000>;
+				};
+
+				partition@0x8c00000 {
+					label = "system";
+					reg = <0x0 0x4c00000 0x1 0xfb400000>;
+				};
+			};
+		};
+	};
+};
+
+&bch {
+	status = "okay";
+};
+
+&mmc0 {
+	bus-width = <4>;
+	max-frequency = <50000000>;
+	status = "okay";
+};
+
+&mmc1 {
+	bus-width = <4>;
+	max-frequency = <50000000>;
+	status = "okay";
+};

arch/mips/dts/comtrend,ar-5315u.dts

@@ -24,6 +24,38 @@
 	status = "okay";
 };
 
+&enet {
+	status = "okay";
+
+	port@0 {
+		compatible = "brcm,enetsw-port";
+		reg = <0>;
+		label = "fe4";
+		brcm,phy-id = <1>;
+	};
+
+	port@1 {
+		compatible = "brcm,enetsw-port";
+		reg = <1>;
+		label = "fe3";
+		brcm,phy-id = <2>;
+	};
+
+	port@2 {
+		compatible = "brcm,enetsw-port";
+		reg = <2>;
+		label = "fe2";
+		brcm,phy-id = <3>;
+	};
+
+	port@3 {
+		compatible = "brcm,enetsw-port";
+		reg = <3>;
+		label = "fe1";
+		brcm,phy-id = <4>;
+	};
+};
+
 &leds {
 	status = "okay";
 

arch/mips/dts/comtrend,ar-5387un.dts

@@ -24,6 +24,38 @@
 	status = "okay";
 };
 
+&enet {
+	status = "okay";
+
+	port@0 {
+		compatible = "brcm,enetsw-port";
+		reg = <0>;
+		label = "fe1";
+		brcm,phy-id = <1>;
+	};
+
+	port@1 {
+		compatible = "brcm,enetsw-port";
+		reg = <1>;
+		label = "fe2";
+		brcm,phy-id = <2>;
+	};
+
+	port@2 {
+		compatible = "brcm,enetsw-port";
+		reg = <2>;
+		label = "fe3";
+		brcm,phy-id = <3>;
+	};
+
+	port@3 {
+		compatible = "brcm,enetsw-port";
+		reg = <3>;
+		label = "fe4";
+		brcm,phy-id = <4>;
+	};
+};
+
 &leds {
 	status = "okay";
 

arch/mips/dts/comtrend,ct-5361.dts

@@ -34,6 +34,18 @@
 	};
 };
 
+&enet1 {
+	status = "okay";
+	phy = <&enet1phy>;
+	phy-mode = "mii";
+
+	enet1phy: fixed-link {
+		reg = <1>;
+		speed = <100>;
+		full-duplex;
+	};
+};
+
 &gpio0 {
 	status = "okay";
 };

arch/mips/dts/comtrend,vr-3032u.dts

@@ -24,6 +24,38 @@
 	status = "okay";
 };
 
+&enet {
+	status = "okay";
+
+	port@0 {
+		compatible = "brcm,enetsw-port";
+		reg = <0>;
+		label = "fe2";
+		brcm,phy-id = <1>;
+	};
+
+	port@1 {
+		compatible = "brcm,enetsw-port";
+		reg = <1>;
+		label = "fe3";
+		brcm,phy-id = <2>;
+	};
+
+	port@2 {
+		compatible = "brcm,enetsw-port";
+		reg = <2>;
+		label = "fe4";
+		brcm,phy-id = <3>;
+	};
+
+	port@3 {
+		compatible = "brcm,enetsw-port";
+		reg = <3>;
+		label = "fe1";
+		brcm,phy-id = <4>;
+	};
+};
+
 &leds {
 	status = "okay";
 	brcm,serial-leds;

arch/mips/dts/comtrend,wap-5813n.dts

@@ -54,6 +54,20 @@
 	status = "okay";
 };
 
+&enet {
+	status = "okay";
+
+	port@4 {
+		compatible = "brcm,enetsw-port";
+		reg = <4>;
+		label = "rgmii";
+		brcm,phy-id = <0xff>;
+		speed = <1000>;
+		full-duplex;
+		bypass-link;
+	};
+};
+
 &gpio0 {
 	status = "okay";
 };

arch/mips/dts/huawei,hg556a.dts

@@ -93,6 +93,18 @@
 	status = "okay";
 };
 
+&enet1 {
+	status = "okay";
+	phy = <&enet1phy>;
+	phy-mode = "mii";
+
+	enet1phy: fixed-link {
+		reg = <1>;
+		speed = <100>;
+		full-duplex;
+	};
+};
+
 &gpio0 {
 	status = "okay";
 };

arch/mips/dts/jz4780.dtsi

@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dt-bindings/clock/jz4780-cgu.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "ingenic,jz4780";
+
+	cpuintc: interrupt-controller {
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "mti,cpu-interrupt-controller";
+	};
+
+	intc: interrupt-controller@10001000 {
+		compatible = "ingenic,jz4780-intc";
+		reg = <0x10001000 0x50>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		interrupt-parent = <&cpuintc>;
+		interrupts = <2>;
+	};
+
+	ext: ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	rtc: rtc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+	};
+
+	cgu: jz4780-cgu@10000000 {
+		compatible = "ingenic,jz4780-cgu";
+		reg = <0x10000000 0x100>;
+
+		clocks = <&ext>, <&rtc>;
+		clock-names = "ext", "rtc";
+
+		#clock-cells = <1>;
+	};
+
+	mmc0: mmc@13450000 {
+		compatible = "ingenic,jz4780-mmc";
+		reg = <0x13450000 0x1000>;
+
+		status = "disabled";
+
+		clocks = <&cgu JZ4780_CLK_MSC0>;
+		clock-names = "mmc";
+	};
+
+	mmc1: mmc@13460000 {
+		compatible = "ingenic,jz4780-mmc";
+		reg = <0x13460000 0x1000>;
+
+		clocks = <&cgu JZ4780_CLK_MSC1>;
+		clock-names = "mmc";
+
+		status = "disabled";
+	};
+
+	uart0: serial@10030000 {
+		compatible = "ingenic,jz4780-uart";
+		reg = <0x10030000 0x100>;
+		reg-shift = <2>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <51>;
+
+		clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+
+	uart1: serial@10031000 {
+		compatible = "ingenic,jz4780-uart";
+		reg = <0x10031000 0x100>;
+		reg-shift = <2>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <50>;
+
+		clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+
+	uart2: serial@10032000 {
+		compatible = "ingenic,jz4780-uart";
+		reg = <0x10032000 0x100>;
+		reg-shift = <2>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <49>;
+
+		clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+
+	uart3: serial@10033000 {
+		compatible = "ingenic,jz4780-uart";
+		reg = <0x10033000 0x100>;
+		reg-shift = <2>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <48>;
+
+		clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+
+	uart4: serial@10034000 {
+		compatible = "ingenic,jz4780-uart";
+		reg = <0x10034000 0x100>;
+		reg-shift = <2>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <34>;
+
+		clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+
+	nemc: nemc@13410000 {
+		compatible = "ingenic,jz4780-nemc";
+		reg = <0x13410000 0x10000>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <1 0 0x1b000000 0x1000000
+			  2 0 0x1a000000 0x1000000
+			  3 0 0x19000000 0x1000000
+			  4 0 0x18000000 0x1000000
+			  5 0 0x17000000 0x1000000
+			  6 0 0x16000000 0x1000000>;
+
+		clocks = <&cgu JZ4780_CLK_NEMC>;
+
+		status = "disabled";
+	};
+
+	bch: bch@134d0000 {
+		compatible = "ingenic,jz4780-bch";
+		reg = <0x134d0000 0x10000>;
+
+		clocks = <&cgu JZ4780_CLK_BCH>;
+
+		status = "disabled";
+	};
+};