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314 Commits

Author SHA1 Message Date
e84f67ebb4 Fix: move watchdog feed more early 2025-03-05 20:38:10 +08:00
6067b3247b board:stm32mp1 feed gpio watchdog 2024-12-10 21:28:18 +08:00
22a8a3cdb6 config: add string to delay autoboot 2024-12-08 22:17:58 +08:00
d8d89f4de8 board: add peripheral gpio control 2024-04-06 15:07:26 +08:00
0fcbc297bf dts: add PanGuBoard with stm32mp157a soc 2024-04-06 15:07:07 +08:00
eca77a9766 board: setup watchdog wdi and enable gpio 2023-07-06 15:18:33 +08:00
f2edc5c545 dts: add stm32mp135 gateway board 2023-07-06 15:18:15 +08:00
3984366f69 Prepare v2021.10-stm32mp-r2
Update version in Makefile to prepare the label v2021.10-stm32mp-r2
for OpenSTLinux V4.1

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I235b2792161ab02f0eee2af19506eed828a8dc6e
2022-10-17 10:48:26 +02:00
a46e065f82 cmd: pxe: support INITRD and FDT selection with FIT
Since the commit d5ba6188df ("cmd: pxe_utils: Check fdtcontroladdr
in label_boot") the FDT or the FDTDIR label is required in extlinux.conf
and the fallback done by bootm command for device tree present is no more
performed when FIT is used for kernel.

When the labels FDT or FDTDIR are absent or if the device tree file is
absent, the PXE command in U-Boot uses the default U-Boot device tree
selected by fdtcontroladdr = gd->fdt_blob, it is the "Scenario 3".

With this patch the bootm FIP fallback is no more possible with
the extlinux.conf when only "kernel" label is present and is a FIP:

  kernel <path>#<conf>[#<extra-conf[#...]]

As the U-Boot FDT is selected in the third bootm argument the device
tree from FIP is not used as it was done previously.

This patch adds a new field kernel_label to save the full kernel label.
The FDT bootm parameters use the kernel address (to avoid to load a
second time the same FIP) and the config when this full label is reused
for "fdt" or "initrd" label.

This FIP support in extlinux.conf is restored when the "FDT" label
can be found and select the same FIP (identical file and configuration):

  kernel <path>#<conf>[#<extra-conf[#...]]
  fdt <path>#<conf>[#<extra-conf[#...]]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I4662774cdd525de1992f84f0ea97255e2e43d8c2
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/268490
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-10-17 10:48:26 +02:00
20db66cc65 cmd: pxe: reorder kernel treatment in label_boot
Reorder kernel treatment in label_boot at the beginning of the function.

This patch doesn't change the pxe command behavior, it is only a
preliminary step for next patch to build bootm_argv[1] before parsing
initrd and fdt to build the next bootm arguments.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: If04f25e393f3af8cd75af331ca2f432a7a1b88e8
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/268489
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-10-17 10:48:26 +02:00
16b09539dc ARM: dts: stm32mp13: remove the stm32mp135d-dk board
Remove the STM32MP135D-DK Discovery Board support; the board
variant without crypto support is canceled and only the crypto
version of this board STM32MP135F-DK will be available.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I258f2c39e93d6e1a52df1d944c91591e5053fff0
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/266791
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-10-17 10:48:26 +02:00
d8af9dc4ae i2c: stm32f7: fix clearing the control register
Bits should be set to 0, not 1.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I067f23215acfa4d468e86806d959d68654289473
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/265893
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Alain VOLMAT <alain.volmat@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:26 +02:00
acb3eaf035 i2c: stm32: fix usage of rise/fall device tree properties
These two device tree properties were not being applied.

Change-Id: Iab376954a5af8f9a6f9b81f81c45c2c3fe6aa3ab
Fixes: 0c63ec6bbf ("i2c: stm32f7: move driver data of each instance in a privdata")
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Alain Volmat <alain.volmat@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/265849
Tested-by: Alain VOLMAT <alain.volmat@foss.st.com>
Reviewed-by: Alain VOLMAT <alain.volmat@foss.st.com>
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:26 +02:00
648aff43b8 i2c: stm32: do not set the STOP condition on error
Current function stm32_i2c_message_xfer is sending a STOP
whatever the result of the transaction is.  This can cause issues
such as making the bus busy since the controller itself is already
sending automatically a STOP when a NACK is generated.

Thanks to Jorge Ramirez-Ortiz for diagnosing and proposing a first
fix for this. [1]

[1] https://lore.kernel.org/u-boot/20220815145211.31342-2-jorge@foundries.io/

Change-Id: I157b95a3b8e411e8591d76e148930cf00f682fc4
Reported-by: Jorge Ramirez-Ortiz, Foundries <jorge@foundries.io>
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/264955
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:26 +02:00
8fffa9e5cc i2c: stm32: remove unused stop parameter in start & reload handling
Functions stm32_i2c_message_start and stm32_i2c_handle_reload
both get a stop boolean indicating if the transfer should end with
a STOP or not.  However no specific handling is needed in those
functions hence remove the parameter.

Change-Id: I681def7666baa987116ee7391cfb7158ed768cb6
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/264954
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Amelie DELAUNAY <amelie.delaunay@foss.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:26 +02:00
5487d29128 i2c: stm32: fix comment and remove unused AUTOEND bit
Comment within stm32_i2c_message_start is misleading, indicating
that AUTOEND bit is setted while it is actually cleared.
Moreover, the bit is actually never setted so there is no need
to clear it hence get rid of this bit clear and the bit macro
as well.

Change-Id: Icbf734d98f127a9e2a52d0f3d138cc9e291cd579
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/264953
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Amelie DELAUNAY <amelie.delaunay@foss.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:26 +02:00
e2e80a4f56 sandbox: remove video test
The sandbox in U-Boot v2021.10 don't support the video test
introduced in commit 8657ad43f3 ("sandbox: video: Add BMP
tests for 32bpp and 8bpp modes"), merged in dm-pull-13jan22
v2022.04-rc1.

Revert the sandbox and test part of previous patch.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ia98e6d864635c901b8dda5f4d359a327082aec81
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/267408
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-10-17 10:48:26 +02:00
664b387431 video: theadorable: Use RGB565 for BMP blitting
At present this uses RGB555 format for blitting to a display. Sandbox uses
565 and that seems to be more normal for BMP as well. Update the code
accordingly and add a test.

Note that this likely breaks the theadorable board so we may need to
discuss supporting both formats.

[Backport of commit 4ea1548210 ("video: theadorable: Use RGB565 for
 BMP blitting")]

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ifae9f08166f4c7c3f8a1aa41f6fc0c898c3be5b5
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/265323
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-10-17 10:48:26 +02:00
7f4912de92 stm32mp: stm32prog: support empty flashlayout
When the STM32CubeProgrammer sent a empty flashlayout.tsv
file, the command stm32prog correctly parse the file
but data->dev_nb = 0 and the stm32prog_devices_init
treatments can be skipped.

Also remove the trace "partition: Done" when GPT partitioning
is not done.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I9928b88f3a453611043b484158b02efe9b0c06bf
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/260198
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-10-17 10:48:26 +02:00
834351a6e7 cmd: pxe_utils: Check fdtcontroladdr in label_boot
If using OF_CONTROL, fdtcontroladdr is set to the fdt used to configure
U-Boot. When using PXE, if no fdt is defined in the menu file, and
there is no fdt at fdt_addr, add fall back on fdtcontroladdr too.

We are developing board support for the Armv8r64 FVP using
config_distro_bootcmd. We are also using OF_BOARD and would like the
PXE boot option to default to the fdt provided by board_fdt_blob_setup.

[Backport of commit d5ba6188df ("cmd: pxe_utils: Check fdtcontroladdr
 in label_boot")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Change-Id: Iad7341a89d9a31a2d58ee831b3808857a763cab5
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/261342
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-10-17 10:48:26 +02:00
89fae04a71 ARM: dts: add wakeup pin for stm32g0 typec controller in stm32mp135f-dk
USB Type-c controller (stm32g0) has an interrupt pin wired to a
STM32MP13 PWR wakeup pin on DK board. It can be used as a wakeup source,
to wakeup the system from standby mode, when changes are identified on the
Type-c connector.
All is configured in OPTEE, adopt it. This will avoid attempt to configure
a secure GPIO

Change-Id: Id2391286462fa394a5dd4d05b0c7666c5ea61ce1
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/260818
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:26 +02:00
873d895ce3 board: st: stm32mp1: use of correct compatible string to add partitions
Current compatible string used to update SPI NAND and SPI NOR devices
can lead to a wrong partitions update (for example, SPI NAND partitions
added to SPI NOR node in the device tree). To avoid this wrong behavior,
use jedec,spi-nor compatible string for SPI NOR devices and spi-nand
compatible string for SPI NAND devices.

Change-Id: Iae28ab1a0be932b26f9cf8b17d870508efa88b79
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/260967
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Christophe KERELLO <christophe.kerello@st.com>
2022-10-17 10:48:26 +02:00
44ae5a1cef clk: stm32-core: introduce multi gate management
Majority of IPs have a peripheral clock and a Kernel clocks.
These clocks are gated with same bit register. Then we have to manage
a counter at gate level.

This patch introduce a new clock "clk_stm32_gate", it will replace
"clk_stm32_setclr_gate".

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I6bb988cb0f7eab5cc8374bc3fe65b37cbcd9a5e0
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/256638
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:26 +02:00
5006f25ce4 clk: stm32-core: fix divider in stm32 composite clock
Divider ops is missing in composite clock.

Fixes: 58291d94e3 ("clk: stm32-core: introduce stm32-clk-core")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I9f939e363d7d9e4024f5ae189ab6fcb6e8e0bde5
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/256637
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:26 +02:00
55dc4842a6 clk: stm32-core: rename parameter name in clk_stm32_register_composite()
Rename "pcfg" parameter into "mcfg" ('m' for mux).

Fixes: 58291d94e3 ("clk: stm32-core: introduce stm32-clk-core")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ia5effceb54b5b8f776d106f01cd89e6c323d19e4
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/256636
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:26 +02:00
fd7254c628 stm32mp: stm32prog: correctly handle OTP when SMC is not supported
As the SMC is only supported in SP-MIN for STM32MP15x, the associated
partition should be absent when the TA NVMEM is not available in OPT-TEE
in STM32MP13x.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I7f5dcb6d058c600d6f67432864c5051d29ba8d7b
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/255734
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-10-17 10:48:26 +02:00
20e17e74b6 pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name
Populate uc_priv->name[] with pinmux node's name in order to indicate
the pinmuxing's label in case GPIO is configured in alternate.

For example, for STM32 SoC's based platform, "gpio status" command
output :

  before
    Bank GPIOZ:
      GPIOZ0: unused : 0 [ ]
      GPIOZ1: unused : 0 [ ]
      GPIOZ2: unused : 0 [ ]
      GPIOZ3: unused : 0 [ ]
      GPIOZ4: func
      GPIOZ5: func
      GPIOZ6: unused : 0 [ ]
      GPIOZ7: unused : 0 [ ]
      GPIOZ8: unknown
      GPIOZ9: unknown
      GPIOZ10: unknown
      GPIOZ11: unknown
      GPIOZ12: unknown
      GPIOZ13: unknown
      GPIOZ14: unknown
      GPIOZ15: unknown

  After
    Bank GPIOZ:
      GPIOZ0: unused : 0 [ ]
      GPIOZ1: unused : 0 [ ]
      GPIOZ2: unused : 0 [ ]
      GPIOZ3: unused : 0 [ ]
      GPIOZ4: func i2c4-0
      GPIOZ5: func i2c4-0
      GPIOZ6: unused : 0 [ ]
      GPIOZ7: unused : 0 [ ]
      GPIOZ8: unknown
      GPIOZ9: unknown
      GPIOZ10: unknown
      GPIOZ11: unknown
      GPIOZ12: unknown
      GPIOZ13: unknown
      GPIOZ14: unknown
      GPIOZ15: unknown

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ib7563ed0d20cece9516e5c5523103990852b4d0f
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/255980
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Fabien DESSENNE <fabien.dessenne@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:25 +02:00
f5798061ec gpio: Fix pin's status display for pin with GPIOF_UNUSED function
Even pin's with GPIOF_UNUSED function can have label.
The criteria to add or not a space character is linked to label not to
the used/unused status.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ic9e92420a339490be694d3eee4daaa348344b5d0
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/255979
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Fabien DESSENNE <fabien.dessenne@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:25 +02:00
60371e490a gpio: Allow to print pin's label even for pin with GPIOF_FUNC function
Currently, if pin's function is GPIOF_FUNC, only "func" if displayed
without any other information. It would be interesting, if information is
available, to indicate which pin's label is used.

For example, for STM32 SoC's based platform, "gpio status" command
output :

   before
    Bank GPIOZ:
      GPIOZ0: unused : 0 [ ]
      GPIOZ1: unused : 0 [ ]
      GPIOZ2: unused : 0 [ ]
      GPIOZ3: unused : 0 [ ]
      GPIOZ4: func
      GPIOZ5: func
      GPIOZ6: unused : 0 [ ]
      GPIOZ7: unused : 0 [ ]
      GPIOZ8: unknown
      GPIOZ9: unknown
      GPIOZ10: unknown
      GPIOZ11: unknown
      GPIOZ12: unknown
      GPIOZ13: unknown
      GPIOZ14: unknown
      GPIOZ15: unknown

   After
    Bank GPIOZ:
      GPIOZ0: unused : 0 [ ]
      GPIOZ1: unused : 0 [ ]
      GPIOZ2: unused : 0 [ ]
      GPIOZ3: unused : 0 [ ]
      GPIOZ4: func i2c4-0
      GPIOZ5: func i2c4-0
      GPIOZ6: unused : 0 [ ]
      GPIOZ7: unused : 0 [ ]
      GPIOZ8: unknown
      GPIOZ9: unknown
      GPIOZ10: unknown
      GPIOZ11: unknown
      GPIOZ12: unknown
      GPIOZ13: unknown
      GPIOZ14: unknown
      GPIOZ15: unknown

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ia935ed2f340b6df1c439389a53e2c05489561983
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/255978
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Fabien DESSENNE <fabien.dessenne@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:25 +02:00
b941fcea8a gpio: stm32_gpio: flag secured pin as protected
When a GPIO is secure-protected, it can't be accessed from U-Boot.
In that case, set its 'function' to GPIOF_PROTECTED.
This makes the "gpio status" command returning the "protected" status.

Example with GPIOA6 pin secure-protected

> gpio status -a
Bank GPIOA:
GPIOA0: unused: 0 [ ]
GPIOA1: func
...
GPIOA6: protected
...

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: If3297d920741a6a1b915503650de1cfb69c726f9
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/252040
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:25 +02:00
a33d8e2f83 dm: gpio: Add GPIOF_PROTECTED flag
Declare the GPIOF_PROTECTED flag, to identify a GPIO which can't be used
because it has a protected access.
This can be used to flag a GPIO that can be accessed only from the Secure
world.

Add a test and support in the gpio sandbox.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: Ic990ca6a02f9cc6f9e84bd94732ea62cfbafb301
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/252039
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:25 +02:00
975f629eb4 stpmic1: remove the debug unit request by debugger
Depending on backup register value, U-Boot SPL maintains the debug unit
powered-on for debugging purpose; only BUCK1 is required for powering
the debug unit, so revert the setting for all the other power lanes,
except BUCK3 that has to be always on.

To be functional this patch requires a modification in the debugger
,openocd for example, to update the STM32MP15 backup register when it is
required to debug SPL after reset. After deeper analysis this behavior
will be never supported in tools so the associated code, will be never
used and the associated code can be removed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I50f3ce7fb4a4bb3169f40cf4bab0ec75936e5c03
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/254231
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-10-17 10:48:25 +02:00
973461aa8d mmc: stm32_sdmmc2: protect against unsupported modes
The UHS modes for SD, HS200 and HS400 modes for eMMC are not supported
by the stm32_sdmmc2 driver.
Make it clear by removing the corresponding caps after parsing the DT.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I53c4e33906fa94a5cf3fafca2ce9e61e0ab65d0a
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/257471
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:25 +02:00
e2cf7fd677 mmc: stm32_sdmmc2: add dual data rate support
To support dual data rate with STM32 sdmmc2 driver, the dedicated bit
(DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass
(no divider) is not allowed in this case.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7f7e6786c6ed43715d1147e5def412c9422910f4
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/257470
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:25 +02:00
8a46bc3005 mmc: stm32_sdmmc2: make reset property optional
Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc node in DT. This reset is already optional in Linux.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I39b69e8dc7b43b8e265e77388fb53f7c1fa2a007
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/250055
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:25 +02:00
ab40d97399 usb: host: ehci-generic: Make usage of clock/reset bulk() API
Make usage of clock and reset bulk API in order to simplify the code

[Backport of ba96176ab7 ("usb: host: ehci-generic: Make usage of
 clock/reset bulk() API")]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ia5711b14a17cf1d042bdab9d3f28437d5c53272c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/246747
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:25 +02:00
7a250cc251 clk: scmi: fix invalid clock name references
Fixes clock name references in scmi_clk driver. SCMI clock names are
retrieved from the SCMI firmware by invoking SCMI commands using the
stack for SCMI response message hence clocks names located in the
stack must be duplicated before being registered in the clock framework.

Change-Id: I4795469625d44c319ed9ba5673a8cdf560b7de6b
Fixes: 7c33f78983 ("clk: scmi: register scmi clocks with CCF")
Reported-by: scan-admin@coverity.com
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/249343
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-10-17 10:48:25 +02:00
0af9d9c82c video: stm32: remove test on CONFIG_DM_REGULATOR
The tests on CONFIG_DM_REGULATOR, added to avoid compilation issues, can now
be removed, they are no more needed since the commit 16cc5ad0b4 ("power:
regulator: add dummy helper").

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I18e4ad5947e3b321573efe2085dd4c593cabbabe
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/250167
2022-10-17 10:48:25 +02:00
de7d8d6764 board: stm32mp1: remove test on CONFIG_DM_REGULATOR
The tests on CONFIG_DM_REGULATOR, added to avoid compilation issues, can now
be removed, they are no more needed since the commit 16cc5ad0b4 ("power:
regulator: add dummy helper").

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: If8c377a910cabf108ec14bc570c381126e1531e9
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/250098
2022-10-17 10:48:25 +02:00
7687a1afaf ARM: dts: stm32mp: allignment with v5.15-stm32mp-r2
Device tree alignment with Linux kernel v5.15-stm32mp-r2

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I497736e0f7416d68d56ac559e4a821ea888ede85
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/254720
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/258865
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/266860
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/271024
2022-10-17 10:48:09 +02:00
9fdc0f208b ARM: dts: stm32: Synchronize DHCOM DTs with Linux 5.15.12
Synchronize DH DHCOM DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The eeprom0 alias and
PHY reset GPIO are now reinstated in SoM u-boot dtsi.

[Backport of commit 332facce6f ("ARM: dts: stm32: Synchronize DHCOM DTs
 with Linux 5.15.12")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I170332856869eae93703b5f10c8038046b2b47a8
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/258864
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-07-06 15:54:27 +02:00
09f8182c94 ARM: dts: stm32: Synchronize DHCOR DTs with Linux 5.15.12
Synchronize DH DHCOR DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The eeprom0 alias is
now reinstated in SoM u-boot dtsi, the PHY reset GPIO is reinstated in AV96
u-boot dtsi.

[Backport of commit 6b8bd70904 ("ARM: dts: stm32: Synchronize DHCOR DTs
 with Linux 5.15.12")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ib1e56f72b77435691c65093eff0c20609e5f719f
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/258863
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-07-06 15:53:03 +02:00
5e7c6582cc stm32mp: fix support of STM32MP13x Rev.Y
Fix support of STM32MP13x Rev.Y for the Silicon revision REV_ID = 0x1003.

Fixes: a28201176d ("stm32mp: add support of STM32MP13x Rev.Y")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I9e5e52a3c12cbfbdb5334d0f74d253bb09f66518
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/256996
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-07-06 15:53:03 +02:00
ef9715e762 Prepare v2021.10-stm32mp-r1
Update version in Makefile to prepare the label v2021.10-stm32mp-r1
for OpenSTLinux V4.0

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie3c8903d82a697e53c8dc711c024998d0833fa00
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/241645
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:02 +02:00
47611d9252 dt-bindings: rtc: stm32: add default value to output property
This patch adds a default config (RTC_NO_OUT)

It could be use to disable an output functionality.


Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifd477c20c62e1b55b8d08bcfef95a9304047dbc7
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/252437
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:02 +02:00
a28201176d stm32mp: add support of STM32MP13x Rev.Y
Add support of STM32MP13x Rev.Y for the Silicon revision REV_ID = 0x1002.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I09a7e6bd976c0720cef2de21e3acd62ff8a7b846
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/251439
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-05-25 16:01:02 +02:00
5dc7c456a1 spi: stm32_qspi: Remove SR_BUSY bit check before sending command
Waiting for SR_BUSY bit when receiving a new command is not needed.
SR_BUSY bit is already managed in the previous command treatment.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: If15940fb19e9d2f9b9d9e67b117b1460c284e927
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/250833
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:02 +02:00
65a6c3beaa spi: stm32_qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd()
Currently, SR_TCF flag is checked in case there is data, this criteria
is not correct.

SR_TCF flags is set when programmed number of bytes have been transferred
to the memory device ("bytes" comprised command and data send to the
SPI device).
So even if there is no data, we must check SR_TCF flag.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Id4e8f33e11a972d985f29b7a4363b1622f4128c2
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/250832
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:02 +02:00
9cf2cc3c51 board: st: stm32mp1: panel detection for stm32mp15 ev1 board
Add panel detection for EV1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yannick FERTRE <yannick.fertre@foss.st.com>
Change-Id: I39ffca9b83525b7abd80fa1709bc5f75cd08a7e6
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237577
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-05-25 16:01:02 +02:00
3c48194ffa configs: stm32mp1: add panel Rocktech HX8394
Add a new panel based on chipset Himax HX8394.

Signed-off-by: Yannick FERTRE <yannick.fertre@foss.st.com>
Change-Id: I88fbd6bd8649de23373fb340cbce7cbed212b9a7
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/238896
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:02 +02:00
ccb3a05989 video: add support of panel Rocktech HX8394
Support for Rocktech HX8394 720p dsi 2dl video mode panel.
This panel driver is based on the Linux Kernel driver from
drivers/gpu/drm/panel/panel-rocktech-hx8394.c.

Change-Id: I116af7c59e8e77217337b25d27beb45d08028500
Signed-off-by: Yannick FERTRE <yannick.fertre@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236113
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:02 +02:00
4a22117825 board: st: common: fix the error messages in stboard command
Add missing \n at the end of the error trace

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id540e65885e62d3a51328b7f4205a137cd249537
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244757
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:02 +02:00
ab357b2439 board: stm32mp1: add detection of GC2145 camera sensor
Detect the GC2145 camera sensor connected to the stm32mp135f-dk
board in order to enable instead the OV5640 if the GC2145 isn't
detected via I2C.  For that purpose, necessary dependencies
(regulator / gpio) are enabled and GC2145 ID registers are checked
to determine if the GC2145 is attached or not.  If it isn't found,
then the device-tree is updated (camera nodes status & stmipid02
CSI bridge remote node phandle) to enable the OV5640 sensor
and the remote-endpoint property setting in the ov5640 to
make it point to the stmipi endpoint node.
This remote-endpoint property is not setted within the DT by
default in order to avoid a non birectionnal graph connection
warning during DT build.

Change-Id: If56f670e530158d21926148eadb9ec004797ac20
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/242645
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/245022
2022-05-25 16:01:02 +02:00
83a972e588 board: st: stm32mp1: touchscreen detection for stm32mp15 dk2 board
Add I2C touchscreen detection for DK2 board only.

Signed-off-by: Yannick FERTRE <yannick.fertre@foss.st.com>
Change-Id: I8356297906cdf741476c31d01cea0e3510ec8cfe
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/241991
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:02 +02:00
3ed350c2a1 configs: stm32mp1: set the console variable for extlinux.conf
Set the environment variable "console", used in extlinux.conf file when it
is generated by YOCTO in OpenSTLinux distribution:

UBOOT_EXTLINUX_CONSOLE ??= "console=${console},${baudrate}"

With these 2 variables, U-Boot give dynamically the used console and
baudrate in the Linux kernel bootargs.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I23ed8b36e294031f1f614d2304ea17085f075612
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/241463
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:02 +02:00
3076f946b7 video: stm32: stm32_ltdc: fix data enable polarity
Wrong DISPLAY_FLAGS used to set the data enable polarity.

Signed-off-by: Yannick FERTRE <yannick.fertre@foss.st.com>
Change-Id: I767c723f7deb853ac09ee1f7e39c057bd37e1a46
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/240655
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Philippe CORNU <philippe.cornu@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:02 +02:00
c92351ea00 stm32mp: stm32prog: handle flashlayout without STM32 image header
Accept flashlayout without header in alternate 0, to simplify
the support of stm32prog command with dfu-util.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I8052625ddd2a94516d82b9b7472a34ba52fbc2fa
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/240548
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-05-25 16:01:02 +02:00
f4037f75b6 stm32mp: stm32prog: handle U-Boot script in flashlayout alternate
Update the stm32prog command to allow the reception of U-Boot script in
the FlashLayout alternate during the first USB enumeration.

This patch is aligned with the last TF-A behavior: the Flashlayout
is now loaded by U-Boot; it is no more present at STM32_DDR_BASE when
the stm32prog is launched after a serial boot, on UART or on USB.

The received script must be a U-Boot legacy image, no more need to add
a stm32image header.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I08598ebf2b427ac25eaf56e05799ac8d2dc42947
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/240544
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-05-25 16:01:02 +02:00
4e4356e9c5 stm32mp: stm32prog: handle interruption during the first enumeration
When a interruption is received during the first USB enumeration
used to received the FlashLayout, with handle ctrl-c, the second
enumeration is not needed and the result for stm32prog_usb_loop
is false (reset is not needed).

This patch avoid the need of a second ctrl to interrupt the command
stm32prog.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie76b6efe731c9d721b794d9ad6b394b38492a4df
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/240543
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-05-25 16:01:02 +02:00
ef28f3f0a6 ARM: stm32mp: skip ft_system_setup when the soc node is absent
The function ft_system_setup should don't return an error when the
/soc node is absent in the provided device tree but just skip the
updates.

This patch solves an issue when the U-Boot pytests is executed on board.

Signed-off-by: Sebastien Pasdeloup <sebastien.pasdeloup-ext@st.com>
Change-Id: Ic7fcf7558ba1c08e031b54acd7b9f3544addb1d8
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/234562
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:02 +02:00
699d8964ba dts: stm32mp1: use a specific GPT partition for environment
As the fip partition is duplicated in eMCC/SDCard for the firmware
update support in TF-A: "fip-a" and "fip-b",  the U-Boot use a dedicated
partition named "u-boot-env" to avoid issue when the FIP is updated by
the update agent.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I1fa341f578929363fb0f0194600009f6c6c9e8a8
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/238557
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:02 +02:00
d64ea4cb86 stm32mp: update MTD partitions for TF-A firmware update support
Add in MTD partitions the new partitions needed by TF-A firmware update:
- metadata to save the TF-A information: 2 copy
- fip-a / fip-b: two FIP slots, used for system A/B (seamless) update
- the previous "fsbl" partition with 2 copy of TFA is replaced
  by 2 partitions (only one copy in each MTD partition) to simplify
  the update: no need to managed this copy on update, need to update the
  two partition (skip bad block for NAND)

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie51edf3fe13dabb66fde99eaf781fdd7b1990e3c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/238556
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Nicolas TOROMANOFF <nicolas.toromanoff@st.com>
Tested-by: Nicolas TOROMANOFF <nicolas.toromanoff@st.com>
2022-05-25 16:01:02 +02:00
2f74425e8b stm32mp: stm32prog: add support of UUID for FIP partition
Add support of UUID for FIP parttion, required by Firmware update
support in TF-A:
- UUID TYPE for FIP partition: 19d5df83-11b0-457b-be2c-7559c13142a5
- "fip-a" partition UUID: 4fd84c93-54ef-463f-a7ef-ae25ff887087
- "fip-b" partition UUID: 09c54952-d5bf-45af-acee-335303766fb3

This check is done with a new partition type "FIP" associated
at the FIP UUID.

The A/B partition UUID is detected by the partition name:
"fip-a", "fip-b".

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I94e74b521fd55dcc68ab8d000cb93ef48fc12f14
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/238555
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:02 +02:00
e117c2ad32 pinctrl: pinctrl_stm32: Update pinmux_mode definition
pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c
So reuse the same gpio_func_t enum value

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I284167e444a8b59066bff10ec2f92ac2b26a2d70
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/239115
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
(cherry picked from commit 312fccd8213bcdefe9d353e4b306748e7b49cd0c)
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/239880
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:02 +02:00
010f0e12ba env: mmc : align erase address and size on erase_grp_size
On eMMC, the erase_grp_size > 1 so the address and size for the erase
block command can be unaligned on erase group size and some strange
trace occurs and the result is not guarantee by MMC devices.

The SD-Card behavior don't change as erase_grp_size = 1 for SD-Card.

For example, on eMMC present on STM32MP15C-EV1, before the patch:

  STM32MP> env erase

  Erasing Environment on MMC...

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x27ff

  16 blocks erased: OK

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x23ff

  16 blocks erased: OK
  OK

After this patch:
  STM32MP> env erase
  Erasing Environment on MMC...
  1024 blocks erased at 0x2000: OK
  1024 blocks erased at 0x2000: OK
  OK

Here the 2 copies of U-Boot environment are in the same devices Erase
group: it is erased twice.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I26fa615c6898db0d17024664b17b20412638bfd7
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/238836
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-05-25 16:01:02 +02:00
cd3d4a9d1f mmc: fix error message for unaligned erase request
Fix the end address in the message for unaligned erase request in
mmc_berase() when start + blkcnt is aligned to erase_grp_size.

for example:
  - start = 0x2000 - 26
  - count = 26
  - erase_grp_size = 0x400

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x27ff

But no issue when the end address is not aligned, for example
  - start = 0x2000 - 2 * 26
  - count = 26
  - erase_grp_size = 0x400

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x23ff

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I5f92544259c3d1dad2df30c9d7762ec7860f07cf
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/238835
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-05-25 16:01:01 +02:00
8b9a2476b7 stm32mp1: Add support for baudrates higher than 115200 for st-link
On STMicroelectronics boards, the UART can reliably go up to
- 2000000 bauds when connected to the on-board ST-LINK-V2 for STM32MP15
- 12000000 bauds when connected to the external ST-LINKV3 for STM32MP13
Unfortunately U-Boot will fall back to 115200 unless higher rates are
declared via CONFIG_SYS_BAUDRATE_TABLE.

This patch add the support of higher baudrates on STMicroelectronics
boards with ST-LINK.

Cc: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: Ie4aa91b7f1b08b59b02853e7f28c2b48445ba0f6
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/241313
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/239497
2022-05-25 16:01:01 +02:00
de79e6949f pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins
GPIOF_UNKNOWN becomes a valid pin muxing information to indicate
that a pin is not mapped.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I659b45eae59374d82103ee15857c35b4f2bcdf75
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/239066
Reviewed-by: Fabien DESSENNE <fabien.dessenne@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:01 +02:00
fba8d6b38c gpio: stm32_gpio: Rework GPIO hole management
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
Example:
  If GPIO bank have 16 GPIO pins [0-15].
  In particular SoC's package case, some GPIO bank can have less GPIO pins:
    - [0-10] => 11 pins;
    - [2-7] => 6 pins.

Commit dbf928dd26 ("gpio: stm32f7: Add gpio bank holes management")
proposed a first implementation by not counting GPIO "inside" hole. GPIO
are not displaying correctly using gpio or pinmux command when GPIO holes
are located at the beginning of GPIO bank.

To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges
struct to indicate if a GPIO is mapped or not. GPIO uclass offers several
GPIO functions ("input", "output", "unused", "unknown" and "func"), use
"unknown" GPIO function to indicate that a GPIO is not mapped.

stm32_offset_to_index() is no more needed and removed.

This must be reflected using the "gpio" command to indicate to user
that a particular GPIO is not mapped (marked as "unknown") as shown below:

Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins
mapped):
GPIOI0          : unknown
GPIOI1          : unknown
GPIOI2          : analog
GPIOI3          : analog
GPIOI4          : alt function 0 push-pull pull-down
GPIOI5          : alt function 0 push-pull pull-down
GPIOI6          : alt function 0 push-pull pull-down
GPIOI7          : analog
GPIOI8          : unknown
GPIOI9          : unknown
GPIOI10         : unknown
GPIOI11         : unknown
GPIOI12         : unknown
GPIOI13         : unknown
GPIOI14         : unknown
GPIOI15         : unknown

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I55c39a2707fa8dae108d90c4a72590f1a4520ca9
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/239065
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Fabien DESSENNE <fabien.dessenne@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
0e3c42448a iio: adc: stm32-adc: add support of generic channels binding
Add support of generic IIO channel binding:
./devicetree/bindings/iio/adc/adc.yaml
Keep support of st,adc-channels for backward compatibility.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Change-Id: Ifb433baf31af3661271d98b7c155958aa5f7afdb
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/238839
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Fabrice GASNIER <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
423ebb16d2 stm32: adc: split channel init into several routines
Split stm32_adc_chan_of_init channel initialization function into
several routines to increase readability and prepare channel
generic binding handling.

Change-Id: Ifdbb454600c4e2d48e6dde70ff5354e4aaff9c17
Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/238838
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Fabrice GASNIER <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
6ee50e27f0 ARM: stm32mp: add usb_pgood_delay for ST boards
With some USB device, usb_pgood_delay must be used to ensure
a correct detection.
Issue encountered with this USB flash disk :
ID 058f:6387 Alcor Micro Corp. Flash Drive

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I5ea27bfe1d09a754c91a12a15e003a6b5f21e9d1
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237940
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
8dfc59ce95 usb: husb: increase HUB_DEBOUNCE_TIMEOUT
Increase HUB_DEBOUNCE_TIMEOUT to 2000 because some usb device
needs around 1.5 or more to make the hub port status to be
connected steadily after being powered off and powered on.

These value is aligned with Linux driver and avoids to configure
"usb_pgood_delay" as a workaround for connection timeout on
some USB device; normally the env variable "usb_pgood_delay" is used
to delay the  first query after power ON and thus the device answer,
not to increase the connection timeout delay.

Commit-notes:
Hi,

I think this patch solves a general issue because a 1s timeout for
USB connection is too short on problematic USB keys.
The issue was introduced by the commit c998da0d67 ("usb: Change
power-on / scanning timeout handling")

Patch in usb_hub allow to avoid patch in each board/driver.

for example, commit 0417169054 ("imx: ventana: add usb_pgood_delay
2sec default") => use pgood_delay = 2s !?

("ARM: stm32: Increase USB power-good delay on DHSOM")
https://patchwork.ozlabs.org/project/uboot/patch/20211113022444.231801-1-marex@denx.de/

or commit 2bf352f0c1 ("usb: dwc2: Add delay to fix the USB
detection problem on SoCFPGA") => patch in USB DWC2 driver to add
a timeout in driver

the commit 319418c01c ("usb: hub: allow pgood_delay to be
specified via env") => introduce env variable for warm-up times

Patrick

END

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I5eabf3f9fdbbaf763cd44e9c018cb5b74a0c65ac
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236836
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:01 +02:00
1d337aa8dc usb: hub: introduce HUB_DEBOUNCE_TIMEOUT
Introduce define for connection timeout, named HUB_DEBOUNCE_TIMEOUT
as in linux kernel drivers/usb/core/hub.c

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ic02e6fb44225d1cfe15506c7c85f70a0893fb880
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236835
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Tested-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-05-25 16:01:01 +02:00
d8c511144a ARM: dts: stm32mp15: remove addon for st,stm32-sdmmc2 compatible
Remove the U-Boot specific add-on for SDMMCv2 IP used in the STM32MP15
as this compatible "st,stm32-sdmmc2" is present in kernel device
tree v5.15-stm32mp-r1.

This patch reduces the device tree difference with kernel device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I1c465a221cb3da2c7b54cbf8467a0f97ba6f397e
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/195269
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:01 +02:00
c189609d33 mmc: stm32_sdmmc2: introduce of_to_plat ops
Add the uclass ops of_to_plat to parse the device tree properties
to respect the expected sequence by the driver model.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie868aca1e057629eb212dcc3c8f463c00d01ccb7
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/235573
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
2022-05-25 16:01:01 +02:00
9bbe98426b mmc: stm32_sdmmc2: remove privdata
All the elements of privdata are static and build from device tree,
they are moved in platdata to prepare the support of ops
of_to_plat.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id78f6e3f0b5deebedc6e5f54dd99b855a163fd2c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/235572
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
2022-05-25 16:01:01 +02:00
3e6ec74c43 mmc: stm32_sdmmc2: cosmetic: rename stm32_sdmmc_bind
Rename stm32_sdmmc_bind to stm32_sdmmc2_bind as all oter function
in SDMMCv2 driver

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Idba00f2816d362a1675c8c74eac80400cb2e4de7
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/235571
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
2022-05-25 16:01:01 +02:00
6ee1aad5b6 net: dwc_eth_qos: restore support of not cache-aligned descriptor
Solve a issue with AXI_WIDTH_32 on a the 64 bytes cache line platform;
in this case the requested descriptor padding length should be 12 but the
associated parameter EQOS_DMA_CH0_CONTROL.DSL is limited at 3bits = 7.

As the DMA descriptor can't be correctly aligned with the cache line,
the maintenance of each descriptor can't be guarantee by a simple cache
line operation: flush or invalid.

To avoid all the maintenance issues, these descripto need to be allocated
in a NOT CACHEABLE memory, allocated by noncached_alloc() when
CONFIG_SYS_NONCACHED_MEMORY is enable.

This patch don't change the current behavior when the descriptor
can be cache-aligned with the filed "Descriptor Skip Length" of
the DMA channel control register, when eqos->desc_pad = true.

Change-Id: Iada23492743e3af977e07c1f1b8c2f32550436f7
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236650
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Christophe ROULLIER <christophe.roullier@st.com>
2022-05-25 16:01:01 +02:00
7c0508bcc8 power: regulator: stm32-verfbuf: add support from mp13
Add support for stm32mp13 verfbuf with minimal voltage value
of 1650mV.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I8fcea9fea3a379dad16816f38b75389f82c55bda
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/235947
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
b25fc67425 clk: manage CLK_SET_RATE_PARENT flags on clk_set_rate()
Add possibility to propagate rate change up one level

Change-Id: I866d25a89cd351ea75cf7e4605397ebe20a60661
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/235018
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
5186289e66 clk: update clk_clean_rate_cache to use private clk struct
In clk_clean_rate_cache, clk->rate should update the private clock
struct when CCF is activated to save the cached rate value.

When clk_get_parent_rate is called, the cached information
is read from pclk->rate, with pclk = clk_get_parent(clk)
which use dev_get_clk_ptr() to access to private data.

As the cached is read from private clk data, the update should
be done also on it.

Series-cc: Tero Kristo <t-kristo@ti.com>
Series-cc: Tero Kristo <kristo@kernel.org>
Fixes: 6b7fd3128f ("clk: fix set_rate to clean up cached rates for the hierarchy")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa06360115ffa3f3307372e6cdd98ec16759d6ba
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236864
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:01 +02:00
97402fc9a3 adc: manage pcsel on end of conversion
Some I/Os are connected to ADC input channels, when the corresponding bit
in PCSEL register are set on STM32H7 and STM32MP15.
PCSEL shouldn't be let enabled when VDDA supply is disabled, to avoid
current leakage. This may occur if the kernel disable the VDDA supply
of the ADC, while the PCSEL remains set, after leaving U-boot.
Clear PCSEL bits after each end of conversion, when relevant, to
prevent this case.

Change-Id: I147f128cd67392220a8924cf407bcdae0e1eb555
Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/233126
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
92f9ee4c50 adc: stm32mp15: probe all adc for calibration on stm32mp15x-dkx
Probe all ADCs on STM32MP15x-DKx boards to support ADC self
calibration.

Depends-on: If9af754d4b91146aafcd9129ba0d618693d75650

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Change-Id: I3f262c54cb05bb0b166ba81d3efbdc02e7ac2e4f
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/231399
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
5f2761e423 adc: stm32: add smart calibration support
Add smart calibration support for STM32MP1.
- STM32MP15x: both linear & offset calibration are supported
- STM32MP13x: Only offset calibration is supported

Linear calibration:
Linear calibration is SoC dependent and does not change over
time. As it is time consuming, do it only once.
Restore calibration data from environment variable to save time.
If no calibration data are found in u-boot environment variables
run a new calibration.

Offset calibration:
This calibration is fast and may vary over time.
Run offset single-ended and differential calibration on each boot.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Change-Id: If8739d96e019d42341901c5da6a83925cc78333a
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/231628
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
b1575c9704 ARM: dts: stm32: Remove u-boot,force-b-session-valid property for stm32mp157a-dk1-u-boot.dtsi
The property u-boot,force-b-session-valid becomes useless, remove it.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I1cc0013b51bd9a0ace665ebc1825edc654c7ca7a
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232356
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
796429d01e ARM: dts: stm32: Remove u-boot,force-b-session-valid property for stm32mp135f-dk-u-boot.dtsi
The property u-boot,force-b-session-valid becomes useless, remove it.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ic21ce52024e4fe98f90332ebbd635fd080d81d6e
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232355
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
f1ee2f5b66 usb: gadget: dwc2_udc_otg: Make usage of typec_get_driver_from_usb()
Before relying on u-boot,force-b-session-valid property presence to set
force_b_session_valid field, use typec_get_driver_from_usb() which check
if a Type-C connector is present. In this case invoke typec_get_data_role()
which indicates if current data role is DEVICE or HOST.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I3dc5da0c332c5b557a855564985317345d25458f
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232354
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
d7cf053394 usb: typec: Add typec_get_driver_from_usb() API
The typec_get_driver_from_usb() allows to retrieve a Type-C device from
an USB device.
typec_get_driver_from_usb() checks in USB device node for port and endpoint
sub-node, if exist, retrieve the connector node, probe the associated
Type-C device and return it.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: If564cdf463f3915bec26f17a4717c9ab9d42f692
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232353
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
7eeb19f152 configs: stm32mp13: Enable STM32G0 relative flags
Enable CONFIG_TYPEC, CONFIG_UCSI and CONFIG_UCSI_STM32G0 flags to be able to
detect USB cable attach/detach on stm32mp13 DK boards.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I4e63ba94d1066fbe9511e0397e1b410c2822eca2
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232351
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
158eb2b33c usb: typec: ucsi: Add STM32G0 UCSI driver support
STM32GO provides an integrated USB Type-C interface.
It handles UCSI protocol over I2C and supports read and write
UCSI uclass ops.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I309b85859f94f284bb62bc3ce7174cf9f49a5e31
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232350
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
32a22b57c8 usb: typec: ucsi: Add UCSI uclass support
Implement a minimal UCSI uclass which allows to send request
to UCSI compatible chip. It provides the read() and write() ops.
It offers 3 services:
  - ucsi_is_attached() which informs if Type-C connector is attached
    or not.
  - ucsi_get_data_role() which informs if the Type-C controller acts
    as Device or host.
  - usci_get_nb_connector() which indicates how many connector are
    managed.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I319cf1f49b0980d33e2b47f1b14a513eb4466da5
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232349
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
892438f57c board: stm32mp1: Update USB Type-C STUSB160x management
Make usage of Type-C uclass API to check if a Type-C device is present.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ia9ee03c3e0630c7dc6ac7c9a060f84cf4c32dc9c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232348
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
43dbc2d182 configs: stm32mp15: Enable Type-C STUSB160x relative flags
Enable CONFIG_TYPEC and CONFIG_TYPEC_STUSB160X flags.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ibdd52ac043fa5dfd4a19aa1e5fc7600852da2ba8
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232346
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
bc1af77ffc usb: typec: Add support for STUSB160x Type-C controller family
Add STMicroelectronics STUSB160x Type-C controller driver
It supports both Type-C uclass ops (.is_attached and .get_data_role).

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I72077e70ff050e9bc463cb096408fd78bd66f318
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232345
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
68a4a0b436 board: stm32mp1; Remove TYPEC_STUB160X config from Kconfig
Remove TYPEC_STUSB160X config from board/st/common/Kconfig
before introduction of real stusb160x Type-C driver.
This will avoid the following Kconfig warning:
drivers/usb/typec/Kconfig:15:warning: ignoring type redefinition of 'TYPEC_STUSB160X' from 'tristate' to 'bool'

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ia464dcc7e1b5e3c6e8c8ccd8c3ac84d858ae8588
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232344
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
3e36da694a usb: Add USB_TYPEC uclass
The USB TypeC uclass exposes 3 services:
  - is_attached() which indicates if connector is attached or not
  - get_data_role() which indicates the current controller role
    (Host or Device)
  - get_nb_connector() which indicates the connector number managed

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I296bc3cb8b180e0adb02171ede5db887fb1f5d6b
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232343
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
b6322ffdec board: stm32mp1: update OP-TEE nodes in Linux device tree for SP-MIN
Update the Linux kernel device tree to support boot with TF-A SP-MIN and
without OP-TEE on STM32MP15 platform.

By default the Linux kernel have OP-TEE nodes, including the SCMI agent,
to support the boot with OP-TEE, the default supported boot mode.

For the TF-A SP-MIN support, the OP-TEE nodes need to be dynamically
updated, including the reserved memory and the SCMI agent nodes.

This patch allows to support this legacy mode, boot with TF-A SP-MIN as
secure monitor and without OP-TEE, with the latest device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I6ba5eb92850869ab08d5c09bf119089fb283a4a8
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/228518
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236082
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:01 +02:00
183f041e38 configs: stm32mp15: increase CONFIG_SYS_MALLOC_F_LEN
Increase the pre-reloc malloc size, requested to support for SCMI
OP-TEE agent.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Iee88574ba7012475245fc9b5d5331aa58c1a074b
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/226786
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@foss.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Tested-by: Lionel DEBIEVE <lionel.debieve@foss.st.com>
2022-05-25 16:01:01 +02:00
04f2753854 arm: stm32mp: adapt the command stm32key for STM32MP13x
Change the mask of OTP0 used to close the device on STM32MP
- STM32MP15x: bit 6 of OPT0
- STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device

And support the 2 keys for STM32MP13x
- PKHTH : Hash of the 8 ECC Public Keys Hashes Table
          (ECDSA is the authentication algorithm)
- EDMK : Encryption/Decryption Master Key

Change-Id: I1431827b62d294343069ff0aa7e59abaacb8bdd5
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/230109
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/242599
2022-05-25 16:01:01 +02:00
0a1a77dd91 arm: stm32mp: support several key in command stm32key
Update the command stm32key to support several keys selected by
key name and managed by the new sub-command:

stm32key list
stm32key select [<key>]
stm32key read -a

This patch don't change the STM32MP15 behavior, only PKH is supported,
but it is a preliminary patch for STM32MP13 support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ic9d9cb1cf9d05b9e305f158b26076cf908d7c0b8
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/230108
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:01 +02:00
51932b5bf2 arm: stm32mp: introduced read_close_status function in stm32key command
Split the read_hash_otp function and introduce the helper function
read_close_status to read the close status in OTP separately of the PKH.

This patch is a preliminary step for STM32MP13 support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ibbcbcbc3b4bf97f9761600ec5ce36f8b40c3c161
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/230107
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:01 +02:00
ebf26f9821 board: st: stm32mp1: Consider USB cable connected when boot device is USB
Always consider USB cable is connected when USB boot device is detected.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I28b7114116aadfaefcaeccd02fb4199f09633b9c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/225864
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
bd92d42f2b net: dwc_eth_qos: Support the phy-supply regulator binding
Configure the phy regulator if defined by the "phy-supply" DT phandle.

Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Change-Id: I9febda03d173d1671b5961bccadefbb21b7a7a09
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/225075
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
530e7bfb2b stm32mp: simplify the package parsing code
Simplify the package parsing code for STM32MP15X as package can be
affected with get_cpu_package() result.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I4d177d06061a5973e5cd25d2b61e74fdb2861a2a
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/225097
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:01 +02:00
1333335513 stm32mp13: add support of touchscreen goodix gt911 used on DK board
Software workaround for I2C issue on DK board, U-Boot need to
configure the IRQ line for touchscreen before LCD reset
to fix the used I2C address for touchsreen goodix gt911.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Iaabbe4524f4371794a4d274add0aca2694274a65
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/220081
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-05-25 16:01:01 +02:00
62a78a33f7 pinctrl: pinctrl_stm32: prevent the use of the secure protected pins
The hardware denies any access from the U-Boot non-secure world to the
secure-protected pins. Hence, prevent any driver to configure such a pin.
Identify the secure pins with "NO ACCESS" through the 'pinmux status -a'
command.
Use a driver data structure to identify which hardware versions support
this feature.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: I7b56a959537b4f201b4ce49a5ee84432684ea0e3
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/215821
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
6f102bacfe gpio: stm32-gpio: prevent the use of the secure protected pins
The hardware denies any access from the U-Boot non-secure world to the
secure-protected pins. Hence, prevent any driver to request such a pin.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: Iabe8941fbad73d7125f0558e13b95dd67806094e
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/215820
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
91c57a9774 configs: stm32mp13: activate support of display
Enable support of display controller.

Change-Id: I96daaa701ff169038f8868243741d75a3611a940
Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/198270
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Philippe CORNU <philippe.cornu@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
0b43c21748 arm: dts: stm32: update panel node of DK for U-Boot
Update panel node of Disco board due to specific part of driver simple-panel.

Change-Id: I3ac5e0e66c98426c37868fd2298f58088560cf8c
Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/198382
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Philippe CORNU <philippe.cornu@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
b8f032657d video: stm32: stm32_ltdc: support several hardware versions
Register mapping & pixel formats depend on version of ltdc
display controller.

Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Change-Id: I4ecd3c23c3ac4fdc2734290b3d432fbc484c568a
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/193320
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Philippe CORNU <philippe.cornu@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
e1c73a5934 doc: st: stm32mp1: add STM32MP13x support
Add in U-Boot documentation the quick instruction for
setup the STMicroelectronics STM32MP13x boards.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ia54d641fbe9119451443b79f0db8cb80453ab3f3
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/195765
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-05-25 16:01:01 +02:00
f82deb4aba configs: stm32mp13: activate support of Microchip MPC23017
Add support for Microchip MCP23017 which I/O expander used on ST board.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Idfee0ec7162d044e03fae4f9434ad8d7f6ed35f2
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/192100
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Tested-by: Patrice CHOTARD <patrice.chotard@st.com>
2022-05-25 16:01:01 +02:00
13492aa128 pinctrl: Add MPC23017 support
Add support for Microchip MCP23017 which is a 16-Bit I/O
expander with I2c interface.

Datasheet is available here:
https://www.microchip.com/wwwproducts/en/MCP23017

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I18d0add0d30970a3f08859f2cf38261f699056fd
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/190046
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrice CHOTARD <patrice.chotard@st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
b088f253a7 configs: add stm32mp13 defconfig
Add a initial config for STM32M13x SOC family, using the stm32mp135f-dk
device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: If62e8c985dd17697c445e229f7375013b22a8c0d
2022-05-25 16:01:01 +02:00
71a2139af6 arm: dts: stm32mp: add stm32mp13 device tree for U-Boot
Compile the device tree of STM32MP13x boards and add the needed
U-Boot add-on.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I8f3aebcc95b60f45691cc7aa918ef5efece05887
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/168740
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/212229
2022-05-25 16:01:01 +02:00
41d06ae22b rng: stm32mp1_rng: add conditional reset feature
New IP adds a conditional reset that impact the clock
error management. It is now linked to a new compatible.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Idaf694f05913720a34cb73c69b896b6ce34a3d9a
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/204120
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:01 +02:00
999f41b7e4 ram: stm32mp1: add support of STM32MP13x
Add support for new compatible "st,stm32mp13-ddr" to manage the
DDR sub system (Controller and PHY) in STM32MP13x SOC:
- only one AXI port
- support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2)

The STM32MP15x SOC have 2 AXI ports and 32 bits support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3c50158401b3eb022059c7394e48980af23b9582
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/195458
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-25 16:01:01 +02:00
cee720d080 board: st: cmd stboard: Add support of STM32MP13x boards
Add board identifiers for STMicroelectronics STM23MP13x boards:
- DISCO board: MB1635

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I5ced2665787083835d5ce398a3bd10163cca62c9
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/186035
2022-05-25 16:01:01 +02:00
64c805e2fa board: stm32pm1: add support of ethernet2 for stm32mp13 platform
Manage 2 ethernet instances, select which instance to configure with mask
If mask is not present in DT, it is stm32mp15 platform

Change-Id: Ia60db8aca57744d04d57d66b2e962955c672fd08
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/179669
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2022-05-25 16:01:00 +02:00
b149a188c3 net: dwc_eth_qos: add rate parameter in board_interface_eth_init
Add rate parameter in the weak function board_interface_eth_init
to provided the PHY frequency when it is used  without
crystal.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I7ef1bc9355fc36f10210751c0785795ee99503bb
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/208103
Tested-by: Christophe ROULLIER <christophe.roullier@st.com>
Reviewed-by: Christophe ROULLIER <christophe.roullier@st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-05-25 16:01:00 +02:00
b943cf2c0b board: stm32pm1: add stm32mp13 board support
Add stm32mp15x prefix to all STM32MP15x board specific function,
this patch is a preliminary step for STM32MP13x support.

This patch also add the RCC probe to avoid circular access with
usbphyc probe as clk provider.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I35fae2ba5868b79e66ccef249270e1cf1bf3f04b
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/195403
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/197872
2022-05-25 16:01:00 +02:00
4959d833e1 adc: add support of adc to stm32mp13
Add support of STM32 ADCs to STM32MP13x. This patch introduces
stm32_adc_regspec structure, as this is already done in kernel
driver, to manage smartly the differences in register set
between STMP32MP15 and STM32MP13 ADCs.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Change-Id: Ifd33c23eea8b18853416f8d1f8c5bf1a88f31b00
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/212227
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Fabrice GASNIER <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-25 16:01:00 +02:00
9796e81234 i2c: stm32: add support for the st,stm32mp13 SOC
The stm32mp13 soc differs from the stm32mp15 in terms of
clear register offset for controlling the FMP (Fast Mode Plus).

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I32e861dc46886c23a866443be2bace22d86ae24e
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/199392
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Tested-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>
2022-05-25 16:01:00 +02:00
ee99077acf net: dwc_eth_qos: add support of stm32mp13 platform
Add compatible "st,stm32mp13-dwmac" to manage STM32MP13 boards

Change-Id: Ie35cc73a27da1729e9cf64b04ba4505a02a38865
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/179668
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2022-05-25 16:01:00 +02:00
00b08c7b1a pinctrl: stm32: add support of STM32MP135
Add support for "st,stm32mp135-pinctrl" for STM32MP13x

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ie30eda7a5fb54abc98f89edeee53932bef15a09f
2022-05-25 16:01:00 +02:00
0e61924d5a clk: stm32mp13: introduce STM32MP13 RCC driver
Introduce STM32MP13 RCC driver using Common Clock Framework.

Change-Id: I98b0b23318f39ef6411b8f96c05f5b11b4cf5de7
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/172245
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/221554
2022-05-25 16:01:00 +02:00
58291d94e3 clk: stm32-core: introduce stm32-clk-core
This patch introduces a mechanism to register clocks from one
configuration table with common clock framework.

Change-Id: I2cd6aa9a10aef893aeb3edaf1aceb9c3863d3405
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/172244
Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
2022-05-25 16:01:00 +02:00
1009730a30 stm32mp: bsec: add support of STM32MP13x
Add support for "st,stm32mp13-bsec" for STM32MP13x

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I5265730f7438c864c93089754fad0f2217da3e51
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/223330
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-05-25 16:01:00 +02:00
8b92965b88 stm32mp: fdt: update etpzc for STM32MP13x
Add support of STM32MP13x the ETPZC part of fdt.c

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I3679840747612f44044942f225f344af9a26dcfd
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/169335
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
2022-05-25 16:01:00 +02:00
0b2a568156 stm32mp: fdt: update etpzc for STM32MP15x
Introduce STM32MP15 function and defines to prepare
STM32MP13 introduction.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ie4f29021d76802af1c22e1df1a6a55ae6a5f55d9
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/169333
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/169334
2022-05-25 16:01:00 +02:00
b5bbc02ae5 arm: dts: stm32mp: add support of STM32MP13x
Add kernel device tree for stm32mp13 Soc and
STMicroelectronics boards

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236375
Change-Id: Ibe5031074c3fdf88bc8aac74a772c03e55962de5
2022-05-25 16:01:00 +02:00
600ae9915d arm: stm32mp: add support of STM32MP13x
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I48a2a2211b9cf24a69030c1499ddeb0a507025d2
2022-05-19 09:21:15 +02:00
4743b6c59d arm: stm32mp: add CONFIG_STM32MP15_PWR
Add config CONFIG_STM32MP15_PWR to handle the
access on regulators managed by the PWR driver defined in
pwr_regulator.c

This driver is only used in U-Boot by STM32MP15x family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifb968953516a3d73a38718892a7c58726bf641ae
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/196369
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-05-19 09:21:15 +02:00
d6a54e7dff arm: stm32mp: Add sub config Kconfig.15x
Add sub Kconfig for each SOC in the STM32 CPU family.

It is a preliminary step to introduce a new SOC in the STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I90e6955a55b1eea31e8a17d216eb9bdd76332f5d

# Conflicts:
#	arch/arm/mach-stm32mp/Kconfig
2022-05-19 09:21:15 +02:00
3930ba7caf arm: stm32mp: add choice for STM32MP SOC family
Add mandatory choice for SOC support in ARCH_STM32MP.

This patch is a preliminary step for new SOC introduction
in STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id34b18d3ce5c7d33defb18c3c6e545f22190372d
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/189947
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-19 09:21:15 +02:00
789f950180 stm32mp: correctly handle Silicon revision
Handle correctly the silicon revision = REV_ID[15:0] of Device Version
and the associated device marking, A to Z on STMicroelectronics MPU.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I46d09f298319fd632eaee4cd8888d751b908f0e6
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/225091
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-19 09:21:15 +02:00
5ce98f7445 arm: stm32mp: move code for STM32MP15x
Move code and defines only needed for CONFIG_STM32MP15x in stm32mp15x.c
when low level init without TFABOOT is supported.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ia90133663740dcf00ee2799a01f92f2acee683da
2022-05-19 09:21:15 +02:00
a0874404b3 configs: stm32mp1: move SUPPORT_SPL in STM32MP15x
The SPL is only supported by STM32MP15x not by all the
SOC with STM32MP arch.
Only TFABOOT is supported in next products.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Iea6a315c629bbbb6cbc18889a2207a465acb9bcc
2022-05-19 09:21:15 +02:00
c2c185aa12 dts: stm32mp1: update DDR node
Remove unnecessary nodes for TFABOOT and move the mandatory part
in SOC dtsi. This patch allow to include stm32mp15-ddr.dtsi only if
it is needed, when TFABOOT is not defined

Change-Id: I1dd8baddc1f804ccab03ffa99bb5b33c924ab07a
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2022-05-19 09:21:15 +02:00
d3fac41f5a clk: stm32mp: handle ck_usbo_48m clock provided by USBPHYC
Handle the input clock of RCC USB_PHY_48, provided by USBPHYC
and named "ck_usbo_48m".

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Idf10564d4e488df57f60640bbe1f8a43e200b56f
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/195030
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-05-19 09:21:15 +02:00
38f55b6ae3 phy: stm32-usbphyc: usbphyc is a clock provider of ck_usbo_48m clock
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I0322692ca3c12c0bcacc7da24804b7dcf3402e58
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/195029
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/246554
2022-05-19 09:21:15 +02:00
c818787718 phy: stm32-usbphyc: add counter of PLL consumer
Add the counter of the PLL user n_pll_cons managed by the 2 functions
stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable.

This counter allow to remove the function stm32_usbphyc_is_init
and it is a preliminary step for ck_usbo_48m introduction.

Change-Id: I15bd7c3c8c983d6a6cec3d2ee371d75fe72fcd41
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/195028
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-19 09:21:15 +02:00
e0408bf8e7 stm32mp: stm32prog: add support of STM32IMAGE version 2
Add support of new header for the STM32IMAGE version V2
in command stm32prog command for sTM32MP13x family.

Change-Id: I23385079e2fd8a2cab3b25e5883b94a25898736d
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/198796
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
2022-05-19 09:21:15 +02:00
48e9be99dc regulator: scmi: scmi regulator supports supply regulator
Add property regulator-supply for SCMI regulator nodes to define
a supply needed by the related SCMI regulator. On regulator enable, the
supply is enabled but on regulator disable, the supply is left as is
since U-Boot regulator class does not make any reference counting on
enable/disable requests.

Add sandbox test for scmi voltage regulators supply regulator
dependencies.

Change-Id: Ica4baa246dd49c3a0d9fa0951ff19dc2b1894f5a
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/194456
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:15 +02:00
887b4b40f1 regulator: scmi regulators can bind with scmi voltage domain names
Allow DT to define the voltage domain name (new string property
voltd-name) instead of the voltage domain ID from property reg.
This change makes SCMI regulators binding more flexible between
SCMI server and U-Boot SCMI agent.

Change-Id: I8e1cbd0745bf61d00238eb1d13ff73ff99920b38
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/194453
2022-05-19 09:21:15 +02:00
bc21c829c4 adc: stm32mp15: add check in power down exit
Check actual power state before requesting ADC wake-up.
This allows to save time on successive conversions.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Change-Id: Ie271447eb36837cb9e50cc5f1d6612c26bede25e
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/223336
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Fabrice GASNIER <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:15 +02:00
2ae4ea6d21 adc: stm32mp15: add calibration support
Add support of offset and linear calibration for STM32MP15.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Change-Id: I12616a161ad14b61957ff2da5357c1220bc0d77b
Reviewed-by: Fabrice GASNIER <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:15 +02:00
023dde0a2a stm32mp15: increase CONFIG_SYS_MALLOC_F_LEN
The STM32MP15 value of CONFIG_SYS_MALLOC_F_LEN (0x3000) would
not provide enough memory for devices initialization.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I371b512bdf9bd50939b4d4910a1c804932314fff
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/223669
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-19 09:21:15 +02:00
75ea9e7593 stm32mp: stm32prog: add TEE support in stm32prog command
When OP-TEE is used, the SMC for BSEC management are not
available and the PTA provisioning for OTP must be used.

U-Boot opens the session to this PTA and use it for OTP
access.

Change-Id: Ic62ab0b22b898fc5dfae530e3560849cd33d5902
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/215405
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-19 09:21:15 +02:00
d57c9df2ec stm32mp: add TEE support in bsec driver
When OP-TEE is used, the SMC for BSEC management are not available and
the PTA BSEC must be used.

The BSEC driver try to open the session to the PTA BSEC at probe,
and when it is detected use it for OTP read or write access
fuse or shadow.

This patch also adapts the command stm32key to handle the BSEC_LOCK_PERM
lock value instead of 1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I1ce5f38d7d31c1cf1429ca1b29ef202a1f5b78c6
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/215404
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/224135
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/220091
2022-05-19 09:21:15 +02:00
07dc0013ca stm32mp1: mark deprecated CONFIG_STM32MP15x_STM32IMAGE
Mark deprecated CONFIG_STM32MP15x_STM32IMAGE as the FIP support
should be used in TF-A instead of STM32 image.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ia2ae32ee8fe3f61d9bdc5dde0a4ae478c65b400f
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/213672
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-05-19 09:21:15 +02:00
a1fd6aa0f7 phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning support
Add support of phy-tuning properties for sm32-usbphyc's phy tuning
aligned with v5.15 kernel bindings.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ie551580e5fb6fda0ef920ad27cb55614d5b75db6
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/211926
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/228125
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:15 +02:00
232062cc15 remoteproc: stm32: update to dynamically detect the OPTEE support
Instead of using compatible field in DT, dynamically detect the presence
of the remoteproc TEE trusted application (TA). If detected the
coprocessor firmware management is delegated to the TA.
Else the driver manages it.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Change-Id: Iebd3a4a94dc737101e09c59ee3de3a0d5ffb214c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/192188
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
2022-05-19 09:21:15 +02:00
abb9b1c968 remoteproc: tee: deinit rproc_optee struct on session close
The TEE session is closed, clean up related context registered
in the rproc_optee structure.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Change-Id: Idbaa8a7eea7ada691353f7e7490edbac61902bf0
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/194401
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
2022-05-19 09:21:15 +02:00
6bcc1dbb4e remoteproc: tee: return an error if tee session can be opened
to be able to dynamically detect the presence of the TEE TA, return an
error if the open session fails.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Change-Id: Icbc243f2c935a9d082ca4055bbd3e087268449d2
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/192187
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
2022-05-19 09:21:15 +02:00
d3a7749fed stm32mp1: add remoteproc TEE support for trusted config
Add CONFIG_REMOTEPROC_OPTEE=y. This only adds in the build the
device to support the management of the Cortex-M4 firmware by OPTEE.
The feature has to be enable using device tree "st,stm32mp1-m4_optee"
compatible.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Change-Id: If7dc8800c09814a49c97275b92b4842c8ac17e07
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/178826
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
(cherry picked from commit 5a79badae72df624446711535e6aa32917e3b6d4)
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/179344
Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2022-05-19 09:21:15 +02:00
e2020ba38b remoteproc: stm32: add support of the remote proc management by OP-TEE
Add possibility to use the OP-TEE trusted application to manage the
cortex M4 firmware for the stm32mp1 machine.
The selection is done using the DT compatibility property
"st,stm32mp1-m4_optee".

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Change-Id: I21b67e48f5abb4016cb22de3d409406983593c5c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/178825
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
(cherry picked from commit 49de5e2be7e13863d9e0939662aec019d0585de1)
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/179343
Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2022-05-19 09:21:15 +02:00
99db47d0d5 remoteproc: Add remoteproc trusted application support
Add rproc-optee.c to implement the interface with the OP-TEE remoteproc
trusted application. This implementation allows to delegate the remote
proc firmware management to OP-TEE in case of firmware secured by OP-TEE.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Change-Id: I48ac13a4499d292f67cf9b7f1865a0867611ebe8
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/178824
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
(cherry picked from commit 6c09605a80bb9aaec5c9c9483dcec43d27c08658)
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/179342
Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2022-05-19 09:21:15 +02:00
5dc7b144d8 doc: add new board in documentation stm32mp1.rst
Add new board in documentation stm32mp1.rst:
+ stm32mp157a-ed1.dts
+ stm32mp157a-ev1.dts
+ stm32mp157d-dk1.dts
+ stm32mp157d-ed1.dts
+ stm32mp157d-ev1.dts
+ stm32mp157f-dk2.dts
+ stm32mp157f-ed1.dts
+ stm32mp157f-ev1.dts

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ic10842f61b46982475da71c5f5fffa4c8ad34f64
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/153293
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
2022-05-19 09:21:15 +02:00
1745850e87 dts: reduce device tree for trusted boot
Remove the SPL only nodes for trusted boot chain with TFABOOT enable.
Prepare the removal of basic defconfig.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I784b62187091557c8b05161b70b578824e549195
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/152522
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
2022-05-19 09:21:15 +02:00
897d27ce00 dts: stm32mp1: alignment with v5.15-stm32mp-r1
Device tree alignment with Linux kernel v5.15-stm32mp-r1

Change-Id: I3eb16a41c799a90081f8d97122fdf6f0c9f45295
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/192682
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/194405
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/194422
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/203329
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/234362
2022-05-19 09:21:15 +02:00
5f6ada1f1e stm32mp1: pwr: use SMC to access secure resources
For trusted boot, STM32MP1 need  to use SMC to access PWR secure
resources.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I65c85d36be51d381c6b95a795f4d589986c01cb3
2022-05-19 09:21:15 +02:00
5df0e43b06 stm32mp1: Add STMicroelectronics proprietary SMC
Add proprietary SMC to access to secure resource provided
or protected by STMicroelectronics TF-A.

Change-Id: I9f54d8f1e560b3a7077f515d0f0f28bd3c346e6d
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/173696
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-19 09:21:15 +02:00
9252e76a85 configs: add support of OPTEE RNG in stm32mp15 defconfig
As the RNG device is secured by default with OP-TEE, only accessible with
the RNG TA, the CONFIG_RNG_OPTEE need to activated for STM32MP15 targets
with OP-TEE support.

CONFIG_RNG_STM32MP1 is not deactivated in the STM32MP15 defconfig,
so the device tree with RNG not secured are still supported ,
when the associated node is activated:

&rng1 {
	status = "okay";
};

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I0782b2e4122e700b562bf2149fa3668e82a15b24
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/241702
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Etienne CARRIERE <etienne.carriere@foss.st.com>
2022-05-19 09:21:15 +02:00
e30b443ca6 tee: optee: bind rng optee driver
In U-Boot, the discovery of TA based on its UUID on the TEE bus is
not supported.

This patch only bind the drivers associated to the new supported
OP-TEE TA = TA_HWRNG when this driver is enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I610cd6d6ab087268c699b320865cffe3bc899ff9
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/240909
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Etienne CARRIERE <etienne.carriere@foss.st.com>
2022-05-19 09:21:15 +02:00
eacb8d4a59 rng: add OP-TEE based Random Number Generator
Add driver for OP-TEE based Random Number Generator on ARM SoCs
where hardware entropy sources are not accessible to normal world
and the RNG service is provided by a HWRNG Trusted Application (TA).

This driver is based on the linux driver: char/hw_random/optee-rng.c

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I6980ad16e38de52ac7fca70c7d06d35bac0f6782
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/246030
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/240908
Reviewed-by: Etienne CARRIERE <etienne.carriere@foss.st.com>
2022-05-19 09:21:15 +02:00
41de7a85dc sandox: test: reactivate tests for the command LOG
Reactivate the CONFIG_CMD_LOG in sandbox to execute the LOG tests
by default and correct the test log format after 72fa1ad8d9 ("log: Allow
padding of the function name").

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I8b2905e3dfc95c21afd004977b40787144509b5c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/234795
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-05-19 09:21:15 +02:00
1a00281673 phy: usbphyc: use regulator_set_enable_if_allowed for disabling vbus supply
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while disabling vbus supply. This way the driver doesn't see an error
when disabling an always-on regulator.

This patch is needed for STM32MP157C-DK2 board with the always-on
regulator v3v3: buck4 used as the phy vbus supply in kernel device tree:

&usbphyc_port0 {
        ...
	/*
	 * Hack to keep hub active until all connected devices are suspended
	 * otherwise the hub will be powered off as soon as the v3v3 is disabled
	 * and it can disturb connected devices.
	 */
	connector {
		compatible = "usb-a-connector";
		vbus-supply = <&v3v3>;
	};
};

Without this patch the command "usb stop" failed and the next command
"usb start" cause a crash.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Iff08cf94aa6c6d3678acb28a8dd012d466184b42
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237035
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Tested-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-05-19 09:21:15 +02:00
35fad85bf6 Revert "spi: Update speed/mode on change"
This reverts commit e2e95e5e25.

The final implementation will be submitted to upstream. As there is
a risk to trigger discussions, a quick fix is to temporarly revert the
culprit patch waiting for validated upstream solution.

Change-Id: Ia0699b1a56b66e4d683e2091b13f563ea8fabd3a
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/235196
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:15 +02:00
e1cfddeba0 configs: stm32mp: Resync with moveconfig
Resync defconfig with tools/moveconfig.py

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ib2c04b92e1c8009d55f850efff59b927d0426da2
2022-05-19 09:21:15 +02:00
03ecc33869 arm: dts: stm32mp15: alignment with v5.17
Device tree alignment with Linux kernel v5.17-rc1
- ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins
  on STM32MP15 DKx boards
- ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15
- ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx
- ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1
- ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk

[Backport of commit 182738fe2f ("arm: dts: stm32mp15: alignment
 with v5.17")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I31f8fb35304486855af3da479195f839c83f195d
2022-05-19 09:21:15 +02:00
23c079ada3 stm32mp1: bsec: add missing dev in function comment
Add the missing @dev reference in some function description.

[Backport of commit 2d48d99c4a ("stm32mp1: bsec: add missing
 dev in function comment")]

Fixes: b66bfdf238 ("arm: stm32mp: bsec: migrate trace to log macro")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ie699b8bb03dfaa3eb5b4e175c0cb5f80fe05a507
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/239800
2022-05-19 09:21:15 +02:00
ac58f7d935 stm32mp: bsec: add permanent lock write support
Add support of the permanent lock support in U-Boot proper
when BSEC is not managed by secure monitor (TF-A SP_MIN or OP-TEE).

This patch avoid issue with stm32key command and fuse command
on basic boot for this missing feature of U-Boot BSEC driver.

[Backport of commit 0c20f53b3f ("stm32mp: bsec: add permanent
 lock write support")]

Reported-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ieeaf41663269419a8dd8a97d43e860dff3bb39ff
2022-05-19 09:21:15 +02:00
01f0f22488 mtd: rawnand: stm32_fmc2: add NAND Write Protect support
This patch adds the support of the WP# signal. WP will be disabled
before the first access to the NAND flash.

[Backport of commit 7ce4f1fad2 ("mtd: rawnand: stm32_fmc2: add
 NAND Write Protect support")]

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I633d6ea7c37b2c80e620285c2e5a915836aca795
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/240166
2022-05-19 09:21:15 +02:00
5be75f2f5c cmd: clk: fix long help message
Fix the long help message for "clk setfreq" command

[Backport of commit 92a1bba857 ("cmd: clk: fix long help message")]

Fixes: 7ab418fbe6 ("clk: add support for setting clk rate from cmdline")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20220131172131.4.Ic863c28ffdcc15b3f4616434c2efd88b4e45495c@changeid
Change-Id: Ic863c28ffdcc15b3f4616434c2efd88b4e45495c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237055
2022-05-19 09:21:14 +02:00
ddd5c9d823 cmd: clk: update result of do_clk_setfreq
Update the result of do_clk_setfreq and always returns a CMD_RET_ value
(-EINVAL was a possible result).

This patch avoid the CLI output "exit not allowed from main input shell."

[Backport of commit 534859ac6b ("cmd: clk: update result of
 do_clk_setfreq")]

Fixes: 7ab418fbe6 ("clk: add support for setting clk rate from cmdline")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20220131172131.3.Iec2029edb7fc0b29e13bcb86058ad2f614f62779@changeid
Change-Id: Iec2029edb7fc0b29e13bcb86058ad2f614f62779
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237054
2022-05-19 09:21:14 +02:00
a37b37e853 cmd: clk: replace clk_lookup by uclass_get_device_by_name
The function clk_lookup can be replaced by a direct call
to uclass_get_device_by_name for UCLASS_CLK.

This patch removes duplicated codes by the generic DM API and avoids
issue in clk_lookup because result of uclass_get_device wasn't tested;
when ret < 0, dev = NULL and dev->name is invalid, the next function
call strcmp(name, dev->name) causes a crash.

[Backport of commit afcc26140b ("cmd: clk: replace clk_lookup by
 uclass_get_device_by_name")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20220131172131.2.I7bc7762eff1e31ab7ff5b34c416ee03b8fe52200@changeid
Change-Id: I7bc7762eff1e31ab7ff5b34c416ee03b8fe52200
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237053
2022-05-19 09:21:14 +02:00
ee5cbb9572 cmd: clk: test the number of argument in setfreq command
Test the number of argument in setfreq command to avoid a crash when
the command setfreq is called without argument:

  STM32MP> clk setfreq
  data abort
  pc : [<ddba3f18>]	   lr : [<ddba3f89>]
  reloc pc : [<c018ff18>]	   lr : [<c018ff89>]
  sp : dbaf45b8  ip : ddb1d859	 fp : 00000002
  r10: dbb3fd80  r9 : dbb11e90	 r8 : ddbf38cc
  r7 : ddb39725  r6 : 00000000	 r5 : 00000000  r4 : dbb3fd84
  r3 : dbb3fd84  r2 : 0000000a	 r1 : dbaf45bc  r0 : 00000011
  Flags: nzCv  IRQs off  FIQs off  Mode SVC_32 (T)
  Code: 4dd3 1062 85a3 ddbd (7803) 2b30
  Resetting CPU ...

[Backport of commit 3386fb1e48 ("cmd: clk: test the number
 of argument in setfreq command")]

Fixes: 7ab418fbe6 ("clk: add support for setting clk rate from cmdline")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20220131172131.1.I32a8f213d330dccd922f7aafc60d3d63fcbe8615@changeid
Change-Id: I32a8f213d330dccd922f7aafc60d3d63fcbe8615
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237052
2022-05-19 09:21:14 +02:00
a0e7701e23 clk: ccf: correct the test on the parent uclass in clk_enable/clk_disable
It is safe to check if the uclass id on the device is UCLASS_CLK
before to call the clk_ functions, but today this comparison is
not done on the device used in API: clkp->dev->parent
but on the device himself: clkp->dev.

This patch corrects this behavior and tests if the parent device
is a clock device before to call the clock API, clk_enable or
clk_disable, on this device.

[Backport of commit b0cdd8287a ("clk: ccf: correct the test on the
 parent uclass in clk_enable/clk_disable")]

Fixes: 0520be0f67 ("clk: prograte clk enable/disable to parent")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/235901
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Change-Id: Ic9cd1563aac729132cadae8c5df372be1a49ecc7
2022-05-19 09:21:14 +02:00
913e44d801 mtd: Remove mtd_erase_callback() entirely
The original purpose of mtd_erase_callback() in Linux at the time it was
imported to U-Boot, was to inform the caller that erasing is done (since
it was an asynchronous operation).

All supplied callback methods in U-Boot do nothing, but the
mtd_erase_callback() function was (until previous patch) grossly abused
in U-Boot's mtdpart implementation for completely different purpose.

Since we got rid of the abusement, remove the mtd_erase_callback()
function and the .callback member from struct erase_info entirely, in
order to avoid such problems in the future.

[Backport of commit 0d1ecc99cb ("mtd: Remove mtd_erase_callback()
 entirely")]

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I375d1c8bc77b0c21f91f94b7d3cd9b000ed4fddc
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244490
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
ce0f986a07 mtd: mtdpart: Make mtdpart's _erase method sane
The _erase() method of the mtdpart driver, part_erase(), currently
implements offset shifting (for given mtdpart partition) in a weird way:
  1. part_erase() adds partition offset to block address
  2. parent driver's _erase() method is called
  3. parent driver's _erase() method calls mtd_erase_callback()
  4. mtd_erase_callback() subtracts partition offset from block address
     so that the callback function is given correct address
The problem here is that if the parent's driver does not call
mtd_erase_callback() in some scenario (this was recently a case for
spi_nor_erase(), which did not call mtd_erase_callback() at all), the
offset is not shifted back.

Moreover the code would be more readable if part_erase() not only added
partition offset before calling parent's _erase(), but also subtracted
it back afterwards. Currently the mtd_erase_callback() is expected to do
this subtracting since it does have to do it anyway.

Add the more steps to this procedure:
  5. mtd_erase_callback() adds partition offset to block address so that
     it returns the the erase_info structure members as it received them
  6. part_erase() subtracts partition offset from block address

This makes the code more logical and also prevents errors in case
parent's driver does not call mtd_erase_callback() for some reason.

(BTW, the purpose of mtd_erase_callback() in Linux is to inform the
 caller that it is done, since in Linux erasing is done asynchronously.
 We are abusing the purpose of mtd_erase_callback() in U-Boot for
 completely different purpose. The callback function itself has empty
 implementation in all cases in U-Boot.)

[Backport of commit a60397d219 ("mtd: mtdpart: Make mtdpart's _erase
 method sane")]

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Change-Id: I3361bf8715b32637de097eb8b79f2cde81d902de
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244489
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
ae882f6ac2 mtd: spi-nor-core: Check for ctrlc() in spi_nor_erase()
May it possible to interrupt the spi_nor_erase() function.

[Backport of commit 1fd5e67595 ("mtd: spi-nor-core: Check for
 ctrlc() in spi_nor_erase()")]

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Change-Id: I4560e016701fa9969f32b11b17f0243bfe675540
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244488
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
b3ba91918e mtd: spi-nor-core: Call mtd_erase_callback() from spi_nor_erase()
The spi_nor_erase() function does not call mtd_erase_callback() as it
should.

The mtdpart code currently implements the subtraction of partition
offset in mtd_erase_callback().

This results in partition offset being added prior calling
spi_nor_erase(), but not subtracted back on return. The result is that
the `mtd erase` command does not erase the whole partition, only some of
it's blocks:

  => mtd erase "Rescue system"
  Erasing 0x00000000 ... 0x006fffff (1792 eraseblock(s))
  jedec_spi_nor spi-nor@0: at 0x100000, len 4096
  jedec_spi_nor spi-nor@0: at 0x201000, len 4096
  jedec_spi_nor spi-nor@0: at 0x302000, len 4096
  jedec_spi_nor spi-nor@0: at 0x403000, len 4096
  jedec_spi_nor spi-nor@0: at 0x504000, len 4096
  jedec_spi_nor spi-nor@0: at 0x605000, len 4096
  jedec_spi_nor spi-nor@0: at 0x706000, len 4096

This is obviously wrong.

Add proper calling of mtd_erase_callback() into the spi_nor_erase()
function.

[Backport of commit ff0000b47d ("mtd: spi-nor-core: Call
 mtd_erase_callback() from spi_nor_erase()")]

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reported-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Change-Id: I7e16c0664ff5d175e3dfe0947a0647b1778156db
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244487
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
ff405804c0 mtd: spi-nor-core: Don't check for zero length in spi_nor_write() / spi_nor_erase()
This check is already done in all callers: mtdcore's mtd_write() /
mtd_erase(), legacy spi_nor_write() / spi_flash_erase(). No reason to do
this here as well.

[Backport of commit 7398c1b758 ("mtd: spi-nor-core: Don't check for zero
 length in spi_nor_write() / spi_nor_erase()")]

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I14c2f9e139117a2209da450617e702d05a65c467
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244486
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
b237385376 mtd: spi-flash: Check for zero length in legacy spi_flash_*()
Check for zero length in the legacy spi_flash_read() /
spi_flash_write() / spi_flash_erase() functions.
On zero length, return 0 immediately, don't call the underlying method.

Rationale:
- these legacy functions call the _read(), _write() and _erase() methods
  of struct mtd
- the DM callers of these methods already check for zero length
- making all callers of these methods check for zero length makes it
  possible to remove the check from implementations of these _read(),
  _write() and _erase() methods

[Backport of commit a67b3719f3 ("mtd: spi-flash: Check for zero
 length in legacy spi_flash_*()")]

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I2b587ef1357036f4307d75170c28c7d30cd647da
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244485
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
0e7a410018 mtd: spi-nor-core: Check return value of write_disable() in spi_nor_erase()
The cleanup code of spi_nor_erase() function calls write_disable(), but
does not return it's return value even in case of failure. Fix this.

[Backport of commit f57277997b ("mtd: spi-nor-core: Check return value
 of write_disable() in spi_nor_erase()")]

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Change-Id: I1a85d03cda1dae8821cbdcf3b7353bc4b954a897
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244484
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
a963928634 mtd: spi-nor-core: Don't overwrite return value if it is non-zero
The cleanup code of the spi_nor_erase() function overwrites the ret
variable with return value of clean_bar(), even if the ret variable is
already set. Fix this.

[Backport of commit a9d9d412e0 ("mtd: spi-nor-core: Don't overwrite
 return value if it is non-zero")]

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Change-Id: Iba2e1466468ad578d1981b53cbd4adce7dfdb6fa
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244483
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
22e746daf3 mtd: spi-nor-core: Check return value of write_enable() in spi_nor_erase()
The spi_nor_erase() function does not check return value of the
write_enable() call. Fix this.

[Backport of commit 5ea6dccee4 ("mtd: spi-nor-core: Check return value
 of write_enable() in spi_nor_erase()")]

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Change-Id: Ia2f47c67d93876f633e2e5b42b67677f596a85ec
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244482
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
ea3b32e88b mtd: spi-nor-core: Try cleaning up in case writing BAR failed
Use the cleanup codepath of spi_nor_erase() also in the event of failure
of writing the BAR register.

[Backport of commit 36384f612d ("mtd: spi-nor-core: Try cleaning up
in case writing BAR failed")]

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Change-Id: If351de924be62299ed7582d19df7bf4fa3f516eb
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/244481
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
7cbb48923a board: st: common: update test on misc_read result in command stboard
Update management of misc_read/misc_write, which now returns length of
data after the commit 8729b1ae2c ("misc: Update read() and write()
methods to return bytes xfered"): raise a error when the result is not
the expected length.

Fixes: 658fde8a36 ("board: stm32mp1: stboard: lock the OTP after programming")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/224136
Change-Id: I772b37f5f94142644b1fb45549e80239a8101263
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237867
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-19 09:21:14 +02:00
34a2d1841e video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate()
The clk_set_rate() function returns rate as an 'ulong' not
an 'int' and rate > 0 by default.

This patch avoids to display the associated warning when
the set rate function returns the new frequency.

Series-cc: Yannick Fertré <yannick.fertre@foss.st.com>
Fixes: aeaf330649 ("video: stm32: stm32_ltdc: add bridge to display controller")
Change-Id: I6a1d7cbbdc7d1b209e4fa704fa7dd6524b4cec9f
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/235744
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237866
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-19 09:21:14 +02:00
0c46193206 clk: scmi: register scmi clock with CCF
Implements SCMI APIs to retrieve the number exposed SCMI clocks using
SCMI_PROTOCOL_ATTRIBUTES messages and the names of the clocks using
SCMI_CLOCK_ATTRIBUTES messages.

This change updates sandbox SCMI clock test driver to manage these
2 new message IDs.

Change-Id: Ib8f6548a4b29d5d7599ae7b7fb79822508ae33c5
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236344
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
59bfe705b0 firmware: scmi: fix sandbox and related tests for clock discovery
Updates sandbox SCMI clock driver and tests since enabling CCF will
mandate clock discovery that is all exposed SCMI clocks shall be
discovered at initialization. For this reason, sandbox SCMI clock
driver must emulate all clocks exposed by SCMI server, not only those
effectively consumed by some other U-Boot devices.

Therefore the sandbox SCMI test driver exposes 3 clocks (IDs 0, 1 and 2)
and sandbox SCMI clock consumer driver gets 2 of them.

Change-Id: If031596fa5d89d1286c892a654b443261516e80a
Series-links: 246809
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236343
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
9b1121a5e9 scmi: change parameter dev in devm_scmi_process_msg
Changes devm_scmi_process_msg() first argument from target parent device
to current SCMI device and lookup the SCMI agent device among SCMI device
parents for find the SCMI agent operator needed for communication with
the firmware.

This change is needed in order to support CCF in clk_scmi driver unless
what CCF will fail to find the right udevice related to exposed SCMI
clocks.

This patch allows to simplify the caller sequence, using SCMI device
reference as parameter instead of knowing SCMI uclass topology. This
change also adds some protection in case devm_scmi_process_msg() API
function is called for invalid device type.

Change-Id: Ic79f2f736b772878a572f856981f3112d2677d7a
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236333
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
fc338e0797 sandbox: scmi: test against a single scmi agent
As per DT bindings since Linux kernel v5.14, the device tree can define
only 1 SCMI agent node that is named scmi [1]. As a consequence, change
implementation of the SCMI driver test through sandbox architecture to
reflect that.

This change updates sandbox test DT and sandbox SCMI driver accordingly
since all these are impacted.

Change-Id: I642704049f6fe50bc13c5cd776250ee34efb570a
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236332
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
4d12f1fb9f doc: binding: scmi: link to latest Linux kernel binding
Changes SCMI bindings documentation to relate to Linux kernel
source tree that recently changed the bindings description to YAML
format.

Change-Id: Ibfb1acfe26042dfd7a9a22fc2bcae486cc9a8bc4
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236331
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-19 09:21:14 +02:00
d71468e79c dm: Fix OF_BAD_ADDR definition
When OF_LIVE flag is enabled on a 64 bits platform, there is an
issue when dev_read_addr() is called and need to perform an address
translation using __of_translate_address().

In case of error, __of_translate_address() return's value is OF_BAD_ADDR
(wich is defined in include/dm/of.h to ((u64)-1) = 0xffffffffffffffff).
The return value of dev_read_addr() is often compared to FDT_ADDR_T_NONE
which is defined as (-1U) = 0xffffffff.
In this case the comparison is always false.

To fix this issue, define FDT_ADDR_T_NONE to (ulong)(-1) in case of
AARCH64. Update accordingly related tests.

[Backport of commit 9876ae7db6 ("dm: Fix OF_BAD_ADDR definition")]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I39eddb1dd012a892f57110722e6c87013f3591ca
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237676
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
dd0f840cf4 dfu: mtd: skip empty pages when writing page for UBI partition
Align the DFU MTD backend for the UBI partitions with the mtd command write
behavior when the option .dontskipff is not used: don't write the empty
pages (full of 0xFF); it is not required for UBI, see [1] for details.

This patch avoids the "free space fixup" procedure in the kernel [2]
and allows to program a UBIFS volume generated by mkfs.ubifs without the
option -F, --space-fixup.

The MTD DFU backend implements this behavior introduced on DFU NAND
backend by the commit 13cb7cc9e8 ("dfu: Add option to skip empty pages
when flashing UBI images to NAND") and also supported by the command nand
by CONFIG_CMD_NAND_TRIMFFS and by commit c9494866df ("cmd_nand: add nand
write.trimffs command").

[1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
[2] http://www.linux-mtd.infradead.org/faq/ubifs.html#L_free_space_fixup

[Backport of commit 562274730a ("dfu: mtd: skip empty pages when writing page for UBI partition")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I161a621b6f151ada380bedac41d2a2bd67d47933
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/231983
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/237675
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-19 09:21:14 +02:00
f72092f680 dfu: handle short frame result of UPLOAD in state_dfu_idle
In DFU v1.1 specification [1] the DFU_UPLOAD (Short Frame)
is handled only in dfuUPLOADIDLE state:

- Figure A.1 Interface state transition diagram

- the state description in chapter A.2

A.2.3 State 2 dfuIDLE
  on Receipt of the DFU_UPLOAD request,and bitCanUpload = 1
  the Next State is dfuUPLOADIDLE

A.2.10 State 9 dfuUPLOAD-IDLE
  When the length of the data transferred by the device in response
  to a DFU_UPLOAD request is less than wLength. (Short frame)
  the Next State is dfuIDLE

In current code, when an UPLOAD is completely performed after the first
request (for example with wLength=200 and data read = 9), the DFU state
stay at dfuUPLOADIDLE until receiving a DFU_UPLOAD or a DFU_ABORT request
even it is unnecessary as the previous DFU_UPLOAD request already reached
the EOF.

This patch proposes to finish the DFU uploading (don't go to dfuUPLOADIDLE)
and completes the control-read operation (go to DFU_STATE_dfuIDLE) when
the first UPLOAD response has a short frame as an end of file (EOF)
indicator even if it is not explicitly allowed in the DFU specification
but this seems logical.

[1] https://www.usb.org/sites/default/files/DFU_1.1.pdf

[Backport of commit 86b6a38863 ("dfu: handle short frame result of UPLOAD in state_dfu_idle")]

Change-Id: I1158bd6d095c996f2dbd4b0aa9327e4eee202331
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/206350
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
2022-05-19 09:21:14 +02:00
244732bcb2 stm32prog: add partition name in treat_partition_list error messages
Add the partition name and remove the line number in error messages
of treat_partition_list() to provide correct information to user of
STM32CubeProgrammer.

The "line number" value was confusing because it is incorrect here;
the index in  part_array[] is not aligned with the line number in
the parsed Layout file, because the empty lines and the lines beginning
by '#' are skipped during the first parsing in parse_flash_layout().

[Backport of commit 94e561f84a ("stm32prog: add partition name in treat_partition_list error messages")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ic9dd7501d7e1e832827438c6a94605cdfdb17f0b
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232876
2022-05-19 09:21:14 +02:00
f34b31e35d board: stm32mp1: solve compilation issue when ENV_IS_IN_MMC is deactivated
Solve compilation issue on undefined CONFIG_SYS_MMC_ENV_DEV when
CONFIG_ENV_IS_IN_MMC is deactivated on STMicroelectronics boards
defconfig

[Backport of commit 046bdb8064 ("board: stm32mp1: solve compilation issue when ENV_IS_IN_MMC is deactivated")]

Fixes: 9f97193616 ("board: stm32mp1: use CONFIG_SYS_MMC_ENV_DEV when available")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ied2e1c9b4790072658cbab4515ba8933878ce029
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/229109
2022-05-19 09:21:14 +02:00
535c255a7f stm32mp: fix board_get_alt_info_mmc()
MAX_SEARCH_PARTITIONS is the highest possible partition number.
Do not skip the last partition in board_get_alt_info_mmc().

[Backport of commit 6ddc71c13e ("stm32mp: fix board_get_alt_info_mmc()")]

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I2fd8cd4dd5f6a6e00166a11fc2ddfd0ae1a6df8d
2022-05-19 09:21:14 +02:00
15c50dcc40 arm: dts: stm32mp15: alignment with v5.16
Device tree alignment with Linux kernel v5.16-rc5
- ARM: dts: stm32: set otg-rev on stm32mp151
- ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151
- ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15
- ARM: dts: stm32: fix SAI sub nodes register range
- ARM: dts: stm32: fix STUSB1600 Type-C irq level on stm32mp15xx-dkx

[Backport of commit bd485f9bcc ("arm: dts: stm32mp15: alignment with v5.16")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ia4289d432cf2f54d83ccade40207060414c45b9f
2022-05-19 09:21:14 +02:00
1d98a266bc stm32mp: correct the dependency for bootcount configs
Default value for CONFIG_SYS_BOOTCOUNT_SINGLEWORD and
CONFIG_SYS_BOOTCOUNT_ADDR are only needed when
CONFIG_BOOTCOUNT_GENERIC is used.

This patch avoids to define these configs when an other bootcount backend
is activated, for example for CONFIG_BOOTCOUNT_ENV.

[Backport of commit 5c68904fe1 ("stm32mp: correct the dependency for bootcount configs")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I6347e4b7268b9a30a04d597cd467fbcf8defd684
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/229111
2022-05-19 09:21:14 +02:00
752892df48 stm32mp: remove the bootcount activation
Today the bootcount is not managed by the Linux kernel for STM32MP15 as
we don't have driver to update the used backup register in TAMP and the
recovery command still executes the normal bootcmd with
'altbootcmd=run bootcmd'.

So the bootcount feature is never used, the config CONFIG_BOOTCOUNT_LIMIT
and the associated environment variable 'altbootcmd' can be removed to
reduce the U-Boot size.

Each boards can re-enable this feature later in their defconfig, if it is
needed, with the expected backend, for example CONFIG_BOOTCOUNT_GENERIC
or CONFIG_BOOTCOUNT_ENV.

[Backport of commit d5e8119bae ("stm32mp: remove the bootcount activation")]

CC: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Iafe36c0d5ba0a3fbd8016d9ae07ef5db77c553c7
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/229112
2022-05-19 09:21:14 +02:00
62b81b7417 clk: define LOG_CATEGORY for generic and ccf clocks
Define LOG_CATEGORY to allow filtering with log command
for generic clock and CCF clocks.

This patch also change existing printf, debug and pr_ macro
to log_ or dev_ macro.

[Backport of commit 560e1e0050 ("clk: define LOG_CATEGORY for generic and ccf clocks")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Change-Id: I7e1b337de95ed3ecef41dace307271e7a412c35c
2022-05-19 09:21:14 +02:00
cb2875221f clk: cosmetic: reorder include files
Reorder include files in the U-Boot expected order:

the common.h header should always be first,
followed by other headers in order,
then headers with directories,
then local files.

It is a preliminary step for next patch.

[Backport of commit 572c446e98 ("clk: cosmetic: reorder include files")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Change-Id: I02f0f915095a8089745f18fb6146ec917ff4d1bd
2022-05-19 09:21:14 +02:00
a3e691ee50 firmware: scmi: fix struct layout for scmi_clk_rate_set_in
First two fields are reversed compared to what is expected by the SCMI
specification.

[Backport of commit 32cc3929a1 ("firmware: scmi: fix struct layout for scmi_clk_rate_set_in")]
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Fixes: 6038884483 ("clk: add clock driver for SCMI agents")
Change-Id: I5c56db4c00714525b4d03ff0dc8e52a01867355c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236654
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:14 +02:00
612f23a797 firmware: scmi: Add OP-TEE transport
This change implements an SCMI transport for agent interfacing the
OP-TEE SCMI service. OP-TEE provides an SCMI PTA (Pseudo-TA) for
non-secure world to send SCMI messages over an identified channel.
The driver implemented here uses a SMT shared memory for passing
messages between client and server.

The implementation opens and releases channel resources for each
passed SCMI message so that resources allocated (sessions) or
registered (shared memory areas) in OP-TEE firmware are released for
example before relocation as the driver will likely allocate/register
them back when probed after relocation.

The integration of the driver using dedicated config switch
CONFIG_SCMI_AGENT_OPTEE is designed on the model posted to the
U-Boot ML by Patrick Delaunay [1].

[Backport of commit 48108f3a6a ("firmware: scmi: Add OP-TEE transport")]

Link: [1] https://lore.kernel.org/all/20211028191222.v3.4.Ib2e58ee67f4d023823d8b5404332dc4d7e847277@changeid/
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I9c0b57b2546ca1f69f693ac3ae2cc75494f4377d
2022-05-19 09:21:14 +02:00
3a64abd3fd dt-bindings: arm: scmi: OP-TEE as transport channel for SCMI messages
Introduce compatible "linaro,scmi-optee" for SCMI transport channel
based on an OP-TEE service invocation.

Define "linaro,optee-channel-id" property to identify the OP-TEE SCMI
channel used by the protocol(s). OP-TEE SCMI transport can either use
shared memory or a static shared memory buffer identified by the DT.

These bindings were posted to the Linux kernel DT bindings mailing list
and acked by maintainer [1].

[Backport of commit fcb41d4db2 ("dt-bindings: arm: scmi: OP-TEE as transport channel for SCMI messages")]

Link: [1] https://lore.kernel.org/linux-arm-kernel/20211029102118.GG6526@e120937-lin/T/
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Change-Id: I03756231fc4e44827847fcfa5da66e19591f4a29
2022-05-19 09:21:14 +02:00
ec76df3f7c tee: optee: define TEE error code TEE_ERROR_SHORT_BUFFER
Adds TEE_ERROR_SHORT_BUFFER as TEE error code. This error code is
commonly used by TEEs to inform caller that the buffer(s) it provided
is too small for the desired operation.

[Backport of commit 1442e9f330 ("tee: optee: define TEE error code TEE_ERROR_SHORT_BUFFER")]

Cc: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Change-Id: I25b093c117709e73f80266229261efd18f756eb4
2022-05-19 09:21:14 +02:00
91b4aec89b tee: optee: remove unused duplicated login Id macros
Remove unused OPTEE_MSG_LOGIN_* ID macros as suitable TEE_LOGIN_* ID
macros are already defined tee.h.

[Backport of commit 7c1a9b2eb9 ("tee: optee: remove unused duplicated login Id macros")]

Cc: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Change-Id: I247ec8c19764a95105980f9910e62699dba16e29
2022-05-19 09:21:14 +02:00
1b7e12085a tee: define session login identifiers
Define identifiers for clnt_login field in struct tee_open_session_arg
based in GlobalPlatform Device TEE IDs and on the REE_KERNEL identifier
extension from OP-TEE OS.

[Backport of commit 1662ed0c1a ("tee: define session login identifiers")]

Cc: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Change-Id: I20fbe41122e8fd2dec48a67bc1f194e90804f952
2022-05-19 09:21:14 +02:00
fa5d924335 firmware: scmi: smccc transport: simplify probe sequence
Minor simplification in scmi_smccc_probe() exit sequence.

[Backport of commit 32190a959d ("firmware: scmi: smccc transport: simplify probe sequence")]

Cc: Simon Glass <sjg@chromium.org>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: If5aa57eec2b6e96683d59917ebef38b7109f1e7f
2022-05-19 09:21:14 +02:00
3526f86bff firmware: scmi: smccc transport: use plat data, not priv data
Change SCMI smccc transport drivers to use platform data rather
than private data for channel reference since it only stores platform
data retrieved from the DT. Consequently the probe handler is replaced
with a of_to_plat handler.

[Backport of commit 3de5aef451 ("firmware: scmi: smccc transport: use plat data, not priv data")]

Cc: Simon Glass <sjg@chromium.org>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I6aa5778eea6819d032743ec641c932b966276ee2
2022-05-19 09:21:14 +02:00
a93ca496b2 firmware: scmi: mailbox transport: use plat data, not priv data
Change SCMI mailbox transport drivers to use platform data rather
than private data for channel reference since it only stores platform
data retrieved from the DT. Consequently the probe handler is replaced
with a of_to_plat handler.

[Backport of commit 88a304f864 ("firmware: scmi: mailbox transport: use plat data, not priv data")]

Cc: Simon Glass <sjg@chromium.org>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifdfefc6f8fd7ef24ad034cc652865161c0263674
2022-05-19 09:21:14 +02:00
2f5d46d0d1 firmware: scmi: mailbox transport: fix probe failure implementation
Correct scmi mailbox probe function that can't free the scmi channel
instance since its auto-allocated by the device model framework.

[Backport of commit 7b4993907a ("firmware: scmi: mailbox transport: fix probe failure implementation")]

Cc: Simon Glass <sjg@chromium.org>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ied97ff5dbf4064456587b8fb40c920eeb140b933
2022-05-19 09:21:14 +02:00
6b0351ebf0 firmware: scmi: fix description of an API function
Correct inline comment describing API function devm_scmi_process_msg().

[Backport of commit 5ddbbd1957 ("firmware: scmi: fix description of an API function")]

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I79fdb25f5f254e69484fb3a9458823a26aba26cb
2022-05-19 09:21:14 +02:00
d4bb6fbb7f stm32mp15: deactivate CONFIG_SCMI_AGENT_MAILBOX
Deactivate the SCMI agent mailbox which is not used on STM32MP15
platforms.

[Backport of commit 7f6743d4f8 ("stm32mp15: deactivate CONFIG_SCMI_AGENT_MAILBOX")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Change-Id: I25b78c7ff42419afa5facdad0cbf5e2ff2bde65e
2022-05-19 09:21:14 +02:00
44a1ac15b3 firmware: scmi: add configs to select the supported agents
Add two configs CONFIG_SCMI_AGENT_MAILBOX and CONFIG_SCMI_AGENT_SMCCC
to select the supported agents as all the agents are not supported.

[Backport of commit 73ead2bcc5 ("firmware: scmi: add configs to select the supported agents")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Change-Id: I5bd5db3cf3cc6dff9e6b5f00f6601e72e4565fca
2022-05-19 09:21:14 +02:00
ad7bc53147 reset: scmi: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

[Backport of commit d96315411c ("reset: scmi: define LOG_CATEGORY")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Change-Id: If594bd1115e62a5a6ccc6e0f414976360bc32164
2022-05-19 09:21:14 +02:00
a840166a74 power: regulator: scmi: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

[Backport of commit d47c4fea8c ("power: regulator: scmi: define LOG_CATEGORY")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: Ic81d66e6b930ff3f8e44267aeb4e2cff3f88c872
2022-05-19 09:21:14 +02:00
a19d014f31 clk: scmi: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

[Backport of commit 31dc56fca5 ("clk: scmi: define LOG_CATEGORY")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Change-Id: Ia58488e27a3fad8f585de1ace1ccb1704005d420
2022-05-19 09:21:14 +02:00
8182257dd0 board: stm32mp1: add support of nor1 device in dfu command
Add support of mtd backend for nor1 when this device is present on the
board, on STM32MP157C-EV1 for example, as the support of several MTD
spi-nor instance are now supported with commit b7f060565e ("mtd:
spi-nor: allow registering multiple MTDs when DM is enabled").

[Backport of commit c7c06fa776 ("board: stm32mp1: add support of nor1 device in dfu command")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ifa1206a0d08c00615e9482ea2fd911c30a5e1fdd
2022-05-19 09:21:14 +02:00
96cc7f779f ram: stm32mp1: remove __maybe_unused on stm32mp1_ddr_setup
Since the commit f42045b2e7 ("stm32mp15: replace CONFIG_TFABOOT when
it is possible") the function stm32mp1_ddr_setup is always called so the
__maybe_unused can be removed.

[Backport of commit b2ac9645e6 ("ram: stm32mp1: remove __maybe_unused on stm32mp1_ddr_setup")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ib33f5447856b8b4de40f0e723581f02622ecd2e6
2022-05-19 09:21:14 +02:00
764d11bfc4 ram: stm32mp1: compute DDR size from DDRCTL registers
Compute the DDR size from DDR controller register (mstr and addrmap)
in U-Boot proper as the DDR information are useful only for SPL
but not for U-Boot proper, for example with TFABOOT.

This patch simplify U-Boot DT when several DDR size are supported
and support of next SOC in STM32MP family.

[Backport of commit d72e7bbe7c ("ram: stm32mp1: compute DDR size from DDRCTL registers")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I0c0981faa0778c7033293fa0d6234469481b56c7
2022-05-19 09:21:14 +02:00
803cd3efbd configs: stm32mp15: deactivate the CONFIG_STM32_IPCC
The IPCC mailbox is only used for communication with M4 firmware but
it is not used in the stm32 remoteproc driver; it was planed but the
support of this mailbox in remoteproc for STM32MP15x is dropped.

So the associated drivers and config CONFIG_STM32_IPCC can be
deactivated to reduce the U-Boot size; the CONFIG_DM_MAILBOX can be
also deactivated as the mailbox UCLASS is no more used.

[Backport of commit e84ee40b0b ("configs: stm32mp15: deactivate the CONFIG_STM32_IPCC")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ie32fc26f389edf7bfbd9820263e260fa7d5008c2
2022-05-19 09:21:14 +02:00
14c24b4d0f board: stm32mp1: enable simple framebuffer node for splashscreen
Enable an existing simple framebuffer node in the Linux kernel device
tree and the add the associated reserved memory node to preserved the
resources (clock, memory) used by the stm32 video driver to display
the splashscreen = background in exlinux.conf file.

These resources will be released by the Linux driver only when the
associated driver is ready to avoid transition issues during the Linux
kernel initialization between U-Boot splash screen and the final display.

See Linux documentation for details:
Documentation/devicetree/bindings/display/simple-framebuffer.yaml

[Backport of commit 8ad37e6f16 ("board: stm32mp1: enable simple framebuffer node for splashscreen")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I8a9c43da9cd49ac56f76da9903bdb1c1ab11c58e
2022-05-19 09:21:13 +02:00
3b44633605 video: stm32: stm32_ltdc: align framebuffer on 2MB
Align the framebuffer size on MMU_SECTION_SIZE in kernel, = max 2MB for
LPAE for armV7, to avoid issue with the simple frame buffer activation,
when U-Boot add a reserved memory in the kernel device tree to preserve
the splash screen until Linux driver initialization.

See Linux documentation for details:
Documentation/devicetree/bindings/display/simple-framebuffer.yaml

[Backport of commit 6cdeb323b8 ("video: stm32: stm32_ltdc: align framebuffer on 2MB")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ifc2d836424147a9aeeb6cf82a019dc27404e658c
2022-05-19 09:21:13 +02:00
56d81b0cdf common: add fdt_simplefb_enable_and_mem_rsv function
Add a new function to activate an existing simple frame buffer node
and add the associated reserved memory, with no-map properties.

This device tree update is only done when the video device is active
and the video buffer is used.

This patch uses '#if CONFIG_IS_ENABLED(DM_VIDEO)' because
gd->video_bottom and gd->video_top are only defined when CONFIG_DM_VIDEO
is activated.

[Backport of commit 77debf61ef ("common: add fdt_simplefb_enable_and_mem_rsv function")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I88c09f1bf230a660894ccaa5cd01ff2a601867bb
2022-05-19 09:21:13 +02:00
8e9b5dba51 video: Add video_is_active function
Add the helper function video_is_active() to test if one video device
is active.

This function can be used in board code to execute operation
only when the display is probed / really used.

[Backport of commit 2e2e6d8cac ("video: Add video_is_active function")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ibe5144de9135347b4a6949af5ebe16a648fce689
2022-05-19 09:21:13 +02:00
c8abb1d5c4 common: rename functions lcd_dt_simplefb to fdt_simplefb
Rename the function named lcd_dt_simplefb* to fdt_simplefb* to be aligned
with the associated file name fdt_simplefb.h/fdt_simplefb.c

[Backport of commit fded97adce ("common: rename functions lcd_dt_simplefb to fdt_simplefb")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Change-Id: I2e93578115e732921ff501244e6cc2c2d2bb2b53
2022-05-19 09:21:13 +02:00
9ade665fdb common: rename lcd_simplefb.c file to fdt_simplefb.c
Rename the file lcd_simplefb.c to fdt_simplefb.c to be aligned
with the configuration name and with the associated include file
./include/fdt_simplefb.h

[Backport of commit 4ca979e314 ("common: rename lcd_simplefb.c file to fdt_simplefb.c")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ie710ba4b30fcd1b63717bfd118265d831a609006

# Conflicts:
#	common/Makefile
2022-05-19 09:21:13 +02:00
26c1a9ba94 Convert CONFIG_LCD_DT_SIMPLEFB to Kconfig
This converts the following to Kconfig:
   CONFIG_LCD_DT_SIMPLEFB

This patch also renames this config to CONFIG_FDT_SIMPLEFB as the code in
common/lcd_simplefb.c support CONFIG_LCD and CONFIG_VIDEO.

[Backport of commit d71587c2ab ("Convert CONFIG_LCD_DT_SIMPLEFB to Kconfig")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Change-Id: Ic2828ce2e8227f0aa65b5f3f98b3dcd44d972256
2022-05-19 09:21:13 +02:00
ca155ce57d stm32mp1: ram: remove tuning support
Remove the DDR interactive command tuning, as the support of a predefined
DDR PHY tuning is removed for STM32MP1 driver in SPL and in TF-A
and the result of this tuning will be never used.

Moreover this SW tuning procedure can failed on some hardware
configuration (to many BIST errors and no convergence); it will be no
more supported in the next delivery of the DDR utilities included in
the CubeMX tool of STMicroelectronics.

[Backport of commit b3c29dc9e5 ("stm32mp1: ram: remove tuning support")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Id6f8d515501c0cc1b2d3c036ada5da7a33d87a87
2022-05-19 09:21:13 +02:00
4a92606312 stm32mp1: ram: remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.

The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by the CubeMX DDR utilities.

This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
  the optional parameter "st,phy-cal"

After this patch, the built-in calibration is always executed
and the calibration registers are moved in the phy dynamic part;
that allows manual tests.

[Backport of commit 9819fe345c ("stm32mp1: ram: remove the support of calibration result")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I9bcea5f88b3cde5417ae2bbc3e288c16708b1515
2022-05-19 09:21:13 +02:00
17d24872c4 stm32mp1: ram: add read valid training support
Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.

This training is supported on the PUBL integrated in the STM32MP15x
DDR subsystem and it is not required for DDR3.

[Backport of commit 4831ba2903 ("stm32mp1: ram: add read valid training support")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I97b9564ad2e5f1895985eca090b0f712c4f19ff2
2022-05-19 09:21:13 +02:00
2e78e9199d ARM: dts: stm32: Auto-detect DHSOM with uSD level translator
The uSD level translator on DHSOM and Avenger96 are optional, however it
is possible to auto-detect it. This is done by setting SD CMD line high,
and then testing whether signal level on CK line matches the signal level
on CKIN line. If so, the uSD level translator is present, otherwise it is
not populated.

[Backport of commit 77d043cac6 ("ARM: dts: stm32: Auto-detect DHSOM with uSD level translator")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ib7ef5a36fc0b4c26d1cf612ee6ed2868b2331360
2022-05-19 09:21:13 +02:00
a989833c02 mmc: stm32_sdmmc2: Add support for probing bus voltage level translator
Add support for testing whether bus voltage level translator is present
and operational. This is useful on systems where the bus voltage level
translator is optional, as the translator can be auto-detected by the
driver and the feedback clock functionality can be disabled if it is
not present.

The translator test sets CMD high to avoid interfering with a card, and
then verifies whether signal set on CK is detected on CKIN. If the signal
is detected, translator is present, otherwise the CKIN feedback clock are
disabled.

[Backport of commit 8e5266eefd ("mmc: stm32_sdmmc2: Add support for probing bus voltage level translator")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ib066453bd287f4285f706bcc71d7d796dda72d3c
2022-05-19 09:21:13 +02:00
53583d5fe3 ARM: stm32: Enable KSZ90x1 PHY driver on DHCOR
Enable KSZ9x01 PHY driver in DHCOR common configuration, since the
AV96 board has this PHY populated on the PCB.

[Backport of commit 7d35a499bd ("ARM: stm32: Enable KSZ90x1 PHY driver on DHCOR")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I2b08d46eb0dc60441996c6bb3e7e0e1213c58894
2022-05-19 09:21:13 +02:00
50c8046e55 ARM: dts: stm32: Add custom PHY reset bindings on AV96
The ethernet PHY must be reset on AV96, however DWMAC currently does
not support the MDIO-bus PHY GPIO reset bindings and the ethernet MAC
PHY reset property is going away on next DT sync. Add PHY specific
reset bindings to trigger the PHY reset and fix sporadic ethernet
malfunctions, until the next DT sync.

[Backport of commit 312011e8e7 ("ARM: dts: stm32: Add custom PHY reset bindings on AV96")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I440f9be69a5db017d9add8acb7f96c1b8f8e1ea0
2022-05-19 09:21:13 +02:00
722acf9498 ARM: stm32: Fix SoM and board coding strap GPIO handling on DHSOM
The variables retaining the strap values have to be initialized, always,
make it so. Moreover, free the requested GPIO list at the end to avoid
wasting memory.

[Backport of commit 525dd34535 ("ARM: stm32: Fix SoM and board coding strap GPIO handling on DHSOM")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id148ef10efdff753ddcbaed554cd903c89f920ab
2022-05-19 09:21:13 +02:00
74f171cb78 ARM: stm32: Increase PHY auto-negotiation timeout to 20s on DHSOM
The Micrel PHYs on known DHSOM based boards take a while to come out
of reset, increase the auto-negotiation timeout to prevent it from
timing out in case the ethernet is used right after the board was
reset.

[Backport of commit 5e3e882cf2 ("ARM: stm32: Increase PHY auto-negotiation timeout to 20s on DHSOM")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I75b8ac110afb7c6c85694aeb57cba478b5f84615
2022-05-19 09:21:13 +02:00
0d11b402ac ARM: stm32: Add update_sf script to install U-Boot into SF on DHSOM
Add script to read U-Boot from SD card and write it to matching
locations in the SPI NOR, thus making the SPI NOR bootable. The
script erases the entire SPI NOR, including U-Boot environment,
to make sure the installation is clean. To retain environment
from current running U-Boot, run 'saveenv' after running the
'update_sf' script.

[Backport of commit 1aba8e51d8 ("ARM: stm32: Add update_sf script to install U-Boot into SF on DHSOM")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I73f68f15dd4e42ab611d3edd89d4f2d265b2eb94
2022-05-19 09:21:13 +02:00
07a21b542d ARM: stm32: Increase USB power-good delay on DHSOM
The USB hub on STM32MP1 DHCOM boards needs to wait a bit longer until
the USB Vbus is stable. Increase the USB power-good delay to 1 s.

This adds default-undefined STM32MP_BOARD_EXTRA_ENV variable into
stm32mp15_common.h to reduce duplication in board-specific config
files adding custom environment.

[Backport of commit 15e20e4bdf ("ARM: stm32: Increase USB power-good delay on DHSOM")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I228f832a4e5df6211aa73d79835b5fd91458abbe
2022-05-19 09:21:13 +02:00
7b602c2a1e pinctrl: stmfx: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

[Backport of commit 4c5956086a ("pinctrl: stmfx: define LOG_CATEGORY")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I715026735ca433a0f7bb87b688a2403e944b0220
2022-05-19 09:21:13 +02:00
88b8b0fae4 ARM: dts: stm32: Use lower-case hex for address for stm32429i-eval-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

[Backport of commit 0c6079c2a9 ("ARM: dts: stm32: Use lower-case hex for address for stm32429i-eval-u-boot.dtsi")]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ia6565b7738b0dbec3d7b43d31ec57f4775195ecf
2022-05-19 09:21:13 +02:00
c6bff9b672 ARM: dts: stm32: Use lower-case hex for address for stm32f746g-eval-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

[Backport of commit a2f823e49e ("ARM: dts: stm32: Use lower-case hex for address for stm32f746g-eval-u-boot.dtsi")]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I543854127540bed5f9c905be106a0b0efa158cfd
2022-05-19 09:21:13 +02:00
ded9b8b5f5 ARM: dts: stm32: Use lower-case hex for address for stm32f429-disco-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

[Backport of commit fbe6b99d96 ("ARM: dts: stm32: Use lower-case hex for address for stm32f429-disco-u-boot.dtsi")]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ic613cc447da712ee0871f9d6ad5dbe811af01818
2022-05-19 09:21:13 +02:00
eb59263402 ARM: dts: stm32: Use lower-case hex for address for stm32f469-disco-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

[Backport of commit e114ddc385 ("ARM: dts: stm32: Use lower-case hex for address for stm32f469-disco-u-boot.dtsi")]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I10304aa255b1d00fdb47925c3f428e3e9805ff2f
2022-05-19 09:21:13 +02:00
cf963a4569 ARM: dts: stm32: Use lower-case hex for address for stm32f7-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

[Backport of commit e447a18095 ("ARM: dts: stm32: Use lower-case hex for address for stm32f7-u-boot.dtsi")]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: If48300f72c6c3eee681e954ce7de027bc912ac80
2022-05-19 09:21:13 +02:00
f6e3980172 ARM: dts: stm32: Use lower-case hex for address for stm32746-disco-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

[Backport of commit 4aace3da3c ("ARM: dts: stm32: Use lower-case hex for address for stm32746-disco-u-boot.dtsi")]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ic8e4bb4976966d00c340e28c0f4e09f4f6c33112
2022-05-19 09:21:13 +02:00
b2e6cc2e21 ARM: dts: stm32: Use lower-case hex for address for stm32f769-disco-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

[Backport of commit f1a3eb59c8 ("ARM: dts: stm32: Use lower-case hex for address for stm32f769-disco-u-boot.dtsi")]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I7e04b4fa388f70b859e13b807dc4973ab69fd351
2022-05-19 09:21:13 +02:00
c808e7dbb8 stm32mp15: tidy up #ifdefs in cpu.c
We should avoid #ifdef in C modules and the unused functions
are eliminated by the linker.

Use the more readable IS_ENABLE() instead.

[Backport of c8b2eef52b ("stm32mp15: tidy up #ifdefs in cpu.c")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I245a84f891205ff0de3d0dfdc915f554733d98a8
2022-05-19 09:21:13 +02:00
3e0c06d6f0 stm32mp15: replace CONFIG_TFABOOT when it is possible
In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced
by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC.

This patch also simplifies the code in cpu.c, stm32mp1_ram.c and
clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and
without TFA) is not supported: the associated initialization code is
present only in SPL.

This cleanup patch is a preliminary step to support SPL load of OP-TEE
in secure world, with SPL in secure world and U-Boot in no-secure world.

[Backport of commit f42045b2e7 ("stm32mp15: replace CONFIG_TFABOOT
 when it is possible")]

Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: If632457b6024170f5096a19ab2a513e2b657162a
2022-05-19 09:21:13 +02:00
cb1bebd7b8 stm32mp15: remove configs dependency on CONFIG_TFABOOT
Remove the dependency on CONFIG_TFABOOT in stm32mp Kconfig
- always activate the ARCH config: CONFIG_ARCH_SUPPORT_PSCI
  and CONFIG_CPU_V7_HAS_NONSEC
- CONFIG_ARMV7_NONSEC is deactivated in trusted defconfig
- the correct sysreset driver is activated in each defconfig:
  CONFIG_SYSRESET_PSCI or SYSRESET_SYSCON

[Backport of commit 17aeb589fa ("stm32mp15: remove configs
 dependency on CONFIG_TFABOOT")]

Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I2a6fc3736770ae75424203c835377c813d71d267
2022-05-19 09:21:13 +02:00
a11fb011b1 arm: stm32mp: bsec: Update OTP shadow registers in SPL
Currently the upper OTP (after 57) are shadowed in U-Boot proper,
when TFABOOT is not used.

This choice cause an issue when U-Boot is not executed after SPL,
so this BSEC initialization is moved in SPL and no more executed in U-Boot,
so it is still executed only one time.

After this patch this BSEC initialization is done in FSBL: SPL or TF-A.

To force this initialization in all the case, the probe of the BSEC
driver is forced in SPL in the arch st32mp function: spl_board_init().

Even if today BSEC driver is already probed in STM32MP15x clock driver
clk_stm32mp1.c because get_cpu_type() is called in
stm32mp1_get_max_opp_freq() function.

[Backport of commit 9788708f03 ("arm: stm32mp: bsec: Update OTP shadow
 registers in SPL")]

Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ib7e4b1ed806bc7c308f0e36f608a4e6e082e2446
2022-05-19 09:21:13 +02:00
7ffe2fed45 ARM: stm32: Align mtdparts with SPI NOR layout on DHSOM
The DHSOM uses different SPI NOR layout than the ST devkit, stop
pulling in the ST specific runtime mtdparts settings and adjust
the mtdparts accordingly.

[Backport of commit 819408d001 ("ARM: stm32: Align mtdparts
 with SPI NOR layout on DHSOM")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ib45f116308edf11d4a16f071cabad8c9c7f3b5e4
2022-05-19 09:21:13 +02:00
52789c337a ARM: stm32: Disable video output on DHSOM
The video output support is unused and disabling it saves about 20 kiB of space.
In case video output support is required, it can be re-enabled.

[Backport of commit d59c65817c ("ARM: stm32: Disable video output on
 DHSOM")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I20d1657e24b75d69e6fb30e456c4f9028c24f367
2022-05-19 09:21:13 +02:00
556623f655 ARM: stm32: Disable EFI on DHSOM
The EFI support is unused and disabling it saves about 70 kiB of space.
In case EFI support is required, it can be re-enabled.

[Backport of commit 00d7878275 ("ARM: stm32: Disable EFI on DHSOM")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I17d0c68caa92f931220087c9d819e7f13604048a
2022-05-19 09:21:13 +02:00
75b8fae9df ARM: stm32: Increase default SF bus frequency to 50 MHz and enable SFDP
Increase default SPI NOR bus frequency from 1 MHz to 50 MHz and
enable SFDP parsing to obtain more accurate SPI NOR configuration.

[Bckport of commit 848da6f17a ("ARM: stm32: Increase default SF bus
 frequency to 50 MHz and enable SFDP")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I1b8c40c7da07055e014f49ebfed2c9a1aeb9d5b2
2022-05-19 09:21:13 +02:00
6559afefe7 ARM: dts: stm32: Drop nWP GPIO hog on DHSOM
The nWP GPIO hog was used to unlock the SPI NOR write protect when U-Boot
used to operate the SPI NOR in 1-1-1 mode. Now that the SPI NOR is operated
in 1-1-4 mode, the hog has adverse effects and causes transfer corruption,
since the hogged pin is also the IO2 pin. Remove the hogs.

[Backport of commit eb319d8795 ("ARM: dts: stm32: Drop nWP GPIO hog on
 DHSOM")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I41090745edccc41a94be8407c3a40e221db8c2b0
2022-05-19 09:21:13 +02:00
edafb68fac ARM: stm32: Enable DFU MTD support on DHSOM
All the STM32MP1 based DHSOM have SPI NOR from which they boot,
enable DFU_MTD support to make it possible to expose that SPI NOR
via the DFU.

[Backport of commit c5eb35651c ("ARM: stm32: Enable DFU MTD
 support on DHSOM")]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ib6dc42c88258be1b32709715176b1009be91c14d
2022-05-19 09:21:13 +02:00
2f55c66b42 gpio: stm32: create include file for driver private data
The stm32 gpio driver private data are not needed in arch include files,
they are not used by code except for stm32 gpio and pincontrol drivers,
using the same IP; the defines for this IP is moved in a new file
"stm32_gpio_priv.h" in driver/gpio.

This patch avoids to have duplicated file gpio.h for each SOC
in MPU directory mach-stm32mp and in each MCU directory arch-stm32*
and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32.

[Backport of commit 56a368f661 ("gpio: stm32: create include file for
 driver private data")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Icc59387789a4f725f3d325cda49777939ee543ff
2022-05-19 09:21:13 +02:00
6bb428adfe board: stmp32mp1: split board and SOC STM32MP15 configuration
Add a configuration file "stm32mp15_st_common.h" to handle the
STMicroelectronics boards configuration and rename stm32mp1.h to
"stm32mp15_common.h" to handle the generic STM32MP15x series configuration.

The configuration file "dh_stm32mp1.h" is also renamed to
"stm32mp15_dh_dhcom" for the configuration of board based on the
dhelectronics STM32MP15x SOM.

In the STMicroelectronics board configuration the default bootcmd
"bootcmd_stm32mp" is updated to only select the extlinux file found on
SD-Card on STM32MP15x EV1 for boot from NOR device.

[Backport of commit c67ca25dfc ("board: stmp32mp1: split board and
 SOC STM32MP15 configuration")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I11ee472d24587efa9d87d62adac7158d52270ecb
2022-05-19 09:21:13 +02:00
b4c0d7446a arm: dts: stm32mp15: alignment with v5.15-rc6
Device tree alignment with Linux kernel v5.15-rc6
- Set {bitclock,frame}-master phandles on ST DKx
- Add coprocessor detach mbox on stm32mp15x-dkx boards
- Add coprocessor detach mbox on stm32mp157c-ed1 board

[Backport of commit 784c567317 ("arm: dts: stm32mp15:
 alignment with v5.15-rc6")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Iac649e9023f13d9144d71a85f4c368a700b9c35f
2022-05-19 09:21:13 +02:00
c1937a96ed stm32mp: add binman support for STM32MP15x
Use binman to add the stm32image header on SPL binary for basic boot
or on U-Boot binary when it is required, i.e. for TF-A boot without FIP
support, when CONFIG_STM32MP15x_STM32IMAGE is activated.

The "binman" tool is the recommended tool for specific image generation.
This patch allows to suppress the config.mk file and it is a preliminary
step to manage FIT generation with binman.

The init_r parsing of U-Boot device tree to search the binman
information is not required for STM32MP15, so the binman library
can be removed in U-Boot (CONFIG_BINMAN_FDT is deactivated).

[Backport of commit 5564b4cd4d ("stm32mp: add binman support for
 STM32MP15x")}

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I8e1d20c718b55731b73aa22758a87777df9ece40
2022-05-19 09:21:13 +02:00
fe30957324 stm32mp: stm32prog: Normalise newlines
The missing trailing newline could confuse check-config.sh if the
definition of an option was on the first line of the next file that
find(1) happened to return.

[Backport of commit 3067971aa9 ("stm32mp: stm32prog: Normalise
 newlines")]

Signed-off-by: William Grant <wgrant@ubuntu.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I91077773b31a501da49029c26a0c870cf2934457
2022-05-19 09:21:13 +02:00
205d9b5c68 lib: uuid: fix the test on RNG device presence
Correct the test on RNG device presence,when ret is equal to 0,
before to call dm_rng_read function.

Without this patch the RNG device is not used when present (when ret == 0)
or a data abort occurs in dm_rng_read when CONFIG_DM_RNG is activated but
the RNG device is not present in device tree (ret != 0 and devp = NULL).

[backport of commit 70a9f4d25b ("lib: uuid: fix the test on RNG device presence")]

Fixes: 92fdad28cf ("lib: uuid: use RNG device if present")
CC: Matthias Brugger <mbrugger@suse.com>
CC: Torsten Duwe <duwe@suse.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I98a420a5666428a3c4737db51d3f9c31d64c66b5
2022-05-19 09:21:13 +02:00
c752c93b62 reboot-mode: migrate uclass to livetree
Use dev_ function to support a live tree.

[backport of commit c3ef4550a2 ("reboot-mode: migrate uclass to livetree")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: Ibe70e88c973d8143ade654e2c36374769af904a9
2022-05-19 09:21:13 +02:00
d914d373cb demo: migrate uclass to livetree
Use dev_ function to read the sides and colour to support a live tree.

[backport of 455f2d15bf ("demo: migrate uclass to livetree")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I0606a98b64d33f5cc04cf034ea789a1369751050
2022-05-19 09:21:13 +02:00
678e6aa8cf remoteproc: migrate uclass to livetree
Use dev_ function to read the name and boolean to support a live tree.

[backport of e2170c29ee ("remoteproc: migrate uclass to livetree")]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: Id5c36114a6fb293d3b00bb9b9b5f5ca4ad6201f4
2022-05-19 09:21:13 +02:00
5f553e98ff test/py: Add usb gadget binding test
Add a specific usb gadget binding test which check that
binding a driver without compatible string is working as expected.

the command "bind /usb@1 usb_ether" should give the following "dm tree"
command output:

[...]
 usb           0  [   ]   usb_sandbox           |-- usb@1
 usb_hub       0  [   ]   usb_hub               |   |-- hub
 usb_emul      0  [   ]   usb_sandbox_hub       |   |   `-- hub-emul
 usb_emul      1  [   ]   usb_sandbox_flash     |   |       |-- flash-stick@0
 usb_emul      2  [   ]   usb_sandbox_flash     |   |       |-- flash-stick@1
 usb_emul      3  [   ]   usb_sandbox_flash     |   |       |-- flash-stick@2
 usb_emul      4  [   ]   usb_sandbox_keyb      |   |       `-- keyb@3
 eth           4  [   ]   usb_ether             |   `-- usb@1
[...]

[Backport of 39bd2c8e1a - test/py: Add usb gadget binding test]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Herbert Poetzl <herbert@13thfloor.at>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: If7db223cb8ca356dc9e388b43a251460c04869f8
2022-05-19 09:21:13 +02:00
25a35b580f configs: sandbox: add USB_ETHER and GADGET_DOWNLOAD gadget support
This is needed for new gadget binding test.

[Backport of 299f12508b - configs: sandbox: add USB_ETHER and GADGET_DOWNLOAD gadget support]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Herbert Poetzl <herbert@13thfloor.at>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I4b0b1e65cfd81da9e7143e19792317981bfa36ec
2022-05-19 09:21:13 +02:00
f434421fa5 usb: sandbox: Add gadget callbacks
Add usb_gadget_handle_interrupts(), usb_gadget_register_driver()
and usb_gadget_unregister_driver() to be able to test
binding usb gadget.

[Backport of 4c3dc6f69a - usb: sandbox: Add gadget callbacks]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Herbert Poetzl <herbert@13thfloor.at>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: Ib39d14124de9f732e4a781f9cb837ef090c99d21
2022-05-19 09:21:13 +02:00
85424c6acd usb: gadget: Add bcdDevice for the DWC2 USB Gadget Controller
Add an entry in usb_gadget_controller_number() for the DWC2
gadget controller. It is used to bind the USB Ethernet driver.

[Backport of 9d591106dc - usb: gadget: Add bcdDevice for the DWC2 USB Gadget Controller]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reported-by: Herbert Poetzl <herbert@13thfloor.at>
Cc: Marek Vasut <marex@denx.de>
Cc: Herbert Poetzl <herbert@13thfloor.at>
Change-Id: I47e828b813f4bedbd1abcda4123c74e8ad948f7d
2022-05-19 09:21:13 +02:00
b4e8c92fd5 cmd: bind: Fix driver binding on a device
Fix a regression brings by commit 84f8e36f03 ("cmd: bind: allow to
bind driver with driver data")

As example, the following bind command doesn't work:

   bind /soc/usb-otg@49000000 usb_ether

As usb_ether driver has no compatible string, it can't be find by
lists_bind_fdt(). In bind_by_node_path(), which called lists_bind_fdt(),
the driver entry is known, pass it to lists_bind_fdt() to force the driver
entry selection.

For this, add a new parameter struct *driver to lists_bind_fdt().
Fix also all lists_bind_fdt() callers.

[Backport 38f7d3b653 - cmd: bind: Fix driver binding on a device]

Fixes: 84f8e36f03 ("cmd: bind: allow to bind driver with driver data")
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reported-by: Herbert Poetzl <herbert@13thfloor.at>
Cc: Marek Vasut <marex@denx.de>
Cc: Herbert Poetzl <herbert@13thfloor.at>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I35308ad4f058bcd7c7ef1c13995f2345ea84281d
2022-05-19 09:21:13 +02:00
e23f1695ab board: dh_stm32mp1: Remove gpio_hog_probe_all() from board
DM_GPIO_HOG flag has been replaced by GPIO_HOG flag since a while in
commit 49b10cb492 ("gpio: fixes for gpio-hog support").

And furthermore, gpio_hog_probe_all() is already called in board_r.c.
So gpio_hog_probe() can be removed from stm32mp1.c.

[Backport of 089e433e56 - board: dh_stm32mp1: Remove gpio_hog_probe_all() from board]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I8a8678312ecc1d895f65a1920b4e104a8c01acfe
2022-05-19 09:21:13 +02:00
5571bfa33d board: stm32mp1: Remove gpio_hog_probe_all() from board
DM_GPIO_HOG flag has been replaced by GPIO_HOG flag since a while in
commit 49b10cb492 ("gpio: fixes for gpio-hog support").

And furthermore, gpio_hog_probe_all() is already called in board_r.c.
So gpio_hog_probe() can be removed from stm32mp1.c.

[Backport of d901d76eca - board: stm32mp1: Remove gpio_hog_probe_all() from board]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I5ff512461a7519711510aeb095843058e3106d1e
2022-05-19 09:21:13 +02:00
e24f1e85ab i2c: stm32f7: compute i2cclk only one time
Compute i2cclk only one time in stm32_i2c_compute_timing()
and remove setup parameter (accessible in i2c_priv).

[Backport of c31cf40096 - i2c: stm32f7: compute i2cclk only one time]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I412ffcccca13d02279d1afd07858e7978148c9b8
2022-05-19 09:21:12 +02:00
19d0c38478 i2c: stm32f7: add support for DNF i2c-digital-filter binding
Add the support for the i2c-digital-filter binding, allowing to enable
the digital filter via the device-tree and indicate its value in the DT

[Backport of 6338b45888 - i2c: stm32f7: add support for DNF i2c-digital-filter binding]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I22fa0da0fe8094f186ead52a1b86340c69761452
2022-05-19 09:21:12 +02:00
dab61d66dc i2c: stm32f7: fix configuration of the digital filter
The digital filter related computation are present in the driver
however the programming of the filter within the IP is missing.
The maximum value for the DNF is wrong and should be 15 instead of 16.

[Backport of 6bbb14f018 - i2c: stm32f7: fix configuration of the digital filter]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ic658478dbd4429fba573d7ce55ab1c29ea91270a
2022-05-19 09:21:12 +02:00
58719fd87a i2c: stm32f7: support DT binding i2c-analog-filter
Replace driver internally coded enabling/disabling of the
analog-filter with the DT binding "i2c-analog-filter".

[Backport of 0959999891 - i2c: stm32f7: support DT binding i2c-analog-filter]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ia9ab11590d325de6c204a48aadc923ff7a89872a
2022-05-19 09:21:12 +02:00
1f3542b9d8 arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32h743
Add i2c-analog-filter property in I2C nodes to enable analog
filter feature.

[Backport of 2aaac1787a - arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32h743]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I8bc9442931d21bd4d92b22e8b722135ddb552c90
2022-05-19 09:21:12 +02:00
b89cb2cd85 arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32f746
Add i2c-analog-filter property in I2C nodes to enable analog
filter feature.

[Backport of 5d59bd553b - arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32f746]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I578ae64dbe7e3aec62a53656ffac3142731ac4a1
2022-05-19 09:21:12 +02:00
0c63ec6bbf i2c: stm32f7: move driver data of each instance in a privdata
Today all the I2C instance point on the same global
variable stm32_i2c_setup according the compatible: i2c_priv->setup =
pointer to the same driver data.

This patch changes this driver data (stm32f7_setup and stm32mp15_setup)
to a const struct and move the timing struct 'setup' as element of i2c
privdata, initialized in stm32_ofdata_to_platdata() with the driver
configuration data.

This patch solves issues when several I2C instance have not the same
clock source or not the same configuration: each timing setup is saved
is the I2C privdata.

[Backport of 1fd9eb68d6 - i2c: stm32f7: move driver data of each instance in a privdata]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Idb7021619fb0d48e7640b76add671ff632b94c1b
2022-05-19 09:21:12 +02:00
f395183193 spi: stm32: Add ofdata_to_platdata() callback
Parse DT in ofdata_to_platdata() callback instead of probe().

[Backport of 81b2445af4 - spi: stm32: Add ofdata_to_platdata() callback]

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ic9a67bd6adf7edf753abf62b4f4a99947e43da93
2022-05-19 09:21:12 +02:00
bcd3802dd7 pm9263: Remove unused CONFIG_USER_LOWLEVEL_INIT
Remove the latest reference of CONFIG_USER_LOWLEVEL_INIT in code

[Backport of b0e763b7b8 - pm9263: Remove unused CONFIG_USER_LOWLEVEL_INIT]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I89c5b2113a298e9edcd3e9acf07f76e8835f01dc
2022-05-19 09:21:12 +02:00
0a58920b36 stv0991: remove specific CONFIG_STV0991 configs
Remove the following STV0991 specific configs:
- CONFIG_STV0991 (never used, only defined in CONFIG_SYS_EXTRA_OPTIONS)
- CONFIG_STV0991_HZ (replaced by generic CONFIG_SYS_HZ)
- CONFIG_STV0991_HZ_CLOCK (replaced by generic CONFIG_SYS_HZ_CLOCK)

This patch allows to reduce the file config_whitelist.txt.

[Backport of 20a3969d33 - stv0991: remove specific CONFIG_STV0991 configs]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I2c6f378cb4451ca0656fdd13e8b1d6ad80a24074
2022-05-19 09:21:12 +02:00
8f82e4f5a0 stm32f429: move CONFIG_BOOTCOMMAND in defconfig
Move CONFIG_BOOTCOMMAND defined in Kconfig in the board defconfig.

[Backport of c7f85e1f61 - stm32f429: move CONFIG_BOOTCOMMAND in defconfig]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I3e407f9bb293ff79063624d3af1b53fee504fd86
2022-05-19 09:21:12 +02:00
e421a5b915 configs: Move some usb config in defconfig
Using the tools moveconfig.py to move the following config in the
defconfig files:
 CONFIG_USB_HOST_ETHER
 CONFIG_USB_ETHER_ASIX
 CONFIG_USB_ETHER_MCS7830
 CONFIG_USB_ETHER_SMSC95XX

These option are already migrated since the commit f58ad98a62 ("usb: net:
migrate USB Ethernet adapters to Kconfig") and the commit ae3584498b
("usb: net: migrate CONFIG_USB_HOST_ETHER to Kconfig").

[Backport of 454994727d - configs: Move some usb config in defconfig]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Ian Ray <ian.ray@ge.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I93bbf1290afc1697cce2f81f95525d649dcdc314
2022-05-19 09:21:12 +02:00
b60f6692ba Convert CONFIG_STM32_FLASH to Kconfig
This converts the CONFIG_STM32_FLASH to Kconfig by using
tools/moveconfig.py

[Backport of cc30ea584e - Convert CONFIG_STM32_FLASH to Kconfig]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Iea1500582ea1adca9151e281995a3dffc8af99dd
2022-05-19 09:21:12 +02:00
52c2efafd9 Revert "configs: stm32mp1: only support SD card after NOR in bootcmd_stm32mp"
This reverts commit d5d726d3cc,
which breaks boards which ship with multiple SD/eMMC sockets.

This stm32mp1.h config is not used only by the ST reference
boards, but all the other STM32MP1 based boards in U-Boot, so
changes to this stm32mp1.h cannot break the other boards.

[Backport of 2d0808161b - Revert "configs: stm32mp1: only support SD card after NOR in bootcmd_stm32mp"]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id325a1b031cec2799bc4a95e116386ea9f05cec3
2022-05-19 09:21:12 +02:00
3f65bea896 phy: stm32-usbphyc: stm32: usbphyc: add protection on phy sub-node
Add protection on presence and order of the phy node sub node
by using the mandatory reg information.

[Backport of 5d81616fb8 - phy: stm32-usbphyc: stm32: usbphyc: add protection on phy sub-node]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I9a7a100a92bbd681c6fcc3802b1b4a1b71158210
2022-05-19 09:21:12 +02:00
8239f309fb phy: stm32-usbphyc: use connector for vbus-supply with phy-stm32-usbphyc
The vbus-supply is an optional property of sub-node connector node.
and no more in the usb phyc node (in first proposed binding).

This regulator for USB VBUS may be needed for host mode.

See the latest kernel binding for details in
Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml.

  usbphyc_port0: usb-phy@0 {
      reg = <0>;
      phy-supply = <&vdd_usb>;
      #phy-cells = <0>;
      connector {
          compatible = "usb-a-connector";
          vbus-supply = <&vbus_sw>;
      };
  };

[Backport of 5b4fa85d65 - phy: stm32-usbphyc: use connector for vbus-supply with phy-stm32-usbphyc]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I00aea12bfe61c5752abfa692e93d66b3e2e1eedf
2022-05-19 09:21:12 +02:00
6e0f44d777 board: stm32: Remove the bi_boot_params initialization
The stm32 platforms never had to support an ATAGs-based Linux Kernel,
so remove the bi_boot_params initialization.

[Backport of e69c4143e8 - board: stm32: Remove the bi_boot_params initialization]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: Ibc6a52313fd69f391abddc9d2c2cb0e20bf4d2d0
2022-05-19 09:21:12 +02:00
0b061541ab arm: stm32: Disable ATAGs support
These platforms never had to support an ATAGs-based Linux Kernel, so
remove the options.

[Backport of b703dcb0fe - arm: stm32: Disable ATAGs support]

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: I22621a3833d0f5b7a889814e1feb1968195de1d1
2022-05-19 09:21:12 +02:00
af69f7c624 SECURITY: add security guide to STMicroelectronics/u-boot repository
Add security guide to STMicroelectronics/u-boot repository.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I8069a38339e6861e3c19212f4ffd15e448e67c47
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/252911
Reviewed-by: Bernard PUEL <bernard.puel@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
2022-05-19 09:21:12 +02:00
a10492dfbe CONTRIBUTING: add contributing guide to STMicroelectronics/u-boot repository
Add contributing guide to STMicroelectronics/u-boot repository.

Signed-off-by: Bernard Puel <bernard.puel@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ia32afcbd025f24949fb27c7fe4db2133a47dcf5b
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/252910
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
2022-05-19 09:21:12 +02:00
d80bb749fa Prepare v2021.10
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-04 11:09:26 -04:00
c2e0363571 mtd: cqspi: Fix division by zero
Both dummy.nbytes and dummy.buswidth may be zero. By not checking
the later, it is possible to trigger division by zero and a crash.
This does happen with tiny SPI NOR framework in SPL. Fix this by
adding the check and returning zero dummy bytes in such a case.

Fixes: 38b0852b0e ("spi: cadence-qspi: Add support for octal DTR flashes")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
[trini: Drop Pratyush's RB as his requested changes weren't made as
        Marek disagreed]
2021-10-04 08:51:14 -04:00
bf9fcc2000 Azure/GitLab CI: Update docker image
Rebuild our current docker image so that ca-certificates will be updated
and Let's Encrypt issued certificates will work again.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-30 12:33:46 -04:00
67ae289723 Merge tag 'rpi-next-2021.10.2' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
- fix usb stopt; usb start; bug
- update Nicolas email address
2021-09-29 15:13:35 -04:00
94647e8920 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Armada8k: Fix CP0 eMMC/SDIO support (Robert)
2021-09-29 15:13:11 -04:00
33166054c7 arm: rpi: perform XHCI firmware upload only once
XHCI firmware upload must be performed only once after initializing the
PCI bridge. This fixes USB stack initialization after calling "usb stop;
usb start" on Raspberry Pi 4B.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-29 15:44:16 +02:00
6f3a9227cc mailmap: Update mail address for Nicolas Saenz julienne
The @suse.de address doesn't exist anymore. Update it to something not
dependent on my workplace.

Signed-off-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-29 15:44:16 +02:00
65513f3c18 arm: dts: armada8040: Fix CP0 eMMC/SDIO support
During the migration to a single DTSI for the CP110-s specific pinctrl
compatibles were moved to the SoC DTSI as CP0 and CP1 have some specifics.
Namely, CP0 eMMC/SDIO support depends on the mvebu-pinctrl driver setting
the BIT(0) in eMMC PHY IO Control 0 Register to 0 in order for the connect
the eMMC/SDIO PHY to the controller and not use it as a MPP pin multiplexor.

So, the mvebu-pinctrl driver check specifically for the
"marvell,armada-8k-cpm-pinctrl" compatible to clear the that bit.

Issue is that compatibles in the 8040 DTSI were set to "marvell,8k-cpm-pinctrl"
for CP0 and "marvell,8k-cps-pinctrl" for the CP1.
This is obviously incorrect as the pinctrl driver does not know about these.

So fix the regression by applying correct compatibles to the DTSI.
Regression found and tested on the Puzzle M801 board.

Fixes: a0ba97e5 ("arm: armada: dts: Use a single dtsi for cp110 die description")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-29 07:13:27 +02:00
b5d7a200a8 Merge branch '2021-09-28-regression-fixes'
- Reintroduce creating internally the "nor%d" style names, in order to
  fix some use U-Boot use-cases involving the "mtd" command.
- Fix a regression over the default SPI bus mode shown by having the
  compiled default actually start being used.  The correct default here
  is 0.
- Fix ethernet on imx7d-sdb
- Fix a regression with MTD NAND devices when OF_LIVE is enabled
2021-09-28 13:57:56 -04:00
24ea366add imx: imx7d-sdb: fix ethernet, sync .dts with linux
Commit 0d52bab46 (mx7dsabre: Enable DM_ETH) changed these flags from 0
(aka GPIO_ACTIVE_HIGH) to GPIO_ACTIVE_LOW. It claimed to "Also sync
device tree with v5.5-rc1", but in the linux tree, these gpios have
always been GPIO_ACTIVE_HIGH ever since this node was introduced
around v4.13 (linux commit 184f39b5).

I'm guessing that the reason for the GPIO_ACTIVE_LOW was to work
around the behaviour of the soft-spi driver back then, which
effectively defaulted to spi-mode 3 and not 0. That was arguably a bug
in the soft-spi driver, which then got fixed in 0e146993bb (spi: add
support for all spi modes with soft spi), but that commit then broke
ethernet on this board.

Fix it by setting the gpios as active high, which as a bonus actually
brings us in sync with the .dts in the linux source tree.

Without this, one gets

    Net:   Could not get PHY for FEC0: addr 0
    No ethernet found.

With this, ethernet (at least ping and tftp) works as expected from
the U-Boot shell.

Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joris Offouga <offougajoris@gmail.com>
Cc: "Christian Bräuner Sørensen" <yocto@bsorensen.net>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-09-28 12:03:21 -04:00
b8919eaa68 mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interface
nand_dt_init() is still using fdtdec_xx() interface.
If OF_LIVE flag is enabled, dt property can't be get anymore.
Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue.

For doing this, node parameter type must be ofnode.

First idea was to convert "node" parameter to ofnode type inside
nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode()
is not bijective, in case OF_LIVE flag is enabled, it performs an assert().

So, this leads to update nand_chip struct flash_node field from int to
ofnode and to update all nand_dt_init() callers.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-28 12:03:21 -04:00
b81ce79df0 mtd: spi: Set CONFIG_SF_DEFAULT_MODE default to 0
Before e2e95e5e25 ("spi: Update speed/mode on change") most systems
silently defaulted to SF bus mode 0. Now the mode is always updated,
which causes breakage. It seems most SF which are used as boot media
operate in bus mode 0, so switch that as the default.

This should fix booting at least on Altera SoCFPGA, ST STM32, Xilinx
ZynqMP, NXP iMX and Rockchip SoCs, which recently ran into trouble
with mode 3. Marvell Kirkwood and Xilinx microblaze need to be checked
as those might need mode 3.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Cc: Andreas Biessmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
2021-09-28 12:03:21 -04:00
a4f2d83414 mtd: spi: nor: force mtd name to "nor%d"
Force the mtd name of spi-nor to "nor" + the driver sequence number:
"nor0", "nor1"... beginning after the existing nor devices.

This patch is coherent with existing "nand" and "spi-nand"
mtd device names.

When CFI MTD NOR device are supported, the spi-nor index is chosen after
the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS.

When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config
is replaced by to cfi_flash_num_flash_banks in the include file
mtd/cfi_flash.h.

This generic name "nor%d" can be use to identify the mtd spi-nor device
without knowing the real device name or the DT path of the device,
used with API get_mtd_device_nm() and is used in mtdparts command.

This patch also avoids issue when the same NOR device is present 2 times,
for example on STM32MP15F-EV1:

STM32MP> mtd list
SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \
total 64 MiB

List of MTD devices:
* nand0
  - type: NAND flash
  - block size: 0x40000 bytes
  - min I/O: 0x1000 bytes
  - OOB size: 224 bytes
  - OOB available: 118 bytes
  - ECC strength: 8 bits
  - ECC step size: 512 bytes
  - bitflip threshold: 6 bits
  - 0x000000000000-0x000040000000 : "nand0"
* mx66l51235l
  - device: mx66l51235l@0
  - parent: spi@58003000
  - driver: jedec_spi_nor
  - path: /soc/spi@58003000/mx66l51235l@0
  - type: NOR flash
  - block size: 0x10000 bytes
  - min I/O: 0x1 bytes
  - 0x000000000000-0x000004000000 : "mx66l51235l"
* mx66l51235l
  - device: mx66l51235l@1
  - parent: spi@58003000
  - driver: jedec_spi_nor
  - path: /soc/spi@58003000/mx66l51235l@1
  - type: NOR flash
  - block size: 0x10000 bytes
  - min I/O: 0x1 bytes
  - 0x000000000000-0x000004000000 : "mx66l51235l"

The same mtd name "mx66l51235l" identify the 2 instances
mx66l51235l@0 and mx66l51235l@1.

This patch fixes a ST32CubeProgrammer / stm32prog command issue
with nor0 target on STM32MP157C-EV1 board introduced by
commit b7f060565e ("mtd: spi-nor: allow registering multiple MTDs when
DM is enabled").

Fixes: b7f060565e ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
[trini: Add <dm/device.h> to <mtd.h> for DM_MAX_SEQ_STR]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-28 12:03:20 -04:00
b218f865e8 mtd: cfi_flash: use cfi_flash_num_flash_banks only when supported
When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated,
CONFIG_SYS_MAX_FLASH_BANKS is replaced by cfi_flash_num_flash_banks,
but this variable is defined in drivers/mtd/cfi_flash.c, which is
compiled only when CONFIG_FLASH_CFI_DRIVER is activated, in U-Boot
or in SPL when CONFIG_SPL_MTD_SUPPORT is activated.

This patch deactivates this feature CONFIG_SYS_MAX_FLASH_BANKS_DETECT
when flash cfi driver is not activated to avoid compilation issue in
the next patch, when CONFIG_SYS_MAX_FLASH_BANKS is used in spi_nor_scan().

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-09-28 08:35:19 -04:00
384 changed files with 24810 additions and 6875 deletions

View File

@ -2,7 +2,7 @@ variables:
windows_vm: vs2017-win2016
ubuntu_vm: ubuntu-18.04
macos_vm: macOS-10.15
ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210723-04Aug2021
ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.

View File

@ -2,7 +2,7 @@
# Grab our configured image. The source for this is found at:
# https://source.denx.de/u-boot/gitlab-ci-runner
image: trini/u-boot-gitlab-ci-runner:focal-20210723-04Aug2021
image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021
# We run some tests in different order, to catch some failures quicker.
stages:

View File

@ -32,6 +32,7 @@ Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
Markus Klotzbuecher <mk@denx.de>
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>

30
CONTRIBUTING.md Normal file
View File

@ -0,0 +1,30 @@
# Contributing guide
This document serves as a checklist before contributing to this repository. It includes links to read up on if topics are unclear to you.
This guide mainly focuses on the proper use of Git.
## 1. Issues
STM32MPU projects do not activate "Github issues" feature for the time being. If you need to report an issue or question about this project deliverables, you can report them using [ ST Support Center ](https://my.st.com/ols#/ols/newrequest) or [ ST Community MPU Forum ](https://community.st.com/s/topic/0TO0X0000003u2AWAQ/stm32-mpus).
## 2. Pull Requests
STMicrolectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure.
* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual CLA (https://cla.st.com).
* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate CLA (https://cla.st.com) mentioning your GitHub account name.
* If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account you can check here (https://cla.st.com).
Please note that:
* The Corporate CLA will always take precedence over the Individual CLA.
* One CLA submission is sufficient, for any project proposed by STMicroelectronics.
__How to proceed__
* We recommend to fork the project in your GitHub account to further develop your contribution. Please use the latest commit version.
* Please, submit one Pull Request for one new feature or proposal. This will ease the analysis and final merge if accepted.
__Note__
Merge will not be done directly in GitHub but it will need first to follow internal integration process before public deliver in a standard release. The Pull request will stay open until it is merged and delivered.

View File

@ -438,6 +438,7 @@ F: drivers/power/regulator/stpmic1.c
F: drivers/ram/stm32mp1/
F: drivers/remoteproc/stm32_copro.c
F: drivers/reset/stm32-reset.c
F: drivers/rng/optee_rng.c
F: drivers/rng/stm32mp1_rng.c
F: drivers/rtc/stm32_rtc.c
F: drivers/serial/serial_stm32.*

View File

@ -3,7 +3,7 @@
VERSION = 2021
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc5
EXTRAVERSION = -stm32mp-r2
NAME =
# *DOCUMENTATION*
@ -843,6 +843,7 @@ libs-y += drivers/usb/mtu3/
libs-y += drivers/usb/musb/
libs-y += drivers/usb/musb-new/
libs-y += drivers/usb/phy/
libs-y += drivers/usb/typec/
libs-y += drivers/usb/ulpi/
ifdef CONFIG_POST
libs-y += post/
@ -1123,6 +1124,13 @@ ifneq ($(CONFIG_DM),y)
@echo >&2 "Failure to update may result in board removal."
@echo >&2 "See doc/driver-model/migration.rst for more info."
@echo >&2 "===================================================="
endif
ifeq ($(CONFIG_STM32MP15x_STM32IMAGE),y)
@echo >&2 "===================== WARNING ======================"
@echo >&2 "This board uses CONFIG_STM32MP15x_STM32IMAGE for STM32 image"
@echo >&2 "support in TF-A and these configuration is deprecated."
@echo >&2 "Please migrate to FIP support in TF-A instead."
@echo >&2 "===================================================="
endif
$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))

8
SECURITY.md Normal file
View File

@ -0,0 +1,8 @@
# Report potential product security vulnerabilities
ST places a high priority on security, and our Product Security Incident Response Team (PSIRT) is committed to rapidly addressing potential security vulnerabilities affecting our products. PSIRT's long history and vast experience in security allows ST to perform clear analyses and provide appropriate guidance on mitigations and solutions when applicable.
If you wish to report potential security vulnerabilities regarding our products, **please do not report them through public GitHub issues.** Instead, we encourage you to report them to our ST PSIRT following the process described at: **https://www.st.com/content/st_com/en/security/report-vulnerabilities.html**
### IMPORTANT - READ CAREFULLY:
STMicroelectronics International N.V., on behalf of itself, its affiliates and subsidiaries, (collectively “ST”) takes all potential security vulnerability reports or other related communications (“Report(s)”) seriously. In order to review Your Report (the terms “You” and “Yours” include your employer, and all affiliates, subsidiaries and related persons or entities) and take actions as deemed appropriate, ST requires that we have the rights and Your permission to do so.
As such, by submitting Your Report to ST, You agree that You have the right to do so, and You grant to ST the rights to use the Report for purposes related to security vulnerability analysis, testing, correction, patching, reporting and any other related purpose or function.
By submitting Your Report, You agree that STs [Privacy Policy](https://www.st.com/content/st_com/en/common/privacy-portal.html) applies to all related communications.

View File

@ -1749,7 +1749,6 @@ config ARCH_STM32
select CPU_V7M
select DM
select DM_SERIAL
select GPIO_EXTRA_HEADER
imply CMD_DM
config ARCH_STI
@ -1775,14 +1774,12 @@ config ARCH_STM32MP
select DM_GPIO
select DM_RESET
select DM_SERIAL
select GPIO_EXTRA_HEADER
select MISC
select OF_CONTROL
select OF_LIBFDT
select OF_SYSTEM_SETUP
select PINCTRL
select REGMAP
select SUPPORT_SPL
select SYSCON
select SYSRESET
select SYS_THUMB_BUILD

View File

@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
@ -67,7 +67,7 @@ void __udelay(unsigned long usec)
{
ulong tmo;
ulong start = get_timer_masked();
ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);
ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;
@ -110,5 +110,5 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk(void)
{
return CONFIG_STV0991_HZ;
return CONFIG_SYS_HZ;
}

View File

@ -1074,9 +1074,14 @@ dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13x) += \
stm32mp135f-dk.dtb \
stm32mp135d-gateway.dtb
dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \
stm32mp157a-avenger96.dtb \
stm32mp157a-ed1.dtb \
stm32mp157a-ev1.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
@ -1086,9 +1091,16 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp157c-ev1.dtb \
stm32mp157c-odyssey.dtb \
stm32mp15xx-dhcom-drc02.dtb \
stm32mp157d-dk1.dtb \
stm32mp157d-ed1.dtb \
stm32mp157d-ev1.dtb \
stm32mp157f-dk2.dtb \
stm32mp157f-ed1.dtb \
stm32mp157f-ev1.dtb \
stm32mp15xx-dhcom-pdk2.dtb \
stm32mp15xx-dhcom-picoitx.dtb \
stm32mp15xx-dhcor-avenger96.dtb
stm32mp15xx-dhcor-avenger96.dtb \
stm32mp157a-panguboard.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \

View File

@ -40,7 +40,7 @@
};
&cp0_pinctl {
compatible = "marvell,mvebu-pinctrl", "marvell,8k-cpm-pinctrl";
compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
bank-name ="cp0-110";
cp0_i2c0_pins: cp0-i2c-pins-0 {
@ -75,7 +75,7 @@
};
&cp1_pinctl {
compatible = "marvell,mvebu-pinctrl", "marvell,8k-cps-pinctrl";
compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cps-pinctrl";
bank-name ="cp1-110";
cp1_ge1_rgmii_pins: cp1-ge-rgmii-pins-0 {

View File

@ -44,9 +44,9 @@
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
gpio-sck = <&gpio1 13 GPIO_ACTIVE_LOW>;
gpio-mosi = <&gpio1 9 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;

View File

@ -33,7 +33,7 @@
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
st,syscfg = <&syscfg>;
pinctrl-0 = <&fmc_pins_d32>;

View File

@ -177,7 +177,7 @@
};
&qspi {
reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>;
qflash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;

View File

@ -33,7 +33,7 @@
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";

View File

@ -34,7 +34,7 @@
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
st,syscfg = <&syscfg>;
pinctrl-0 = <&fmc_pins_d32>;
@ -70,7 +70,7 @@
compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <91>;
spi-max-frequency = <108000000>;
@ -236,7 +236,7 @@
};
&qspi {
reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>;
flash0: n25q128a@0 {
#address-cells = <1>;
#size-cells = <1>;

View File

@ -7,7 +7,7 @@
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
reg = <0xa0000000 0x1000>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
@ -46,7 +46,7 @@
compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <92>;
spi-max-frequency = <108000000>;

View File

@ -228,7 +228,7 @@
};
&qspi {
reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>;
qflash0: n25q128a@0 {
#address-cells = <1>;
#size-cells = <1>;

View File

@ -313,6 +313,7 @@
clocks = <&rcc 1 CLK_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -325,6 +326,7 @@
clocks = <&rcc 1 CLK_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -337,6 +339,7 @@
clocks = <&rcc 1 CLK_I2C3>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};
@ -349,6 +352,7 @@
clocks = <&rcc 1 CLK_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
status = "disabled";
};

View File

@ -53,9 +53,9 @@
soc {
dsi: dsi@40016c00 {
compatible = "st,stm32-dsi";
reg = <0x40016C00 0x800>;
reg = <0x40016c00 0x800>;
resets = <&rcc STM32F7_APB2_RESET(DSI)>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
<&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
<&clk_hse>;
clock-names = "pclk", "px_clk", "ref";
@ -227,7 +227,7 @@
};
&qspi {
reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>;
flash0: mx66l51235l@0 {
#address-cells = <1>;
#size-cells = <1>;

View File

@ -124,6 +124,7 @@
<32>;
resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
clocks = <&rcc I2C1_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -136,6 +137,7 @@
<34>;
resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
clocks = <&rcc I2C2_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -148,6 +150,7 @@
<73>;
resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
clocks = <&rcc I2C3_CK>;
i2c-analog-filter;
status = "disabled";
};
@ -395,6 +398,7 @@
<96>;
resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
clocks = <&rcc I2C4_CK>;
i2c-analog-filter;
status = "disabled";
};

View File

@ -0,0 +1,662 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) i2SOM 2023 - All Rights Reserved
* Author: Steve Chen <steve.chen@i2som.com>
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1 in12 */
<STM32_PINMUX('A', 5, ANALOG)>; /* ADC1 in6 */
};
};
eth1_rgmii_pins_a: eth1_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 7, AF10)>, /* ETH1_RX_CLK */
<STM32_PINMUX('A', 7, AF11)>, /* ETH1_RX_CTL */
<STM32_PINMUX('B', 0, AF11)>, /* ETH1_RXD2 */
<STM32_PINMUX('B', 1, AF11)>, /* ETH1_RXD3 */
<STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('B', 11, AF11)>, /* ETH1_TX_CTL */
<STM32_PINMUX('C', 1, AF11)>, /* ETH1_GTX_CLK */
<STM32_PINMUX('C', 2, AF11)>, /* ETH1_TXD2 */
<STM32_PINMUX('E', 5, AF10)>, /* ETH1_TXD3 */
<STM32_PINMUX('F', 12, AF11)>, /* ETH1_CLK125 */
<STM32_PINMUX('G', 2, AF11)>, /* ETH1_MDC */
<STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
<STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
eth1_rgmii_sleep_pins_a: eth1_sleep_mx-0 {
pins {
pinmux = <STM32_PINMUX('D', 7, ANALOG)>, /* ETH1_RX_CLK */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
<STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_RX_CTL */
<STM32_PINMUX('B', 0, ANALOG)>, /* ETH1_RXD2 */
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH1_RXD3 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_CTL */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_GTX_CLK */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH1_TXD2 */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
<STM32_PINMUX('E', 5, ANALOG)>, /* ETH1_TXD3 */
<STM32_PINMUX('F', 12, ANALOG)>, /* ETH1_CLK125 */
<STM32_PINMUX('G', 2, ANALOG)>, /* ETH1_MDC */
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
};
};
eth2_rgmii_pins_a: eth2_mx-0 {
pins1 {
pinmux =
<STM32_PINMUX('F', 7, AF11)>, /* ETH2_TXD0 */
<STM32_PINMUX('G', 11, AF10)>, /* ETH2_TXD1 */
<STM32_PINMUX('G', 1, AF10)>, /* ETH2_TXD2 */
<STM32_PINMUX('E', 6, AF11)>, /* ETH2_TXD3 */
<STM32_PINMUX('F', 6, AF11)>, /* ETH2_TX_CTL */
<STM32_PINMUX('G', 3, AF10)>, /* ETH2_GTX_CLK */
<STM32_PINMUX('G', 5, AF10)>, /* ETH2_MDC */
<STM32_PINMUX('B', 6, AF11)>, /* ETH2_MDIO */
<STM32_PINMUX('H', 2, AF13)>; /* ETH2_CLK125 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux =
<STM32_PINMUX('A', 12, AF11)>, /* ETH2_RX_CTL */
<STM32_PINMUX('F', 4, AF11)>, /* ETH2_RXD0 */
<STM32_PINMUX('E', 2, AF10)>, /* ETH2_RXD1 */
<STM32_PINMUX('H', 6, AF12)>, /* ETH2_RXD2 */
<STM32_PINMUX('A', 8, AF11)>, /* ETH2_RXD3 */
<STM32_PINMUX('H', 11, AF11)>; /* ETH2_RX_CLK */
bias-disable;
};
};
eth2_rgmii_sleep_pins_a: eth2_sleep_mx-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* ETH2_RXD3 */
<STM32_PINMUX('A', 12, ANALOG)>, /* ETH2_RX_CTL */
<STM32_PINMUX('B', 6, ANALOG)>, /* ETH2_MDIO */
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH2_RXD1 */
<STM32_PINMUX('E', 6, ANALOG)>, /* ETH2_TXD3 */
<STM32_PINMUX('F', 4, ANALOG)>, /* ETH2_RXD0 */
<STM32_PINMUX('F', 6, ANALOG)>, /* ETH2_TX_CTL */
<STM32_PINMUX('F', 7, ANALOG)>, /* ETH2_TXD0 */
<STM32_PINMUX('G', 1, ANALOG)>, /* ETH2_TXD2 */
<STM32_PINMUX('G', 3, ANALOG)>, /* ETH2_GTX_CLK */
<STM32_PINMUX('G', 5, ANALOG)>, /* ETH2_MDC */
<STM32_PINMUX('G', 11, ANALOG)>, /* ETH2_TXD1 */
<STM32_PINMUX('H', 2, ANALOG)>, /* ETH2_CLK125 */
<STM32_PINMUX('H', 6, ANALOG)>, /* ETH2_RXD2 */
<STM32_PINMUX('H', 11, ANALOG)>; /* ETH2_RX_CLK */
};
};
goodix_pins_a: goodix-0 {
pins {
pinmux = <STM32_PINMUX('F', 5, GPIO)>;
bias-pull-down;
};
};
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
<STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c1_sleep_pins_a: i2c1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
<STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
};
};
i2c3_pins_test_b: i2c3-test-1 {
pins {
pinmux = <STM32_PINMUX('H', 3, AF4)>, /* i2c3_SCL */
<STM32_PINMUX('H', 7, AF5)>; /* i2c3_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c3_sleep_pins_test_b: i2c3-test-sleep-1 {
pins {
pinmux = <STM32_PINMUX('H', 3, ANALOG)>, /* i2c3_SCL */
<STM32_PINMUX('H', 7, ANALOG)>; /* i2c3_SDA */
};
};
i2c5_pins_a: i2c5-0 {
pins {
pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
<STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c5_sleep_pins_a: i2c5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
<STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
};
};
ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
<STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */
<STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */
<STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */
<STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */
<STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */
<STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */
<STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */
<STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */
<STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
<STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */
<STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */
<STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */
<STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */
<STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */
<STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */
<STM32_PINMUX('F', 2, AF14)>, /* LCD_B3 */
<STM32_PINMUX('H', 14, AF11)>, /* LCD_B4 */
<STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */
<STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */
<STM32_PINMUX('F', 1, AF13)>; /* LCD_B7 */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
ltdc_sleep_pins_a: ltdc-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
<STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */
<STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */
<STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */
<STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */
<STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */
<STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */
<STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */
<STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */
<STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */
<STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
<STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */
<STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */
<STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */
<STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */
<STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */
<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */
<STM32_PINMUX('F', 2, ANALOG)>, /* LCD_B3 */
<STM32_PINMUX('H', 14, ANALOG)>, /* LCD_B4 */
<STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */
<STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */
<STM32_PINMUX('F', 1, ANALOG)>; /* LCD_B7 */
};
};
m_can2_pins_a: m-can2-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 1, AF9)>; /* CAN2_TX */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('G', 3, AF9)>; /* CAN2_RX */
bias-disable;
};
};
m_can2_sleep_pins_a: m_can2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('G', 1, ANALOG)>, /* CAN2_TX */
<STM32_PINMUX('G', 3, ANALOG)>; /* CAN2_RX */
};
};
pwm3_pins_a: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm3_sleep_pins_a: pwm3-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
};
};
pwm4_pins_a: pwm4-0 {
pins {
pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm4_sleep_pins_a: pwm4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
};
};
pwm8_pins_a: pwm8-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm8_sleep_pins_a: pwm8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
};
};
pwm14_pins_a: pwm12-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm14_sleep_pins_a: pwm12-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
};
};
rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
pins {
pinmux = <STM32_PINMUX('I', 1, ANALOG)>; /* RTC_OUT2_RMP */
};
};
sai1_pins_a: sai1-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
<STM32_PINMUX('A', 0, AF6)>, /* SAI1_SD_B */
<STM32_PINMUX('A', 5, AF6)>, /* SAI1_SD_A */
<STM32_PINMUX('F', 11, AF6)>; /* SAI1_FS_A */
slew-rate = <0>;
drive-push-pull;
bias-disable;
};
};
sai1_sleep_pins_a: sai1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
<STM32_PINMUX('A', 0, ANALOG)>, /* SAI1_SD_B */
<STM32_PINMUX('A', 5, ANALOG)>, /* SAI1_SD_A */
<STM32_PINMUX('F', 11, ANALOG)>; /* SAI1_FS_A */
};
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-open-drain;
bias-disable;
};
};
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
};
};
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
pins {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
<STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
<STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>, /* SDMMC2_D7 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
<STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
<STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
pins2 {
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-open-drain;
bias-pull-up;
};
};
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
<STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC2_D7 */
<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
pins {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
spi5_pins_a: spi5-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
<STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
bias-disable;
};
};
spi5_sleep_pins_a: spi5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
<STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
<STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
};
};
stm32g0_intn_pins_a: stm32g0-intn-0 {
pins {
pinmux = <STM32_PINMUX('I', 2, GPIO)>;
bias-pull-up;
};
};
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_idle_pins_a: uart4-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_sleep_pins_a: uart4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
};
};
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
uart8_idle_pins_a: uart8-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
uart8_sleep_pins_a: uart8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
<STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
};
};
usart1_idle_pins_a: usart1-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
bias-pull-up;
};
};
usart1_sleep_pins_a: usart1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
<STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
<STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
<STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
bias-disable;
};
};
usart2_idle_pins_a: usart2-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
bias-disable;
};
};
usart2_sleep_pins_a: usart2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
};
m_can2_pins_a: m-can2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
bias-disable;
};
};
m_can2_sleep_pins_a: m_can2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
<STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
};
};
quadspi_pins_mx: quadspi_mx-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* QUADSPI_BK1_NCS */
<STM32_PINMUX('D', 7, AF11)>, /* QUADSPI_BK1_IO2 */
<STM32_PINMUX('D', 13, AF9)>, /* QUADSPI_BK1_IO3 */
<STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>; /* QUADSPI_BK1_IO1 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
quadspi_sleep_pins_mx: quadspi_sleep_mx-0 {
pins {
pinmux = <STM32_PINMUX('B', 2, ANALOG)>, /* QUADSPI_BK1_NCS */
<STM32_PINMUX('D', 7, ANALOG)>, /* QUADSPI_BK1_IO2 */
<STM32_PINMUX('D', 13, ANALOG)>, /* QUADSPI_BK1_IO3 */
<STM32_PINMUX('F', 8, ANALOG)>, /* QUADSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, ANALOG)>, /* QUADSPI_BK1_IO1 */
<STM32_PINMUX('F', 10, ANALOG)>; /* QUADSPI_CLK */
};
};
};

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@ -0,0 +1,644 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
<STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
};
};
dcmipp_pins_a: dcmi-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
<STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */
<STM32_PINMUX('B', 7, AF14)>,/* DCMI_PIXCLK */
<STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
<STM32_PINMUX('D', 0, AF13)>,/* DCMI_D1 */
<STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */
<STM32_PINMUX('E', 4, AF13)>,/* DCMI_D3 */
<STM32_PINMUX('D', 11, AF14)>,/* DCMI_D4 */
<STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
<STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
<STM32_PINMUX('E', 14, AF13)>;/* DCMI_D7 */
bias-disable;
};
};
dcmipp_sleep_pins_a: dcmi-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
<STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */
<STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_PIXCLK */
<STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
<STM32_PINMUX('D', 0, ANALOG)>,/* DCMI_D1 */
<STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */
<STM32_PINMUX('E', 4, ANALOG)>,/* DCMI_D3 */
<STM32_PINMUX('D', 11, ANALOG)>,/* DCMI_D4 */
<STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
<STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
<STM32_PINMUX('E', 14, ANALOG)>;/* DCMI_D7 */
};
};
dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 {
pins {
pinmux = <STM32_PINMUX('C', 3, AF3)>; /* DFSDM_CKOUT */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 {
pins {
pinmux = <STM32_PINMUX('C', 3, ANALOG)>; /* DFSDM_CKOUT */
};
};
dfsdm_datin1_pins_a: dfsdm-datin1-pins-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, AF6)>; /* DFSDM_DATIN1 */
};
};
dfsdm_datin1_sleep_pins_a: dfsdm-datin1-sleep-pins-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* DFSDM_DATIN1 */
};
};
dfsdm_datin3_pins_a: dfsdm-datin3-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 13, AF6)>; /* DFSDM_DATIN3 */
};
};
dfsdm_datin3_sleep_pins_a: dfsdm-datin3-sleep-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 13, ANALOG)>; /* DFSDM_DATIN3 */
};
};
eth1_rmii_pins_a: eth1-rmii-1 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */
<STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */
bias-disable;
};
};
eth1_rmii_sleep_pins_a: eth1-rmii-sleep-1 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */
<STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */
};
};
eth2_rmii_pins_a: eth2-rmii-2 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */
<STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */
<STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */
bias-disable;
};
};
eth2_rmii_sleep_pins_a: eth2-rmii-sleep-2 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */
<STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */
<STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */
};
};
goodix_pins_a: goodix-0 {
pins {
pinmux = <STM32_PINMUX('F', 5, GPIO)>;
bias-pull-down;
};
};
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
<STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c1_sleep_pins_a: i2c1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
<STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
};
};
i2c5_pins_a: i2c5-0 {
pins {
pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
<STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c5_sleep_pins_a: i2c5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
<STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
};
};
ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
<STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */
<STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */
<STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */
<STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */
<STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */
<STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */
<STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */
<STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */
<STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
<STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */
<STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */
<STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */
<STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */
<STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */
<STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */
<STM32_PINMUX('F', 2, AF14)>, /* LCD_B3 */
<STM32_PINMUX('H', 14, AF11)>, /* LCD_B4 */
<STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */
<STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */
<STM32_PINMUX('F', 1, AF13)>; /* LCD_B7 */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
ltdc_sleep_pins_a: ltdc-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
<STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */
<STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */
<STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */
<STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */
<STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */
<STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */
<STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */
<STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */
<STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */
<STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
<STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */
<STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */
<STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */
<STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */
<STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */
<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */
<STM32_PINMUX('F', 2, ANALOG)>, /* LCD_B3 */
<STM32_PINMUX('H', 14, ANALOG)>, /* LCD_B4 */
<STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */
<STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */
<STM32_PINMUX('F', 1, ANALOG)>; /* LCD_B7 */
};
};
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, GPIO)>;
bias-pull-up;
};
};
m_can2_pins_a: m-can2-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 1, AF9)>; /* CAN2_TX */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('G', 3, AF9)>; /* CAN2_RX */
bias-disable;
};
};
m_can2_sleep_pins_a: m_can2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('G', 1, ANALOG)>, /* CAN2_TX */
<STM32_PINMUX('G', 3, ANALOG)>; /* CAN2_RX */
};
};
pwm3_pins_a: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm3_sleep_pins_a: pwm3-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
};
};
pwm4_pins_a: pwm4-0 {
pins {
pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm4_sleep_pins_a: pwm4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
};
};
pwm8_pins_a: pwm8-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm8_sleep_pins_a: pwm8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
};
};
pwm14_pins_a: pwm12-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm14_sleep_pins_a: pwm12-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
};
};
rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
pins {
pinmux = <STM32_PINMUX('I', 1, ANALOG)>; /* RTC_OUT2_RMP */
};
};
sai1_pins_a: sai1-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
<STM32_PINMUX('A', 0, AF6)>, /* SAI1_SD_B */
<STM32_PINMUX('A', 5, AF6)>, /* SAI1_SD_A */
<STM32_PINMUX('F', 11, AF6)>; /* SAI1_FS_A */
slew-rate = <0>;
drive-push-pull;
bias-disable;
};
};
sai1_sleep_pins_a: sai1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
<STM32_PINMUX('A', 0, ANALOG)>, /* SAI1_SD_B */
<STM32_PINMUX('A', 5, ANALOG)>, /* SAI1_SD_A */
<STM32_PINMUX('F', 11, ANALOG)>; /* SAI1_FS_A */
};
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-open-drain;
bias-disable;
};
};
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
};
};
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
pins {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
pins2 {
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-open-drain;
bias-pull-up;
};
};
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
};
};
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
pins {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
spi5_pins_a: spi5-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
<STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
bias-disable;
};
};
spi5_sleep_pins_a: spi5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
<STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
<STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
};
};
stm32g0_intn_pins_a: stm32g0-intn-0 {
pins {
pinmux = <STM32_PINMUX('I', 2, GPIO)>;
bias-pull-up;
};
};
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_idle_pins_a: uart4-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_sleep_pins_a: uart4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
};
};
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
uart8_idle_pins_a: uart8-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
uart8_sleep_pins_a: uart8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
<STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
};
};
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
<STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
bias-pull-up;
};
};
usart1_idle_pins_a: usart1-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
bias-pull-up;
};
};
usart1_sleep_pins_a: usart1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
<STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
<STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
<STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
bias-disable;
};
};
usart2_idle_pins_a: usart2-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
bias-disable;
};
};
usart2_sleep_pins_a: usart2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
};
};

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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2020
*/
/ {
aliases {
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
pinctrl0 = &pinctrl;
};
firmware {
optee {
u-boot,dm-pre-reloc;
};
};
/* need PSCI for sysreset during board_f */
psci {
u-boot,dm-pre-proper;
};
soc {
u-boot,dm-pre-reloc;
ddr: ddr@5a003000 {
u-boot,dm-pre-reloc;
compatible = "st,stm32mp13-ddr";
reg = <0x5A003000 0x550
0x5A004000 0x234>;
status = "okay";
};
};
};
&bsec {
u-boot,dm-pre-reloc;
};
&gpioa {
u-boot,dm-pre-reloc;
};
&gpiob {
u-boot,dm-pre-reloc;
};
&gpioc {
u-boot,dm-pre-reloc;
};
&gpiod {
u-boot,dm-pre-reloc;
};
&gpioe {
u-boot,dm-pre-reloc;
};
&gpiof {
u-boot,dm-pre-reloc;
};
&gpiog {
u-boot,dm-pre-reloc;
};
&gpioh {
u-boot,dm-pre-reloc;
};
&gpioi {
u-boot,dm-pre-reloc;
};
&iwdg2 {
u-boot,dm-pre-reloc;
};
/* pre-reloc probe = reserve video frame buffer in video_reserve() */
&ltdc {
u-boot,dm-pre-proper;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&rcc {
u-boot,dm-pre-reloc;
};
&scmi {
u-boot,dm-pre-reloc;
};
&scmi_clk {
u-boot,dm-pre-reloc;
};
&scmi_reset {
u-boot,dm-pre-reloc;
};
&scmi_shm {
u-boot,dm-pre-reloc;
};
&scmi_sram {
u-boot,dm-pre-reloc;
};
&syscfg {
u-boot,dm-pre-reloc;
};
&usbphyc {
/* stm32-usbphyc-clk = ck_usbo_48m is a source clock of RCC CCF */
u-boot,dm-pre-reloc;
};

1742
arch/arm/dts/stm32mp131.dtsi Normal file

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp131.dtsi"
/ {
soc {
adc_1: adc@48003000 {
compatible = "st,stm32mp13-adc-core";
reg = <0x48003000 0x400>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc ADC1>, <&rcc ADC1_K>;
clock-names = "bus", "adc";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
adc1: adc@0 {
compatible = "st,stm32mp13-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc_1>;
interrupts = <0>;
dmas = <&dmamux1 9 0x400 0x80000001>;
dma-names = "rx";
nvmem-cells = <&vrefint>;
nvmem-cell-names = "vrefint";
status = "disabled";
channel@18 {
reg = <18>;
label = "vrefint";
};
};
};
m_can1: can@4400e000 {
compatible = "bosch,m_can";
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
};
m_can2: can@4400f000 {
compatible = "bosch,m_can";
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
};
eth2: eth2@5800e000 {
compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
reg = <0x5800e000 0x2000>;
reg-names = "stmmaceth";
interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
"ethstp",
"eth-ck";
clocks = <&rcc ETH2MAC>,
<&rcc ETH2TX>,
<&rcc ETH2RX>,
<&rcc ETH2STP>,
<&rcc ETH2CK_K>;
st,syscon = <&syscfg 0x4 0xff000000>;
snps,mixed-burst;
snps,pbl = <2>;
snps,axi-config = <&stmmac_axi_config_2>;
snps,tso;
status = "disabled";
stmmac_axi_config_2: stmmac-axi-config {
snps,wr_osr_lmt = <0x7>;
snps,rd_osr_lmt = <0x7>;
snps,blen = <0 0 0 0 16 8 4>;
};
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/rtc/rtc-stm32.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
#include "stm32mp13-gateway-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32MP135F-DK Discovery Board";
compatible = "st,stm32mp135f-dk", "st,stm32mp135";
aliases {
ethernet0 = &eth1;
ethernet1 = &eth2;
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
serial3 = &usart2;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_mco1: clk-mco1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
/*
leds {
compatible = "gpio-leds";
led-blue {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
*/
v3v3_ao: v3v3_ao {
compatible = "regulator-fixed";
regulator-name = "v3v3_ao";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_usb: vdd_usb {
compatible = "regulator-fixed";
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&crc1 {
status = "okay";
};
&cryp {
status = "okay";
};
&dcmipp {
status = "disabled";
};
&dma1 {
sram = <&dma_pool>;
};
&dma2 {
sram = <&dma_pool>;
};
&dts {
status = "okay";
};
&i2c3 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c3_pins_test_b>;
pinctrl-1 = <&i2c3_sleep_pins_test_b>;
i2c-scl-rising-time-ns = <285>;
i2c-scl-falling-time-ns = <9>;
clock-frequency = <400000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&eth1 {
status = "okay";
pinctrl-0 = <&eth1_rgmii_pins_a>;
pinctrl-1 = <&eth1_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0_eth1>;
// st,ext-phyclk;
// st,eth-clk-sel;
st,phy-reset-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>;
mdio1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0_eth1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&eth2 {
status = "okay";
pinctrl-0 = <&eth2_rgmii_pins_a>;
pinctrl-1 = <&eth2_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0_eth2>;
// st,ext-phyclk;
// st,eth-clk-sel;
phy-supply = <&v3v3_ao>;
st,phy-reset-gpios = <&gpioh 5 GPIO_ACTIVE_HIGH>;
// reset-deassert-us = <1000>;
// reset-assert-us = <1000>;
mdio1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0_eth2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
};
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-1 = <&i2c1_sleep_pins_a>;
i2c-scl-rising-time-ns = <96>;
i2c-scl-falling-time-ns = <3>;
clock-frequency = <1000000>;
status = "disabled";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_pins_a>;
pinctrl-1 = <&i2c5_sleep_pins_a>;
i2c-scl-rising-time-ns = <170>;
i2c-scl-falling-time-ns = <5>;
clock-frequency = <400000>;
status = "disabled";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&ltdc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_a>;
pinctrl-1 = <&ltdc_sleep_pins_a>;
status = "disabled";
};
&rtc {
st,lsco = <RTC_OUT2_RMP>;
pinctrl-0 = <&rtc_out2_rmp_pins_a>;
pinctrl-names = "default";
status = "okay";
};
/* TF */
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3_ao>;
status = "okay";
};
/* eMMC */
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
non-removable;
no-sd;
no-sdio;
// st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3_ao>;
vqmmc-supply = <&v3v3_ao>;
// mmc-pwrseq = <&wifi_pwrseq>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
&spi5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi5_pins_a>;
pinctrl-1 = <&spi5_sleep_pins_a>;
status = "disabled";
};
&sram {
dma_pool: dma-sram@0 {
reg = <0x0 0x4000>;
pool;
};
};
&timers3 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm3_pins_a>;
pinctrl-1 = <&pwm3_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@2 {
status = "okay";
};
};
&timers4 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm4_pins_a>;
pinctrl-1 = <&pwm4_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@3 {
status = "okay";
};
};
&timers8 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm8_pins_a>;
pinctrl-1 = <&pwm8_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@7 {
status = "okay";
};
};
&timers14 {
status = "disabled";
pwm {
pinctrl-0 = <&pwm14_pins_a>;
pinctrl-1 = <&pwm14_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@13 {
status = "okay";
};
};
&uart4 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&uart8 {
pinctrl-names = "default", "sleep", "idle";
// pinctrl-0 = <&uart8_pins_a>;
// pinctrl-1 = <&uart8_sleep_pins_a>;
// pinctrl-2 = <&uart8_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
};
&usart1 {
pinctrl-names = "default", "sleep", "idle";
// pinctrl-0 = <&usart1_pins_a>;
// pinctrl-1 = <&usart1_sleep_pins_a>;
// pinctrl-2 = <&usart1_idle_pins_a>;
// uart-has-rtscts;
status = "disabled";
};
&usart2 {
pinctrl-names = "default", "sleep", "idle";
// pinctrl-0 = <&usart2_pins_a>;
// pinctrl-1 = <&usart2_sleep_pins_a>;
// pinctrl-2 = <&usart2_idle_pins_a>;
// uart-has-rtscts;
status = "disabled";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
u-boot,force-b-session-valid;
u-boot,force-vbus-detection;
dr_mode = "peripheral";
usb-role-switch;
role-switch-default-mode = "peripheral";
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};
&vdd_usb {
u-boot,dm-pre-reloc;
};
/*
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&quadspi_pins_mx>;
pinctrl-1 = <&quadspi_sleep_pins_mx>;
reg = <0x58003000 0x1000>,
<0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
flash0: MT29F2G01AB@0 {
compatible = "spi-nand";
reg = <0>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <64000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
*/

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp133.dtsi"
/ {
soc {
dcmipp: dcmipp@5a000000 {
compatible = "st,stm32mp13-dcmipp";
reg = <0x5a000000 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc DCMIPP_R>;
clocks = <&rcc DCMIPP_K>;
clock-names = "kclk";
status = "disabled";
};
ltdc: display-controller@5a001000 {
compatible = "st,stm32-ltdc";
reg = <0x5a001000 0x400>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LTDC_PX>;
clock-names = "lcd";
resets = <&scmi_reset RST_SCMI_LTDC>;
status = "disabled";
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
*/
#include "stm32mp13-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdmmc1;
usb0 = &usbotg_hs;
};
config {
//u-boot,boot-led = "led-blue";
//u-boot,error-led = "led-red";
u-boot,mmc-env-partition = "u-boot-env";
st,adc_usb_pd = <&adc1 6>, <&adc1 12>;
//st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
//st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
watchdog-gpios = <&gpiod 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
watchdog-wdi-gpios = <&gpiod 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
};
//leds {
// led-red {
// color = <LED_COLOR_ID_RED>;
// gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
// default-state = "off";
// };
//};
};
&adc_1 {
status = "okay";
};
&uart4 {
u-boot,dm-pre-reloc;
};
&uart4_pins_a {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp135-gwbase.dts"
/ {
model = "i2SOM STM32MP135 GW103 Board";
compatible = "stm32mp135-gw103", "st,stm32mp135";
aliases {
ethernet0 = &eth1;
ethernet1 = &eth2;
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
serial3 = &usart2;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
optee_framebuffer@dd000000 {
reg = <0xdd000000 0x1000000>;
no-map;
};
optee@de000000 {
reg = <0xde000000 0x2000000>;
no-map;
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
*/
#include "stm32mp13-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdmmc1;
usb0 = &usbotg_hs;
};
config {
u-boot,boot-led = "led-blue";
u-boot,error-led = "led-red";
u-boot,mmc-env-partition = "u-boot-env";
st,adc_usb_pd = <&adc1 6>, <&adc1 12>;
st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
leds {
led-red {
color = <LED_COLOR_ID_RED>;
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
};
&adc_1 {
status = "okay";
};
&panel_rgb {
compatible = "rocktech,rk043fn48h","simple-panel";
display-timings {
timing@0 {
clock-frequency = <10000000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <10>;
hback-porch = <10>;
hsync-len = <52>;
vfront-porch = <10>;
vback-porch = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
&uart4 {
u-boot,dm-pre-reloc;
};
&uart4_pins_a {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/rtc/rtc-stm32.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
#include "stm32mp13-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32MP135F-DK Discovery Board";
compatible = "st,stm32mp135f-dk", "st,stm32mp135";
aliases {
ethernet0 = &eth1;
ethernet1 = &eth2;
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
serial3 = &usart2;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_mco1: clk-mco1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
gpio-keys {
compatible = "gpio-keys";
user-pa13 {
label = "User-PA13";
linux,code = <BTN_1>;
gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
};
leds {
compatible = "gpio-leds";
led-blue {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
optee_framebuffer@dd000000 {
reg = <0xdd000000 0x1000000>;
no-map;
};
optee@de000000 {
reg = <0xde000000 0x2000000>;
no-map;
};
};
v3v3_ao: v3v3_ao {
compatible = "regulator-fixed";
regulator-name = "v3v3_ao";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
panel_backlight: panel-backlight {
compatible = "gpio-backlight";
gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
default-on;
default-brightness-level = <0>;
status = "okay";
};
panel_rgb: panel-rgb {
compatible = "rocktech,rk043fn48h", "panel-dpi";
enable-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
backlight = <&panel_backlight>;
power-supply = <&scmi_v3v3_sw>;
data-mapping = "bgr666";
status = "okay";
width-mm = <105>;
height-mm = <67>;
port {
panel_in_rgb: endpoint {
remote-endpoint = <&ltdc_out_rgb>;
};
};
panel-timing {
clock-frequency = <10000000>;
hactive = <480>;
vactive = <272>;
hsync-len = <52>;
hfront-porch = <10>;
hback-porch = <10>;
vsync-len = <10>;
vfront-porch = <10>;
vback-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&mcp23017 11 GPIO_ACTIVE_LOW>;
};
wake_up {
compatible = "gpio-keys";
status = "okay";
button {
label = "wake-up";
linux,code = <KEY_WAKEUP>;
interrupts-extended = <&optee 0>;
status = "okay";
};
};
};
&adc_1 {
pinctrl-names = "default";
pinctrl-0 = <&adc1_usb_cc_pins_a>;
vdda-supply = <&scmi_vdd_adc>;
vref-supply = <&scmi_vdd_adc>;
status = "okay";
adc1: adc@0 {
status = "okay";
/*
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12.
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
* 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
* Use arbitrary margin here (e.g. 5us).
*/
channel@6 {
reg = <6>;
st,min-sample-time-ns = <5000>;
};
channel@12 {
reg = <12>;
st,min-sample-time-ns = <5000>;
};
};
};
&crc1 {
status = "okay";
};
&cryp {
status = "okay";
};
&dcmipp {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcmipp_pins_a>;
pinctrl-1 = <&dcmipp_sleep_pins_a>;
port {
dcmipp_0: endpoint {
remote-endpoint = <&mipid02_2>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <0>;
pclk-max-frequency = <120000000>;
};
};
};
&dma1 {
sram = <&dma_pool>;
};
&dma2 {
sram = <&dma_pool>;
};
&dts {
status = "okay";
};
&eth1 {
status = "okay";
pinctrl-0 = <&eth1_rmii_pins_a>;
pinctrl-1 = <&eth1_rmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0_eth1>;
nvmem-cells = <&ethernet_mac1_address>;
nvmem-cell-names = "mac-address";
mdio1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0_eth1: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.c131";
reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
reg = <0>;
wakeup-source;
};
};
};
&eth2 {
status = "okay";
pinctrl-0 = <&eth2_rmii_pins_a>;
pinctrl-1 = <&eth2_rmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0_eth2>;
st,ext-phyclk;
phy-supply = <&scmi_v3v3_sw>;
nvmem-cells = <&ethernet_mac2_address>;
nvmem-cell-names = "mac-address";
mdio1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0_eth2: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.c131";
reset-gpios = <&mcp23017 10 GPIO_ACTIVE_LOW>;
reg = <0>;
};
};
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-1 = <&i2c1_sleep_pins_a>;
i2c-scl-rising-time-ns = <96>;
i2c-scl-falling-time-ns = <3>;
clock-frequency = <1000000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
mcp23017: pinctrl@21 {
compatible = "microchip,mcp23017";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpiog>;
pinctrl-names = "default";
pinctrl-0 = <&mcp23017_pins_a>;
interrupt-controller;
#interrupt-cells = <2>;
microchip,irq-mirror;
};
stm32g0@53 {
compatible = "st,stm32g0-typec";
reg = <0x53>;
/* Alert pin on PI2 (PWR wakeup pin), managed by optee */
interrupts-extended = <&optee 1>;
firmware-name = "stm32g0-ucsi.mp135f-dk.fw";
wakeup-source;
connector {
compatible = "usb-c-connector";
label = "USB-C";
port {
con_usb_c_g0_ep: endpoint {
remote-endpoint = <&usbotg_hs_ep>;
};
};
};
};
};
&i2c5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_pins_a>;
pinctrl-1 = <&i2c5_sleep_pins_a>;
i2c-scl-rising-time-ns = <170>;
i2c-scl-falling-time-ns = <5>;
clock-frequency = <400000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
gc2145: gc2145@3c {
compatible = "galaxycore,gc2145";
reg = <0x3c>;
clocks = <&clk_ext_camera>;
IOVDD-supply = <&scmi_v3v3_sw>;
AVDD-supply = <&scmi_v3v3_sw>;
DVDD-supply = <&scmi_v3v3_sw>;
powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
status = "okay";
port {
gc2145_ep: endpoint {
remote-endpoint = <&mipid02_0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
goodix: goodix_ts@5d {
compatible = "goodix,gt911";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&goodix_pins_a>;
interrupt-parent = <&gpiof>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpioh 2 GPIO_ACTIVE_LOW>;
AVDD28-supply = <&scmi_v3v3_sw>;
VDDIO-supply = <&scmi_v3v3_sw>;
touchscreen-size-x = <480>;
touchscreen-size-y = <272>;
status = "okay";
};
ov5640: camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ext_camera>;
clock-names = "xclk";
DOVDD-supply = <&scmi_v3v3_sw>;
status = "disabled";
powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
port {
ov5640_0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
stmipi: stmipi@14 {
compatible = "st,st-mipid02";
reg = <0x14>;
status = "okay";
clocks = <&clk_mco1>;
clock-names = "xclk";
VDDE-supply = <&scmi_v1v8_periph>;
VDDIN-supply = <&scmi_v1v8_periph>;
reset-gpios = <&mcp23017 2 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mipid02_0: endpoint {
data-lanes = <1 2>;
lane-polarities = <0 0 0>;
remote-endpoint = <&gc2145_ep>;
};
};
port@2 {
reg = <2>;
mipid02_2: endpoint {
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <0>;
remote-endpoint = <&dcmipp_0>;
};
};
};
};
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&ltdc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_a>;
pinctrl-1 = <&ltdc_sleep_pins_a>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_out_rgb: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_rgb>;
};
};
};
&rtc {
st,lsco = <RTC_OUT2_RMP>;
pinctrl-0 = <&rtc_out2_rmp_pins_a>;
pinctrl-names = "default";
status = "okay";
};
&scmi_regu {
scmi_vddcpu: voltd-vddcpu {
voltd-name = "vddcpu";
regulator-name = "vddcpu";
};
scmi_vdd: voltd-vdd {
voltd-name = "vdd";
regulator-name = "vdd";
};
scmi_vddcore: voltd-vddcore {
voltd-name = "vddcore";
regulator-name = "vddcore";
};
scmi_vdd_adc: voltd-vdd_adc {
voltd-name = "vdd_adc";
regulator-name = "vdd_adc";
};
scmi_vdd_usb: voltd-vdd_usb {
voltd-name = "vdd_usb";
regulator-name = "vdd_usb";
};
scmi_vdd_sd: voltd-vdd_sd {
voltd-name = "vdd_sd";
regulator-name = "vdd_sd";
};
scmi_v1v8_periph: voltd-v1v8_periph {
voltd-name = "v1v8_periph";
regulator-name = "v1v8_periph";
};
scmi_v3v3_sw: voltd-v3v3_sw {
voltd-name = "v3v3_sw";
regulator-name = "v3v3_sw";
};
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&scmi_vdd_sd>;
status = "okay";
};
/* Wifi */
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
non-removable;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3_ao>;
mmc-pwrseq = <&wifi_pwrseq>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&spi5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi5_pins_a>;
pinctrl-1 = <&spi5_sleep_pins_a>;
status = "disabled";
};
&sram {
dma_pool: dma-sram@0 {
reg = <0x0 0x4000>;
pool;
};
};
&timers3 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm3_pins_a>;
pinctrl-1 = <&pwm3_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@2 {
status = "okay";
};
};
&timers4 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm4_pins_a>;
pinctrl-1 = <&pwm4_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@3 {
status = "okay";
};
};
&timers8 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm8_pins_a>;
pinctrl-1 = <&pwm8_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@7 {
status = "okay";
};
};
&timers14 {
status = "disabled";
pwm {
pinctrl-0 = <&pwm14_pins_a>;
pinctrl-1 = <&pwm14_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@13 {
status = "okay";
};
};
&uart4 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&uart8 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart8_pins_a>;
pinctrl-1 = <&uart8_sleep_pins_a>;
pinctrl-2 = <&uart8_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
};
&usart1 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart1_pins_a>;
pinctrl-1 = <&usart1_sleep_pins_a>;
pinctrl-2 = <&usart1_idle_pins_a>;
uart-has-rtscts;
status = "disabled";
};
/* Bluetooth */
&usart2 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_sleep_pins_a>;
pinctrl-2 = <&usart2_idle_pins_a>;
uart-has-rtscts;
status = "okay";
bluetooth {
shutdown-gpios = <&mcp23017 13 GPIO_ACTIVE_HIGH>;
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
vbat-supply = <&v3v3_ao>;
vddio-supply = <&v3v3_ao>;
};
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
usb-role-switch;
status = "okay";
port {
usbotg_hs_ep: endpoint {
remote-endpoint = <&con_usb_c_g0_ep>;
};
};
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&scmi_vdd_usb>;
st,current-boost-microamp = <1000>;
st,decrease-hs-slew-rate;
st,tune-hs-dc-level = <2>;
st,enable-hs-rftime-reduction;
st,trim-hs-current = <11>;
st,trim-hs-impedance = <2>;
st,tune-squelch-level = <1>;
st,enable-hs-rx-gain-eq;
st,no-hs-ftime-ctrl;
st,no-lsfs-sc;
/*
* Hack to keep hub active if wakeup source is enabled
* otherwise the hub will wakeup the port0 as soon as the v3v3_sw is disabled
*/
connector {
compatible = "usb-a-connector";
vbus-supply = <&scmi_v3v3_sw>;
};
};
&usbphyc_port1 {
phy-supply = <&scmi_vdd_usb>;
st,current-boost-microamp = <1000>;
st,decrease-hs-slew-rate;
st,tune-hs-dc-level = <2>;
st,enable-hs-rftime-reduction;
st,trim-hs-current = <11>;
st,trim-hs-impedance = <2>;
st,tune-squelch-level = <1>;
st,enable-hs-rx-gain-eq;
st,no-hs-ftime-ctrl;
st,no-lsfs-sc;
};

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@ -0,0 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/

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@ -0,0 +1,21 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
soc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
dmas = <&mdma 28 0x0 0x400202 0x0 0x0 0x0>,
<&mdma 29 0x3 0x400808 0x0 0x0 0x0>;
dma-names = "in", "out";
status = "disabled";
};
};
};

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@ -0,0 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/

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@ -0,0 +1,21 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
soc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
dmas = <&mdma 28 0x0 0x400202 0x0 0x0 0x0>,
<&mdma 29 0x3 0x400808 0x0 0x0 0x0>;
dma-names = "in", "out";
status = "disabled";
};
};
};

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@ -4,10 +4,24 @@
*/
#include <linux/stringify.h>
#ifdef CONFIG_SPL
&ddr {
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
config-DDR_MEM_COMPATIBLE {
u-boot,dm-pre-reloc;
compatible = __stringify(st,DDR_MEM_COMPATIBLE);
st,mem-name = DDR_MEM_NAME;
@ -116,27 +130,10 @@
DDR_MR3
>;
#ifdef DDR_PHY_CAL_SKIP
st,phy-cal = <
DDR_DX0DLLCR
DDR_DX0DQTR
DDR_DX0DQSTR
DDR_DX1DLLCR
DDR_DX1DQTR
DDR_DX1DQSTR
DDR_DX2DLLCR
DDR_DX2DQTR
DDR_DX2DQSTR
DDR_DX3DLLCR
DDR_DX3DQTR
DDR_DX3DQSTR
>;
#endif
status = "okay";
};
};
#endif
#undef DDR_MEM_COMPATIBLE
#undef DDR_MEM_NAME
@ -224,18 +221,6 @@
#undef DDR_ODTCR
#undef DDR_ZQ0CR1
#undef DDR_DX0GCR
#undef DDR_DX0DLLCR
#undef DDR_DX0DQTR
#undef DDR_DX0DQSTR
#undef DDR_DX1GCR
#undef DDR_DX1DLLCR
#undef DDR_DX1DQTR
#undef DDR_DX1DQSTR
#undef DDR_DX2GCR
#undef DDR_DX2DLLCR
#undef DDR_DX2DQTR
#undef DDR_DX2DQSTR
#undef DDR_DX3GCR
#undef DDR_DX3DLLCR
#undef DDR_DX3DQTR
#undef DDR_DX3DQSTR

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@ -100,20 +100,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE80
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

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@ -100,20 +100,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

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@ -101,20 +101,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

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@ -101,20 +101,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

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@ -101,20 +101,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

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@ -100,20 +100,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

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@ -0,0 +1,524 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
*/
&pinctrl {
m4_adc1_in6_pins_a: m4-adc1-in6 {
pins {
pinmux = <STM32_PINMUX('F', 12, RSVD)>;
};
};
m4_adc12_ain_pins_a: m4-adc12-ain-0 {
pins {
pinmux = <STM32_PINMUX('C', 3, RSVD)>, /* ADC1 in13 */
<STM32_PINMUX('F', 12, RSVD)>, /* ADC1 in6 */
<STM32_PINMUX('F', 13, RSVD)>, /* ADC2 in2 */
<STM32_PINMUX('F', 14, RSVD)>; /* ADC2 in6 */
};
};
m4_adc12_usb_pwr_pins_a: m4-adc12-usb-pwr-pins-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, RSVD)>, /* ADC12 in18 */
<STM32_PINMUX('A', 5, RSVD)>; /* ADC12 in19 */
};
};
m4_cec_pins_a: m4-cec-0 {
pins {
pinmux = <STM32_PINMUX('A', 15, RSVD)>;
};
};
m4_cec_pins_b: m4-cec-1 {
pins {
pinmux = <STM32_PINMUX('B', 6, RSVD)>;
};
};
m4_dac_ch1_pins_a: m4-dac-ch1 {
pins {
pinmux = <STM32_PINMUX('A', 4, RSVD)>;
};
};
m4_dac_ch2_pins_a: m4-dac-ch2 {
pins {
pinmux = <STM32_PINMUX('A', 5, RSVD)>;
};
};
m4_dcmi_pins_a: m4-dcmi-0 {
pins {
pinmux = <STM32_PINMUX('H', 8, RSVD)>,/* DCMI_HSYNC */
<STM32_PINMUX('B', 7, RSVD)>,/* DCMI_VSYNC */
<STM32_PINMUX('A', 6, RSVD)>,/* DCMI_PIXCLK */
<STM32_PINMUX('H', 9, RSVD)>,/* DCMI_D0 */
<STM32_PINMUX('H', 10, RSVD)>,/* DCMI_D1 */
<STM32_PINMUX('H', 11, RSVD)>,/* DCMI_D2 */
<STM32_PINMUX('H', 12, RSVD)>,/* DCMI_D3 */
<STM32_PINMUX('H', 14, RSVD)>,/* DCMI_D4 */
<STM32_PINMUX('I', 4, RSVD)>,/* DCMI_D5 */
<STM32_PINMUX('B', 8, RSVD)>,/* DCMI_D6 */
<STM32_PINMUX('E', 6, RSVD)>,/* DCMI_D7 */
<STM32_PINMUX('I', 1, RSVD)>,/* DCMI_D8 */
<STM32_PINMUX('H', 7, RSVD)>,/* DCMI_D9 */
<STM32_PINMUX('I', 3, RSVD)>,/* DCMI_D10 */
<STM32_PINMUX('H', 15, RSVD)>;/* DCMI_D11 */
};
};
m4_dfsdm_clkout_pins_a: m4-dfsdm-clkout-pins-0 {
pins {
pinmux = <STM32_PINMUX('B', 13, RSVD)>; /* DFSDM_CKOUT */
};
};
m4_dfsdm_data1_pins_a: m4-dfsdm-data1-pins-0 {
pins {
pinmux = <STM32_PINMUX('C', 3, RSVD)>; /* DFSDM_DATA1 */
};
};
m4_dfsdm_data3_pins_a: m4-dfsdm-data3-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 13, RSVD)>; /* DFSDM_DATA3 */
};
};
m4_ethernet0_rgmii_pins_a: m4-ethernet0-rgmii-0 {
pins {
pinmux = <STM32_PINMUX('G', 5, RSVD)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, RSVD)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('G', 13, RSVD)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, RSVD)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, RSVD)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 2, RSVD)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, RSVD)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('C', 1, RSVD)>, /* ETH_MDC */
<STM32_PINMUX('A', 2, RSVD)>, /* ETH_MDIO */
<STM32_PINMUX('C', 4, RSVD)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, RSVD)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('B', 0, RSVD)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('B', 1, RSVD)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 1, RSVD)>, /* ETH_RGMII_RX_CLK */
<STM32_PINMUX('A', 7, RSVD)>; /* ETH_RGMII_RX_CTL */
};
};
m4_fmc_pins_a: m4-fmc-0 {
pins {
pinmux = <STM32_PINMUX('D', 4, RSVD)>, /* FMC_NOE */
<STM32_PINMUX('D', 5, RSVD)>, /* FMC_NWE */
<STM32_PINMUX('D', 11, RSVD)>, /* FMC_A16_FMC_CLE */
<STM32_PINMUX('D', 12, RSVD)>, /* FMC_A17_FMC_ALE */
<STM32_PINMUX('D', 14, RSVD)>, /* FMC_D0 */
<STM32_PINMUX('D', 15, RSVD)>, /* FMC_D1 */
<STM32_PINMUX('D', 0, RSVD)>, /* FMC_D2 */
<STM32_PINMUX('D', 1, RSVD)>, /* FMC_D3 */
<STM32_PINMUX('E', 7, RSVD)>, /* FMC_D4 */
<STM32_PINMUX('E', 8, RSVD)>, /* FMC_D5 */
<STM32_PINMUX('E', 9, RSVD)>, /* FMC_D6 */
<STM32_PINMUX('E', 10, RSVD)>, /* FMC_D7 */
<STM32_PINMUX('G', 9, RSVD)>, /* FMC_NE2_FMC_NCE */
<STM32_PINMUX('D', 6, RSVD)>; /* FMC_NWAIT */
};
};
m4_hdp0_pins_a: m4-hdp0-0 {
pins {
pinmux = <STM32_PINMUX('I', 12, RSVD)>; /* HDP0 */
};
};
m4_hdp6_pins_a: m4-hdp6-0 {
pins {
pinmux = <STM32_PINMUX('K', 5, RSVD)>; /* HDP6 */
};
};
m4_hdp7_pins_a: m4-hdp7-0 {
pins {
pinmux = <STM32_PINMUX('K', 6, RSVD)>; /* HDP7 */
};
};
m4_i2c1_pins_a: m4-i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, RSVD)>, /* I2C1_SCL */
<STM32_PINMUX('F', 15, RSVD)>; /* I2C1_SDA */
};
};
m4_i2c2_pins_a: m4-i2c2-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, RSVD)>, /* I2C2_SCL */
<STM32_PINMUX('H', 5, RSVD)>; /* I2C2_SDA */
};
};
m4_i2c5_pins_a: m4-i2c5-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* I2C5_SCL */
<STM32_PINMUX('A', 12, RSVD)>; /* I2C5_SDA */
};
};
m4_i2s2_pins_a: m4-i2s2-0 {
pins {
pinmux = <STM32_PINMUX('I', 3, RSVD)>, /* I2S2_SDO */
<STM32_PINMUX('B', 9, RSVD)>, /* I2S2_WS */
<STM32_PINMUX('A', 9, RSVD)>; /* I2S2_CK */
};
};
m4_ltdc_pins_a: m4-ltdc-a-0 {
pins {
pinmux = <STM32_PINMUX('G', 7, RSVD)>, /* LCD_CLK */
<STM32_PINMUX('I', 10, RSVD)>, /* LCD_HSYNC */
<STM32_PINMUX('I', 9, RSVD)>, /* LCD_VSYNC */
<STM32_PINMUX('F', 10, RSVD)>, /* LCD_DE */
<STM32_PINMUX('H', 2, RSVD)>, /* LCD_R0 */
<STM32_PINMUX('H', 3, RSVD)>, /* LCD_R1 */
<STM32_PINMUX('H', 8, RSVD)>, /* LCD_R2 */
<STM32_PINMUX('H', 9, RSVD)>, /* LCD_R3 */
<STM32_PINMUX('H', 10, RSVD)>, /* LCD_R4 */
<STM32_PINMUX('C', 0, RSVD)>, /* LCD_R5 */
<STM32_PINMUX('H', 12, RSVD)>, /* LCD_R6 */
<STM32_PINMUX('E', 15, RSVD)>, /* LCD_R7 */
<STM32_PINMUX('E', 5, RSVD)>, /* LCD_G0 */
<STM32_PINMUX('E', 6, RSVD)>, /* LCD_G1 */
<STM32_PINMUX('H', 13, RSVD)>, /* LCD_G2 */
<STM32_PINMUX('H', 14, RSVD)>, /* LCD_G3 */
<STM32_PINMUX('H', 15, RSVD)>, /* LCD_G4 */
<STM32_PINMUX('I', 0, RSVD)>, /* LCD_G5 */
<STM32_PINMUX('I', 1, RSVD)>, /* LCD_G6 */
<STM32_PINMUX('I', 2, RSVD)>, /* LCD_G7 */
<STM32_PINMUX('D', 9, RSVD)>, /* LCD_B0 */
<STM32_PINMUX('G', 12, RSVD)>, /* LCD_B1 */
<STM32_PINMUX('G', 10, RSVD)>, /* LCD_B2 */
<STM32_PINMUX('D', 10, RSVD)>, /* LCD_B3 */
<STM32_PINMUX('I', 4, RSVD)>, /* LCD_B4 */
<STM32_PINMUX('A', 3, RSVD)>, /* LCD_B5 */
<STM32_PINMUX('B', 8, RSVD)>, /* LCD_B6 */
<STM32_PINMUX('D', 8, RSVD)>; /* LCD_B7 */
};
};
m4_ltdc_pins_b: m4-ltdc-b-0 {
pins {
pinmux = <STM32_PINMUX('I', 14, RSVD)>, /* LCD_CLK */
<STM32_PINMUX('I', 12, RSVD)>, /* LCD_HSYNC */
<STM32_PINMUX('I', 13, RSVD)>, /* LCD_VSYNC */
<STM32_PINMUX('K', 7, RSVD)>, /* LCD_DE */
<STM32_PINMUX('I', 15, RSVD)>, /* LCD_R0 */
<STM32_PINMUX('J', 0, RSVD)>, /* LCD_R1 */
<STM32_PINMUX('J', 1, RSVD)>, /* LCD_R2 */
<STM32_PINMUX('J', 2, RSVD)>, /* LCD_R3 */
<STM32_PINMUX('J', 3, RSVD)>, /* LCD_R4 */
<STM32_PINMUX('J', 4, RSVD)>, /* LCD_R5 */
<STM32_PINMUX('J', 5, RSVD)>, /* LCD_R6 */
<STM32_PINMUX('J', 6, RSVD)>, /* LCD_R7 */
<STM32_PINMUX('J', 7, RSVD)>, /* LCD_G0 */
<STM32_PINMUX('J', 8, RSVD)>, /* LCD_G1 */
<STM32_PINMUX('J', 9, RSVD)>, /* LCD_G2 */
<STM32_PINMUX('J', 10, RSVD)>, /* LCD_G3 */
<STM32_PINMUX('J', 11, RSVD)>, /* LCD_G4 */
<STM32_PINMUX('K', 0, RSVD)>, /* LCD_G5 */
<STM32_PINMUX('K', 1, RSVD)>, /* LCD_G6 */
<STM32_PINMUX('K', 2, RSVD)>, /* LCD_G7 */
<STM32_PINMUX('J', 12, RSVD)>, /* LCD_B0 */
<STM32_PINMUX('J', 13, RSVD)>, /* LCD_B1 */
<STM32_PINMUX('J', 14, RSVD)>, /* LCD_B2 */
<STM32_PINMUX('J', 15, RSVD)>, /* LCD_B3 */
<STM32_PINMUX('K', 3, RSVD)>, /* LCD_B4 */
<STM32_PINMUX('K', 4, RSVD)>, /* LCD_B5 */
<STM32_PINMUX('K', 5, RSVD)>, /* LCD_B6 */
<STM32_PINMUX('K', 6, RSVD)>; /* LCD_B7 */
};
};
m4_m_can1_pins_a: m4-m-can1-0 {
pins {
pinmux = <STM32_PINMUX('H', 13, RSVD)>, /* CAN1_TX */
<STM32_PINMUX('I', 9, RSVD)>; /* CAN1_RX */
};
};
m4_pwm1_pins_a: m4-pwm1-0 {
pins {
pinmux = <STM32_PINMUX('E', 9, RSVD)>, /* TIM1_CH1 */
<STM32_PINMUX('E', 11, RSVD)>, /* TIM1_CH2 */
<STM32_PINMUX('E', 14, RSVD)>; /* TIM1_CH4 */
};
};
m4_pwm2_pins_a: m4-pwm2-0 {
pins {
pinmux = <STM32_PINMUX('A', 3, RSVD)>; /* TIM2_CH4 */
};
};
m4_pwm3_pins_a: m4-pwm3-0 {
pins {
pinmux = <STM32_PINMUX('C', 7, RSVD)>; /* TIM3_CH2 */
};
};
m4_pwm4_pins_a: m4-pwm4-0 {
pins {
pinmux = <STM32_PINMUX('D', 14, RSVD)>, /* TIM4_CH3 */
<STM32_PINMUX('D', 15, RSVD)>; /* TIM4_CH4 */
};
};
m4_pwm4_pins_b: m4-pwm4-1 {
pins {
pinmux = <STM32_PINMUX('D', 13, RSVD)>; /* TIM4_CH2 */
};
};
m4_pwm5_pins_a: m4-pwm5-0 {
pins {
pinmux = <STM32_PINMUX('H', 11, RSVD)>; /* TIM5_CH2 */
};
};
m4_pwm8_pins_a: m4-pwm8-0 {
pins {
pinmux = <STM32_PINMUX('I', 2, RSVD)>; /* TIM8_CH4 */
};
};
m4_pwm12_pins_a: m4-pwm12-0 {
pins {
pinmux = <STM32_PINMUX('H', 6, RSVD)>; /* TIM12_CH1 */
};
};
m4_qspi_bk1_pins_a: m4-qspi-bk1-0 {
pins {
pinmux = <STM32_PINMUX('F', 8, RSVD)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, RSVD)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, RSVD)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('F', 6, RSVD)>, /* QSPI_BK1_IO3 */
<STM32_PINMUX('B', 6, RSVD)>; /* QSPI_BK1_NCS */
};
};
m4_qspi_bk2_pins_a: m4-qspi-bk2-0 {
pins {
pinmux = <STM32_PINMUX('H', 2, RSVD)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, RSVD)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, RSVD)>, /* QSPI_BK2_IO2 */
<STM32_PINMUX('G', 7, RSVD)>, /* QSPI_BK2_IO3 */
<STM32_PINMUX('C', 0, RSVD)>; /* QSPI_BK2_NCS */
};
};
m4_qspi_clk_pins_a: m4-qspi-clk-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, RSVD)>; /* QSPI_CLK */
};
};
m4_rtc_out2_rmp_pins_a: m4-rtc-out2-rmp-pins-0 {
pins {
pinmux = <STM32_PINMUX('I', 8, RSVD)>; /* RTC_OUT2_RMP */
};
};
m4_sai2a_pins_a: m4-sai2a-0 {
pins {
pinmux = <STM32_PINMUX('I', 5, RSVD)>, /* SAI2_SCK_A */
<STM32_PINMUX('I', 6, RSVD)>, /* SAI2_SD_A */
<STM32_PINMUX('I', 7, RSVD)>, /* SAI2_FS_A */
<STM32_PINMUX('E', 0, RSVD)>; /* SAI2_MCLK_A */
};
};
m4_sai2b_pins_a: m4-sai2b-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SAI2_SCK_B */
<STM32_PINMUX('E', 13, RSVD)>, /* SAI2_FS_B */
<STM32_PINMUX('E', 14, RSVD)>, /* SAI2_MCLK_B */
<STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
};
};
m4_sai2b_pins_b: m4-sai2b-2 {
pins {
pinmux = <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
};
};
m4_sai4a_pins_a: m4-sai4a-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, RSVD)>; /* SAI4_SD_A */
};
};
m4_sdmmc1_b4_pins_a: m4-sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, RSVD)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, RSVD)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, RSVD)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, RSVD)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, RSVD)>, /* SDMMC1_CMD */
<STM32_PINMUX('C', 12, RSVD)>; /* SDMMC1_CK */
};
};
m4_sdmmc1_dir_pins_a: m4-sdmmc1-dir-0 {
pins {
pinmux = <STM32_PINMUX('F', 2, RSVD)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('C', 7, RSVD)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('B', 9, RSVD)>, /* SDMMC1_CDIR */
<STM32_PINMUX('E', 4, RSVD)>; /* SDMMC1_CKIN */
};
};
m4_sdmmc2_b4_pins_a: m4-sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
<STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
<STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
};
};
m4_sdmmc2_b4_pins_b: m4-sdmmc2-b4-1 {
pins {
pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
<STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
<STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
};
};
m4_sdmmc2_d47_pins_a: m4-sdmmc2-d47-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, RSVD)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, RSVD)>, /* SDMMC2_D5 */
<STM32_PINMUX('E', 5, RSVD)>, /* SDMMC2_D6 */
<STM32_PINMUX('D', 3, RSVD)>; /* SDMMC2_D7 */
};
};
m4_sdmmc3_b4_pins_a: m4-sdmmc3-b4-0 {
pins {
pinmux = <STM32_PINMUX('F', 0, RSVD)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 4, RSVD)>, /* SDMMC3_D1 */
<STM32_PINMUX('F', 5, RSVD)>, /* SDMMC3_D2 */
<STM32_PINMUX('D', 7, RSVD)>, /* SDMMC3_D3 */
<STM32_PINMUX('F', 1, RSVD)>, /* SDMMC3_CMD */
<STM32_PINMUX('G', 15, RSVD)>; /* SDMMC3_CK */
};
};
m4_spdifrx_pins_a: m4-spdifrx-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, RSVD)>; /* SPDIF_IN1 */
};
};
m4_spi4_pins_a: m4-spi4-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SPI4_SCK */
<STM32_PINMUX('E', 14, RSVD)>, /* SPI4_MOSI */
<STM32_PINMUX('E', 13, RSVD)>; /* SPI4_MISO */
};
};
m4_spi5_pins_a: m4-spi5-0 {
pins {
pinmux = <STM32_PINMUX('F', 7, RSVD)>, /* SPI5_SCK */
<STM32_PINMUX('F', 9, RSVD)>, /* SPI5_MOSI */
<STM32_PINMUX('F', 8, RSVD)>; /* SPI5_MISO */
};
};
m4_stusb1600_pins_a: m4-stusb1600-0 {
pins {
pinmux = <STM32_PINMUX('I', 11, RSVD)>;
};
};
m4_uart4_pins_a: m4-uart4-0 {
pins {
pinmux = <STM32_PINMUX('G', 11, RSVD)>, /* UART4_TX */
<STM32_PINMUX('B', 2, RSVD)>; /* UART4_RX */
};
};
m4_uart7_pins_a: m4-uart7-0 {
pins {
pinmux = <STM32_PINMUX('E', 8, RSVD)>, /* USART7_TX */
<STM32_PINMUX('E', 7, RSVD)>; /* USART7_RX */
};
};
m4_usart2_pins_a: m4-usart2-0 {
pins {
pinmux = <STM32_PINMUX('D', 5, RSVD)>, /* USART2_TX */
<STM32_PINMUX('D', 4, RSVD)>, /* USART2_RTS */
<STM32_PINMUX('D', 6, RSVD)>, /* USART2_RX */
<STM32_PINMUX('D', 3, RSVD)>; /* USART2_CTS_NSS */
};
};
m4_usart3_pins_a: m4-usart3-0 {
pins {
pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
<STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
<STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
<STM32_PINMUX('I', 10, RSVD)>; /* USART3_CTS_NSS */
};
};
m4_usart3_pins_b: m4-usart3-1 {
pins {
pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
<STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
<STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
<STM32_PINMUX('B', 13, RSVD)>; /* USART3_CTS_NSS */
};
};
m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* OTG_FS_DM */
<STM32_PINMUX('A', 12, RSVD)>; /* OTG_FS_DP */
};
};
m4_usbotg_hs_pins_a: m4-usbotg_hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, RSVD)>; /* OTG_ID */
};
};
};
&pinctrl_z {
m4_i2c4_pins_a: m4-i2c4-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, RSVD)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, RSVD)>; /* I2C4_SDA */
};
};
m4_spi1_pins_a: m4-spi1-0 {
pins {
pinmux = <STM32_PINMUX('Z', 0, RSVD)>, /* SPI1_SCK */
<STM32_PINMUX('Z', 2, RSVD)>, /* SPI1_MOSI */
<STM32_PINMUX('Z', 1, RSVD)>; /* SPI1_MISO */
};
};
};

View File

@ -0,0 +1,447 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
*/
&m4_rproc {
m4_system_resources {
#address-cells = <1>;
#size-cells = <0>;
m4_timers2: timer@40000000 {
compatible = "rproc-srm-dev";
reg = <0x40000000 0x400>;
clocks = <&rcc TIM2_K>;
clock-names = "int";
status = "disabled";
};
m4_timers3: timer@40001000 {
compatible = "rproc-srm-dev";
reg = <0x40001000 0x400>;
clocks = <&rcc TIM3_K>;
clock-names = "int";
status = "disabled";
};
m4_timers4: timer@40002000 {
compatible = "rproc-srm-dev";
reg = <0x40002000 0x400>;
clocks = <&rcc TIM4_K>;
clock-names = "int";
status = "disabled";
};
m4_timers5: timer@40003000 {
compatible = "rproc-srm-dev";
reg = <0x40003000 0x400>;
clocks = <&rcc TIM5_K>;
clock-names = "int";
status = "disabled";
};
m4_timers6: timer@40004000 {
compatible = "rproc-srm-dev";
reg = <0x40004000 0x400>;
clocks = <&rcc TIM6_K>;
clock-names = "int";
status = "disabled";
};
m4_timers7: timer@40005000 {
compatible = "rproc-srm-dev";
reg = <0x40005000 0x400>;
clocks = <&rcc TIM7_K>;
clock-names = "int";
status = "disabled";
};
m4_timers12: timer@40006000 {
compatible = "rproc-srm-dev";
reg = <0x40006000 0x400>;
clocks = <&rcc TIM12_K>;
clock-names = "int";
status = "disabled";
};
m4_timers13: timer@40007000 {
compatible = "rproc-srm-dev";
reg = <0x40007000 0x400>;
clocks = <&rcc TIM13_K>;
clock-names = "int";
status = "disabled";
};
m4_timers14: timer@40008000 {
compatible = "rproc-srm-dev";
reg = <0x40008000 0x400>;
clocks = <&rcc TIM14_K>;
clock-names = "int";
status = "disabled";
};
m4_lptimer1: timer@40009000 {
compatible = "rproc-srm-dev";
reg = <0x40009000 0x400>;
clocks = <&rcc LPTIM1_K>;
clock-names = "mux";
status = "disabled";
};
m4_spi2: spi@4000b000 {
compatible = "rproc-srm-dev";
reg = <0x4000b000 0x400>;
clocks = <&rcc SPI2_K>;
status = "disabled";
};
m4_i2s2: audio-controller@4000b000 {
compatible = "rproc-srm-dev";
reg = <0x4000b000 0x400>;
status = "disabled";
};
m4_spi3: spi@4000c000 {
compatible = "rproc-srm-dev";
reg = <0x4000c000 0x400>;
clocks = <&rcc SPI3_K>;
status = "disabled";
};
m4_i2s3: audio-controller@4000c000 {
compatible = "rproc-srm-dev";
reg = <0x4000c000 0x400>;
status = "disabled";
};
m4_spdifrx: audio-controller@4000d000 {
compatible = "rproc-srm-dev";
reg = <0x4000d000 0x400>;
clocks = <&rcc SPDIF_K>;
clock-names = "kclk";
status = "disabled";
};
m4_usart2: serial@4000e000 {
compatible = "rproc-srm-dev";
reg = <0x4000e000 0x400>;
interrupt-parent = <&exti>;
interrupts = <27 1>;
clocks = <&rcc USART2_K>;
status = "disabled";
};
m4_usart3: serial@4000f000 {
compatible = "rproc-srm-dev";
reg = <0x4000f000 0x400>;
interrupt-parent = <&exti>;
interrupts = <28 1>;
clocks = <&rcc USART3_K>;
status = "disabled";
};
m4_uart4: serial@40010000 {
compatible = "rproc-srm-dev";
reg = <0x40010000 0x400>;
interrupt-parent = <&exti>;
interrupts = <30 1>;
clocks = <&rcc UART4_K>;
status = "disabled";
};
m4_uart5: serial@40011000 {
compatible = "rproc-srm-dev";
reg = <0x40011000 0x400>;
interrupt-parent = <&exti>;
interrupts = <31 1>;
clocks = <&rcc UART5_K>;
status = "disabled";
};
m4_i2c1: i2c@40012000 {
compatible = "rproc-srm-dev";
reg = <0x40012000 0x400>;
interrupt-parent = <&exti>;
interrupts = <21 1>;
clocks = <&rcc I2C1_K>;
status = "disabled";
};
m4_i2c2: i2c@40013000 {
compatible = "rproc-srm-dev";
reg = <0x40013000 0x400>;
interrupt-parent = <&exti>;
interrupts = <22 1>;
clocks = <&rcc I2C2_K>;
status = "disabled";
};
m4_i2c3: i2c@40014000 {
compatible = "rproc-srm-dev";
reg = <0x40014000 0x400>;
interrupt-parent = <&exti>;
interrupts = <23 1>;
clocks = <&rcc I2C3_K>;
status = "disabled";
};
m4_i2c5: i2c@40015000 {
compatible = "rproc-srm-dev";
reg = <0x40015000 0x400>;
interrupt-parent = <&exti>;
interrupts = <25 1>;
clocks = <&rcc I2C5_K>;
status = "disabled";
};
m4_cec: cec@40016000 {
compatible = "rproc-srm-dev";
reg = <0x40016000 0x400>;
interrupt-parent = <&exti>;
interrupts = <69 1>;
clocks = <&rcc CEC_K>, <&rcc CEC>;
clock-names = "cec", "hdmi-cec";
status = "disabled";
};
m4_dac: dac@40017000 {
compatible = "rproc-srm-dev";
reg = <0x40017000 0x400>;
clocks = <&rcc DAC12>;
clock-names = "pclk";
status = "disabled";
};
m4_uart7: serial@40018000 {
compatible = "rproc-srm-dev";
reg = <0x40018000 0x400>;
interrupt-parent = <&exti>;
interrupts = <32 1>;
clocks = <&rcc UART7_K>;
status = "disabled";
};
m4_uart8: serial@40019000 {
compatible = "rproc-srm-dev";
reg = <0x40019000 0x400>;
interrupt-parent = <&exti>;
interrupts = <33 1>;
clocks = <&rcc UART8_K>;
status = "disabled";
};
m4_timers1: timer@44000000 {
compatible = "rproc-srm-dev";
reg = <0x44000000 0x400>;
clocks = <&rcc TIM1_K>;
clock-names = "int";
status = "disabled";
};
m4_timers8: timer@44001000 {
compatible = "rproc-srm-dev";
reg = <0x44001000 0x400>;
clocks = <&rcc TIM8_K>;
clock-names = "int";
status = "disabled";
};
m4_usart6: serial@44003000 {
compatible = "rproc-srm-dev";
reg = <0x44003000 0x400>;
interrupt-parent = <&exti>;
interrupts = <29 1>;
clocks = <&rcc USART6_K>;
status = "disabled";
};
m4_spi1: spi@44004000 {
compatible = "rproc-srm-dev";
reg = <0x44004000 0x400>;
clocks = <&rcc SPI1_K>;
status = "disabled";
};
m4_i2s1: audio-controller@44004000 {
compatible = "rproc-srm-dev";
reg = <0x44004000 0x400>;
status = "disabled";
};
m4_spi4: spi@44005000 {
compatible = "rproc-srm-dev";
reg = <0x44005000 0x400>;
clocks = <&rcc SPI4_K>;
status = "disabled";
};
m4_timers15: timer@44006000 {
compatible = "rproc-srm-dev";
reg = <0x44006000 0x400>;
clocks = <&rcc TIM15_K>;
clock-names = "int";
status = "disabled";
};
m4_timers16: timer@44007000 {
compatible = "rproc-srm-dev";
reg = <0x44007000 0x400>;
clocks = <&rcc TIM16_K>;
clock-names = "int";
status = "disabled";
};
m4_timers17: timer@44008000 {
compatible = "rproc-srm-dev";
reg = <0x44008000 0x400>;
clocks = <&rcc TIM17_K>;
clock-names = "int";
status = "disabled";
};
m4_spi5: spi@44009000 {
compatible = "rproc-srm-dev";
reg = <0x44009000 0x400>;
clocks = <&rcc SPI5_K>;
status = "disabled";
};
m4_sai1: sai@4400a000 {
compatible = "rproc-srm-dev";
reg = <0x4400a000 0x4>;
clocks = <&rcc SAI1_K>;
clock-names = "sai_ck";
status = "disabled";
};
m4_sai2: sai@4400b000 {
compatible = "rproc-srm-dev";
reg = <0x4400b000 0x4>;
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
status = "disabled";
};
m4_sai3: sai@4400c000 {
compatible = "rproc-srm-dev";
reg = <0x4400c000 0x4>;
clocks = <&rcc SAI3_K>;
clock-names = "sai_ck";
status = "disabled";
};
m4_dfsdm: dfsdm@4400d000 {
compatible = "rproc-srm-dev";
reg = <0x4400d000 0x800>;
clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
clock-names = "dfsdm", "audio";
status = "disabled";
};
m4_m_can1: can@4400e000 {
compatible = "rproc-srm-dev";
reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
status = "disabled";
};
m4_m_can2: can@4400f000 {
compatible = "rproc-srm-dev";
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
status = "disabled";
};
m4_dma1: dma@48000000 {
compatible = "rproc-srm-dev";
reg = <0x48000000 0x400>;
clocks = <&rcc DMA1>;
status = "disabled";
};
m4_dma2: dma@48001000 {
compatible = "rproc-srm-dev";
reg = <0x48001000 0x400>;
clocks = <&rcc DMA2>;
status = "disabled";
};
m4_dmamux1: dma-router@48002000 {
compatible = "rproc-srm-dev";
reg = <0x48002000 0x1c>;
clocks = <&rcc DMAMUX>;
status = "disabled";
};
m4_adc: adc@48003000 {
compatible = "rproc-srm-dev";
reg = <0x48003000 0x400>;
clocks = <&rcc ADC12>, <&rcc ADC12_K>;
clock-names = "bus", "adc";
status = "disabled";
};
m4_sdmmc3: sdmmc@48004000 {
compatible = "rproc-srm-dev";
reg = <0x48004000 0x400>, <0x48005000 0x400>;
clocks = <&rcc SDMMC3_K>;
status = "disabled";
};
m4_usbotg_hs: usb-otg@49000000 {
compatible = "rproc-srm-dev";
reg = <0x49000000 0x10000>;
clocks = <&rcc USBO_K>;
clock-names = "otg";
status = "disabled";
};
m4_hash2: hash@4c002000 {
compatible = "rproc-srm-dev";
reg = <0x4c002000 0x400>;
clocks = <&rcc HASH2>;
status = "disabled";
};
m4_rng2: rng@4c003000 {
compatible = "rproc-srm-dev";
reg = <0x4c003000 0x400>;
clocks = <&rcc RNG2_K>;
status = "disabled";
};
m4_crc2: crc@4c004000 {
compatible = "rproc-srm-dev";
reg = <0x4c004000 0x400>;
clocks = <&rcc CRC2>;
status = "disabled";
};
m4_cryp2: cryp@4c005000 {
compatible = "rproc-srm-dev";
reg = <0x4c005000 0x400>;
clocks = <&rcc CRYP2>;
status = "disabled";
};
m4_dcmi: dcmi@4c006000 {
compatible = "rproc-srm-dev";
reg = <0x4c006000 0x400>;
clocks = <&rcc DCMI>;
clock-names = "mclk";
status = "disabled";
};
m4_lptimer2: timer@50021000 {
compatible = "rproc-srm-dev";
reg = <0x50021000 0x400>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
status = "disabled";
};
m4_lptimer3: timer@50022000 {
compatible = "rproc-srm-dev";
reg = <0x50022000 0x400>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
status = "disabled";
};
m4_lptimer4: timer@50023000 {
compatible = "rproc-srm-dev";
reg = <0x50023000 0x400>;
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
status = "disabled";
};
m4_lptimer5: timer@50024000 {
compatible = "rproc-srm-dev";
reg = <0x50024000 0x400>;
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
status = "disabled";
};
m4_sai4: sai@50027000 {
compatible = "rproc-srm-dev";
reg = <0x50027000 0x4>;
clocks = <&rcc SAI4_K>;
clock-names = "sai_ck";
status = "disabled";
};
m4_fmc: memory-controller@58002000 {
compatible = "rproc-srm-dev";
reg = <0x5800200 0x1000>;
clocks = <&rcc FMC_K>;
status = "disabled";
};
m4_qspi: qspi@58003000 {
compatible = "rproc-srm-dev";
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
clocks = <&rcc QSPI_K>;
status = "disabled";
};
m4_ethernet0: ethernet@5800a000 {
compatible = "rproc-srm-dev";
reg = <0x5800a000 0x2000>;
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
"ethstp",
"syscfg-clk";
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
<&rcc ETHSTP>,
<&rcc SYSCFG>;
status = "disabled";
};
};
};

View File

@ -0,0 +1,152 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2020 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
/ {
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_csi: clk-csi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <4000000>;
};
};
cpus {
cpu0: cpu@0 {
clocks = <&rcc CK_MPU>;
};
cpu1: cpu@1 {
clocks = <&rcc CK_MPU>;
};
};
reboot {
compatible = "syscon-reboot";
regmap = <&rcc>;
offset = <0x404>;
mask = <0x1>;
};
soc {
m_can1: can@4400e000 {
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
};
m_can2: can@4400f000 {
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
};
cryp1: cryp@54001000 {
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
};
dsi: dsi@5a000000 {
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
};
};
ahb {
m4_rproc: m4@10000000 {
resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>;
m4_system_resources {
m4_m_can1: can@4400e000 {
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
};
m4_m_can2: can@4400f000 {
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
};
};
};
};
firmware {
/delete-node/ scmi;
};
/delete-node/ sram@2ffff000;
};
&bsec {
clocks = <&rcc BSEC>;
};
&gpioz {
clocks = <&rcc GPIOZ>;
};
&hash1 {
clocks = <&rcc HASH1>;
resets = <&rcc HASH1_R>;
};
&i2c4 {
clocks = <&rcc I2C4_K>;
resets = <&rcc I2C4_R>;
};
&i2c6 {
clocks = <&rcc I2C6_K>;
resets = <&rcc I2C6_R>;
};
&iwdg2 {
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
};
&mdma1 {
clocks = <&rcc MDMA>;
resets = <&rcc MDMA_R>;
};
&rcc {
compatible = "st,stm32mp1-rcc", "syscon";
clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>;
};
&rng1 {
clocks = <&rcc RNG1_K>;
resets = <&rcc RNG1_R>;
};
&rtc {
clocks = <&rcc RTCAPB>, <&rcc RTC>;
};
&spi6 {
clocks = <&rcc SPI6_K>;
resets = <&rcc SPI6_R>;
};
&usart1 {
clocks = <&rcc USART1_K>;
};

View File

@ -151,7 +151,46 @@
};
};
ethernet0_rgmii_pins_a: rgmii-0 {
dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 {
pins {
pinmux = <STM32_PINMUX('B', 13, AF3)>; /* DFSDM_CKOUT */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 {
pins {
pinmux = <STM32_PINMUX('B', 13, ANALOG)>; /* DFSDM_CKOUT */
};
};
dfsdm_data1_pins_a: dfsdm-data1-pins-0 {
pins {
pinmux = <STM32_PINMUX('C', 3, AF3)>; /* DFSDM_DATA1 */
};
};
dfsdm_data1_sleep_pins_a: dfsdm-data1-sleep-pins-0 {
pins {
pinmux = <STM32_PINMUX('C', 3, ANALOG)>; /* DFSDM_DATA1 */
};
};
dfsdm_data3_pins_a: dfsdm-data3-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 13, AF6)>; /* DFSDM_DATA3 */
};
};
dfsdm_data3_sleep_pins_a: dfsdm-data3-sleep-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 13, ANALOG)>; /* DFSDM_DATA3 */
};
};
ethernet0_rgmii_pins_a: ethernet0-rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
@ -182,7 +221,7 @@
};
};
ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
ethernet0_rgmii_sleep_pins_a: ethernet0-rgmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
@ -202,7 +241,7 @@
};
};
ethernet0_rgmii_pins_b: rgmii-1 {
ethernet0_rgmii_pins_b: ethernet0-rgmii-1 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
@ -233,7 +272,7 @@
};
};
ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
ethernet0_rgmii_sleep_pins_b: ethernet0-rgmii-sleep-1 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
@ -253,7 +292,7 @@
};
};
ethernet0_rgmii_pins_c: rgmii-2 {
ethernet0_rgmii_pins_c: ethernet0-rgmii-2 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
@ -284,7 +323,7 @@
};
};
ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
ethernet0_rgmii_sleep_pins_c: ethernet0-rgmii-sleep-2 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
@ -304,7 +343,7 @@
};
};
ethernet0_rmii_pins_a: rmii-0 {
ethernet0_rmii_pins_a: ethernet0-rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
@ -324,7 +363,7 @@
};
};
ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
ethernet0_rmii_sleep_pins_a: ethernet0-rmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
@ -437,6 +476,51 @@
};
};
hdp0_pins_a: hdp0-0 {
pins {
pinmux = <STM32_PINMUX('I', 12, AF2)>; /* HDP0 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
hdp0_pins_sleep_a: hdp0-sleep-0 {
pins {
pinmux = <STM32_PINMUX('I', 12, ANALOG)>; /* HDP0 */
};
};
hdp6_pins_a: hdp6-0 {
pins {
pinmux = <STM32_PINMUX('K', 5, AF2)>; /* HDP6 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
hdp6_pins_sleep_a: hdp6-sleep-0 {
pins {
pinmux = <STM32_PINMUX('K', 5, ANALOG)>; /* HDP6 */
};
};
hdp7_pins_a: hdp7-0 {
pins {
pinmux = <STM32_PINMUX('K', 6, AF2)>; /* HDP7 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
hdp7_pins_sleep_a: hdp7-sleep-0 {
pins {
pinmux = <STM32_PINMUX('K', 6, ANALOG)>; /* HDP7 */
};
};
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@ -861,7 +945,7 @@
};
};
m_can1_sleep_pins_a: m_can1-sleep-0 {
m_can1_sleep_pins_a: m-can1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
<STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
@ -881,7 +965,7 @@
};
};
m_can1_sleep_pins_b: m_can1-sleep-1 {
m_can1_sleep_pins_b: m-can1-sleep-1 {
pins {
pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
<STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
@ -901,7 +985,7 @@
};
};
m_can2_sleep_pins_a: m_can2-sleep-0 {
m_can2_sleep_pins_a: m-can2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
<STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
@ -1068,6 +1152,48 @@
};
};
qspi_bk1_pins_a: qspi-bk1-0 {
pins {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
};
qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */
};
};
qspi_bk2_pins_a: qspi-bk2-0 {
pins {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
};
qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
<STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */
};
};
qspi_clk_pins_a: qspi-clk-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
@ -1083,17 +1209,8 @@
};
};
qspi_bk1_pins_a: qspi-bk1-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
qspi_cs1_pins_a: qspi-cs1-0 {
pins {
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
bias-pull-up;
drive-push-pull;
@ -1101,27 +1218,14 @@
};
};
qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
<STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
};
};
qspi_bk2_pins_a: qspi-bk2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
qspi_cs2_pins_a: qspi-cs2-0 {
pins {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up;
drive-push-pull;
@ -1129,13 +1233,15 @@
};
};
qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
<STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
<STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
};
};
rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
pins {
pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */
};
};
@ -1179,7 +1285,7 @@
};
};
sai2a_pins_c: sai2a-4 {
sai2a_pins_c: sai2a-2 {
pins {
pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
<STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
@ -1190,7 +1296,7 @@
};
};
sai2a_sleep_pins_c: sai2a-5 {
sai2a_sleep_pins_c: sai2a-sleep-2 {
pins {
pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
<STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
@ -1235,14 +1341,14 @@
};
};
sai2b_pins_c: sai2a-4 {
sai2b_pins_c: sai2b-2 {
pins1 {
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-disable;
};
};
sai2b_sleep_pins_c: sai2a-sleep-5 {
sai2b_sleep_pins_c: sai2b-sleep-2 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
};
@ -1282,6 +1388,18 @@
};
};
sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@ -1306,18 +1424,6 @@
};
};
sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
@ -1716,9 +1822,55 @@
};
};
spi4_pins_b: spi4-1 {
pins1 {
pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
<STM32_PINMUX('E', 14, AF5)>; /* SPI4_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
bias-disable;
};
};
spi4_sleep_pins_b: spi4-sleep-1 {
pins {
pinmux = <STM32_PINMUX('E', 12, ANALOG)>, /* SPI4_SCK */
<STM32_PINMUX('E', 13, ANALOG)>, /* SPI4_MISO */
<STM32_PINMUX('E', 14, ANALOG)>; /* SPI4_MOSI */
};
};
spi5_pins_a: spi5-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
<STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
bias-disable;
};
};
spi5_sleep_pins_a: spi5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* SPI5_SCK */
<STM32_PINMUX('F', 8, ANALOG)>, /* SPI5_MISO */
<STM32_PINMUX('F', 9, ANALOG)>; /* SPI5_MOSI */
};
};
stusb1600_pins_a: stusb1600-0 {
pins {
pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
pinmux = <STM32_PINMUX('I', 11, GPIO)>;
bias-pull-up;
};
};
@ -1737,20 +1889,20 @@
};
uart4_idle_pins_a: uart4-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
pins1 {
pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_sleep_pins_a: uart4-sleep-0 {
pins {
pins {
pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
};
};
};
uart4_pins_b: uart4-1 {
@ -1816,7 +1968,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
bias-disable;
bias-pull-up;
};
};
@ -1826,7 +1978,7 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
bias-disable;
bias-pull-up;
};
};
@ -1850,7 +2002,7 @@
};
};
uart8_rtscts_pins_a: uart8rtscts-0 {
uart8_rtscts_pins_a: uart8-rtscts-0 {
pins {
pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */
<STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */
@ -1912,7 +2064,7 @@
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <3>;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@ -1930,7 +2082,7 @@
pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <3>;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
@ -2012,7 +2164,7 @@
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
bias-disable;
bias-pull-up;
};
};
@ -2029,7 +2181,7 @@
};
pins3 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
bias-pull-up;
};
};
@ -2042,18 +2194,18 @@
};
};
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
};
};
usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
<STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
};
};
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
};
};
};
&pinctrl_z {
@ -2120,4 +2272,12 @@
bias-disable;
};
};
spi1_sleep_pins_a: spi1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
<STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
<STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
};
};
};

View File

@ -21,8 +21,14 @@
pinctrl1 = &pinctrl_z;
};
clocks {
u-boot,dm-pre-reloc;
binman: binman {
multiple-images;
};
firmware {
optee {
u-boot,dm-pre-reloc;
};
};
/* need PSCI for sysreset during board_f */
@ -30,14 +36,6 @@
u-boot,dm-pre-proper;
};
reboot {
u-boot,dm-pre-reloc;
compatible = "syscon-reboot";
regmap = <&rcc>;
offset = <0x404>;
mask = <0x1>;
};
soc {
u-boot,dm-pre-reloc;
@ -49,20 +47,6 @@
reg = <0x5A003000 0x550
0x5A004000 0x234>;
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
status = "okay";
};
};
@ -72,36 +56,6 @@
u-boot,dm-pre-reloc;
};
&clk_csi {
u-boot,dm-pre-reloc;
};
&clk_hsi {
u-boot,dm-pre-reloc;
};
&clk_hse {
u-boot,dm-pre-reloc;
};
&clk_lsi {
u-boot,dm-pre-reloc;
};
&clk_lse {
u-boot,dm-pre-reloc;
};
&cpu0_opp_table {
u-boot,dm-spl;
opp-650000000 {
u-boot,dm-spl;
};
opp-800000000 {
u-boot,dm-spl;
};
};
&gpioa {
u-boot,dm-pre-reloc;
};
@ -159,13 +113,6 @@
u-boot,dm-pre-proper;
};
/* temp = waiting kernel update */
&m4_rproc {
resets = <&rcc MCU_R>,
<&rcc MCU_HOLD_BOOT_R>;
reset-names = "mcu_rst", "hold_boot";
};
&pinctrl {
u-boot,dm-pre-reloc;
};
@ -174,30 +121,34 @@
u-boot,dm-pre-reloc;
};
&pwr_regulators {
u-boot,dm-pre-reloc;
};
&rcc {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
};
&sdmmc1 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
#ifdef CONFIG_TFABOOT
&scmi {
u-boot,dm-pre-reloc;
};
&sdmmc2 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
&scmi_clk {
u-boot,dm-pre-reloc;
};
&sdmmc3 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
&scmi_reset {
u-boot,dm-pre-reloc;
};
&scmi_shm {
u-boot,dm-pre-reloc;
};
&scmi_sram {
u-boot,dm-pre-reloc;
};
#endif
&usart1 {
resets = <&rcc USART1_R>;
resets = <&scmi_reset RST_SCMI_USART1>;
};
&usart2 {
@ -228,3 +179,89 @@
resets = <&rcc UART8_R>;
};
#if defined(CONFIG_STM32MP15x_STM32IMAGE)
&binman {
u-boot-stm32 {
filename = "u-boot.stm32";
mkimage {
args = "-T stm32image -a 0xC0100000 -e 0xC0100000";
u-boot {
};
};
};
};
#endif
#if defined(CONFIG_SPL)
&binman {
spl-stm32 {
filename = "u-boot-spl.stm32";
mkimage {
args = "-T stm32image -a 0x2FFC2500 -e 0x2FFC2500";
u-boot-spl {
};
};
};
};
#endif
/* NO MORE USE SCMI SUPPORT for BASIC boot chain */
#ifndef CONFIG_TFABOOT
#include "stm32mp15-no-scmi.dtsi"
/ {
clocks {
u-boot,dm-pre-reloc;
clk_hse: clk-hse {
u-boot,dm-pre-reloc;
};
clk_hsi: clk-hsi {
u-boot,dm-pre-reloc;
};
clk_lse: clk-lse {
u-boot,dm-pre-reloc;
};
clk_lsi: clk-lsi {
u-boot,dm-pre-reloc;
};
clk_csi: clk-csi {
u-boot,dm-pre-reloc;
};
};
reboot {
u-boot,dm-pre-reloc;
};
};
&cpu0_opp_table {
u-boot,dm-spl;
opp-650000000 {
u-boot,dm-spl;
};
opp-800000000 {
u-boot,dm-spl;
};
};
/* only for vdd-supply in sysconf_init() */
&pwr_regulators {
u-boot,dm-pre-reloc;
};
&rcc {
#address-cells = <1>;
#size-cells = <0>;
};
&usart1 {
resets = <&rcc USART1_R>;
};
#endif /* CONFIG_TFABOOT */

File diff suppressed because it is too large Load Diff

View File

@ -10,9 +10,11 @@
cpus {
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
clock-frequency = <650000000>;
device_type = "cpu";
reg = <1>;
clocks = <&scmi_clk CK_SCMI_MPU>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
};
};
@ -22,6 +24,13 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";
@ -30,7 +39,7 @@
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
@ -43,7 +52,7 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";

View File

@ -20,7 +20,8 @@
dsi: dsi@5a000000 {
compatible = "st,stm32-dsi";
reg = <0x5a000000 0x800>;
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
phy-dsi-supply = <&reg18>;
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
clock-names = "pclk", "ref", "px_clk";
resets = <&rcc DSI_R>;
reset-names = "apb";

View File

@ -1,8 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
/* This is kept for backward compatibility and will be removed */
#include "stm32mp15xx-dhcor-avenger96.dts"

View File

@ -0,0 +1,38 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*
* DHCOR STM32MP1 variant:
* DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG
* DHCOR PCB number: 586-100 or newer
* Avenger96 PCB number: 588-200 or newer
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcor-som.dtsi"
#include "stm32mp15xx-dhcor-avenger96.dtsi"
/ {
model = "Arrow Electronics STM32MP157A Avenger96 board";
compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som",
"st,stm32mp157";
};
&m_can1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can1_pins_b>;
pinctrl-1 = <&m_can1_sleep_pins_b>;
status = "disabled";
};
&m_can2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can2_pins_a>;
pinctrl-1 = <&m_can2_sleep_pins_a>;
status = "disabled";
};

View File

@ -15,7 +15,7 @@
config {
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
u-boot,mmc-env-partition = "fip";
u-boot,mmc-env-partition = "u-boot-env";
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
@ -27,28 +27,16 @@
};
#endif
#ifdef CONFIG_STM32MP15x_STM32IMAGE
/* only needed for boot with TF-A, witout FIP support */
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
reserved-memory {
u-boot,dm-spl;
optee@de000000 {
reg = <0xde000000 0x02000000>;
no-map;
u-boot,dm-spl;
};
};
#endif
led {
red {
led-red {
label = "error";
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
default-state = "off";
@ -61,6 +49,7 @@
status = "okay";
};
#ifndef CONFIG_TFABOOT
&clk_hse {
st,digbypass;
};
@ -76,6 +65,10 @@
};
};
&i2s2 {
clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
};
&pmic {
u-boot,dm-pre-reloc;
};
@ -172,6 +165,10 @@
};
};
&sai2 {
clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
};
&sdmmc1 {
u-boot,dm-spl;
};
@ -185,6 +182,7 @@
u-boot,dm-spl;
};
};
#endif
&uart4 {
u-boot,dm-pre-reloc;
@ -202,6 +200,3 @@
};
};
&usbotg_hs {
u-boot,force-b-session-valid;
};

View File

@ -7,6 +7,7 @@
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xa.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15xx-dkx.dtsi"
@ -15,13 +16,6 @@
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};

View File

@ -0,0 +1,211 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2018
*/
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-u-boot.dtsi"
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
/ {
aliases {
i2c3 = &i2c4;
};
config {
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
u-boot,mmc-env-partition = "u-boot-env";
st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
led {
led-red {
label = "error";
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
default-state = "off";
status = "okay";
};
};
#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
config {
u-boot,mmc-env-partition = "ssbl";
};
#endif
};
#ifndef CONFIG_TFABOOT
&clk_hse {
st,digbypass;
};
&i2c4 {
u-boot,dm-pre-reloc;
};
&i2c4_pins_a {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
};
};
&pmic {
u-boot,dm-pre-reloc;
};
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_LSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};
&sdmmc1 {
u-boot,dm-spl;
};
&sdmmc1_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc1_dir_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2 {
u-boot,dm-spl;
};
&sdmmc2_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2_d47_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
#endif
&uart4 {
u-boot,dm-pre-reloc;
};
&uart4_pins_a {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
/* pull-up on rx to avoid floating level */
bias-pull-up;
};
};

View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xa.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
#include "stm32mp15xx-edx.dtsi"
/ {
model = "STMicroelectronics STM32MP157A eval daughter";
compatible = "st,stm32mp157a-ed1", "st,stm32mp157";
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
gpu_reserved: gpu@f6000000 {
reg = <0xf6000000 0x8000000>;
no-map;
};
};
};
&gpu {
contiguous-area = <&gpu_reserved>;
};

View File

@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2018
*/
#include "stm32mp157c-ed1-u-boot.dtsi"
/ {
aliases {
gpio26 = &stmfx_pinctrl;
i2c1 = &i2c2;
i2c4 = &i2c5;
pinctrl2 = &stmfx_pinctrl;
spi0 = &qspi;
usb0 = &usbotg_hs;
};
};
#ifndef CONFIG_TFABOOT
&flash0 {
u-boot,dm-spl;
};
&qspi {
u-boot,dm-spl;
};
&qspi_clk_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&qspi_bk1_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&qspi_bk2_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sai2 {
clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
};
&sai4 {
clocks = <&rcc SAI4>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
};
#endif

View File

@ -0,0 +1,103 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157a-ed1.dts"
#include "stm32mp15xx-evx.dtsi"
/ {
model = "STMicroelectronics STM32MP157A eval daughter on eval mother";
compatible = "st,stm32mp157a-ev1", "st,stm32mp157a-ed1", "st,stm32mp157";
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
aliases {
ethernet0 = &ethernet0;
};
panel_backlight: panel-backlight {
compatible = "gpio-backlight";
gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
default-on;
status = "okay";
};
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ltdc_ep0_out>;
};
};
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&dsi_panel_in>;
};
};
};
panel_dsi: panel-dsi@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
backlight = <&panel_backlight>;
power-supply = <&v3v3>;
status = "okay";
port {
dsi_panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
&i2c2 {
gt9147: goodix_ts@5d {
compatible = "goodix,gt9147";
reg = <0x5d>;
panel = <&panel_dsi>;
pinctrl-0 = <&goodix_pins>;
pinctrl-names = "default";
status = "okay";
interrupts = <14 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&stmfx_pinctrl>;
};
};
&ltdc {
status = "okay";
port {
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&dsi_in>;
};
};
};

View File

@ -53,6 +53,7 @@
u-boot,dm-pre-reloc;
};
#ifndef CONFIG_TFABOOT
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
@ -144,3 +145,4 @@
u-boot,dm-pre-reloc;
};
};
#endif

View File

@ -25,6 +25,7 @@
u-boot,dm-pre-reloc;
};
#ifndef CONFIG_TFABOOT
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
@ -116,3 +117,4 @@
u-boot,dm-pre-reloc;
};
};
#endif

View File

@ -0,0 +1,202 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2018
*/
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-u-boot.dtsi"
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
/ {
aliases {
i2c3 = &i2c4;
usb0 = &usbotg_hs;
};
config {
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
u-boot,mmc-env-partition = "u-boot-env";
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
config {
u-boot,mmc-env-partition = "ssbl";
};
#endif
reserved-memory {
u-boot,dm-spl;
optee@de000000 {
u-boot,dm-spl;
};
};
led {
led-red {
label = "error";
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
default-state = "off";
status = "okay";
};
};
};
&adc {
status = "okay";
};
#ifndef CONFIG_TFABOOT
&clk_hse {
st,digbypass;
};
&i2c4 {
u-boot,dm-pre-reloc;
};
&i2c4_pins_a {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
};
};
&i2s2 {
clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
};
&pmic {
u-boot,dm-pre-reloc;
};
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_LSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};
&sai2 {
clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
};
&sdmmc1 {
u-boot,dm-spl;
};
&sdmmc1_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
#endif
&uart4 {
u-boot,dm-pre-reloc;
};
&uart4_pins_a {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
/* pull-up on rx to avoid floating level */
bias-pull-up;
};
};

View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xa.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15xx-panguboard.dtsi"
/ {
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
chosen {
stdout-path = "serial0:115200n8";
};
};

View File

@ -11,21 +11,32 @@
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15xx-dkx.dtsi"
#include <dt-bindings/rtc/rtc-stm32.h>
/ {
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
serial3 = &usart2;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
};
};
@ -35,7 +46,6 @@
&dsi {
status = "okay";
phy-dsi-supply = <&reg18>;
ports {
port@0 {
@ -53,7 +63,7 @@
};
};
panel@0 {
panel_otm8009a: panel-otm8009a@0 {
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
@ -77,6 +87,9 @@
interrupt-controller;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
panel = <&panel_otm8009a>;
vcc-supply = <&v3v3>;
iovcc-supply = <&v3v3>;
status = "okay";
};
};
@ -92,10 +105,47 @@
};
};
&rtc {
st,lsco = <RTC_OUT2_RMP>;
pinctrl-0 = <&rtc_out2_rmp_pins_a>;
pinctrl-names = "default";
};
/* Wifi */
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
non-removable;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* Bluetooth */
&usart2 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart2_pins_c>;
pinctrl-1 = <&usart2_sleep_pins_c>;
pinctrl-2 = <&usart2_idle_pins_c>;
status = "disabled";
uart-has-rtscts;
status = "okay";
bluetooth {
shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
vbat-supply = <&v3v3>;
vddio-supply = <&v3v3>;
};
};

View File

@ -3,224 +3,4 @@
* Copyright : STMicroelectronics 2018
*/
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-u-boot.dtsi"
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
/ {
aliases {
i2c3 = &i2c4;
};
config {
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
u-boot,mmc-env-partition = "fip";
st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
config {
u-boot,mmc-env-partition = "ssbl";
};
#endif
#ifdef CONFIG_STM32MP15x_STM32IMAGE
/* only needed for boot with TF-A, witout FIP support */
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
reserved-memory {
optee@fe000000 {
reg = <0xfe000000 0x02000000>;
no-map;
};
};
#endif
led {
red {
label = "error";
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
default-state = "off";
status = "okay";
};
};
};
&clk_hse {
st,digbypass;
};
&i2c4 {
u-boot,dm-pre-reloc;
};
&i2c4_pins_a {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
};
};
&pmic {
u-boot,dm-pre-reloc;
};
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_LSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};
&sdmmc1 {
u-boot,dm-spl;
};
&sdmmc1_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc1_dir_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2 {
u-boot,dm-spl;
};
&sdmmc2_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2_d47_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&uart4 {
u-boot,dm-pre-reloc;
};
&uart4_pins_a {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
/* pull-up on rx to avoid floating level */
bias-pull-up;
};
};
#include "stm32mp157a-ed1-u-boot.dtsi"

View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
@ -9,8 +9,7 @@
#include "stm32mp15xc.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
#include "stm32mp15xx-edx.dtsi"
/ {
model = "STMicroelectronics STM32MP157C eval daughter";
@ -20,389 +19,18 @@
stdout-path = "serial0:115200n8";
};
memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
mcuram2: mcuram2@10000000 {
compatible = "shared-dma-pool";
reg = <0x10000000 0x40000>;
no-map;
};
vdev0vring0: vdev0vring0@10040000 {
compatible = "shared-dma-pool";
reg = <0x10040000 0x1000>;
no-map;
};
vdev0vring1: vdev0vring1@10041000 {
compatible = "shared-dma-pool";
reg = <0x10041000 0x1000>;
no-map;
};
vdev0buffer: vdev0buffer@10042000 {
compatible = "shared-dma-pool";
reg = <0x10042000 0x4000>;
no-map;
};
mcuram: mcuram@30000000 {
compatible = "shared-dma-pool";
reg = <0x30000000 0x40000>;
no-map;
};
retram: retram@38000000 {
compatible = "shared-dma-pool";
reg = <0x38000000 0x10000>;
no-map;
};
gpu_reserved: gpu@e8000000 {
reg = <0xe8000000 0x8000000>;
gpu_reserved: gpu@f6000000 {
reg = <0xf6000000 0x8000000>;
no-map;
};
};
aliases {
serial0 = &uart4;
};
sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";
regulator-name = "sd_switch";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-type = "voltage";
regulator-always-on;
gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1>,
<2900000 0x0>;
};
vin: vin {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&adc {
/* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
pinctrl-0 = <&adc1_in6_pins_a>;
pinctrl-names = "default";
vdd-supply = <&vdd>;
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "disabled";
adc1: adc@0 {
st,adc-channels = <0 1 6>;
/* 16.5 ck_cycles sampling time */
st,min-sample-time-nsecs = <400>;
status = "okay";
};
};
&cpu0{
cpu-supply = <&vddcore>;
};
&cpu1{
cpu-supply = <&vddcore>;
};
&crc1 {
status = "okay";
};
&cryp1 {
status = "okay";
};
&dac {
pinctrl-names = "default";
pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
vref-supply = <&vdda>;
status = "disabled";
dac1: dac@1 {
status = "okay";
};
dac2: dac@2 {
status = "okay";
};
};
&dts {
status = "okay";
};
&gpu {
contiguous-area = <&gpu_reserved>;
};
&hash1 {
status = "okay";
};
&i2c4 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_pins_a>;
pinctrl-1 = <&i2c4_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
clock-frequency = <400000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
regulators {
compatible = "st,stpmic1-regulators";
buck1-supply = <&vin>;
buck2-supply = <&vin>;
buck3-supply = <&vin>;
buck4-supply = <&vin>;
ldo1-supply = <&v3v3>;
ldo2-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo4-supply = <&vin>;
ldo5-supply = <&v3v3>;
ldo6-supply = <&v3v3>;
vref_ddr-supply = <&vin>;
boost-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd_ddr: buck2 {
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask-reset;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
v3v3: buck4 {
regulator-name = "v3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
regulator-initial-mode = <0>;
};
vdda: ldo1 {
regulator-name = "vdda";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO1 0>;
};
v2v8: ldo2 {
regulator-name = "v2v8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
interrupts = <IT_CURLIM_LDO2 0>;
};
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
interrupts = <IT_CURLIM_LDO4 0>;
};
vdd_sd: ldo5 {
regulator-name = "vdd_sd";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO5 0>;
regulator-boot-on;
};
v1v8: ldo6 {
regulator-name = "v1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO6 0>;
};
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
};
bst_out: boost {
regulator-name = "bst_out";
interrupts = <IT_OCP_BOOST 0>;
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge = <1>;
};
};
onkey {
compatible = "st,stpmic1-onkey";
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
interrupt-names = "onkey-falling", "onkey-rising";
power-off-time-sec = <10>;
status = "okay";
};
watchdog {
compatible = "st,stpmic1-wdt";
status = "disabled";
};
};
};
&ipcc {
status = "okay";
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";
};
&pwr_regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&rng1 {
status = "okay";
};
&rtc {
status = "okay";
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,sig-dir;
st,neg-edge;
st,use-ckin;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&sd_switch>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-ddr50;
status = "okay";
};
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
non-removable;
no-sd;
no-sdio;
st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&vdd>;
mmc-ddr-3_3v;
status = "okay";
};
&timers6 {
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
timer@5 {
status = "okay";
};
};
&uart4 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
status = "okay";
};
&usbotg_hs {
vbus-supply = <&vbus_otg>;
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

View File

@ -3,51 +3,4 @@
* Copyright : STMicroelectronics 2018
*/
#include "stm32mp157c-ed1-u-boot.dtsi"
/ {
aliases {
gpio26 = &stmfx_pinctrl;
i2c1 = &i2c2;
i2c4 = &i2c5;
pinctrl2 = &stmfx_pinctrl;
spi0 = &qspi;
usb0 = &usbotg_hs;
};
};
&flash0 {
u-boot,dm-spl;
};
&qspi {
u-boot,dm-spl;
};
&qspi_clk_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&qspi_bk1_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&qspi_bk2_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
#include "stm32mp157a-ev1-u-boot.dtsi"

View File

@ -1,69 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157c-ed1.dts"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "stm32mp15xx-evx.dtsi"
/ {
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart4;
serial1 = &usart3;
ethernet0 = &ethernet0;
};
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
joystick {
compatible = "gpio-keys";
pinctrl-0 = <&joystick_pins>;
pinctrl-names = "default";
button-0 {
label = "JoySel";
linux,code = <KEY_ENTER>;
interrupt-parent = <&stmfx_pinctrl>;
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
};
button-1 {
label = "JoyDown";
linux,code = <KEY_DOWN>;
interrupt-parent = <&stmfx_pinctrl>;
interrupts = <1 IRQ_TYPE_EDGE_RISING>;
};
button-2 {
label = "JoyLeft";
linux,code = <KEY_LEFT>;
interrupt-parent = <&stmfx_pinctrl>;
interrupts = <2 IRQ_TYPE_EDGE_RISING>;
};
button-3 {
label = "JoyRight";
linux,code = <KEY_RIGHT>;
interrupt-parent = <&stmfx_pinctrl>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
};
button-4 {
label = "JoyUp";
linux,code = <KEY_UP>;
interrupt-parent = <&stmfx_pinctrl>;
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
@ -75,35 +33,15 @@
};
};
&cec {
pinctrl-names = "default";
pinctrl-0 = <&cec_pins_a>;
status = "okay";
};
&dcmi {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcmi_pins_a>;
pinctrl-1 = <&dcmi_sleep_pins_a>;
port {
dcmi_0: endpoint {
remote-endpoint = <&ov5640_0>;
bus-type = <5>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <1>;
};
};
};
&dsi {
phy-dsi-supply = <&reg18>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
@ -119,7 +57,7 @@
};
};
panel-dsi@0 {
panel_dsi: panel-dsi@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
@ -135,104 +73,18 @@
};
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&fmc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&fmc_pins_a>;
pinctrl-1 = <&fmc_sleep_pins_a>;
status = "okay";
nand-controller@4,0 {
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&i2c2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_pins_a>;
pinctrl-1 = <&i2c2_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
ov5640: camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ext_camera>;
clock-names = "xclk";
DOVDD-supply = <&v2v8>;
powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
rotation = <180>;
gt9147: goodix_ts@5d {
compatible = "goodix,gt9147";
reg = <0x5d>;
panel = <&panel_dsi>;
pinctrl-0 = <&goodix_pins>;
pinctrl-names = "default";
status = "okay";
port {
ov5640_0: endpoint {
remote-endpoint = <&dcmi_0>;
bus-width = <8>;
data-shift = <2>; /* lines 9:2 are used */
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <1>;
};
};
interrupts = <14 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&stmfx_pinctrl>;
};
stmfx: stmfx@42 {
compatible = "st,stmfx-0300";
reg = <0x42>;
interrupts = <8 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&gpioi>;
vdd-supply = <&v3v3>;
stmfx_pinctrl: pinctrl {
compatible = "st,stmfx-0300-pinctrl";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&stmfx_pinctrl 0 0 24>;
joystick_pins: joystick-pins {
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
bias-pull-down;
};
};
};
};
&i2c5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_pins_a>;
pinctrl-1 = <&i2c5_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
&ltdc {
@ -245,133 +97,3 @@
};
};
};
&m_can1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can1_pins_a>;
pinctrl-1 = <&m_can1_sleep_pins_a>;
status = "okay";
};
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: mx66l51235l@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
flash1: mx66l51235l@1 {
compatible = "jedec,spi-nor";
reg = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&sdmmc3 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc3_b4_pins_a>;
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
broken-cd;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
status = "disabled";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
status = "disabled";
};
&timers2 {
/* spare dmas for other usage (un-delete to enable pwm capture) */
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm2_pins_a>;
pinctrl-1 = <&pwm2_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@1 {
status = "okay";
};
};
&timers8 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm8_pins_a>;
pinctrl-1 = <&pwm8_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@7 {
status = "okay";
};
};
&timers12 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm12_pins_a>;
pinctrl-1 = <&pwm12_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@11 {
status = "okay";
};
};
&usart3 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart3_pins_b>;
pinctrl-1 = <&usart3_sleep_pins_b>;
pinctrl-2 = <&usart3_idle_pins_b>;
/*
* HW flow control USART3_RTS is optional, and isn't default wired to
* the connector. SB23 needs to be soldered in order to use it, and R77
* (ETH_CLK) should be removed.
*/
uart-has-rtscts;
status = "disabled";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
status = "okay";
};
&usbphyc {
status = "okay";
};

View File

@ -13,9 +13,11 @@
};
};
#ifndef CONFIG_TFABOOT
&clk_hse {
st,digbypass;
};
#endif
&i2c2 {
u-boot,dm-pre-reloc;
@ -32,6 +34,7 @@
u-boot,dm-pre-reloc;
};
#ifndef CONFIG_TFABOOT
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
@ -144,3 +147,4 @@
u-boot,dm-spl;
};
};
#endif

View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2019
*/
#include "stm32mp157a-dk1-u-boot.dtsi"

View File

@ -0,0 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xd.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15xx-dkx.dtsi"
/ {
model = "STMicroelectronics STM32MP157D-DK1 Discovery Board";
compatible = "st,stm32mp157d-dk1", "st,stm32mp157";
aliases {
ethernet0 = &ethernet0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};

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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2019
*/
#include "stm32mp157a-ed1-u-boot.dtsi"

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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xd.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
#include "stm32mp15xx-edx.dtsi"
/ {
model = "STMicroelectronics STM32MP157D eval daughter";
compatible = "st,stm32mp157d-ed1", "st,stm32mp157";
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
gpu_reserved: gpu@f6000000 {
reg = <0xf6000000 0x8000000>;
no-map;
};
};
};
&gpu {
contiguous-area = <&gpu_reserved>;
};

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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2019
*/
#include "stm32mp157a-ev1-u-boot.dtsi"

View File

@ -0,0 +1,103 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157d-ed1.dts"
#include "stm32mp15xx-evx.dtsi"
/ {
model = "STMicroelectronics STM32MP157D eval daughter on eval mother";
compatible = "st,stm32mp157d-ev1", "st,stm32mp157d-ed1", "st,stm32mp157";
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
aliases {
ethernet0 = &ethernet0;
};
panel_backlight: panel-backlight {
compatible = "gpio-backlight";
gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
default-on;
status = "okay";
};
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ltdc_ep0_out>;
};
};
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&dsi_panel_in>;
};
};
};
panel_dsi: panel-dsi@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
backlight = <&panel_backlight>;
power-supply = <&v3v3>;
status = "okay";
port {
dsi_panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
&i2c2 {
gt9147: goodix_ts@5d {
compatible = "goodix,gt9147";
reg = <0x5d>;
panel = <&panel_dsi>;
pinctrl-0 = <&goodix_pins>;
pinctrl-names = "default";
status = "okay";
interrupts = <14 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&stmfx_pinctrl>;
};
};
&ltdc {
status = "okay";
port {
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&dsi_in>;
};
};
};

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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2019
*/
#include "stm32mp157c-dk2-u-boot.dtsi"

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@ -0,0 +1,151 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xf.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15xx-dkx.dtsi"
#include <dt-bindings/rtc/rtc-stm32.h>
/ {
model = "STMicroelectronics STM32MP157F-DK2 Discovery Board";
compatible = "st,stm32mp157f-dk2", "st,stm32mp157";
aliases {
serial3 = &usart2;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
};
};
&cryp1 {
status = "okay";
};
&dsi {
status = "okay";
ports {
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ltdc_ep1_out>;
};
};
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
panel_otm8009a: panel-otm8009a@0 {
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
power-supply = <&v3v3>;
status = "okay";
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
&i2c1 {
touchscreen@38 {
compatible = "focaltech,ft6236";
reg = <0x38>;
interrupts = <2 2>;
interrupt-parent = <&gpiof>;
interrupt-controller;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
panel = <&panel_otm8009a>;
vcc-supply = <&v3v3>;
iovcc-supply = <&v3v3>;
status = "okay";
};
};
&ltdc {
status = "okay";
port {
ltdc_ep1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in>;
};
};
};
&rtc {
st,lsco = <RTC_OUT2_RMP>;
pinctrl-0 = <&rtc_out2_rmp_pins_a>;
pinctrl-names = "default";
};
/* Wifi */
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
non-removable;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* Bluetooth */
&usart2 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart2_pins_c>;
pinctrl-1 = <&usart2_sleep_pins_c>;
pinctrl-2 = <&usart2_idle_pins_c>;
uart-has-rtscts;
status = "okay";
bluetooth {
shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
vbat-supply = <&v3v3>;
vddio-supply = <&v3v3>;
};
};

View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2019
*/
#include "stm32mp157c-ed1-u-boot.dtsi"

View File

@ -0,0 +1,36 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xf.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
#include "stm32mp15xx-edx.dtsi"
/ {
model = "STMicroelectronics STM32MP157F eval daughter";
compatible = "st,stm32mp157f-ed1", "st,stm32mp157";
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
gpu_reserved: gpu@f6000000 {
reg = <0xf6000000 0x8000000>;
no-map;
};
};
};
&cryp1 {
status = "okay";
};
&gpu {
contiguous-area = <&gpu_reserved>;
};

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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2019
*/
#include "stm32mp157c-ev1-u-boot.dtsi"

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@ -0,0 +1,99 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157f-ed1.dts"
#include "stm32mp15xx-evx.dtsi"
/ {
model = "STMicroelectronics STM32MP157F eval daughter on eval mother";
compatible = "st,stm32mp157f-ev1", "st,stm32mp157f-ed1", "st,stm32mp157";
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
status = "disabled";
};
};
panel_backlight: panel-backlight {
compatible = "gpio-backlight";
gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
default-on;
status = "okay";
};
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ltdc_ep0_out>;
};
};
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&dsi_panel_in>;
};
};
};
panel_dsi: panel-dsi@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
backlight = <&panel_backlight>;
power-supply = <&v3v3>;
status = "okay";
port {
dsi_panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
&i2c2 {
gt9147: goodix_ts@5d {
compatible = "goodix,gt9147";
reg = <0x5d>;
panel = <&panel_dsi>;
pinctrl-0 = <&goodix_pins>;
pinctrl-names = "default";
status = "okay";
interrupts = <14 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&stmfx_pinctrl>;
};
};
&ltdc {
status = "okay";
port {
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&dsi_in>;
};
};
};

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@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
&cpu0_opp_table {
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-microvolt = <1200000>;
opp-supported-hw = <0x1>;
};
};

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@ -4,14 +4,19 @@
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
#include "stm32mp15xa.dtsi"
/ {
soc {
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
clocks = <&scmi_clk CK_SCMI_CRYP1>;
resets = <&scmi_reset RST_SCMI_CRYP1>;
dmas = <&mdma1 29 0x0 0x400202 0x0 0x0 0x0>,
<&mdma1 30 0x3 0x400808 0x0 0x0 0x0>;
dma-names = "in", "out";
status = "disabled";
};
};

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@ -0,0 +1,42 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
&cpu0_opp_table {
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1350000>;
opp-supported-hw = <0x2>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1200000>;
opp-supported-hw = <0x2>;
opp-suspend;
};
};
&cpu_thermal {
trips {
cpu-crit {
temperature = <105000>;
hysteresis = <0>;
type = "critical";
};
cpu_alert: cpu-alert {
temperature = <95000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device = <&cpu0 1 1>;
};
};
};

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@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
#include "stm32mp15xd.dtsi"
/ {
soc {
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_CRYP1>;
resets = <&scmi_reset RST_SCMI_CRYP1>;
dmas = <&mdma1 29 0x0 0x400202 0x0 0x0 0x0>,
<&mdma1 30 0x3 0x400808 0x0 0x0 0x0>;
dma-names = "in", "out";
status = "disabled";
};
};
};

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@ -2,166 +2,14 @@
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "stm32mp15xx-dhcom.dtsi"
#include "stm32mp151.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcom-som.dtsi"
#include "stm32mp15xx-dhcom-drc02.dtsi"
/ {
model = "DH Electronics STM32MP15xx DHCOM DRC02";
compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx";
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&adc {
status = "disabled";
};
&dac {
status = "disabled";
};
&gpiob {
/*
* NOTE: On DRC02, the RS485_RX_En is controlled by a separate
* GPIO line, however the STM32 UART driver assumes RX happens
* during TX anyway and that it only controls drive enable DE
* line. Hence, the RX is always enabled here.
*/
usb-hub {
gpio-hog;
gpios = <8 0>;
output-high;
line-name = "rs485-rx-en";
};
};
&gpiod {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "Out1",
"Out2", "", "", "";
};
&gpioi {
gpio-line-names = "In1", "", "", "",
"", "", "", "",
"In2", "", "", "",
"", "", "", "";
/*
* NOTE: The USB Hub on the DRC02 needs a reset signal to be
* pulled high in order to be detected by the USB Controller.
* This signal should be handled by USB power sequencing in
* order to reset the Hub when USB bus is powered down, but
* so far there is no such functionality.
*/
usb-hub {
gpio-hog;
gpios = <2 0>;
output-high;
line-name = "usb-hub-reset";
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c5 { /* TP7/TP8 */
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&sdmmc3 {
/*
* On DRC02, the SoM does not have SDIO WiFi. The pins
* are used for on-board microSD slot instead.
*/
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc3_b4_pins_a>;
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
cs-gpios = <&gpioz 3 0>;
/* Use PIO for the display */
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled"; /* Enable once there is display driver */
/*
* Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
* also connected to the display board connector.
*/
};
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
status = "okay";
};
/*
* Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
* however the STM32MP1 pinmux cannot map them to UART4 .
*/
&uart8 { /* RS485 */
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
};

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@ -0,0 +1,165 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&adc {
status = "disabled";
};
&dac {
status = "disabled";
};
&gpiob {
/*
* NOTE: On DRC02, the RS485_RX_En is controlled by a separate
* GPIO line, however the STM32 UART driver assumes RX happens
* during TX anyway and that it only controls drive enable DE
* line. Hence, the RX is always enabled here.
*/
rs485-rx-en-hog {
gpio-hog;
gpios = <8 0>;
output-low;
line-name = "rs485-rx-en";
};
};
&gpiod {
gpio-line-names = "", "", "", "",
"", "", "DHCOM-B", "",
"", "", "", "DRC02-Out1",
"DRC02-Out2", "", "", "";
};
&gpioi {
gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I",
"DHCOM-R", "DHCOM-M", "", "",
"DRC02-In2", "", "", "",
"", "", "", "";
/*
* NOTE: The USB Hub on the DRC02 needs a reset signal to be
* pulled high in order to be detected by the USB Controller.
* This signal should be handled by USB power sequencing in
* order to reset the Hub when USB bus is powered down, but
* so far there is no such functionality.
*/
usb-hub-hog {
gpio-hog;
gpios = <2 0>;
output-high;
line-name = "usb-hub-reset";
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c4 {
touchscreen@49 {
status = "disabled";
};
};
&i2c5 { /* TP7/TP8 */
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&sdmmc3 {
/*
* On DRC02, the SoM does not have SDIO WiFi. The pins
* are used for on-board microSD slot instead.
*/
/delete-property/broken-cd;
cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
disable-wp;
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
cs-gpios = <&gpioz 3 0>;
/* Use PIO for the display */
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled"; /* Enable once there is display driver */
/*
* Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
* also connected to the display board connector.
*/
};
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
status = "okay";
};
/*
* Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
* however the STM32MP1 pinmux cannot map them to UART4 .
*/
&uart8 { /* RS485 */
linux,rs485-enabled-at-boot-time;
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

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@ -4,3 +4,7 @@
*/
#include "stm32mp15xx-dhcom-u-boot.dtsi"
&usbotg_hs {
dr_mode = "peripheral";
};

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@ -2,18 +2,14 @@
/*
* Copyright (C) 2019 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "stm32mp15xx-dhcom.dtsi"
#include "stm32mp151.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcom-som.dtsi"
#include "stm32mp15xx-dhcom-pdk2.dtsi"
/ {
model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)";
compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x";
aliases {
serial0 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
};

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@ -0,0 +1,325 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
clk_ext_audio_codec: clock-codec {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
display_bl: display-bl {
compatible = "pwm-backlight";
pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
default-brightness-level = <8>;
enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_panel_bl>;
status = "okay";
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
poll-interval = <20>;
/*
* The EXTi IRQ line 3 is shared with ethernet,
* so mark this as polled GPIO key.
*/
button-0 {
label = "TA1-GPIO-A";
linux,code = <KEY_A>;
gpios = <&gpiof 3 GPIO_ACTIVE_LOW>;
};
/*
* The EXTi IRQ line 6 is shared with touchscreen,
* so mark this as polled GPIO key.
*/
button-1 {
label = "TA2-GPIO-B";
linux,code = <KEY_B>;
gpios = <&gpiod 6 GPIO_ACTIVE_LOW>;
};
/*
* The EXTi IRQ line 0 is shared with PMIC,
* so mark this as polled GPIO key.
*/
button-2 {
label = "TA3-GPIO-C";
linux,code = <KEY_C>;
gpios = <&gpiog 0 GPIO_ACTIVE_LOW>;
};
};
gpio-keys {
compatible = "gpio-keys";
button-3 {
label = "TA4-GPIO-D";
linux,code = <KEY_D>;
gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
led {
compatible = "gpio-leds";
led-0 {
label = "green:led5";
gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
status = "disabled";
};
led-1 {
label = "green:led6";
gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-2 {
label = "green:led7";
gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-3 {
label = "green:led8";
gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
panel {
compatible = "edt,etm0700g0edh6";
backlight = <&display_bl>;
power-supply = <&reg_panel_bl>;
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
reg_panel_bl: regulator-panel-bl {
compatible = "regulator-fixed";
regulator-name = "panel_backlight";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_panel_supply>;
};
reg_panel_supply: regulator-panel-supply {
compatible = "regulator-fixed";
regulator-name = "panel_supply";
regulator-min-microvolt = <24000000>;
regulator-max-microvolt = <24000000>;
};
sound {
compatible = "audio-graph-card";
routing =
"MIC_IN", "Capture",
"Capture", "Mic Bias",
"Playback", "HP_OUT";
dais = <&sai2a_port &sai2b_port>;
status = "okay";
};
};
&cec {
pinctrl-names = "default";
pinctrl-0 = <&cec_pins_a>;
status = "okay";
};
&i2c2 { /* Header X22 */
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&i2c5 { /* Header X21 */
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clk_ext_audio_codec>;
VDDA-supply = <&v3v3>;
VDDIO-supply = <&vdd>;
sgtl5000_port: port {
#address-cells = <1>;
#size-cells = <0>;
sgtl5000_tx_endpoint: endpoint@0 {
reg = <0>;
remote-endpoint = <&sai2a_endpoint>;
frame-master = <&sgtl5000_tx_endpoint>;
bitclock-master = <&sgtl5000_tx_endpoint>;
};
sgtl5000_rx_endpoint: endpoint@1 {
reg = <1>;
remote-endpoint = <&sai2b_endpoint>;
frame-master = <&sgtl5000_rx_endpoint>;
bitclock-master = <&sgtl5000_rx_endpoint>;
};
};
};
touchscreen@38 {
compatible = "edt,edt-ft5406";
reg = <0x38>;
interrupt-parent = <&gpioc>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
};
};
&ltdc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_b>;
pinctrl-1 = <&ltdc_sleep_pins_b>;
status = "okay";
port {
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
&sai2 {
clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "x8k", "x11k";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>;
pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>;
status = "okay";
sai2a: audio-controller@4400b004 {
#clock-cells = <0>;
dma-names = "tx";
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
status = "okay";
sai2a_port: port {
sai2a_endpoint: endpoint {
remote-endpoint = <&sgtl5000_tx_endpoint>;
format = "i2s";
mclk-fs = <512>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
};
};
sai2b: audio-controller@4400b024 {
dma-names = "rx";
st,sync = <&sai2a 2>;
clocks = <&rcc SAI2_K>, <&sai2a>;
clock-names = "sai_ck", "MCLK";
status = "okay";
sai2b_port: port {
sai2b_endpoint: endpoint {
remote-endpoint = <&sgtl5000_rx_endpoint>;
format = "i2s";
mclk-fs = <512>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
};
};
};
&timers2 {
/* spare dmas for other usage (un-delete to enable pwm capture) */
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
pwm2: pwm {
pinctrl-0 = <&pwm2_pins_a>;
pinctrl-names = "default";
status = "okay";
};
timer@1 {
status = "okay";
};
};
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
status = "okay";
};
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
uart-has-rtscts;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
dr_mode = "otg";
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
phy-names = "usb2-phy";
phys = <&usbphyc_port1 0>;
vbus-supply = <&vbus_otg>;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

View File

@ -11,4 +11,8 @@
};
};
/delete-node/ &ksz8851;
/delete-node/ &ks8851;
&usbotg_hs {
dr_mode = "peripheral";
};

View File

@ -2,92 +2,14 @@
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "stm32mp15xx-dhcom.dtsi"
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcom-som.dtsi"
#include "stm32mp15xx-dhcom-picoitx.dtsi"
/ {
model = "DH Electronics STM32MP15xx DHCOM PicoITX";
compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx";
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&adc {
status = "disabled";
};
&dac {
status = "disabled";
};
&gpioa {
/*
* NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable
* port power. This signal should be handled by USB power sequencing
* in order to turn on port power when USB bus is powered up, but so
* far there is no such functionality.
*/
usb-port-power {
gpio-hog;
gpios = <13 0>;
output-low;
line-name = "usb-port-power";
};
};
&i2c2 { /* On board-to-board connector (optional) */
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c5 { /* On board-to-board connector */
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
status = "okay";
};
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
};

View File

@ -0,0 +1,147 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
led {
compatible = "gpio-leds";
led-0 {
label = "yellow:led";
gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
};
&adc {
status = "disabled";
};
&dac {
status = "disabled";
};
&fmc {
status = "disabled";
};
&gpioa {
/*
* NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable
* port power. This signal should be handled by USB power sequencing
* in order to turn on port power when USB bus is powered up, but so
* far there is no such functionality.
*/
usb-port-power-hog {
gpio-hog;
gpios = <13 0>;
output-low;
line-name = "usb-port-power";
};
};
&gpioc {
gpio-line-names = "", "", "", "",
"", "", "PicoITX-In1", "",
"", "", "", "",
"", "", "", "";
};
&gpiod {
gpio-line-names = "", "", "", "",
"", "", "DHCOM-B", "",
"", "", "", "PicoITX-Out1",
"PicoITX-Out2", "", "", "";
};
&gpiog {
gpio-line-names = "PicoITX-In2", "", "", "",
"", "", "", "",
"DHCOM-L", "", "", "",
"", "", "", "";
};
&i2c2 { /* On board-to-board connector (optional) */
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c5 { /* On board-to-board connector */
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&ksz8851 {
status = "disabled";
};
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
status = "okay";
};
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbh_ohci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
dr_mode = "otg";
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
phy-names = "usb2-phy";
phys = <&usbphyc_port1 0>;
vbus-supply = <&vbus_otg>;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

View File

@ -1,11 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2019 Marek Vasut <marex@denx.de>
* Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
@ -13,8 +10,10 @@
/ {
aliases {
eeprom0 = &eeprom0;
ethernet0 = &ethernet0;
ethernet1 = &ksz8851;
rtc0 = &hwrtc;
rtc1 = &rtc;
};
memory@c0000000 {
@ -22,6 +21,48 @@
reg = <0xC0000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
mcuram2: mcuram2@10000000 {
compatible = "shared-dma-pool";
reg = <0x10000000 0x40000>;
no-map;
};
vdev0vring0: vdev0vring0@10040000 {
compatible = "shared-dma-pool";
reg = <0x10040000 0x1000>;
no-map;
};
vdev0vring1: vdev0vring1@10041000 {
compatible = "shared-dma-pool";
reg = <0x10041000 0x1000>;
no-map;
};
vdev0buffer: vdev0buffer@10042000 {
compatible = "shared-dma-pool";
reg = <0x10042000 0x4000>;
no-map;
};
mcuram: mcuram@30000000 {
compatible = "shared-dma-pool";
reg = <0x30000000 0x40000>;
no-map;
};
retram: retram@38000000 {
compatible = "shared-dma-pool";
reg = <0x38000000 0x10000>;
no-map;
};
};
ethernet_vio: vioregulator {
compatible = "regulator-fixed";
regulator-name = "vio";
@ -30,20 +71,49 @@
gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd>;
};
};
&cec {
pinctrl-names = "default";
pinctrl-0 = <&cec_pins_a>;
&adc {
vdd-supply = <&vdd>;
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
adc1: adc@0 {
status = "okay";
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
};
adc2: adc@100 {
status = "okay";
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
};
};
&crc1 {
status = "okay";
};
&dcmi {
&dac {
pinctrl-names = "default";
pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
vref-supply = <&vdda>;
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcmi_pins_a>;
pinctrl-1 = <&dcmi_sleep_pins_a>;
dac1: dac@1 {
status = "okay";
};
dac2: dac@2 {
status = "okay";
};
};
&dts {
@ -53,12 +123,12 @@
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rmii_pins_a>;
pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
st,eth-ref-clk-sel;
mdio0 {
#address-cells = <1>;
@ -67,16 +137,112 @@
phy0: ethernet-phy@1 {
reg = <1>;
/* LAN8710Ai */
compatible = "ethernet-phy-id0007.c0f0",
"ethernet-phy-ieee802.3-c22";
clocks = <&rcc ETHCK_K>;
reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
reset-assert-us = <500>;
reset-deassert-us = <500>;
smsc,disable-energy-detect;
interrupt-parent = <&gpioi>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
&fmc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&fmc_pins_b>;
pinctrl-1 = <&fmc_sleep_pins_b>;
status = "okay";
ksz8851: ethernet@1,0 {
compatible = "micrel,ks8851-mll";
reg = <1 0x0 0x2>, <1 0x2 0x20000>;
interrupt-parent = <&gpioc>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
bank-width = <2>;
/* Timing values are in nS */
st,fmc2-ebi-cs-mux-enable;
st,fmc2-ebi-cs-transaction-type = <4>;
st,fmc2-ebi-cs-buswidth = <16>;
st,fmc2-ebi-cs-address-setup-ns = <5>;
st,fmc2-ebi-cs-address-hold-ns = <5>;
st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
st,fmc2-ebi-cs-data-setup-ns = <45>;
st,fmc2-ebi-cs-data-hold-ns = <1>;
st,fmc2-ebi-cs-write-address-setup-ns = <5>;
st,fmc2-ebi-cs-write-address-hold-ns = <5>;
st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>;
st,fmc2-ebi-cs-write-data-setup-ns = <45>;
st,fmc2-ebi-cs-write-data-hold-ns = <1>;
};
};
&gpioa {
gpio-line-names = "", "", "", "",
"", "", "DHCOM-K", "",
"", "", "", "",
"", "", "", "";
};
&gpiob {
gpio-line-names = "", "", "", "",
"", "", "", "",
"DHCOM-Q", "", "", "",
"", "", "", "";
};
&gpioc {
gpio-line-names = "", "", "", "",
"", "", "DHCOM-E", "",
"", "", "", "",
"", "", "", "";
status = "okay";
};
&gpiod {
gpio-line-names = "", "", "", "",
"", "", "DHCOM-B", "",
"", "", "", "DHCOM-F",
"DHCOM-D", "", "", "";
};
&gpioe {
gpio-line-names = "", "", "", "",
"", "", "DHCOM-P", "",
"", "", "", "",
"", "", "", "";
};
&gpiof {
gpio-line-names = "", "", "", "DHCOM-A",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpiog {
gpio-line-names = "DHCOM-C", "", "", "",
"", "", "", "",
"DHCOM-L", "", "", "",
"", "", "", "";
};
&gpioh {
gpio-line-names = "", "", "", "",
"", "", "", "DHCOM-N",
"DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U",
"DHCOM-T", "", "DHCOM-S", "";
};
&gpioi {
gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I",
"DHCOM-R", "DHCOM-M", "", "",
"", "", "", "",
"", "", "", "";
};
&i2c4 {
@ -89,6 +255,11 @@
/delete-property/dmas;
/delete-property/dma-names;
hwrtc: rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
@ -146,6 +317,7 @@
vdda: ldo1 {
regulator-name = "vdda";
regulator-always-on;
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO1 0>;
@ -168,8 +340,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@ -191,24 +361,23 @@
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
regulator-over-current-protection;
};
bst_out: boost {
bst_out: boost {
regulator-name = "bst_out";
interrupts = <IT_OCP_BOOST 0>;
};
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
};
};
vbus_sw: pwr_sw2 {
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge;
};
regulator-active-discharge = <1>;
};
};
onkey {
@ -225,21 +394,20 @@
};
};
eeprom0: eeprom@50 {
touchscreen@49 {
compatible = "ti,tsc2004";
reg = <0x49>;
vio-supply = <&v3v3>;
interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
&ipcc {
status = "okay";
};
@ -250,8 +418,12 @@
};
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";
};
@ -260,42 +432,6 @@
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&pinctrl {
ethernet0_rmii_pins_a: rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
<STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
bias-disable;
};
};
ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
};
};
};
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
@ -305,7 +441,7 @@
#size-cells = <0>;
status = "okay";
flash0: mx66l51235l@0 {
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
@ -324,14 +460,19 @@
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-names = "default", "opendrain", "sleep", "init";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>;
cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,sig-dir;
st,neg-edge;
st,use-ckin;
st,cmd-gpios = <&gpiod 2 0>;
st,ck-gpios = <&gpioc 12 0>;
st,ckin-gpios = <&gpioe 4 0>;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
status = "okay";
@ -352,75 +493,33 @@
};
&sdmmc2 {
pinctrl-names = "default";
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
non-removable;
no-sd;
no-sdio;
st,sig-dir;
st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
status = "disabled";
};
&timers2 {
/* spare dmas for other usage (un-delete to enable pwm capture) */
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm2_pins_a>;
pinctrl-names = "default";
status = "okay";
};
timer@1 {
status = "okay";
};
};
&timers6 {
&sdmmc3 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc3_b4_pins_a>;
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
broken-cd;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
timer@5 {
status = "okay";
};
};
&timers8 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm8_pins_a>;
pinctrl-names = "default";
status = "okay";
};
timer@7 {
status = "okay";
};
};
&timers12 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm12_pins_a>;
pinctrl-names = "default";
status = "okay";
};
timer@11 {
status = "okay";
};
};
&uart4 {
@ -428,29 +527,3 @@
pinctrl-0 = <&uart4_pins_a>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
phy-names = "usb";
status = "okay";
};
&usbotg_hs {
dr_mode = "peripheral";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
vbus-supply = <&vbus_otg>;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

View File

@ -9,6 +9,8 @@
#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
/delete-node/ &ksz8851;
/ {
aliases {
i2c1 = &i2c2;
@ -18,7 +20,8 @@
mmc1 = &sdmmc2;
spi0 = &qspi;
usb0 = &usbotg_hs;
ethernet1 = &ksz8851;
eeprom0 = &eeprom0;
ethernet1 = &ks8851;
};
config {
@ -30,37 +33,34 @@
dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
};
led {
red {
label = "error";
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
default-state = "off";
status = "okay";
};
blue {
default-state = "on";
};
};
/* This is actually on FMC2, but we do not have bus driver for that */
ksz8851: ks8851mll@64000000 {
ks8851: ks8851mll@64000000 {
compatible = "micrel,ks8851-mll";
reg = <0x64000000 0x20000>;
};
};
&gpiof {
snor-nwp {
gpio-hog;
gpios = <7 0>;
output-high;
line-name = "spi-nor-nwp";
&ethernet0 {
phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
/delete-property/ st,eth-ref-clk-sel;
};
&ethernet0_rmii_pins_a {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
};
};
&i2c4 {
u-boot,dm-pre-reloc;
eeprom0: eeprom@50 {
};
};
&i2c4_pins_a {
@ -70,6 +70,10 @@
};
};
&phy0 {
/delete-property/ reset-gpios;
};
&pinctrl {
/* These should bound to FMC2 bus driver, but we do not have one */
pinctrl-0 = <&fmc_pins_b &mco2_pins_a>;
@ -131,6 +135,7 @@
};
};
#ifndef CONFIG_TFABOOT
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
@ -222,9 +227,14 @@
u-boot,dm-pre-reloc;
};
};
#endif
&sdmmc1 {
u-boot,dm-spl;
st,use-ckin;
st,cmd-gpios = <&gpiod 2 0>;
st,ck-gpios = <&gpioc 12 0>;
st,ckin-gpios = <&gpioe 4 0>;
};
&sdmmc1_b4_pins_a {

View File

@ -19,8 +19,25 @@
};
};
&ethernet0 {
phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
mdio0 {
ethernet-phy@7 {
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <1000>;
};
};
};
&sdmmc1 {
u-boot,dm-spl;
st,use-ckin;
st,cmd-gpios = <&gpiod 2 0>;
st,ck-gpios = <&gpioc 12 0>;
st,ckin-gpios = <&gpioe 4 0>;
};
&sdmmc1_b4_pins_a {

View File

@ -7,206 +7,12 @@
/dts-v1/;
#include "stm32mp15xx-dhcor-io1v8.dtsi"
#include "stm32mp15xx-dhcor-avenger96-u-boot.dtsi"
#include "stm32mp151.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcor-som.dtsi"
#include "stm32mp15xx-dhcor-avenger96.dtsi"
/ {
model = "Arrow Electronics STM32MP15xx Avenger96 board";
compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x";
aliases {
eeprom0 = &eeprom0;
ethernet0 = &ethernet0;
mmc0 = &sdmmc1;
serial0 = &uart4;
serial1 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
led {
compatible = "gpio-leds";
led1 {
label = "green:user0";
gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led2 {
label = "green:user1";
gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
default-state = "off";
};
led3 {
label = "green:user2";
gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
default-state = "off";
};
led4 {
label = "green:user3";
gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
panic-indicator;
};
led5 {
label = "yellow:wifi";
gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
led6 {
label = "blue:bt";
gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "bluetooth-power";
default-state = "off";
};
};
sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";
regulator-name = "sd_switch";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-type = "voltage";
regulator-always-on;
gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1>,
<2900000 0x0>;
};
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_c>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii";
max-speed = <1000>;
phy-handle = <&phy0>;
phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@7 {
reg = <7>;
};
};
};
&i2c1 { /* X6 I2C1 */
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_b>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c2 { /* X6 I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_c>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c4 {
eeprom0: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
disable-wp;
st,sig-dir;
st,neg-edge;
st,use-ckin;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&sd_switch>;
status = "okay";
};
&sdmmc2 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
non-removable;
no-sd;
no-sdio;
st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
};
&uart4 {
/* On Low speed expansion header */
label = "LS-UART1";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_b>;
status = "okay";
};
&uart7 {
/* On Low speed expansion header */
label = "LS-UART0";
pinctrl-names = "default";
pinctrl-0 = <&uart7_pins_a>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
phy-names = "usb";
status = "okay";
};
&usbotg_hs {
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

View File

@ -0,0 +1,451 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */
#include "stm32mp15xx-dhcor-io1v8.dtsi"
/ {
aliases {
ethernet0 = &ethernet0;
mmc0 = &sdmmc1;
serial0 = &uart4;
serial1 = &uart7;
serial2 = &usart2;
spi0 = &qspi;
};
/* XTal Q1 */
cec_clock: clk-cec-fixed {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7513_out>;
};
};
};
led {
compatible = "gpio-leds";
led1 {
label = "green:user0";
gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led2 {
label = "green:user1";
gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
default-state = "off";
};
led3 {
label = "green:user2";
gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
default-state = "off";
};
led4 {
label = "green:user3";
gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
panic-indicator;
};
};
sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";
regulator-name = "sd_switch";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-type = "voltage";
regulator-always-on;
gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1>,
<2900000 0x0>;
};
sound {
compatible = "audio-graph-card";
label = "STM32MP1-AV96-HDMI";
dais = <&sai2a_port>;
status = "okay";
};
wlan_pwr: regulator-wlan {
compatible = "regulator-fixed";
regulator-name = "wl-reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adc {
pinctrl-names = "default";
pinctrl-0 = <&adc12_ain_pins_b>;
vdd-supply = <&vdd>;
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
adc1: adc@0 {
status = "okay";
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
channel@6 {
reg = <6>;
st,min-sample-time-ns = <5000>;
};
};
adc2: adc@100 {
status = "okay";
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
channel@2 {
reg = <2>;
st,min-sample-time-ns = <5000>;
};
};
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_c>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii";
max-speed = <1000>;
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
phy0: ethernet-phy@7 {
reg = <7>;
rxc-skew-ps = <1500>;
rxdv-skew-ps = <540>;
rxd0-skew-ps = <420>;
rxd1-skew-ps = <420>;
rxd2-skew-ps = <420>;
rxd3-skew-ps = <420>;
txc-skew-ps = <1440>;
txen-skew-ps = <540>;
txd0-skew-ps = <420>;
txd1-skew-ps = <420>;
txd2-skew-ps = <420>;
txd3-skew-ps = <420>;
};
};
};
&gpioa {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "AV96-K",
"AV96-I", "", "AV96-A", "";
};
&gpiob {
gpio-line-names = "", "", "", "",
"", "AV96-J", "", "",
"", "", "", "AV96-B",
"", "AV96-L", "", "";
};
&gpioc {
gpio-line-names = "", "", "", "AV96-C",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpiod {
gpio-line-names = "", "", "", "",
"", "", "", "",
"AV96-D", "", "", "",
"", "", "AV96-E", "AV96-F";
};
&gpiof {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "",
"AV96-G", "AV96-H", "", "";
};
&i2c1 { /* X6 I2C1 */
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_b>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c2 { /* X6 I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_c>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c4 {
hdmi-transmitter@3d {
compatible = "adi,adv7513";
reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
reg-names = "main", "edid", "cec", "packet";
clocks = <&cec_clock>;
clock-names = "cec";
avdd-supply = <&v3v3>;
dvdd-supply = <&v3v3>;
pvdd-supply = <&v3v3>;
dvdd-3v-supply = <&v3v3>;
bgvdd-supply = <&v3v3>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpiog>;
status = "okay";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7513_in: endpoint {
remote-endpoint = <&ltdc_ep0_out>;
};
};
port@1 {
reg = <1>;
adv7513_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
port@2 {
reg = <2>;
adv7513_i2s0: endpoint {
remote-endpoint = <&sai2a_endpoint>;
};
};
};
};
};
&ltdc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_d>;
pinctrl-1 = <&ltdc_sleep_pins_d>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&adv7513_in>;
};
};
};
&sai2 {
clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sai2a_pins_c>;
pinctrl-1 = <&sai2a_sleep_pins_c>;
clock-names = "pclk", "x8k", "x11k";
status = "okay";
sai2a: audio-controller@4400b004 {
#clock-cells = <0>;
dma-names = "tx";
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
status = "okay";
sai2a_port: port {
sai2a_endpoint: endpoint {
remote-endpoint = <&adv7513_i2s0>;
format = "i2s";
mclk-fs = <256>;
};
};
};
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,sig-dir;
st,neg-edge;
st,use-ckin;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&sd_switch>;
status = "okay";
};
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
bus-width = <8>;
mmc-ddr-1_8v;
no-sd;
no-sdio;
non-removable;
st,neg-edge;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&vdd_io>;
status = "okay";
};
&sdmmc3 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc3_b4_pins_b>;
pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
broken-cd;
non-removable;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&wlan_pwr>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
cs-gpios = <&gpioi 0 0>;
status = "disabled";
/delete-property/dmas;
/delete-property/dma-names;
};
&uart4 {
/* On Low speed expansion header */
label = "LS-UART1";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_b>;
status = "okay";
};
&uart7 {
/* On Low speed expansion header */
label = "LS-UART0";
pinctrl-names = "default";
pinctrl-0 = <&uart7_pins_a>;
uart-has-rtscts;
status = "okay";
};
/* Bluetooth */
&usart2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_sleep_pins_a>;
st,hw-flow-ctrl;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
};
};
&usbh_ehci {
phys = <&usbphyc_port0>;
phy-names = "usb";
status = "okay";
};
&usbotg_hs {
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
phy-names = "usb2-phy";
phys = <&usbphyc_port1 0>;
status = "okay";
vbus-supply = <&vbus_otg>;
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

View File

@ -1,12 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
#include "stm32mp15xx-dhcor-io3v3.dtsi"
/ {
/* Enpirion EP3A8LQI U2 on the 1V8 IO DHCOR */
/* Enpirion EP3A8LQI U2 on the DHCOR */
vdd_io: regulator-buck-io {
compatible = "regulator-fixed";
regulator-name = "buck-io";
@ -20,5 +20,4 @@
&pwr_regulators {
vdd-supply = <&vdd_io>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};

View File

@ -4,9 +4,7 @@
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
@ -23,6 +21,14 @@
};
};
&crc1 {
status = "okay";
};
&dts {
status = "okay";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
@ -35,7 +41,7 @@
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>;
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
@ -53,7 +59,7 @@
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <800000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
@ -92,7 +98,6 @@
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO1 0>;
interrupt-parent = <&pmic>;
};
v2v8: ldo2 {
@ -100,7 +105,6 @@
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
interrupts = <IT_CURLIM_LDO2 0>;
interrupt-parent = <&pmic>;
};
vtt_ddr: ldo3 {
@ -114,7 +118,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
interrupts = <IT_CURLIM_LDO4 0>;
interrupt-parent = <&pmic>;
};
vdd_sd: ldo5 {
@ -122,7 +125,6 @@
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO5 0>;
interrupt-parent = <&pmic>;
regulator-boot-on;
};
@ -131,7 +133,6 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO6 0>;
interrupt-parent = <&pmic>;
regulator-enable-ramp-delay = <300000>;
};
@ -143,20 +144,17 @@
bst_out: boost {
regulator-name = "bst_out";
interrupts = <IT_OCP_BOOST 0>;
interrupt-parent = <&pmic>;
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
interrupt-parent = <&pmic>;
regulator-active-discharge = <1>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
interrupt-parent = <&pmic>;
regulator-active-discharge = <1>;
};
};
@ -173,6 +171,12 @@
status = "disabled";
};
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
&iwdg2 {
@ -194,7 +198,7 @@
#size-cells = <0>;
status = "okay";
flash0: spi-flash@0 {
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;

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