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MLK-23349-4 usb: cdns3: ep0: toggle cycle bit before reset endpoint

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If there are TRBs pending during reset endpoint operation, the
DMA will advance after reset operation, but it isn't expected,
since the data is not yet available (For OUT, the data is not
yet available). After the data is ready, there won't be any
interrupt since the EP_TRADDR already points to next TRB entry
and doorbell is not set.

To fix it, it toggles cycle bit before reset operation, and restores
it after reset, itt could avoid unexpected DMA advance later due
to TRB content is changed during the reset.

Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
This commit is contained in:
Peter Chen
2020-02-14 10:09:51 +08:00
parent b201be8945
commit 282ed22da0
1 changed files with 10 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/usb/cdns3/ep0.c
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@ -387,6 +387,8 @@ static int cdns3_ep0_feature_handle_endpoint(struct cdns3_device *priv_dev,
priv_ep->flags |= EP_STALL;
} else {
struct usb_request *request;
struct cdns3_request *priv_req;
struct cdns3_trb *trb;
if (priv_dev->eps[index]->flags & EP_WEDGE) {
cdns3_select_ep(priv_dev, 0x00);
@ -396,6 +398,13 @@ static int cdns3_ep0_feature_handle_endpoint(struct cdns3_device *priv_dev,
cdns3_dbg(priv_ep->cdns3_dev, "Clear Stalled endpoint %s\n",
priv_ep->name);
request = cdns3_next_request(&priv_ep->pending_req_list);
if (request) {
priv_req = to_cdns3_request(request);
trb = priv_req->trb;
trb->control = trb->control ^ TRB_CYCLE;
}
writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
/* wait for EPRST cleared */
@ -406,11 +415,10 @@ static int cdns3_ep0_feature_handle_endpoint(struct cdns3_device *priv_dev,
priv_ep->flags &= ~EP_STALL;
request = cdns3_next_request(&priv_ep->pending_req_list);
if (request) {
cdns3_dbg(priv_ep->cdns3_dev, "Resume transfer for %s\n",
priv_ep->name);
trb->control = trb->control ^ TRB_CYCLE;
cdns3_rearm_transfer(priv_ep, 1);
}
}