When early_power_on is present in power domain dtb node, it
will be powered on during resume regardless of whether the
related module is enabled or NOT, this will cause cm4_intmux
always power ON after first time resume when cm4_intmux is
NOT enabled.
So move this early_power_on property to board level dtb, ONLY
when cm4_intmux is enabled, then this property is added.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
When early_power_on is present in power domain dtb node, it
will be powered on during resume regardless of whether the
related module is enabled or NOT, this will cause cm4_intmux
always power ON after first time resume when cm4_intmux is
NOT enabled.
So move this early_power_on property to board level dtb, ONLY
when cm4_intmux is enabled, then this property is added.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
1. Dom0 dts include fsl-imx8qm-mek.dtsi
2. Add /memreserve/ according to reserved-memory no-map node, then
xen will not use these memory. The memory region are used by
vpu/dsp/rpmsg, so xen should not touch them.
3. correct dom0 cma area, CM4 has limitation that the max access address
is 0xE0000000, so the alloc-ranges should consider the limitation,
otherwise rpmsg dma allocation will alloc memory higher than
0xE0000000 and M4 will crash.
4. Hook CM41 with SMMU, added the addresses the CM41 will access, then
after SMMU enabled, CM41 could access the address. To support
Rear-View Camera, CM41 is kicked off by SCU at very early stage,
DomU memory almost has no chance to have machine address 0x90000000
included which is the vring desc buffer. So we have to enable SMMU
to let CM41 access the memory.
5. Since DomU Guest RAM0 base is moved to 0x80000000, Let's change DomU
ip address space to their machine address, since there is no conflict
now.
6. Add reserved-memory in DomU dts, we enabled xen xl to copy that
to DomU dtb.
7. Mark PCI/VPU as xen,passthrough, but not supported in DomU now.
8. Add Pixel_combiner2 passthrough to make dpu2 display work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Rename fsl-imx8qm-mek.dts to fsl-imx8qm-mek.dtsi and keep /dts-v1/ in
fsl-imx8qm-mek.dts, then let fsl-imx8qm-mek.dts include
fsl-imx8qm-mek.dtsi.
This is to prepare adding /memreserve/ for mek dom0 dts.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Adjust passive trip point temperature to be 20 degree C
below than the critical trip point temperature on i.MX8X
platforms.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit cefa63c1b9)
Use MQ specific ak5558 sound card compatible string in order to
handle properly 1:2 bclk:mclk SAI ratio.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 20d6d65c330a1560407bc99e0a7f90225ceaf7d8)
This patch adds pixel combiner node support for i.MX8dx DT
file and hooks the pixel combiner node to the DPU node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner nodes support for i.MX8qm DT
file and hooks the pixel combiner nodes to the DPU nodes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
With these two properties enabled, the dwc3 driver at 850D can ACk
LPM packet from host, and the later suspend/resume signals are correct.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
When system enter suspend, the system counter timer will stop counting.
So need to add "arm,no-tick-in-suspend" flag. Otherwise, the system
timekeeping will be wrong.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 1e15dda8c50a474891ccd1cb7fa7b41a8abbadc2)
According to IC reply, 8QXP B0 still has some issue on its DPLL.
Though we still not find any issue when usdhc use PLL0(DPLL), but better
to change back to PLL1(APLL) just in case any problem. So this patch change
back the usdhc clock parent to PLL1.
To track the history, refer to commit 7834eee6df ("MLK-17188-2
ARM64: dts: imx8qxp: assign usdhc clock parent") and commit 0611d9138e
("MLK-18003 ARM64: dts: imx8qxp: change back usdhc clock parent to PLL0").
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Since the rev. B4 of the 8MQ EVK board, the i2c of the DSI was moved
from i2c1 to i2c3. Since ADV7535 needs these i2c lines, it was the only
one affected by this change.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
i.MX8QXP DDR3L board includes i.MX8QXP LPDDR4 ARM2 board's dts,
but need to overwrite the model name accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Increase i.MX8QM CMA size to 960MB to meet 4K video requirement.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
CEC and EDID are not supported by lpddr4 arm4 board.
So remove fsl,cec and add fsl,no_edid properity.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit fbf7da4423c74e59830cf460e8f06cbd174d7be8)
With the updated i.MX8QM silicon, prg1/10 may be shared bewteen
dpr1/3_channel1 and dpr1/3_channel2 respectively with appropriate
mux configurations in SCU firmware. If prg1/10 are attached to
dpr1/3_channel2, then they act as the auxiliary prg to process
chroma pixels for SC_R_DC_0/1_BLIT1. Otherwise, they act as the
primary prg to process RGB pixels for SC_R_DC_0/1_BLIT0.
Let's reflect this update in the device tree file.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit dab218c3c4)
For add flexcan node in dtsi and xen doesn't support can, add "delete
flexcan node" for DomUs now.
Change interrupt-parent to gic, for xen does not support "wu"
interrupt controller.
Signed-off-by: Xiaoning Wang <xiaoning.wang@nxp.com>
This patch adds device tree support for i.MX8QXP DDR3L validation
board, it ONLY has 1GB memory, so CMA size needs to be reduced
when including the i.MX8QXP LPDDR4 ARM2 board device tree file.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 3005f91cef3057aa6eeb168415ec42e57fc993f9)
By default, imx8qm b0 silicon set the IO voltage to 2.5v, but the arm2
board is designed as 1.8v voltage for enet IO, so force the IO voltage
to 1.8 by setting COMP_CTL_GPIO_1V8_3V3 pins like:
For ENET0: SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB
For ENET1: SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA
The pin setting:
1.8V/3.3V : bit4=0, bit[30]=1, bit[2:0]=000
2.5V : bit4=1, bit[30]=1, bit[2:0]=010
For 2.5v IO timing test, HW board need to do some rework:
- Force PHY work at 2.5v mode
- Supply 2.5v voltage to VDD_ENETx
Tested-by: Sandor Yu <Sandor.yu@nxp.com>
Tested-by: Jason Liu <jason.hui.liu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
The IMX_DMATYPE_SAI(24) performance is not enough to support high
sample rate/channels of audio case, there is a lot of underrun and
the sound is noise, the reason is that with this script, sdma copy data
through a long path (SDMA->pl301_audio -> pl301_display -> … ->
pl301_wakeup -> AIPS1 -> SPBA2 -> SAI).
The IMX_DMATYPE_SSI_SP(2) performance is better, which go through a shorter
path (SDMA -> SPBA2 -> SAI).
So we switch to use the IMX_DMATYPE_SSI_SP script, then 384k/32b/16c is
supported well.
Cloned from commit d5b70e9232 ("MLK-18643: ARM64: dts: imx8mm: change the
sdma script for SAI").
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 390620091748db98216c2f95fe95fb4ac3284564)
The existing implementation calculates mclk rate as function
of audio sample rate multiplied to multiplier taken from Table 5.
However this is not accurate for Manual Setting Mode - tables 3 & 4 from
AK4458 RM defines rate (LRCK/FS) and frame width (MCLK/16fs..1152fs) ranges
as parameters to calculate mclk frequency. Aside of this - adjust
bclk:mclk ratio from machine driver as function of "compatible" id.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 527b8b7032dcb75c14bb2790330ab96743d83b16)
To support lowest power mode for suspend, if no wakeup source
from non-secure partition is enabled, IRQSTEER can be powered
off when suspend, so non-secure linux OS needs to pass WU
irqchip wakeup source info to ATF, as MU is always enabled
as wakeup source, and it is a system level resource, so no
need to have it in WU domain.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit d45b2fd47417cc1c4e03616007271e07834cf415)
In imx8mm-evk DTS both AUDIO PLL rates are configured, so SPDIF1
pll8k and pll11k clocks can be set accordingly.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 4ee8ed7f91ebc96ee398ec1382fac738d79cfe6c)
Enable USBOTG2 port, there are some limitations for USB port usage
from hardware engineer:
USBOTG2 port must be connected to Host or Charger at anytime as the
power supply.
USBOTG1 port can be connected to Host, device or charger only after
USBOTG2 port is connected.
This limitation is caused by SIP team's load switch, the debouce time
is too long, so when power supply switches from one port to another,
system might lose power and reboot.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Add support for i.MX8QM B0 vpu decoder and encoder and it is compatiable
with i.MX8QXP B0 VPU.
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
(cherry picked from commit f2d7823da29c55644299eea84a2e866ea188c698)
xen does not support wu interrupt controller, it will cause dom0
boot failure, modify the nodes that use wu to use gic and remove wu.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
add new dts for m4 audio playback
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 7343c0bd256d7ade1152f83bd0eb395d29e03620)
There is a change in imx8mm evk revb board, which is to add a i2c
control for power enablement of audio board, that software can
control the power of audio board, which can resolve the issue that
with audio board the cpu board can't reboot issue.
In this patch add power supply for each AK series codecs
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 1d3d7e6d6ecd0ab62fb9bb568a5afeb2fbeda1ca)
only support playback for rpmsg device on imx8mm evk.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit a6e9ff5efc814fa08f7e4664f584861b4a4d5792)
Add dom0/domu device tree for i.MX8QM LPDDR4 ARM2 board to support
dual OS running based on xen.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
(cherry picked from commit 40cc9ab8f4d301660a7697a4f90b136a7f8199e9)
We load DSP firmware from the ARM side at 0x556e8000 but because the
compiler generated memory layout starts at 0x596e8000 we need to do
some fixups.
Thus, each address (in DSP local memory) generated by the compiler
needs to be substracted an offset = 0x596e8000 - 0x556e8000 = 0x4000000.
Because this only happens on QM we will use dts to specify the offset.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 8d4518d2a5d956549e829470af15003d7adff841)
i.mx8QM B0 comes with a DSP (placed in the VPU unit).
From the ARM core side DSP local memory (Inst/Data) is mapped at
0x55000000-0x55FFFFFF range.
DSP also uses code located in SDRAM mapping starting at 0x92400000.
While at it, move rpmsg_node up in order to have all reserved
areas sorted by address.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 1eb4b2ee64c6f1fd7a5d6ceb1f019e876dbdfeb9)
Add support for AVPLL for DisplayPort on iMX8QM.
The AVPLL will be the default pixel clock source for DisplayPort.
Use fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dts to support the legacy (iMX8QM-A0) clock configuraiotn.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
