Since MU now is NOT in WU irq domain, so there is no irq_set_wake
callback available, below message will come out during kernel boot
up:
imx8mu_init: set_irq_wake failed: -6
GIC/MU now are powered off during suspend, so it is unnecessary to
call irq_set_irq_wake() for MU, we can remove it to avoid the failure
message.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Right now power_on always returns true even if SCFW reports a failure.
Since the target resource is still unpowered this quickly turns into a
hang when we attempt to access it.
Handle this by reporting an error to the PM core instead and also print
the sc_err number to help with debugging.
This fixes boot on 8qm A0: instead of hanging on boot we print an error
and refuse to probe the VPU.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Dong Aisheng <Aisheng.dong@nxp.com>
update the noc QoS setting for CPU & VPU on i.MX8MQ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
(cherry picked from commit 45d2dcaecce6d83e5c4a7e9488c651a05b0f05ac)
Add PAD wakeup support for i.MX8 platforms with system
controller present, with PAD wakeup feature enabled,
the corresponding resource's power is no need to be
kept enabled when linux suspend, thus save a sub-system's
power consumption.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 3b5d781273b22461de9aaea337f9da9b2fdb643e)
This patch enabled the TKT340553_SW_WORKAROUND on i.MX8QM RevB
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 35cfd2953a795caa93312394a05c4811c9d3bd6c)
MU is shared between rpmsg driver and the multi-core
power management on i.MX6SX and i.MX7D, the RIE3 is
enabled by MU driver, but when rpmsg is probed, it
will call MU_Init and RIE3 will be clear and cause
multi-core power management never work, so do NOT
clear RIEn during MU initialization for i.MX6SX and
i.MX7D.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
add busfreq support on i.MX8MM. when system is running at low bus or
audio bus mode, the dram & bus clock will be reduced to a lower rate:
NOC: 150MHZ, AXI: 24MHz, AXI 20MHZ, DRAM core clock: 25MHz.
when system is running at high bus mode, all the bus clock and dram
clock will be restore to the highest one.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
To support lowest power mode for suspend, if no wakeup source
from non-secure partition is enabled, IRQSTEER can be powered
off when suspend, otherwise, IRQSTEER needs to be powered on
to support wakeup, so need to pass WU domain wakeup source
info to ATF, then ATF will decide if to power off IRQSTEER
when system suspend.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Let Dom0 use hvc to trap to xen to communicate with SCU.
xen could reuse the MU used by Dom0 before. By reusing
the MU in Dom0, xen has power to control resources owned
by DomU.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add MU restore function to support MU power off
in system suspend mode, need to re-initialize
MU after resume, since MU might lose power when
suspend.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
The vendor tree does imx7 PGC management through regulator notifiers
while upstream implemented the same features using power domains. These
two drivers have entirely different interfaces with higher-level IP
blocks.
Resolve this conflict by moving the old code to drivers/soc and
supporting both power-domain and regulator interfaces. This effectively
merges the two drivers and is similar to how imx6sx implements both
power domains and a regulator notifier for pcie specifically.
Supporting both interfaces allows consumes to switch one-by-one, for
example by having PCI work with a power-domains reference while usb hsic
still uses the regulator enable/disable interface.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Correct MIPI/PCIe/USB_HSIC's PGC offset based on
design RTL, the value on Reference Manual are incorrect.
The correct offset should be as below:
0x800 ~ 0x83F: PGC for core0 of A7 platform;
0x840 ~ 0x87F: PGC for core1 of A7 platform;
0x880 ~ 0x8BF: PGC for SCU of A7 platform;
0xA00 ~ 0xA3F: PGC for fastmix/megamix;
0xC00 ~ 0xC3F: PGC for MIPI PHY;
0xC40 ~ 0xC7F: PGC for PCIe_PHY;
0xC80 ~ 0xCBF: PGC for USB OTG1 PHY;
0xCC0 ~ 0xCFF: PGC for USB OTG2 PHY;
0xD00 ~ 0xD3F: PGC for USB HSIC PHY;
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Use correct MU for SCFW API calls to comply with boot
container intended usage. Since ATF uses MU0 and kernel
uses MU1, update the MU id in api calls.
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
This fixes graphics on imx6sx by aligning closer to upstream instead of
adding new features to old bindings.
Upstream adds a 4th power domain for PCI but this is is wrong: the PCI
block is in the DISPMIX domain and only PCIE_PHY is in the PCIE_PHY
power domain.
Manual is not very clear on this but in section 10.4.1.4.1 there is this
statement: "The DISPLAY domain contains GIS, CSI, PXP, LCDIF, PCIe,
DCIC, and LDB. It is supplied by internal regulator."
Placing pcie in a 4th power domain makes lspci hang when display is
turned off.
In upstream the dispmix domain is not actually touched on 6sx so it's
always on, this is why pci seems to work.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
This was introduced while porting patches from imx_4.9.y. In the 4.9
branch there are specific power_on and power_off functions for PU but in
upstream this code was refactored to make the code generic for each PGC
block.
Fixes: ce181a6440dc ("MLK-13479-1: ARM: imx: gpc: delay 2us instead of sw+sw2iso delay")
While we're at it remove GPU_VPU_{PUP,PND}_REQ because they're not used.
Upstream forgot to delete these bits while refactoring.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
With new bindings the PU regulator is fetched much later, after
imx_gpc_probe is complete. So hack the imx_pgc_power_domain_probe
function to check for fsl,ldo-bypass at this point.
This issue only actually affects imx6qp because on other SOCs with a
vddpu regulator is it disabled on boot and settings are copied from
vddsoc on first enable, see commit 64dd7300a334 ("MLK-11407-3:
regulator: anatop: force vddpu to use same voltage level as vddsoc")
On imx6qp however disabling the PU regulator is not allowed because of
hardware errata.
Fixes: 94e8d6daea9a ("MLK-11407-1 soc: imx: gpc: enable PU bypass")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
This patch adds resources power mode dump from debugfs,
it is for i.MX SoCs which have SCFW to control overall
resources power mode, such as i.MX8QM/QXP, example
as below:
croot@imx8qmmek:~# cat /sys/kernel/debug/imx_rsrc_pm/imx_rsrc_pm_summary
resource_id power_mode
----------------------------------------------
0 ON
1 ON
2 ON
3 ON
4 ON
5 ON
6 ON
7 ON
8 FAIL
9 FAIL
10 ON
11 ON
12 ON
13 ON
14 OFF
.....
533 OFF
534 FAIL
535 FAIL
536 FAIL
537 FAIL
538 FAIL
539 FAIL
540 OFF
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Because of the TO1.0 issue on i.MX8QM, we need to let DomU
know that errata, then DomU big.Little guest could work correctly.
This is not that good to add compatible for xen vm machine in
imx8 soc code. Another method is to modify xen toolstack to create
the imx8qm compatible in domu dts, but this is not welcomed, from
xen maitainer's view "Domu should be not binded with a dedicated SoC".
For supporting i.MX8QM, Let's first use the compatible. This might
cause qxp Domu thinking it is 8QM, but we do not support passthrough
on 8QXP, because no smmu.
So it is ok to add the compatible here.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
When irq_set_irq_wake error, it means no irq wakeup capability,
showing the error msg is enough, no need to abort and cause
kernel stop.
For xen, currently we do not support suspend/resume, and
no wu interrupt controller support now, so need to remove
"return err" to avoid kernel stop.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
The MU works just fine without interrupts because sc_call_rpc will poll
waiting for a response. Make this explicit because it allows easier
emulation for virtualization.
The request_irq error is just reported but doesn't fail the probe,
however failing to set that irq as a wake source is fatal.
This was introduced recently:
commit 3b20aa779f ("MLK-17072-1: soc: imx: sc: ipc: enable MU
interrupt as wakeup source")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Currently, on imx8mq evk board, we only support 3200mts and 667mts
frequency setpoints. So the DDR DVFS flow need to be updated accordingly.
The dram pll and dram apb clock rate is changed in ATF when doing frequency,
in kernel side, we need to call the clk API to update the clock rate info
in clock tree.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
A 'return' statement is missed before, So the mutex will be unlocked
twice, in some corner case, one core will unlock the mutex that locked
by anohter core wrongly. Then lead to concurrent access to the DVFS
at the same time.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
imx8_rsrc_clk->parent may be cleared during last probe failure.
So we need explicitly call CLK APIs clk_get_parent to get the cached
parent for the later restore. Otherwise, it may reparent to NULL parent
which results in 0 clk rate.
Fixes: 05caa1390f (" MLK-17363-1 imx8: pm-domain: fix clock parent restore issue after suspend/resume")
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
The clocks list associated with a PD is the same across all devices
attached to the same PD. Re-initializing it each time a new device is
attached results in missing some clocks.
[ Aisheng: "Improve commit message" ]
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Currently the clock parent actually is failed to be restored in power
domain driver due to the set_parent will bail out early as the clk core
already cached the same old parent.
Implement a CLK_SET_PARENT_NOCACHE flag in clk core and register all
SC mux clocks with this flag to make sure the clk core won't bypass
the SC clock parent setting.
[ Aisheng: "Add commit message" ]
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
When the resource id is larger than 512, the wakeup_rsrc_id array
will overflow, then the resource may always power on.
So align the IRQ with resource number to fix the issue.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
If the system is currently in low bus mode, if the audio device
request the audio bus mode, the NOC, AHB and AXI bus clock rate
will be set wrongly, then bus will run at very low frequency, then
lead to audio playback underrun.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Anson Huang <anson.huang@nxp.com>
In current gpc-psci.c file, the irqchip driver and gpc power
domain driver use the same spinlock to prevent concurrent
access to the GPC module. But actually, the irq and power domain
are two seperated function and controlled by different registers.
when using the same spinlock for these two funcition, in some corner
case the system will be deadlock if the spinlock is already acquired
by the power domain, but the power domain on/off is interrupted by
timer IRQ. So adding a mutex for power domain driver.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
With current design, there may be a clock state issue lost due to driver
probe fail and power domain go to OFF. Then the next driver probe using the
same domain and clocks may fail because the kernel already caches the last clk
settings, the next retry will return directly. As a result, driver may believe
the the clk setting is passed but actually no in HW. So a state mismatach
happenes between SW and HW.
This is actually a nature limitation with current design as there's no state
alignment mechanism between clk SW status and HW status. Power Domain and CLK
subsystem are two separate subsystems in current kernel design, re-architecure
the kernel power domain and clk probably is the best way to handle this issue.
However, this patch implements a quick workaround to trap the possible state
lost case and give the driver one more chance to re-set the clk when power
domain is enabled. This can tempororily fix this issue although may be not
be so good from architecture point of view.
One note is that as a parent clk rate restore will cause the clk recalc
to all possible child clks which may result in child clk previous state lost
due to power domain lost before, we have to first walk through all child clks
to retrieve the state via clk_hw_get_rate which bypassed the clk recalc,
then we can restore them one by one.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Config NOC to limit bandwidth to 4GB for both VPU
and CPU to avoid lcdif flickering only when lcdif is enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 8ab89ebeb94a423792bf588bdf2354c5960d8f13)
Currently, kernel still can be wakeup-ed by MU even without enabling it
as a wakeup source. That's because of MU never off in suspend and scfw
can wakeup A53 if MU interrupt not disabled or masked in GIC. But in a
corner case that the MU interrupt coming after suspend_device_irqs, MU
interrupt will be masked by below code in handle_fasteoi_irq:
if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
desc->istate |= IRQS_PENDING;
mask_irq(desc);
goto out;
}
Thus, next MU interrupt after kernel suspend can't wakeup A53 since it's
masked in GIC and scfw can't see the 'wakeup' interrupt to power up A53.
But from kernel view, that's ok since MU interrupt not set to a wakeup
source. Enable MU as a wakeup source to follow the normal kernel wakeup
device/source flow.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Current power domain driver only setup all domain callbacks during second
level power domains intialization. However, there're also some root power
domain nodes having valid SC resource handler which may be used by device
as well. Missing to setup them may result in some features lost on these
domains.
e.g.
pd_dc0: PD_DC_0 {
compatible = "nxp,imx8-pd";
reg = <SC_R_DC_0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
...
}
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
During 4.14 rebase added dynamic allocation of genpd.states, required by
upstream commit 59d65b73a2 ("PM / Domains: Make genpd state allocation dynamic")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
There're fundanmental difference between the using of start/stop and pd
mode selection. Start/stop actually can only reflect device state, not
power domain state. So actually we're abusing it here.
e.g. take a consider of two devices on the same domain.
PD mode should be selected by power domain gorvernor or power domain core.
This patch totally remove the wrong use of start/stop and runtime_idle_active
to indicate which PD mode to enter.
By apply this patch, the power domain lower power mode selection will have
no dependency on the per device runtime status anymore.
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
MX8 power domain supports two low power modes: LP and OFF.
So adding them accordingly to make the power domain core be aware of it.
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
The power domain core alreadys checked it, no need check it anymore.
Besides that, removing it make the driver be able to switch to different
low power mode in the future. Identically the power on check is also
removed.
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Add one more 'group' parameter to notification so that rtc/temperature
driver can check if this MU interrupt is for themselves or not. Worst
case as before, different irq group with the same irq_status can't be
distinguished, such as 'SC_IRQ_BUTTON' and 'SC_IRQ_RTC'(all is 1), which
means both notification will be called once any of both interrupts
triggered. Besides, refine check irq_status code.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
reduce the NOC, main AXI and AHB bus clock frequency to save power when DDR enter low
frequency mode. VDDSOC is ~195mA during video play, and ~180mA in idle.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
If audio device is the only that access to ddr memory, the DDR
frequency can be reduce to 25MHz to save power. when DDR run in
25MHz frequency, the memory bandwidth is about 66MB/s, it can
meet the performance requirement for audio only case.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
On i.MX8MQ, we need the handle the correspoding IMR registers in gpc
to make sure the IRQ affinity to the specific core can be wakeup
successfully from power down idle state.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
