commit 3f0191b80cf1 ("MLK-14381 mmc: sdhci-esdhc-imx: reset tuning
circuit when system resume") add tuning reset when the timing is
MMC_TIMING_LEGACY/MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS. For timing
MMC_TIMING_MMC_HS, we can not do tuning reset, otherwise HS400
timing is not right.
Here is the process of config HS400, it do tuning in HS200 mode,
then switch to HS mode and 8 bit DDR mode, finally switch to HS400
mode. If we do tuning reset in HS mode, this will cause HS400 mode
lost the tuning setting, which will cause CRC error.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
If we could not get a valid pd for gate/mux, print a warning log.
And use IS_ERR_OR_NULL to check the pd pointer.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The function of driver is to communicate with hifi firmware.
The mu13 is dedicated for hifi communication, driver allocate
a share memory for message transfer between driver and firmware.
The calling sequence is that LOAD_CODEC,INIT_CODEC,CODEC_OPEN,
DECODE_ONE_FRAME, CODEC_CLOSE.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
fxas2100: CONFIG_SENSORS_FXAS2100X
fxos8700: CONFIG_SENSORS_FXOS8700
isl29023: CONFIG_INPUT_ISL29023
mpl3115 : CONFIG_INPUT_MPL3115
This patch also enable CONFIG_INPUT_POLLDEV, because sensor driver
depends on input-polldev.c
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
The lpi2c IP needs two clks: ipg clk and per clk. The old lpi2c
driver missed ipg clk. This patch adds ipg clk for lpi2c driver.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
Ensure that both PLL and IPG clocks are enabled and set by
the HDMI irqsteer device tree entry.
Fix some HDMI clock names.
The HDMI irqsteer incorrectly assumed that the HDMI bus clock will
be enabled automatically by the SCFW when HDMI SS is powered up.
Fix HDMI clocks so that the HDMI IPG clock is enabled when required.
Also fix all the LPCG addresses by HDMI clocks.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
with "echo 1 > /sys/class/graphics/fb0/blank", and there is no
usb connected on board, the system may enter low power mode,
then audio playback will be failed. use pm_qos to prevent A7
core enter low power mode during audio playback and recording.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Some DMA operation APIs are not exported, so when load driver as module,
there will error saying some APIs can not be found.
This patch exported these DMA related APIs.
Signed-off-by: Shawn Xiao <b49994@freescale.com>
lpuart only use NXP/FSL eDMA dmaengine in i.MX/Vybrid/LS1021a platform,
and eDMA driver don't reuse descriptor then no need to check the
flag DMA_CTRL_ACK. And current eDMA driver use virt chan mechanism and
free tx_descriptor memory after .callback(), but .lpuart_timer_func()
first to terminate the chans that free the tx_descriptor memory, then
access the tx->flags, which cause kmem_cache_alloc() failed to allocate
the freed memory. So remove the unnecessary .async_tx_ack().
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
The IrqSteer module redirects/steers the incoming interrupts to output
interrupts of a selected/designated channel as specified by a set of
configuration registers.
NXP i.MX8x chips integrate IrqSteer controller for some DSC to share irq
line for all modules in the subsystem which can reduce the IRQ lines
connected to the parent interrupt controller GIC, so IrqSteer irqchip
acts as the second irq domain in the system.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Using CLK_OF_DECLARE will register clks at very early stage
that AP-SC communication still not ready.
MU driver is registered by early_initcall, so using core_initcall
to delay the registeration of clk driver is ok.
Move channel open function into probe to avoid core_init sequence
not in our expected order. If MU not ready, return defer probe
for clk driver.
Later when we switch to use interrupt driver AP-SC communication,
we could also return defer probe in clk probe function to wait
until AP-SC communication ready.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
After soft reset, the irq register value will be zero, so we need set it to enable
all pxp interrupts.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
M4 has use case of video and need more DDR space
for video buffer, reserve more DDR space for it.
0x80000000 - 0x800fffff: ARM Trusted Firmware;
0x80100000 - 0x87ffffff: M4/RPMSG;
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
M4 has use case of video and need more DDR space
for video buffer, reserve more DDR space for it.
0x80000000 - 0x800fffff: ARM Trusted Firmware;
0x80100000 - 0x87ffffff: M4/RPMSG;
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
CAAM uses DMA to transfer data to and from memory, if
DMA and CPU accessed data share the same cacheline cache
pollution will occur. Marking the result as cacheline aligned
moves it to a separate cache line.
Signed-off-by: Radu Solea <radu.solea@nxp.com>
Some drivers may access dma_async_tx_descriptor in callback such as
tty/serial/fsl_lpuart.c, but the description has already been freed
before callback, memory corrupt here. Move the free description
behind of callback.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Enable chipidea usb controller driver and mxs usb phy driver for imx8.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
If the vbus is controlled by ehci port power bit, we need set power
polarity of vbus enable signal according to the vbus power supply
chip on board.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Set the OTG1 vbus power polarity to be active high on
fsl-imx8qm-lpddr4-arm2.dts.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
USB host vbus control can be via port power(PP) bit of ehci, there
is a polarity setting in controller register for this signal, if
power supply chip use active high, add this property.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
When starting a playback the initialization data used to reduce underruns
was send to the transmit data register after the DMA requests were enabled.
This patch moves the initialization phase before enabling the DMA so the
data is transmitted in correct order.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Auto Enable LOCALVERSION_AUTO
so show git commit hash value in boot log
Linux version 4.9.11-02242-gf4b0aff-dirty
Signed-off-by: Frank Li <Frank.Li@nxp.com>
For samples with more than 2 and odd number of channels the I2S mode
does not work correctly. In I2S mode we are required to activate an even
number of channels (possibly on multiple datalines) and thus configure
the BCLK for even channels. In this case samples with odd (smaller) number
of channels are played faster and the sound is distorted.
To fix this behavior we can enable TDM mode for the special cases of
samples with 3, 5 or 7 channels. But even TDM has some restrictions that
prevent us from having full support for the special cases:
1. TDM is not supported by codec in master mode so 3, 5 and 7 channels
usage is denied.
2. In codec slave mode TDM works only with 8 slots and slot width of 32
bits. For an often used MCLK frequency of 24MHz and the above restrictions
the maximum sample rate is limited to 48KHz = 24576000/(2*8*32).
The 2 denominator is required by ESAI BCLK divisors.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
switch to use new format. Split mux out from pad config.
Change the high two bits in pad config to 0, because driver
will automatically set that two bits to 1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
