The 'nand_usdhc_bus' clock is only need to be enabled when usdhc
or nand module is active, so change it to non-critical clock type.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Add driver support for i.MX8DXL DB Perf, which supports AXI ID PORT
CHANNEL filter.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Add clock support for Perf in DB SS, since Perf LPCG has the clocks off
by default.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
There is a PMU in DB(DRAM Block) which has the same function with PMU in DDR
subsystem, the difference is PMU in DB only supports cycles, axid-read,
axid-write events.
The role of the DB is to route the read/write transaction from connected
subsystems to either the DDR subsystem, or to any other subsystems. The AXI
IDs used is the one seen at the PORT.
e.g.
perf stat -a -e imx8_db0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_port=0xPP,axi_channel=0xH/ cmd
perf stat -a -e imx8_db0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_port=0xPP,axi_channel=0xH/ cmd
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Add driver support for i.MX8DXL DDR Perf, which supports AXI ID PORT
CHANNEL filter.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
This is the extension of AXI ID filter.
Filter is defined with 2 configuration registers per counter 1-3 (counter 0 is
not used for filtering and lacks these registers).
* Counter N MASK COMP register - AXI_ID and AXI_MASKING.
* Counter N MUX CNTL register - AXI CHANNEL and AXI PORT.
-- 0: address channel
-- 1: data channel
This filter is exposed to userspace as an additional (channel, port) pair. The
definition of axi_channel is inverted in userspace, and it will be reverted in
driver automatically.
AXI filter of Perf Monitor in DDR Subsystem, only a single port0 exist, so
axi_port is reserved which should be 0.
e.g.
perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd
perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
MMU enable shift mapping for the reserved memory from 4GB above range,
4GB above address is truncated for mtlb offset falling into dynamic area,
need check shift mapping to avoid dynamic error for the truncated mtlb.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
support memory-region for gpu reserved memory from DTS,
keep contiguous_mem compatibility if no memory-region.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Commit 729dcffd1e ("usb: dwc3: gadget: Add support for disabling
U1 and U2 entries") give detail explaination for user case of
disable u1 and u2 in gadget mode:
"Usecase 1:
When combining dwc3 with an redriver for a USB Type-C device
solution, itsometimes have problems with leaving U1/U2 for
certain hosts, resulting in link training errors and reconnects.
For this U1/U2 state entries may be avoided."
on imx8mq-evk board, we have typec and redriver used and android
reported unstable issue when use some host PC for adb, so to have
a better performance, we disable u1 and u2 entries.
Reported-by: Richard Liu <xuegang.liu@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
dai-index property must match dai-index from topology. FSL DAI
driver uses it for now figure out the correct DAI name, but might
be used for other things in the future.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
With the help of dai-index we figure out the correct name for a DAI.
In topology files DAI name is formed by concatenating DAI type ("sai",
"esai", etc) with DAI index.
So, this patch removes hardcoded DAI names esai0, sai1 and figures out
the names based on DAI type/index.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
With the reserved memory for optee, Linux is no
longer able to allocate CMA within the allocation
range defined in the dtb.
Increase the alloc-range so that Linux can allocate in the 4G
address range (in case some DMA are not able to address more).
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
When TX fifo has dirty data, user initialize the port and
wait transmit engine complete, it should disable flow control,
otherwise tx fifo never be empty.
Tested-by: Yang Tian <yang.tian@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
mdio bus reset should not happen during resume back for
most of phys, so let mdio bus reset is decided by dts.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Start phylink instance and resume back the PHY to supply
RX clock to MAC before MAC layer initialization by calling
.stmmac_hw_setup(), since DMA reset depends on the RX clock,
otherwise DMA reset cost maximum timeout value then finally
timeout.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Correct the HDMI irqsteer's interrupt controller parent, otherwise the HDMI
irq can NOT wakeup the cpu core from idle timely, then HDMI performance
will be impacted.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Currently, the voltage of AUX channel under lower level, it was
not satisfied DP spec, this patch will be used to increase voltage
of the AUX channel for DP port.
Signed-off-by: Wen He <wen.he_1@nxp.com>
It should not return -EINVAL if the request role is the same with
current role, return non-error and without do anything instead.
If the user input is neither "host" nor "gadget", return -EINVAL.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
It should not return -EINVAL if the request role is the same with
current role, return non-error and without do anything instead.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
IC confirmed the both imx8qm and imx8qxp could use 250M as usb3_clk
and no performance drop.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
If there are TRBs pending during reset endpoint operation, the
DMA will advance after reset operation, but it isn't expected,
since the data is not yet available (For OUT, the data is not
yet available). After the data is ready, there won't be any
interrupt since the EP_TRADDR already points to next TRB entry
and doorbell is not set.
To fix it, it toggles cycle bit before reset operation, and restores
it after reset, itt could avoid unexpected DMA advance later due
to TRB content is changed during the reset.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
It has marked the dequeue trb as link trb, but its next segment
pointer is still itself, it causes the transfer can't go on. Fix
it by set its pointer as the trb address for the next request.
Reviewed-by: Jun Li <jun.li@nxp.com>
Fixes: f616c3bda4 ("usb: cdns3: Fix dequeue implementation")
Signed-off-by: Peter Chen <peter.chen@nxp.com>
After below code:
if (role == CI_ROLE_GADGET)
ci_handle_vbus_change(ci);
It has already handled the VBUS event in suspend for device mode.
In fact, it just reverts 5f59266728 ("MLK-12344-1 usb: chipidea:
otg: add vbus connect for gadget after sleep"), but git refuses
to revert this commit, so we it with a new patch.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Dequeuing implementation in cdns3_gadget_ep_dequeue gets first request from
deferred_req_list and changed TRB associated with it to LINK TRB.
This approach is incorrect because deferred_req_list contains requests
that have not been placed on hardware RING. In this case driver should
just giveback this request to gadget driver.
The patch implements new approach that first checks where dequeuing
request is located and only when it's on Transfer Ring then changes TRB
associated with it to LINK TRB.
During processing completed transfers such LINK TRB will be ignored.
Reported-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Fixes: 7733f6c32e ("usb: cdns3: Add Cadence USB3 DRD Driver")
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Link: https://lore.kernel.org/r/1570958420-22196-1-git-send-email-pawell@cadence.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add new compatible 'imx8mp-sdma' for sdma2/sdma3 to support resume back after
audiomix off.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add sdma restore back for i.mx8mp since its power resource audioimx will
be off after suspend.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
tls module lacks an alias, thus cannot be auto-loaded.
Note that all crypto modules have to be "protected" under the namespace
created by the "crypto-" prefix:
commit 5d26a105b5 ("crypto: prefix module autoloading with "crypto-"")
Fixes: a61cc4776299 ("crypto: add support for TLS 1.0 record encryption")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Valentin Ciocoi Radulescu <valentin.ciocoi@nxp.com>
Topology is similar with the one for i.MX8QXP but now we really
use correct name for SAI: sai3 instead of sai1.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
The GPU AXI/AHB & ML AXI/AHB clock must be on when doing corresponding
power domain on/off, so Add these clocks to GPUMIX & MLMIX power domain.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
The hack was added to allow XCVR to record data at high FS rate,
remove it since it impacts other drivers such as MICFIL.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Need set 4GB address limit flag on 8mm/8mn as 8mq,
because these platform GPU can't handle physical
address large than 4GB due to hardware system
integration limitation.
Signed-off-by: Richard Liu <xuegang.liu@nxp.com>
With GPC as interrupt parent, need set edac and irqsteer interrupt
parent as gpc.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
iMX8DXL EVK board only has 1GB DDR, so it can't allocate 960MB CMA.
Change the CMA size to 320M to align with 8DX.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
