Current the CMA size is 128M, after GPU enabled, there is no
space left for other drivers. So increase it to 640M, which is
align with imx8qm
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
In imx8qxp rev1, there is hardware issue (TKT331800). ESAI
dma request signal connection issue in SS_ADMA top level
integration, The ESAI dma request signal are active_low, the EDMA
input is high active, but there is no polarity convert logic
between them.
This patch is to add a workaround for this issue. It use the
GPT to convert dma request signal to EDMA, and use anther GPT
to clear the dma request.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
The difference of imx-pcm-dma and imx-pcm-dma-v2 is that first
one will request dma channel in probe, the second one request
dma channel when substream is opened.
When the case is ASRC+ ESAI, the FE+BE is working, which need
to reconfigure the dma channel, so use the imx-pcm-dma-v2 is
more flexible
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Add one more cell in edma note, which is the property of
local/remote access. The default access is local.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
update fsl_edma_v3 document for #dma-cell is changed
one more cell is added, which is for local/remote access.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
The parameter is "is_remote", which is to use remote access for
edma, the default access is local access.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
The type of irqstat in irqsteer_irqchip_data unsigned long, actually
it needs to be 32bits width, so use unsigned int.
And use sizeof(irqsteer_data->irqstat[0]), instead of 4 when alloc
memory for irqsteer_data.
for_each_set_bit needs the second param type is unsigned long *, so
cast the irqsteer_data->irqstat to unsigned long *, this is safe here.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
On i.MX8QM, as there is no SoC platform broadcast timer
available now, remove the local-timer-stop flag for
cpu-idle driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Update i.MX8QM cpu-freq opp table according to SCFW setting,
and move the cpu-freq opp table to soc dtsi instead of board
dtb, as it is SoC feature.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Update i.MX8QXP cpu-freq opp table according to SCFW setting,
and move the cpu-freq opp table to soc dtsi instead of board
dtb, as it is SoC feature.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
commit 3f0191b80cf1 ("MLK-14381 mmc: sdhci-esdhc-imx: reset tuning
circuit when system resume") add tuning reset when the timing is
MMC_TIMING_LEGACY/MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS. For timing
MMC_TIMING_MMC_HS, we can not do tuning reset, otherwise HS400
timing is not right.
Here is the process of config HS400, it do tuning in HS200 mode,
then switch to HS mode and 8 bit DDR mode, finally switch to HS400
mode. If we do tuning reset in HS mode, this will cause HS400 mode
lost the tuning setting, which will cause CRC error.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
If we could not get a valid pd for gate/mux, print a warning log.
And use IS_ERR_OR_NULL to check the pd pointer.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The function of driver is to communicate with hifi firmware.
The mu13 is dedicated for hifi communication, driver allocate
a share memory for message transfer between driver and firmware.
The calling sequence is that LOAD_CODEC,INIT_CODEC,CODEC_OPEN,
DECODE_ONE_FRAME, CODEC_CLOSE.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
fxas2100: CONFIG_SENSORS_FXAS2100X
fxos8700: CONFIG_SENSORS_FXOS8700
isl29023: CONFIG_INPUT_ISL29023
mpl3115 : CONFIG_INPUT_MPL3115
This patch also enable CONFIG_INPUT_POLLDEV, because sensor driver
depends on input-polldev.c
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
The lpi2c IP needs two clks: ipg clk and per clk. The old lpi2c
driver missed ipg clk. This patch adds ipg clk for lpi2c driver.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
Ensure that both PLL and IPG clocks are enabled and set by
the HDMI irqsteer device tree entry.
Fix some HDMI clock names.
The HDMI irqsteer incorrectly assumed that the HDMI bus clock will
be enabled automatically by the SCFW when HDMI SS is powered up.
Fix HDMI clocks so that the HDMI IPG clock is enabled when required.
Also fix all the LPCG addresses by HDMI clocks.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
with "echo 1 > /sys/class/graphics/fb0/blank", and there is no
usb connected on board, the system may enter low power mode,
then audio playback will be failed. use pm_qos to prevent A7
core enter low power mode during audio playback and recording.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Some DMA operation APIs are not exported, so when load driver as module,
there will error saying some APIs can not be found.
This patch exported these DMA related APIs.
Signed-off-by: Shawn Xiao <b49994@freescale.com>
lpuart only use NXP/FSL eDMA dmaengine in i.MX/Vybrid/LS1021a platform,
and eDMA driver don't reuse descriptor then no need to check the
flag DMA_CTRL_ACK. And current eDMA driver use virt chan mechanism and
free tx_descriptor memory after .callback(), but .lpuart_timer_func()
first to terminate the chans that free the tx_descriptor memory, then
access the tx->flags, which cause kmem_cache_alloc() failed to allocate
the freed memory. So remove the unnecessary .async_tx_ack().
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
The IrqSteer module redirects/steers the incoming interrupts to output
interrupts of a selected/designated channel as specified by a set of
configuration registers.
NXP i.MX8x chips integrate IrqSteer controller for some DSC to share irq
line for all modules in the subsystem which can reduce the IRQ lines
connected to the parent interrupt controller GIC, so IrqSteer irqchip
acts as the second irq domain in the system.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Using CLK_OF_DECLARE will register clks at very early stage
that AP-SC communication still not ready.
MU driver is registered by early_initcall, so using core_initcall
to delay the registeration of clk driver is ok.
Move channel open function into probe to avoid core_init sequence
not in our expected order. If MU not ready, return defer probe
for clk driver.
Later when we switch to use interrupt driver AP-SC communication,
we could also return defer probe in clk probe function to wait
until AP-SC communication ready.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
After soft reset, the irq register value will be zero, so we need set it to enable
all pxp interrupts.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
