This patch allows to read back the EXT_CSD[179] partition_config
register, just specifying the dev param:
U-Boot> mmc partconf 0
EXT_CSD[179], PARTITION_CONFIG register:
BOOT_ACK: 0
BOOT_PARTITION_ENABLE: 0
PARTITION_ACCESS: 0
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
The u-boot of i.MX6ULL chip needs header data.The update_nand.c will
add header data when writing into NAND flash.
These code reference from Digi ccimx6ul.
Add Android support for mx6qarm2 lpddr2 pop target
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(Cherry picked from commit 6356f2b420f3571493755f6b3a307a66a539b60c)
Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar
board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok
to work.
The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when
it is needed.
The DDR3 script is using version 1.2:
File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc
Test: 3 boards passed memtester.
Build target:
mx6ull_14x14_evk_defconfig
Signed-off-by: Ye Li <ye.li@nxp.com>
Due to TSC pin conflict with I2C1 bus, and PMIC is this I2C1 bus's
slave, this patch add new TSC config for i.mx6ull_14x14_ddr3_arm2
board, disable PMIC and ldo bypass check.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.
Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.
Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable
using these pins.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To align with i.MX6UL, add the chip package size info to the i.MX6ULL ARM2 board
build target and loading dtb file name. So that mfgtool and yocto can follow i.MX6UL
naming rule to process i.MX6ULL.
Signed-off-by: Ye Li <ye.li@nxp.com>
Current environment offset on NAND is 37MB, this will cause a alignment
issue when erasing if nand erase block is 2MB. The saveenv is failed.
=> saveenv
Saving Environment to NAND...
Erasing NAND...
Attempt to erase non block-aligned data
Since the max erase block we supported is 4MB, adjust the env offset to 60MB,
where is the last 4MB in 64MB reserved area for boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which
conflicts with QSPIA and NAND, that we have to disable them at same time.
2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which
conflicts with SD2 and NAND, that we have to disable them at same time.
3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK
4. Enable QSPI support for default SD boot case.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 00f36b3e9445ff47ed68262ef2d656e410cd8fcd)
Support mx6ull ddr3 arm2 board.
DDR script version 1.1. Passed memtester on 3 boards.
Take mx6ul 14x14 ddr3 arm2 as reference.
Note:
LCD/NAND/ECSPI not tested, need hardware rework.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 584050b98c)
On mx6qsabreauto and mx6sx ARM2 boards, the EIMNOR sector size is 128KB.
And its u-boot environment offset is 4 sectors (512KB). But u-boot size has
exceeds it, so change to 6 sectors offset (768KB).
To align the environment configurations for all i.MX, also change the configuration
for mx6ul and mx7d, which has EIMNOR with 256KB sectors.
Signed-off-by: Ye Li <ye.li@nxp.com>
Since the u-boot size has exceeded the 512KB on some platforms,
so we set the environment offset to 768KB for all i.MX6 and i.MX7
reference boards.
Signed-off-by: Ye Li <ye.li@nxp.com>
Since the QSPI needs to rework on this board, at default the QSPI is disabled.
So bind the M4 QSPI boot with QSPI enabled u-boot image, set default
M4 boot to TCM. Need to use TCM m4 image at default.
Additional, on SDB there is only one QSPI flash. Considering the A7 QSPI boot
case, we have to move M4 image to 1M offset to give enough space for u-boot
and env.
Signed-off-by: Ye Li <ye.li@nxp.com>
Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for
module fuse check. And modify board level codes for SD, FEC and EIM.
Signed-off-by: Ye Li <ye.li@nxp.com>
Setup MMDC in two channel fixed mode
Initialize dram banks for two channel fixed mode
DRAM bank = 0x00000000
-> start = 0x10000000
-> size = 0x20000000
DRAM bank = 0x00000001
-> start = 0x80000000
-> size = 0x20000000
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Debug monitor will print out last failed AXI access info when
system reboot is caused by AXI access failure, only works when
debug monitor is enabled.
Enable this module on i.MX6SX.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit df6ac8531d)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Set the CONFIG_SUPPORT_EMMC_BOOT in mx6_common.h to enable the eMMC
boot support for all mx6 platforms. Remove the duplicated definition
in board's header file.
Signed-off-by: Ye Li <ye.li@nxp.com>
The ARM errata 751472, 794072, 761320, 845369 only applied
to the following configuration:
This erratum affects configurations with either:
- One processor if the ACP is present
- Two or more processors
i.MX6 family does not have the ACP and thus only the MPCore system
will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
(cherry picked from commit 0db960784b)
Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 70ad44e523)
This is a demo that CM4 will boot up by u-boot without typing any
command. It boots up at u-boot early init, try to minimize the time
from power up to the CM4 running.
Since CM4 runs on QSPI NOR XIP, we have to disable the QSPI driver in
u-boot to avoid conflict.
RDC for shared GPIO1 is added, but not enabled, because the kernel is
not ready for shared GPIO1. Users can uncomment the CONFIG_IMX_RDC to
enable it.
Some legacy codes in mx6sxsabreauto are removed. We only need this work
on mx6sxsabresd as a demo.
Signed-off-by: Ye Li <ye.li@nxp.com>
Add board level support for android fastboot feature. Each board has
a android specified header file for defining android related configuraitons.
And add build targets for their android uboot images building.
For mx6qsabreauto, mx6sabresd and mx7dsabresd, we enable the android
fastboot exclusive with DFU.
Signed-off-by: Ye Li <ye.li@nxp.com>
Integrate the FSL android fastboot features into community's fastboot.
1. Use USB gadget g_dnl driver
2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and
EFI partitions are not support by i.MX.
3. Add FDT support to community's android image.
4. Add a new boot command "boota" for android image boot. The boota
implements to load ramdisk and fdt to their loading addresses
specified in boot.img header, while bootm won't do it for android image.
5. Support the authentication of boot.img at the "load_addr" for
both SD and NAND.
6. We use new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot
with relevant header file "fsl_fastboot.h". While disabling the
configuration, the community fastboot is used.
7. Overwrite the cmdline in boot.img by using bootargs saved in local environment.
8. Add recovery and reboot-bootloader support.
Signed-off-by: Ye Li <ye.li@nxp.com>
The i.MX6SL EVK needs this driver in android fastboot support. Add
this driver to u-boot.
To use the driver, user must define:
CONFIG_MXC_KPD Enable the driver
CONFIG_MXC_KEYMAPPING Key mapping matrix
CONFIG_MXC_KPD_COLMAX The column size of key mapping matrix
CONFIG_MXC_KPD_ROWMAX The row size of the key mapping matrix
Signed-off-by: Ye Li <ye.li@nxp.com>
The CONFIG_MX7_SEC is not set at default, so the MX7 goes to non-secure mode
before jumping to kernel, and needs PSCI works for secure mode operations.
We have to set the CONFIG_MX7_SEC to enable the secure mode, otherwise we
will get some kernel panic issues.
Signed-off-by: Ye Li <ye.li@nxp.com>
Modify the picosom to be suit for Brillo configurations.
Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com>
(cherry picked from commit 864fd4f019)
To align with 2016.03, fix several places.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change CONFIG_MXC_RDC to CONFIG_IMX_RDC.
Do misc update in board header file to support RDC for M4 usage.
Fix rdc interface imx_rdc_check_permission change in mxc_gpio.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
