This patch allows to read back the EXT_CSD[179] partition_config
register, just specifying the dev param:
U-Boot> mmc partconf 0
EXT_CSD[179], PARTITION_CONFIG register:
BOOT_ACK: 0
BOOT_PARTITION_ENABLE: 0
PARTITION_ACCESS: 0
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
This patch from Digi u-boot source code
There is an inconsistency in U-Boot v2015.04 handling unique
identifiers.
The binary data may be read out into strings as GUID format, but the
'gpt'
command expects strings to be passed in UUID format.
When partitions info is written with 'gpt' in v2015.04 using the UUID
string stored in an environment variable, for example:
- $part1_uuid=43f1961b-ce4c-4e6c-8f22-2230c5d532bd
- gpt write mmc 0
"...start=2MiB,name=linux,size=64MiB,uuid=${part1_uuid}..."
then reading out the UUID with the part command will return:
- part uuid mmc 0:1
1b96f143-4cce-6c4e-8f22-2230c5d532bd
which is the same string in UUID string representation. This,
however,
cannot be string compared to the value in the variable.
This commit does not try to resolve the inconsistency of uuid/guid
naming
and handling in U-Boot source code, but rather maintain the
backwards
compatibility with the UUID was written and interpreted.
The u-boot of i.MX6ULL chip needs header data.The update_nand.c will
add header data when writing into NAND flash.
These code reference from Digi ccimx6ul.
Add fastboot and recovery mode support for mx6qarm
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(Cherry picked from commit 505e899ce582118da28ca1f4487ce7f179225bd7)
Add Android support for mx6qarm2 lpddr2 pop target
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(Cherry picked from commit 6356f2b420f3571493755f6b3a307a66a539b60c)
Adjust ahb/axi clock root podf dividers to be divided by 1
to allow ahb/axi clock root to be 24Mhz when sourced
from osc_clk.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(Cherry picked from commit 9e80234c823d6a2a0d9e10ab4c4c605bf646bd22)
VGEN3 and VGEN5 have been fused the right value in PF0100 on i.mx6qp board,
so software didn't need to change their voltage output anymore. Otherwise,
VGEN3 will be wrongly updated from 1.8v to 2.8v.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 6f7f185664a401f03f6ce6c81b996c1f27fdbe73)
On i.MX6ULL, according to the latest REFTOP_TRIM fuse define, we need
to set the REFTOP_VBGADJ bits in PMU_MISC0 register as below table:
'000" - set REFTOP_VBGADJ[2:0] to 3'b000
'001" - set REFTOP_VBGADJ[2:0] to 3'b001
'010" - set REFTOP_VBGADJ[2:0] to 3'b010
'011" - set REFTOP_VBGADJ[2:0] to 3'b011
'100" - set REFTOP_VBGADJ[2:0] to 3'b100
'101" - set REFTOP_VBGADJ[2:0] to 3'b101
'110" - set REFTOP_VBGADJ[2:0] to 3'b110
'111" - set REFTOP_VBGADJ[2:0] to 3'b111
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit b2690f5cf54390999acb2f1f7b788bfd18fa11be)
Per to design team, we need to set REFTOP_VBGADJ
in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the
actually table is as below:
'000' - set REFTOP_VBGADJ[2:0] to 3b'110
'110' - set REFTOP_VBGADJ[2:0] to 3b'000
'001' - set REFTOP_VBGADJ[2:0] to 3b'001
'010' - set REFTOP_VBGADJ[2:0] to 3b'010
'011' - set REFTOP_VBGADJ[2:0] to 3b'011
'100' - set REFTOP_VBGADJ[2:0] to 3b'100
'101' - set REFTOP_VBGADJ[2:0] to 3b'101
'111' - set REFTOP_VBGADJ[2:0] to 3b'111
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Update the LPDDR2 script to 1.2 rev with delay line settings changed.
File:
IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc
https://nxp1.sharepoint.com/teams/123/IMX6ULL/SitePages/Documents.aspx
Changes:
Update Delay Line Settings based on the delay line calibration results of more boards.
MMDC_MPRDDLCTL = 0x40403439
MMDC_MPWRDLCTL = 0X4040342D
Test:
One 9x9 EVK board pass stress memtester.
Signed-off-by: Ye Li <ye.li@nxp.com>
Add two build configs for i.MX6ULL 9X9 EVK. And update lpddr2 script
for the board to version 1.0.
DDR script:
IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.0.inc
Changes:
Initial version
Test:
Passed memtester overnight test on 1 board.
Signed-off-by: Ye Li <ye.li@nxp.com>
We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before
this changing, SATA read/write can't work after it. And we have to re-init SATA.
The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.
This patch is an work around that moves the ENET clock setting
(enable_fec_anatop_clock) from ethernet init to board_init which is prior
than SATA initialization. So there is no PLL6 change after SATA init.
Signed-off-by: Ye Li <ye.li@nxp.com>
Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar
board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok
to work.
The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when
it is needed.
The DDR3 script is using version 1.2:
File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc
Test: 3 boards passed memtester.
Build target:
mx6ull_14x14_evk_defconfig
Signed-off-by: Ye Li <ye.li@nxp.com>
When dfu_fill_entity fail, need to free dfu to avoid memory leak.
Reported by Coverity:
"
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable dfu going out of scope leaks the storage
it points to.
"
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
(cherry picked from commit 5d8fae79163e94671956c99654abf48cf49757ba)
