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Author SHA1 Message Date
c253573f3e Prepare v2017.11
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-13 20:08:06 -05:00
be135cc5eb Revert "console: simplify puts()"
This reverts commit c61d0009fe.

A tbs2910 board user reported a very slow console frambuffer as
regression in current u-boot. I could bisect this down to the
above mentioned commit.

This revert brings back the fast framebuffer console (one
cache flush per string in puts(), not after each char).

Reported-by: Uwe Scheffler <scheffler.u@web.de>
Signed-off-by: Soeren Moch <smoch@web.de>
Tested-by: Uwe Scheffler <scheffler.u@web.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-12 16:18:16 -05:00
ae147ab4a8 board: sysam: stmark2: add missing environment location
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-11-12 16:18:16 -05:00
2bfd43e550 ARM: rmobile: Fix eMMC signal voltage on Salvator-X/XS
The eMMC is 1V8 device only and the signaling is always 1V8,
fix the DT for Salvator-X/XS to describe the hardware correctly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-12 16:17:31 -05:00
66bd5a3ebb Merge git://git.denx.de/u-boot-sunxi 2017-11-10 10:04:21 -05:00
8e2c2d413c sunxi: SATA link timeout fix
After updating u-boot from v2016.01 to 2017.09, issue with
"SATA link 0 timeout." on my Cubietruck board.

mdelay milled after moving satapwr code to board.
"sunxi: Turn satapwr on from board_init"
(sha1: 9fbb0c3aa4)

After adding the "mdelay(500);"
line that was lost in the path the error is gone.

Signed-off-by: Werner Böllmann <Werner.Boellmann@fh-dortmund.de>
[Rebased and updated change and commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-10 19:21:24 +05:30
13ae2a40e7 net: sun8i_emac: Fix build for non-H3/H5 SoCs
Only the H3/H5 SoCs have an internal PHY and its related clock and
reset controls.

Use an #ifdef to guard the internal PHY control code block so it
can be built for other SoCs, such as the A83T or A64.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-10 19:10:33 +05:30
60567a320f Merge git://git.denx.de/u-boot-rockchip 2017-11-10 08:19:01 -05:00
36b6e0cc3c rockchip: configs: vyasa: Update falcon offsets
Update the falcon offsets for args to 16MB and kernel to 17MB
Since the below commit updated U-Boot proper location along
with rockchip boot image offsets
"spl: set SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x4000 for rockchip"
(sha1: 8f4d62b403)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-10 14:08:22 +01:00
d80599e894 rockchip: doc: Fix U-Boot proper location for falcon
This patch fixed U-Boot proper location has been
missed to update in bewlo commit
"rockchip: doc: update U-Boot location info"
(sha1: 73e6dbe855)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-10 14:08:21 +01:00
341e44ed66 rockchip: doc: update U-Boot location info
The U-Boot location has been moved to block 16384.
This is 8MB, not 4MB.

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-10 14:08:20 +01:00
1c4043e532 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-11-09 08:11:40 -05:00
3c674b7e87 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-11-09 08:11:30 -05:00
9c8979cdb7 imx7: Add include guards for include/asm/arch-mx7/sys_proto.h file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
e895e996ab imx5: Add include guards for include/asm/arch-mx5/sys_proto.h file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
90d0e38c1e imx6: Add include guards for include/asm/arch-mx6/sys_proto.h file
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
a3eec24ad3 imx:display5: Add support for LWN's DISPLAY5 board
This commit provides support for LWN's IMX6Q based DISPLAY5 board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
ec1b26973c imx6: iomux: Add generic function to set RGMII IO voltage on IMX6 SoCs
This commit provides generic function to set the RGMII/HSIC IO voltage
level on iMX6 devices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
8ea754da60 board: imx6: marsboard: Remove doubled #include <asm/arch/sys_proto.h>
The sys_proto.h file has been included earlier in this file.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-09 11:32:49 +01:00
6270a3f035 sunxi: restore PHYLIB for CONFIG_SUN4I_EMAC users
due misnaming of CONFIG_SUN4I_EMAC in include/configs/sunxi-common.h,
likely missed in:
	commit 3146f0c017 ("Move PHYLIB to Kconfig")

Signed-off-by: Artturi Alm <artturi.alm@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-09 14:39:30 +05:30
e286fada9d sunxi: fix CONFIG_SUNXI_EMAC references
fixes CONFIG_SUNXI_EMAC references from drivers/net/Makefile and
include/configs/sunxi-common.h likely forgotten in:
	commit abc3e4df59 ("sunxi: Convert SUNXI_EMAC to Kconfig")

Signed-off-by: Artturi Alm <artturi.alm@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-09 14:39:09 +05:30
bcfb365375 mmc: fsl_esdhc: Fix PIO timeout
The following error has been observed on i.MX25 with a high-speed SDSC
card:
    Data Write Failed in PIO Mode.

It was caused by the timeout set on PRSSTAT.BWEN, which was triggered
because this bit takes 15 ms to be set after writing the first block to
DATPORT with this card. Without this timeout, all the blocks are
properly written.

This timeout was implemented by decrementing a variable, so it was
depending on the CPU frequency. Fix this issue by setting this timeout
to a long enough absolute duration (500 ms).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-07 10:26:27 +01:00
cc65e354fe i.MX6: engicam: Fix MAINTAINERS/README
- Update newly added include/configs file in MAINTAINERS
- Update newly added defconfig file in README

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-07 10:13:39 +01:00
b2e6ad451b mx51: Select the ESDHC_A001 erratum
When a high speed card is connected to mx51evk the following error is seen:

U-Boot 2017.11-rc2 (Oct 18 2017 - 13:49:26 -0200)

CPU:   Freescale i.MX51 rev3.0 at 800 MHz
Reset cause: POR
Board: MX51EVK
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - read failed, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0
=> saveenv
Saving Environment to MMC...
Writing to MMC(0)... failed

The root cause for the failure is the eSDHC-A001 erratum:

"eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for
values of 0x4,0x8, and 0xC" that is listed
on some PowerArchitecture chips:
https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf

Even though eSDHC-A001 is not documented on the i.MX51 errata document,
I have confirmed with the NXP design team that this erratum does affect
i.MX51, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001
at SoC level.

The i.MX51 ts4800 board already selects this option, but it is better
to move this selection to the i.MX51 SoC level instead.

Successfully tested with a high speed SD card on a mx51evk board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
2017-11-07 10:13:11 +01:00
5d09c27138 mx25: Select the ESDHC_A001 erratum
When a high speed card is connected to mx25 the following error is seen:

U-Boot 2017.11-rc2-00104-gb79372a (Oct 31 2017 - 11:02:22 -0200)

CPU:   Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: POR
Board: MX25PDK
I2C:   ready
DRAM:  64 MiB
No arch specific invalidate_icache_all available!
MMC:   FSL_SDHC: 0
*** Warning - read failed, using default environment
In:    serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0
=> saveenv
Saving Environment to MMC...
Writing to MMC(0)... failed

, which prevents any usage of the SD card.

The root cause for the failure is the eSDHC-A001 erratum:

"eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for
values of 0x4,0x8, and 0xC" that is listed
on some PowerArchitecture chips:
https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf

Even though eSDHC-A001 is not documented on the i.MX25 errata document,
I have confirmed with the NXP design team that this erratum does affect
i.MX25, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001
at SoC level.

Successfully tested with a high speed SD card on a mx25pdk board.

Suggested-by: Benoît Thébaudeau <benoit@wsystem.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Otavio Salvador <otavio@ossystems.com.br> # mx25pdk
2017-11-07 10:13:00 +01:00
07df697e14 mx25: Move MX25 selection to Kconfig
The motivation for moving MX25 selection to Kconfig is to be
able to better handle MX25 specific errata, so that an errata option
can be selected at SoC level instead of board level.

This selection method also aligns with the way other i.MX SoCs are
selected in U-Boot.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2017-11-07 10:12:50 +01:00
021a8ae00a rockchip: remove SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR from defconfig
Use default value 0x4000 for SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR instead
of define a new one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:58 +01:00
73e6dbe855 rockchip: doc: update U-Boot location info
Update rockchip U-Boot location to 0x4000/16384.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
8f4d62b403 spl: set SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x4000 for rockchip
Rockchip use a 'loader2' partition for U-Boot, so u-boot.bin or
u-boot.itb load by SPL need to locate at0x4000. Detail here:
http://opensource.rock-chips.com/wiki_Boot_option

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
b5557ffc0f rockchip: board: puma_rk3399: make env location selectable via Kconfig
The environment storage location is selectable via Kconfig. We support
eMMC, SD and SPI-NOR as location for U-Boot. This adds support to store
the environment in the SPI-NOR additional to the default eMMC location.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
4f70039b36 rockchip: dts: rk3399: change sd-card io voltage to 3.0V
The VCC_SD and VCC_SDIO rail should only be powered up to 3.0V on RK3399
platforms.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
366812fa26 rockchip: dts: Use defines for pin names in rk3399-puma.dtsi and rk3368-lion.dts
pinctrl/rockchip.h provides defines that map pin numbers to pin names.
Use them to make the dts more human readable.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
b1e1ce2cd4 rockchip: dts: rk3399-puma: update USB configuration
This change updates the USB configuration for the RK3399-Q7 in the DTS:
 * fixes the OTG board configuration by enabling it ('okay')
 * improves the speed of 'usb start' by disabling the unused EHCI/OHCI
   controllers

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
f2a9513168 rockchip: dts: rk3399-puma: update usbhub_enable regulator
To correctly model the usbhub_enable regulator for U-Boot, we need
to change the settings to:
 * the GPIO polarity is GPIO_ACTIVE_LOW
 * should be set to inactive (enable-active-low) when boot-on settings
   are applied
 * it can be changed at runtime (i.e. remove the always-on)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:57 +01:00
df1e6212f9 rockchip: dts: rk3399-puma: fix the modelling of BIOS_DISABLE
The fixed regulator for overriding BIOS_DISABLE had been modelling
backwards (i.e. the GPIO polarity and the enable-active-low/high
property had both been inverted), causing the 'regulator' command
to always print/expect 'disabled'/'enabled' backwards.

This fixes the mix-up and models it correctly:
 * the GPIO is low-active
 * the regulator should be enabled (enable-active-high) during
   boot-on initialisation

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-07 09:16:56 +01:00
be942f2e0d rockchip: config: use common CONFIG_ENV_SIZE for all SoCs
All Rockchip SoCs use 32KB as CONFIG_ENV_SIZE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:56 +01:00
c742043f74 rockchip: config: sync the ENV offset from rockchip legacy U-Boot
Using the ENV offset from rockchip legacy U-Boot for all SoCs,
the offset is 4MB-32KB

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:56 +01:00
5d2f1d8271 rockchip: rock: remove CONFIG_ENV_OFFSET
We use the same default ENV setting in rockchip_common.h for all SoC.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-07 09:16:56 +01:00
7a69604bce Prepare v2017.11-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-06 18:25:37 -05:00
fc85605018 cosmetic: rmobile: renesas spelled wrong
Renesas was spelled wrong.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
2017-11-06 09:59:03 -05:00
b95a5190ba Do not attempt to use the systemwide libfdt
U-Boot bundles a patched copy of libfdt, so it's wrong to attempt to
include it <like/this>. This breaks the build for me when I have dtc
fully installed in my host -- as happened earlier tonight with
Buildroot, for example.

There are several other occurrences throughout the code where '<libfdt'
matches. I'm not modifying these because I have no clue why the
<systemwide> include style is being used -- IMHO wrongly.

Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
2017-11-06 09:59:02 -05:00
6ba2da90de m68k: doc: update outdated documentation
Update m68k documentation to reflect the current ColdFire
architecture support status.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2017-11-06 09:59:02 -05:00
8f7102cf6b disk: part_dos: fix part_get_info_extended() function
The check in part_get_info_extended() for a successful partition
searching misses a condition for extended partition. In case of
(ext_part_sector == 0), we should anyway mark the partition as found,
even if it's an extended partition, i.e. (is_extended(pt->sys_ind) == 0).
Otherwise, the extended partition (type 0x0f) will never be identified,
and the following recursive call to part_get_info_extended() will get a
wrong 'part_num' and 'which_part' parameter.  In the end, all those
partitions in extended table will not be identified.

Let's add the missing OR condition of (ext_part_sector == 0) for
is_extended() check to fix the problem.

The issue is discovered by running fastboot flash to an extended
partition on eMMC.

  $ fastboot flash mmcsda5 cache.img
  target reported max download size of 536870912 bytes
  sending 'mmcsda5' (18796 KB)...
  OKAY [  2.144s]
  writing 'mmcsda5'...
  FAILED (remote: cannot find partition)
  finished. total time: 2.261s

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2017-11-06 09:59:01 -05:00
bb021013ba gpt: Use cache aligned buffers for gpt_h and gpt_e
Before this patch one could receive following errors when executing
"gpt write" command on machine with cache enabled:

display5 factory > gpt write mmc ${mmcdev} ${partitions}
Writing GPT:
CACHE: Misaligned operation at range [4ef8f7f0, 4ef8f9f0]
CACHE: Misaligned operation at range [4ef8f9f8, 4ef939f8]
CACHE: Misaligned operation at range [4ef8f9f8, 4ef939f8]
CACHE: Misaligned operation at range [4ef8f7f0, 4ef8f9f0]
success!

To alleviate this problem - the calloc()s have been replaced with
malloc_cache_aligned() and memset().

After those changes the buffers are properly aligned (with both start
address and size) to SoC cache line.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-11-06 09:59:01 -05:00
76b9cbab25 tools: image: fix message when fail to add verification data for config
This function is called when signing configuration nodes.  Adjust
the error message.

I do not know why we do not need to show the error message in case of
ENOSPC.  Remove the if-conditional that seems unnecessary.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-06 09:59:01 -05:00
6793d017a7 tools: image: allow to sign image nodes without -K option
If -K option is missing when you sign image nodes, it fails with
an unclear error message:

  tools/mkimage Can't add hashes to FIT blob: -1

It is hard to figure out the cause of the failure.

In contrast, when you sign configuration nodes, -K is optional because
fit_config_process_sig() returns successfully if keydest is unset.
Probably this is a preferred behavior when you want to update FIT with
the same key; you do not have to update the public key in this case.

So, this commit changes fit_image_process_sig() to continue signing
without keydest.  If ->add_verify_data() fails, show a clearer error
message, which has been borrowed from fit_config_process_sig().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-06 09:59:00 -05:00
1d88a99d1b tools: image: fix "algo" property of public key for verified boot
The "algo_name" points to a property in a blob being edited.  The
pointer becomes stale when fit_image_write_sig() inserts signatures.
Then crypto->add_verify_data() writes wrong data to the public key
destination.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-06 09:59:00 -05:00
ac122efdb6 test/py: regenerate persistent GPT image if code changes
test_gpt generates a persistent disk image which can be re-used across
multiple test runs. Currently, if the Python code that generates the disk
image change, the image is not regenerated, which could cause test
failures e.g. if a test was updated to expect some new partition name or
size, yet the persistent disk image contained the old name or size. This
change introduces functionality to regenerate the disk image if the
instructions to generate the image have changed.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-11-06 09:59:00 -05:00
84d46e7e89 tools: env: allow to print U-Boot version
The fw_env utility family has a default environment compiled in
which ties it quite strongly to the U-Boot source/config it has
been built with. Allow to display the U-Boot version it has been
built with using the -v/--version argument.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2017-11-06 09:58:59 -05:00
8ec87df376 image-sig: use designated initializers for algorithm
Designated initializers are more readable because we do not
have to check the order in the struct definitions.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-06 09:58:59 -05:00
79df00fdb4 MAINTAINERS: Add missing boards and config entries
As part of my usual round of build testing, output about missing
MAINTAINERS information was not logged, and thus often overlooked.
Correct that mistake by ensuring that I log the output of
genboardscfg.py every time.  As part of that, address a number of
missing MAINTAINERS entires.  In the case of a missing file, I have put
the original submitter down.  In the rest of the cases I have added the
config (and sometimes relevant header file) to the existing set of file
globs.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-06 09:58:51 -05:00
05cd11948e tpm: st33zp24: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights header

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
e36591c350 spear: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for SPEAR
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
1537d38619 stv0991: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for STV0991
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
3bc599c956 stm32: fix STMicroelectronics copyright
Uniformize STMicroelectronics copyrights headers for STM32
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
fb48bc448c sti: fix STMicroelectronics copyright
Uniformize all STMicroelectronics copyrights headers for STi
related code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06 09:51:01 -05:00
57270eca55 Merge git://git.denx.de/u-boot-samsung 2017-11-06 09:24:55 -05:00
460b15adc9 video: sunxi: de2: fix SimpleFB node creation when HDMI not initialized
When HDMI is not initialized (e.g. no monitor is plugged), the current
SimpleFB code will still create a broken SimpleFB node.

Detect whether HDMI is initialized when creating SimpleFB node.

Fixes: be5b96f0e4 ("sunxi: setup simplefb for Allwinner DE2")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-11-06 13:43:28 +05:30
568197fa03 ARM: dts: exynos: fix property values of LDO15/17 for ODROID-XU3/4
Looking at the schematic, LDO15 and LDO17 are tied as a power source of a
builtin network chipset. The voltage on LDO15 is corrected to 3.3V and the
name of LDO17 is corrected to "vdd_ldo17".

Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-11-06 16:59:32 +09:00
43ede0bca7 Kconfig: Migrate MTDIDS_DEFAULT / MTDPARTS_DEFAULT
We move all instances of CONFIG_MTDIDS_DEFAULT and
CONFIG_MTDPARTS_DEFAULT from the header files to the defconfig files.
There's a few cases here where we need to expand upon what was in the
header file.

Tested-by: Adam Ford <aford173@gmail.com>  #omap3_logic
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-05 11:21:35 -05:00
804dcf771a Merge tag 'xilinx-fixes-for-v2017.11' of git://www.denx.de/git/u-boot-microblaze
Xilinx fix for v2017.11

- Fix ceva sata initialization
2017-11-03 10:02:29 -04:00
cba64a2a73 scsi: ceva: Start port in probe
The patch:
"dm: ahci: Unwind the confusing init code"
(sha1: 7cf1afce7f)
introduce bug for ceva sata because port didn't start.
On the other hand the dwc_ahci.c was fixed correctly.
Do the same change for ceva too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
2017-11-03 09:31:27 +01:00
a0cdb534e1 Merge git://git.denx.de/u-boot-rockchip 2017-11-01 09:32:14 -04:00
ed6be4fcdf rockchip: lion-rk3368: defconfig: select PHY_MICREL_KSZ90X1
The RK3368-uQ7 uses a KSZ9031 PHY on-module.  Enable PHY_MICREL_KSZ90X1
in the associated defconfig.

References: da3b9e7f ("Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
18a158979c rockchip: puma-rk3399: defconfig: select PHY_MICREL_KSZ90X1
The RK3368-uQ7 uses a KSZ9031 PHY on-module.  Enable PHY_MICREL_KSZ90X1
in the associated defconfig (this somehow got lost with da3b9e7f).

References: da3b9e7f ("Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
4c1a60c597 rockchip: evb-rk3328: remove CONFIG_ENV_OFFSET
Remove CONFIG_ENV_OFFSET for there already have one in rockchip_common.h

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
36de37f5ca rockchip: rk3328: fix rockchip_get_cru api
The API for get priv pointer is wrong, fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
9f636a249c rockchip: rk3399: init CPU clock when rkclk_init()
Init the CPU and its buses to speed up the boot time.
Move rkclk_init() to a place after rk3399_configure_cpu has defined
at the same time, or else there will be a warning.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
6e278a8c1c rockchip: configs: only add available BOOT_TARGET_DEVICES
BOOT_TARGET_DEVICES should only be added if the corresponding u-boot
command is enabled.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
e3e842f17c rockchip: configs: use rockchip-common.h for rk3368
rockchip-common.h already defines values that are missing from
rk3368_common.h

For example BOOT_TARGET_DEVICES was defined empty and therefore
distroboot had no boot targets.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
3c1af17c5e Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-10-31 08:14:53 -04:00
40b0dae151 mx6slevk: Call gpio_request()
We should call gpio_request() prior to reading the GPIO value.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-31 11:35:01 +01:00
0d6a41edb5 udoo: Remove cpu type check prior to setup_sata()
Inside setup_sata() there is a cpu type check, so there is no need to
do this check in the board file.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-31 11:13:56 +01:00
d7f7eb749f wandboard: Remove cpu type check prior to setup_sata()
Inside setup_sata() there is a cpu type check, so there is no need to
do this check in the board file.

This also brings the benefit to allowing setup_sata() to be called for the
mx6qp wandboard variant.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-31 11:13:33 +01:00
506abdb4ee ARM: imx6: Enable UMS and DFU on DHCOM i.MX6 PDK
Enable UMS and DFU, so that the eMMC can be accessed via the
USB gadget port on the board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2017-10-31 11:11:10 +01:00
27dc324a10 imx: mx6slevk: cleanup board usb code
Since DM_USB enabled, no need the usb code in board file.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-31 11:10:41 +01:00
723dfe8f02 mx6slevk: Fix MMC breakage for the SPL target
Commit 001cdbbb32 ("imx: mx6slevk: enable more DM drivers") breaks
MMC support in U-Boot proper on the mx6slevk_spl_defconfig target:

U-Boot SPL 2017.09-00396-g6ca43a5 (Oct 01 2017 - 16:20:18)
Trying to boot from MMC1

U-Boot 2017.09-00396-g6ca43a5 (Oct 01 2017 - 16:20:18 -0300)

CPU:   Freescale i.MX6SL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 33C
Reset cause: POR
Board: MX6SLEVK
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
MMC Device 1 not found
*** Warning - No MMC card found, using default environment

As mx6slevk_spl_defconfig does not use CONFIG_DM_MMC and its
board file does not register the mmc controller for U-Boot proper,
let's fix this by adding CONFIG_DM_MMC=y and device tree support.

While at it, add more DM drivers, so that it becomes closer to
mx6slevk_defconfig.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-31 11:10:18 +01:00
e1f0715f64 wandboard: Add support for the MX6QP variant
Add support for the latest MX6QP wandboard variant.

Based on Richard Hu's work from Technexion's U-Boot tree.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-31 11:01:38 +01:00
c0f432c377 configs: vf610: increase maximum size and enforce correct limit
On Vybrid SoCs U-Boot gets loaded into GFX SRAM which is 512KiB.
Currently 32KiB is reserved for the IMX header. However, this is
not reflected in the size limit. In v2017.11-rc2 the actual size
limit (512KiB-32KiB) has been reached for Colibri VF61, which
lead to a successful build of U-Boot but not a working binary.

The IMX header is much smaller than 32KiB, typically around 1KiB.
Decrease the reserved size to 4KiB and specify the correct U-Boot
size limit. Apply this new base address and limit for all Vybrid
based boards.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2017-10-31 11:00:54 +01:00
da125b72fd Prepare v2017.11-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-30 21:28:51 -04:00
41b93679fd net: fec_mxc: Change "error frame" message to debug level
As reported by Jonathan Gray:

"After the recent changes to add SimpleNetworkProtocol to efi_loader
when booting off mmc via an efi payload that doesn't use
SimpleNetworkProtocol U-Boot's fec_mxc driver will now display
various "error frame" messages.
....
MMC Device 1 not found
MMC Device 2 not found
MMC Device 3 not found
Scanning disks on sata...
Found 6 disks
reading efi/boot/bootarm.efi
67372 bytes read in 32 ms (2 MiB/s)
## Starting EFI application at 12000000 ...
>> OpenBSD/armv7 BOOTARM 1.0
error frame: 0x8f57ec40 0x00003d74
error frame: 0x8f57ec40 0x00007079
error frame: 0x8f57ec40 0x00006964
error frame: 0x8f57ec40 0x00006f6f
error frame: 0x8f57ec40 0x0000726f
error frame: 0x8f57ec40 0x00002074
error frame: 0x8f57ec40 0x00006f6f"

Heinrich Schuchardt explains:

"A receive FIFO overrun can be expected if network packages are not
processed.
With the network patches we check if a package is available quite often."

Move the "error frame" messages to debug level so that a clean output
log can be seen.

Reported-by: Jonathan Gray <jsg@jsg.id.au>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-10-30 18:57:42 +01:00
c46305a829 imx: Fix regression with CONFIG_DM_MMC=y
When CONFIG_DM_MMC=y, CONFIG_BLK should be selected, otherwise the
SD/eMMC card cannot be used.

Also, select CONFIG_DM_USB=y when CONFIG_USB=y to avoid build failure.

Tested on mx6slevk, mx7dsabresd and mx6ullevk.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Adam Ford <aford173@gmail.com>
Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-30 18:54:38 +01:00
73dd818cc4 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-30 12:58:33 -04:00
b79372ae94 scripts/get_maintainer.pl: enable find_maintainer_files
Many MAINTAINERS files are in subdirectories.
We should enable searching these.

Reported-by: Walt Feasel <waltfeasel@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-29 10:13:10 -04:00
9ef2684c03 checkpatch: Support wide strings
Allow prefixing typical strings with L for wide strings

Patch originally by Joe Perches
https://lkml.org/lkml/2017/10/17/1117

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-29 10:13:10 -04:00
2d5e6b4aac Merge git://git.denx.de/u-boot-video 2017-10-29 10:11:08 -04:00
9b73bcc6c3 exynos: video: fix typo in DisplayPort driver
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
CC: Simon Glass <sjg@chromium.org>
CC: Minkyu Kang <mk7.kang@samsung.com>
2017-10-29 14:33:55 +01:00
963be68937 video/da8xx-fb: Cache-align memory allocations
Resort to malloc_cache_aligned() rather than malloc() which also removes
'CACHE: Misaligned operation at range' warnings.

Signed-off-by: Niko Mauno <niko.mauno@vaisala.com>
2017-10-29 14:33:24 +01:00
405835645a efi_loader: Disable env_save() call on boot
With the introduction of EFI variable support, we also wanted to persist
these EFI variables. However, the way it was implemented we ended up
persisting all U-Boot environment variables on every EFI boot.

That could potentially lead to unexpected side effects because variables
that were not supposed to be written to persisted env get written. It also
means we may end up writing the environment more often than we should.

For this release, let's just disable EFI variable persistence and instead
implement it properly for the next one.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Fixes: ad644e7c18 ("efi_loader: efi variable support")
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-29 07:59:08 -04:00
bb3d9ed3a9 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-10-27 21:59:10 -04:00
9b3f40ad09 armv8: sec_firmware: Add support for loadables in FIT
Enable support for loadables in SEC firmware FIT image. Currently
support is added for single loadable image.

Brief description of implementation:
  Add two more address pointers (loadable_h, loadable_l) as arguments to
  sec_firmware_init() api.
  Create new api: sec_firmware_checks_copy_loadable() to check if loadables
  node is present in SEC firmware FIT image. If present, verify loadable
  image and copies it to secure DDR memory.
  Populate address pointers with secure DDR memory addresses where loadable
  is copied.

Example use-case could be trusted OS (tee.bin) as loadables node in SEC
firmware FIT image.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:14 -07:00
9781d9ff5f armv8: layerscape: Allocate 66 MB DDR for secure memory
Change DDR allocated for secure memory from 2 MB to 66 MB. This
additional 64 MB secure memory is required for trusted OS running
in Trusted Execution Environment using ARMv8 TrustZone.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:14 -07:00
18ed801e10 armv8: ls1088aqds: Enable USB command on QDS for qspi-boot
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:14 -07:00
d4c746c7b1 armv8: ls1088ardb: Enable USB command RDB qspi-boot
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:47:06 -07:00
90be2fe37e arm: layerscape: Remove CONFIG_USB_MAX_CONTROLLER_COUNT
Because COMFIG_DM_USB has been enabled and will not use it anymore.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:44:31 -07:00
420b0eba3c usb: host: Move CONFIG_XHCI_FSL to Kconfig
use Kconfig to select xhci accordingly.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:44:06 -07:00
4417e83495 arm64: layerscape: Move CONFIG_HAS_FSL_XHCI_USB to Kconfig
Use Kconfig to select QE-HDLC and USB pin-mux.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:43:57 -07:00
2af1b08a1a armv8: ls1088aqds: Change phy mode to PHY_INTERFACE_MODE_RGMII_ID
Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
PHY_INTERFACE_MODE_RGMII_TXID.

These change where introduced in phy driver in commit 05b29aa0cb
("net: phy: realtek: fix enabling of the TX-delay for RTL8211F").

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:41:12 -07:00
b584510f07 armv8: configs: ls1012a: correct the generic timer frequency
On ls1012a soc, core clock source frequency is fixed at 100Mhz.
Generic timer frequency is core clock source divided by 4, which
is 25Mhz.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:39:49 -07:00
f89072ab92 armv8: ls1088: Move CONFIG_ENV_IS_IN_SPI_FLASH to defconfig
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:39:34 -07:00
a572fb6bdd driver: fsl-mc: use calloc instead malloc
Memory allocated via malloc is not guaranteed to be zeroized.
So explicitly use calloc instead of malloc.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:38:29 -07:00
33fe271278 AT91: remove CONFIG_PMECC_INDEX_TABLE_OFFSET
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
268d05f552 exynos: remove CONFIG_LCD_MENU_BOARD
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2017-10-27 08:52:22 -04:00
795428fc67 net: remove CONFIG_NET_MULTI
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:52:22 -04:00
a28b90b787 mpc85xx: xpedite550x: remove CONFIG_FDT_FIXUP_PCI_IRQ
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
1c0eece3d8 AM33XX: etamin: remove CONFIG_DFU_MTD
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
eac89575af MX28: remove CONFIG_DEFAULT_SPI_CS
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
00687674a9 exynos: remove CONFIG_CORE_COUNT
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2017-10-27 08:52:22 -04:00
08019ccf9c omap4: sdp4430: match the #endif comment to #ifdef
This comment creates a wrong entry in config_whitelist.txt.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
a0dd989ffb SOCFPGA: remove CONFIG_AUTONEG_TIMEOUT
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
ac47750460 ARC: remove CONFIG_ARC_UART_BASE
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
e5fa2b368c sh7734: remove CONFIG_553MHZ_MODE
This macro only appears in commented-out lines.  It is not referenced
by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
020e701d8d mpc85xx: freescale: remove CONFIG_ADDR_STREAMING
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-27 08:52:22 -04:00
8e07bb2b2b omap4: sdp4430: remove CONFIG_4430SDP
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-27 08:52:22 -04:00
b7e4dadfd9 IMX: novena: remove CONFIG_I2C_MXC
This macro is defined, but not referenced by anyone.

I did not touch config_whitelist.txt - the CONFIG will be dropped
by the next re-sync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher<hs@denx.de>
2017-10-27 08:52:22 -04:00
af6715bfb4 i2c: fti2c010: remove unused/unmaintained driver
CONFIG_SYS_I2C_FTI2C010 is not enabled by anyone.

Commit 2852709676 ("dm: i2c: Add a note to I2C drivers which need
conversion") prompted to convert this driver to DM before June 2017,
but not converted yet.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
2017-10-27 08:52:22 -04:00
1d14cbdcd8 i2c: adi_i2c: remove left-over Blackfin I2C driver
This driver was used by Blackfin boards, but Blackfin support is
gone.  There is no user of this driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
2017-10-27 08:52:22 -04:00
ae6ac0a06e Merge git://git.denx.de/u-boot-x86 2017-10-27 08:50:16 -04:00
1d7eef3f3f sunxi: video: add LCD support to DE2 driver
Extend DE2 driver with LCD support. Tested on Pinebook which is based
on A64 and has ANX6345 eDP bridge with eDP panel connected to it.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: rebased v5 on u-boot-video/master]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-27 09:44:48 +02:00
79f285ddeb sunxi: video: split out PLL configuration code
It will be reused in new DM LCD driver.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2017-10-27 09:39:19 +02:00
411898dc87 x86: acpi: Put sleepstates.asl to the common place
The supported sleep states are generic on Intel processors. Move the
ASL definition to the common place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
dc80d3b230 x86: fsp: graphics: Add some notes about the graphics info hob
On some platforms (eg: Braswell), the FSP will not produce the
graphics info HOB unless you plug some cables to the display
interface (eg: HDMI) on the board. Add such notes in the FSP
video driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
4c9f4c5ee4 x86: braswell: cherryhill: Update dts for SPI lock down
Intel Braswell FSP requires SPI controller settings to be locked down,
let's do this in the chrryhill.dts and remove previous Kconfig option.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
ab20107468 spi: ich: Lock down controller settings if required
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
fb2c53091f Revert "x86: fsp: Configure SPI opcode registers before SPI is locked down"
This reverts commit 1e6ebee667.

It's not appropriate to call the Intel SPI driver specific stuff in
the FSP codes. We may add a simple DTS property "intel,spi-lock-down"
and let the Intel SPI driver call these stuff instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-27 15:13:47 +08:00
aa9c5956c9 x86: Fix ACPI resume dependency to MRC cache
In an S3 resume path, MRC cache is mandatory. Enforce the dependency
in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
3a856473fd env: x86: braswell: Set ENV_IS_IN_SPI_FLASH as default
Imply does not work for a Kconfig choice. Update ENV_IS_IN_SPI_FLASH
to be the default one for Intel Braswell.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
4a5a7fcac2 x86: braswell: Fix unexpected crash during Linux kernel boot
It was observed that when booting Linux kernel on Intel Cherry Hill
board, unexpected crash happens quite randomly. Sometimes kernel
just oops, while sometimes kernel throws MCE errors and hangs:

  mce: [Hardware Error]: Machine check events logged
  mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: c400000000010151
  mce: [Hardware Error]: TSC 0 ADDR 130f3f2c0
  mce: [Hardware Error]: PROCESSOR 0:406c3 TIME 1508160686 SOCKET 0 APIC 0 microcode 363

This looks like a hardware error per mcelog. After debugging, it
seems turning off turbo mode on the processor does not expose this
behavior, although U-Boot runs OK with turbo mode on. Suspect it is
related to an errata of Braswell processor.

To fix this, remove the Braswell cpu driver which does the turbo
mode configuration, and switch to use the generic cpu-x86 driver.
Also there is a configuration option in the FSP that turns on the
turbo mode and that has been turned off too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
7995dd3782 x86: galileo: Fix boot failure
With latest codes on mainstream master, Intel Galileo board does not
boot unfortunately. Git biset leads to b383d6c0 "bootstage: Convert
to use malloc()".

Disable bootstage support to make it boot again. The root cause needs
to be investigated however.

Fixes: b383d6c0 ("bootstage: Convert to use malloc()")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-27 15:13:47 +08:00
ddeaaefde3 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-10-26 11:50:33 -04:00
491041c749 video: add anx6345 DM driver
This is a eDP bridge similar to ANX9804, it allows to connect eDP panels
to the chips that can output only parallel signal

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: fixed most checkpatch errors/warnings]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-26 15:43:11 +02:00
24bf59d024 video: anx9804: split out registers definitions into a separate header
This header will be used in anx6345 driver

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: moved header to drivers/video]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-10-26 14:31:42 +02:00
fdb5525572 dm: video: bridge: add operation to read EDID
Add an operation to read EDID, since bridge may have ability to read
EDID from the panel that is connected to it, for example LCD<->eDP bridge.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2017-10-26 14:17:01 +02:00
be5b96f0e4 sunxi: setup simplefb for Allwinner DE2
As the support of EFI boot on Allwinner H3 is broken, we still need to
use simplefb to pass the framebuffer to Linux.

Add code to setup simplefb for Allwinner DE2 driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:57:14 +02:00
f6bdddc92b video: add an option for video simplefb via DT
Add an option to indicate that the video driver should setup a SimpleFB
node that passes the video framebuffer initialized by U-Boot to the
operating system kernel.

Currently only the Allwinner DE driver uses this option, and the
definition of this option in the sunxi-common.h config header is
converted to an imply of this option from CONFIG_VIDEO_SUNXI.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:53:39 +02:00
e5f92467d7 video: sunxi: extract simplefb match code to a new file
As the DE2 simplefb setup code can also benefit from the simplefb match
code, extract it to a new source file.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-26 11:51:45 +02:00
401a3ca0fb sunxi: change the DE1 video option to CONFIG_VIDEO_SUNXI
The sunxi DE1 video option used to be CONFIG_VIDEO, which has the same
name as the "Enable legacy video support" option in
drivers/video/Kconfig.

Change the option name to CONFIG_VIDEO_SUNXI, which is really used by
Makefile under drivers/video/sunxi/, and defined in sunxi-common.h
when CONFIG_VIDEO is selected before this change. Now CONFIG_VIDEO_SUNXI
selects CONFIG_VIDEO and the usages of CONFIG_VIDEO in sunxi Kconfig and
config headers are all converted to use CONFIG_VIDEO_SUNXI.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2017-10-26 11:48:49 +02:00
819f1e081c sunxi: binman: Add U-Boot binary size check
The U-Boot binary may trip over its actual allocated size in the storage.
In such a case, the environment will not be readable anymore (because
corrupted when the new image was flashed), and any attempt at using saveenv
to reconstruct the environment will result in a corrupted U-Boot binary.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
ce2e44d836 sunxi: Enable THUMB build for the U-Boot binary
We start to get to the limit of our main U-Boot binary size (with some
boards even crossing it). Enable its build using thumb2 to get some extra
room.

Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
7514069aa3 sunxi: Add support for the Banana Pi M2-Magic
The Banana Pi M2-Magic is a small board with an Allwinner A33, an eMMC, a
wifi chip and some pin headers. Enable support for it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
7dec673ea9 cmd: fastboot: Enable FASTBOOT_FLASH_NAND for SUNXI_NAND devices
Encountered an issue where fastboot can't write to NAND on a CHIP_pro,
the symbol was neither present in the board's config header, nor the
Kconfig, this patch puts it in the Kconfig and defaults on when
SUNXI_NAND is selected.

Signed-off-by: Ben Young <computermouth@crunchbangplusplus.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:06 +02:00
c96f598be7 sunxi: clk: fix N formula for CPUX clocks
As explained in arch/arm/mach-sunxi/clock_sun8i_a83t.c, clk for CPU
clusters is computed as clk = 24*n. However, the current formula is clk
= 24*(n-1).

This results in a clock set to a frequency that isn't specified as
possible for CPUs.

Let's use the correct formula.

Fixes: f542948b1e ("sunxi: clk: add basic clocks for A83T")

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-25 10:05:05 +02:00
a722359de4 SPL: SPI: select SPL_SPI_FLASH_SUPPORT on SPL_SPI_SUNXI
The Allwinner SPI flash SPL boot support is guarded by the SPL_SPI_SUNXI
symbol. But despite its generic name, the actual only use case for this
is to provide SPI flash support to the SPL, which requires
CONFIG_SPL_SPI_FLASH_SUPPORT to be defined.
Select this symbol from the SPL_SPI_SUNXI Kconfig definition. This
avoids doing this explicitly in the defconfig, and fixes SPI booting on
the Pine64 SoPine (and -LTS version) and the OrangePi Win board (both with
SPI flash).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-25 10:05:05 +02:00
4c7a211046 Kconfig: add CONFIG_BROKEN
Provide a Kconfig option that we can use as dependency for
features that are broken. This allows to easily disable them
without removing the code.

As no short text is supplied the option will not appear in
menuconfig.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-23 17:28:18 -04:00
6af5520fe1 doc: verified-boot: fix crypto algorithm examples
As you see in crypto_algos in common/image-sig.c, the algorithm
should be either "rsa2048" or "rsa4096".  "rs2048" is a typo.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-23 17:28:18 -04:00
16067e6b87 tools: image: fix node name of signature node in FIT
Both "conf_name" and "sig_name" point to the name of config node.
The latter should be the name of the signature node.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-23 17:28:17 -04:00
3aca4a44f8 test/py: fix typos in README.md
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2017-10-23 17:28:17 -04:00
3a2605fa87 cmd: gpt: solve issue for swap and rename command
don't use prettyprint_part_size() in create_gpt_partitions_list()
that avoid to align offset and size to 1 MiB and increase precision for
start and size.
This patch avoid the risk to change partition size and lost data during
rename or swap.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-10-23 17:28:11 -04:00
0cf02ff612 test/py: gpt: test start LBA for sub-command rename and swap
Add test of first and last LBA in gpt for rename and swap.
Only the name is expected to change, so test 3 columns
for part command
1: first LBA (start)
2: last LBA (end)
3: partition name

After rename, the last LBA change and it is a error in current U-Boot code
+ "first" = 0x7ff : invalid value (<start)
+ "second" = 0x17ff => size increasing !

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-10-23 17:28:08 -04:00
b61a3b5c8d test/py: gpt: add test for sub-command write
+ test write for one partition on all the device (size=0)
+ test write with disk uuid and 2 partitions

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-10-23 17:27:58 -04:00
ae0e0228e6 disk: efi: correct the overlap check on GPT header and PTE
the partition starting at 0x4400 is refused with overlap error:
  $> gpt write mmc 0 "name=test,start=0x4400,size=0"
  Writing GPT: Partition overlap
  error!

even if the 0x4400 is the first available offset for LBA35 with default
value:
- MBR=LBA1
- GPT header=LBA2
- PTE= 32 LBAs (128 entry), 3 to 34

And the command to have one partition for all the disk failed also :
  $> gpt write mmc 0 "name=test,size=0"

After the patch :

  $> gpt write mmc 0 "name=test,size=0"
  Writing GPT: success!
  $> part list mmc 0

  Partition Map for MMC device 0  --   Partition Type: EFI

  Part	Start LBA	End LBA		Name
	Attributes
	Type GUID
	Partition GUID
  1	0x00000022	0x01ce9fde	"test"
	attrs:	0x0000000000000000
	type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
	type:	data
	guid:	b4b84b8a-04e3-4000-0036-aff5c9c495b1

And 0x22 = 34 LBA => offset = 0x4400 is accepted as expected

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-10-23 17:27:48 -04:00
30ef7cbb81 test/py: gpt: add test for sub-command read and verify
add sandbox test for some gpt sub-command
- gpt read / part list : read the gpt partition created by sgdisk on host
  test start, size, LBA and name output
- gpt verify : verify the gpt partition create by sgdisk on host

PS: persistent data test_gpt_disk_image.bin are udpated

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-10-23 17:27:42 -04:00
da4c4bbd61 test/py: gpt: copy persistent file
copy the persistent gpt binary file as it can be modified during the test
that avoid issue if the test fail: the test always restart with clean file

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-10-23 17:27:05 -04:00
6087be2ba6 rtc: mc146818: Correct alarm message for day alarm
RTC_CONFIG_D register contains the day within the month to generate
an alarm, not the month. This corrects the printf to indicate it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-23 17:25:40 -04:00
d17207ea83 chiliboard config: use CONFIG_DEFAULT_FDT_FILE as env variable
Remove hardcoded ftd file name from environment variables.
Use CONFIG_DEFAULT_FDT_FILE macro instead.

Signed-off-by: Michal Oleszczyk <m.oleszczyk@grinn-global.com>
2017-10-23 17:25:40 -04:00
3d569a807e simple-bus: remove DECLARE_GLOBAL_DATA_PTR
No global pointer is used in this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-23 17:25:40 -04:00
1e0d51a6c4 powerpc: mpc85xx: Implement CPU erratum A-007907 for secondary cores
Commit 06ad970b53 ("powerpc: mpc85xx: Implemente workaround for CPU
erratum A-007907") clears L1CSR2 for the boot core, but other cores
don't run through the workaround. Add similar code for secondary
cores to clear DCSTASHID field in L1CSR2 register.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-10-23 14:02:48 -07:00
8b7f4b9cc1 mtd: remove MTDDEBUG() and CONFIG_MTD_DEBUG
All users of this macro have been converted.  Remove MTDDEBUG and
related CONFIG options.

ubifs_dbg_msg_key() is kept.  It is silent unless DEBUG is defined.

I am not touching scripts/config_whitelist.txt.  The deprecated options
will be dropped by the next resync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 14:07:26 -04:00
166cae20dd mtd: replace MTDDEBUG() with pr_debug()
In old days, the MTD subsystem in Linux had debug facility like
DEBUG(MTD_DEBUG_LEVEL1, ...).

They were all replaced with pr_debug() until Linux 3.2.  See Linux
commit 289c05222172 ("mtd: replace DEBUG() with pr_debug()").

U-Boot still uses similar macros.  Covert all of them for easier sync.

Done with the help of Coccinelle.

The semantic patch I used is as follows:

// <smpl>
@@
expression e1, e2;
@@
-MTDDEBUG(e1, e2)
+pr_debug(e2)
@@
expression e1, e2;
@@
-MTDDEBUG(e1, e2,
+pr_debug(e2,
 ...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 14:07:26 -04:00
ce0dea889a Merge git://git.denx.de/u-boot-uniphier 2017-10-22 19:21:04 -04:00
624c0954c7 ARM: uniphier: use pr_*() more where appropriate
Commit dd74b945af ("ARM: uniphier: use pr_() instead of printf()
where appropriate"), but I missed to update this file for some reason.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:09:22 +09:00
9e19031ca3 doc: uniphier: add simple guide to Verified Boot
Add a simple documentation about how to use the Verified Boot on
UniPhier boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:09:22 +09:00
15d0f3538a ARM: uniphier: remove verify=n from environments
If the environment "verify" is set to n, the image verification
is entirely skipped.  Remove it as a preparation for verified boot.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
571e050b45 ARM: uniphier: increase CONFIG_SYS_BOOTM_LEN to 32MB
The default value of CONFIG_SYS_BOOTM_LEN, 0x800000, causes error
when uncompressing Image.gz out of FIT image.

   Uncompressing Kernel Image ... Error: inflate() returned -5
Image too large: increase CONFIG_SYS_BOOTM_LEN

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
272874879b ARM: dts: uniphier: sync DT with Linux 4.14-rc5
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
9ac0e7b37a ARM: uniphier: split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi
UniPhier 32-bit SoCs use CONFIG_SPL_OF_CONTROL.  So, many nodes must
be marked as dm-pre-reloc to prevent fdtgrep from stripping them off.

Sprinkling U-Boot-specific properties all over the place is painful
because DT files are synced with Linux from time to time.

Split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi, which is
appended to UniPhier V7 DTS before the build.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-23 01:02:05 +09:00
d0df9588e8 ARM: uniphier: remove CONFIG_UNIPHIER_ETH
The option is never enabled by anyone.  Remove the code surrounded
by its ifdef.  This should be handled by the clock/reset drivers.

CONFIG_UNIPHIER_ETH in scripts/config_whitelist.txt will be dropped
by the next resync.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
0b55abd34a ARM: uniphier: enable DWC3 xHCI driver really
I thought commit d37d31849c ("ARM: uniphier: enable DWC3 xHCI
driver") enabled CONFIG_USB_DWC3_UNIPHIER, but CONFIG_USB_XHCI_DWC3
was missing in uniphier_v7_defconfig.  Re-add.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 01:02:05 +09:00
23d51bef94 uniphier_ld4_sld8: Re-add SMC911X_BASE address
This was dropped by accident in the Kconfig conversion.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-21 10:26:34 -04:00
8daec2d9d3 net: Add SMC911X driver to Kconfig, convert
We add the various SMC91XX symbols to drivers/net/Kconfig and then this
converts the following to Kconfig:
   CONFIG_SMC911X
   CONFIG_SMC911X_BASE
   CONFIG_SMC911X_16_BIT
   CONFIG_SMC911X_32_BIT

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Apply to the rest of the tree, re-squash old and new patch]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-20 21:40:26 -04:00
0a9ef45158 Convert CONFIG_NAND_OMAP_GPMC et al and CONFIG_NAND_MXC to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND_MXC
   CONFIG_NAND_OMAP_GPMC
   CONFIG_NAND_OMAP_GPMC_PREFETCH
   CONFIG_NAND_OMAP_ELM
   CONFIG_SPL_NAND_AM33XX_BCH
   CONFIG_SPL_NAND_SIMPLE
   CONFIG_SYS_NAND_BUSWIDTH_16BIT

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues,
        add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-20 16:44:07 -04:00
0def58f7fd Merge git://git.denx.de/u-boot-x86 2017-10-19 11:19:38 -04:00
9af43acba6 x86: conga-qeval20-qa3-e3845-internal-uart_defconfig: Add ACPI resume support
I've missed to add the ACPI resume support to this x86 build target.
This patch adds the ACPI resume support enabling S3 suspend /
resume.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-19 11:37:51 +08:00
871aa41d4c x86: provide CONFIG_BUILD_ROM
Up to now we depended on an exported variable to build u-boot.rom.
We should be able to specify it in the configuration file, too.

With this patch this becomes possible using the new Kconfig option
CONFIG_BUILD_ROM.

This option depends on CONFIG_X86 and is selected in
qemu-x86_defconfig and qemu-x86_64_defconfig.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-19 11:37:51 +08:00
83262f99cd x86: baytrail: fsp: Move Azalia update codes to board
Azalia configuration may be different across boards, hence it's not
appropriate to do that in the SoC level. Instead, let's make the
SoC update_fsp_azalia_configs() routine as a weak version, and do
the actual work in the board codes.

So far it seems only som-db5800-som-6867 board enables the Azalia.
Move the original codes into som-db5800-som-6867.c.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
f6859558ca x86: baytrail: fsp: Use a function to update the Azalia config pointer
At present we directly pass the Azalia config pointer to the FSP UPD.
This updates to use a function to do the stuff, like Braswell does.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
abddcd52ab x86: fsp: Consolidate Azalia header file
So far there are two copies of Azalia struct defines with one in
baytrail and the other one in braswell. This consolidates these
two into one, put it in the common place, and remove the prefix
pch_ to these structs to make their names more generic.

This also corrects reset_wait_timer from us to ms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
3322a8e1a3 x86: Turn off running VGA ROM during S3 resume
This is only needed when graphics console is used. For kernel with
native graphics driver, this can be turned off to speed up.

Change this option's default to n in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
febdfaabc7 x86: baytrail: Fix unstable ACPI S3 resume
It was observed that when booting a Ubuntu 16.04 kernel, doing ACPI
S3 suspend/resume sometimes causes the Ubuntu kernel hang forever.
The issue is however not reproduced with a kernel built from i386/
x86_64 defconfig configuration.

The unstability is actually caused by unexpected interrupts being
generated during the S3 resume. For some unknown reason, FSP (gold4)
for BayTrail configures the GPIO DFX5 PAD to enable level interrupt
(bit 24 and 25). As this pin keeps generating interrupts during an
S3 resume, and there is no IRQ requester in the kernel to handle it,
the kernel seems to hang and does not continue resuming.

Clear the mysterious interrupt bits for this pin.

Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
917d3565b5 x86: minnowmax: Adjust VGA rom address
Adjust VGA rom address to 0xfffb0000 so that u-boot.rom image
can be built again.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
6b0fea3342 Merge git://git.denx.de/u-boot-i2c 2017-10-18 09:32:35 -04:00
002e91087c Merge git://git.denx.de/u-boot-spi 2017-10-18 09:32:21 -04:00
d10bd6cfd8 i2c: stm32f7_i2c: fix usage of useless local variable
Remove useless local variable "s" and use directly
function's parameter "output"

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-17 11:28:41 +02:00
81c4843763 i2c: stm32f7_i2c: fix data abort
As "v" is a local variable in stm32_i2c_choose_solution()
"v" has to be copied into "s" to avoid data abort in
stm32_i2c_compute_timing().

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-17 11:28:27 +02:00
c4e5990ad2 i2c: remove DECLARE_GLOBAL_DATA_PTR from i2c-uclass
No global pointer is used in this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2017-10-17 11:27:42 +02:00
ca1ac16da0 sf: bar: Clean BA24 Bank Address Register bit after read/write/erase operation
The content of Bank Address Register (BAR) is volatile. It is cleared
after power cycle or reset command (RESET F0h).

Some memories (like e.g. s25fl256s) use it to access memory larger than
0x1000000 (16 MiB).

The problem shows up when one:

1. Reads/writes/erases memory > 16 MiB
2. Calls "reset" u-boot command (which is not causing BAR to be cleared)

In the above scenario, the SoC ROM sends 0x000000 address to read SPL.
Unfortunately, the BA24 bit is still set and hence it receives content
from 0x1000000 (16 MiB) memory address.
As a result the SoC aborts and we hang. Only power cycle can take the
SoC out of this state.

How to reproduce/test:

sf probe; sf erase 0x1200000 0x800000; reset
sf probe; sf erase 0x1200000 0x800000; sf write 0x11000000 0x1200000 0x800000; reset
sf probe; sf read 0x11000000 0x1200000 0x800000; reset

Signed-off-by: Lukasz Majewski <lukma@denx.de>
[Fixed comment text on clean_bar function]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-27 13:31:59 +05:30
ba09440131 SPL: SPI: sunxi: add SPL FIT image support
The sunxi-specific SPI load routine only knows how to load a legacy
U-Boot image.
Teach it how to handle FIT images as well, simply by providing the
existing SPL FIT loader with the right loader routine to access the SPI
NOR flash.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Peter Kosa <kope@madnet.sk>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-27 12:45:32 +05:30
930 changed files with 5939 additions and 3916 deletions

15
Kconfig
View File

@ -14,6 +14,12 @@ source "arch/Kconfig"
menu "General setup"
config BROKEN
bool
help
This option cannot be enabled. It is used as dependency
for broken and incomplete features.
config LOCALVERSION
string "Local version - append to U-Boot release"
help
@ -158,6 +164,15 @@ config PHYS_64BIT
This can be used not only for 64bit SoCs, but also for
large physical address extention on 32bit SoCs.
config BUILD_ROM
bool "Build U-Boot as BIOS replacement"
depends on X86
help
This option allows to build a ROM version of U-Boot.
The build process generally requires several binary blobs
which are not shipped in the U-Boot source tree.
Please, see doc/README.x86 for details.
endmenu # General setup
menu "Boot images"

View File

@ -5,7 +5,7 @@
VERSION = 2017
PATCHLEVEL = 11
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION =
NAME =
# *DOCUMENTATION*
@ -796,7 +796,7 @@ ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
ALL-$(CONFIG_EFI_APP) += u-boot-app.efi
ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi
ifneq ($(BUILD_ROM),)
ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
endif

15
README
View File

@ -1028,21 +1028,6 @@ The following options need to be configured:
control registers. This behavior won't affect the
correctnessof 10/100 link speed update.
CONFIG_SMC911X
Support for SMSC's LAN911x and LAN921x chips
CONFIG_SMC911X_BASE
Define this to hold the physical address
of the device (I/O space)
CONFIG_SMC911X_32_BIT
Define this if data bus is 32 bits
CONFIG_SMC911X_16_BIT
Define this if data bus is 16 bits. If your processor
automatically converts one 32 bit word to two 16 bit
words you may also try CONFIG_SMC911X_32_BIT.
CONFIG_SH_ETHER
Support for Renesas on-chip Ethernet controller

View File

@ -341,17 +341,6 @@ config TARGET_WORK_92105
select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_MX25PDK
bool "Support mx25pdk"
select BOARD_LATE_INIT
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
config TARGET_ZMX25
bool "Support zmx25"
select BOARD_LATE_INIT
select CPU_ARM926EJS
config TARGET_APF27
bool "Support apf27"
select CPU_ARM926EJS
@ -599,6 +588,10 @@ config ARCH_MESON
targeted at media players and tablet computers. We currently
support the S905 (GXBaby) 64-bit SoC.
config ARCH_MX25
bool "NXP MX25"
select CPU_ARM926EJS
config ARCH_MX7ULP
bool "NXP MX7ULP"
select CPU_V7
@ -698,6 +691,7 @@ config ARCH_SUNXI
select SPL_SYS_MALLOC_SIMPLE if SPL
select SYS_NS16550
select SPL_SYS_THUMB_BUILD if !ARM64
select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
select USB_STORAGE if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS
@ -1161,6 +1155,8 @@ source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx2/Kconfig"
source "arch/arm/mach-imx/mx7ulp/Kconfig"
source "arch/arm/mach-imx/mx7/Kconfig"
@ -1243,7 +1239,6 @@ source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
source "board/freescale/mx31ads/Kconfig"
source "board/freescale/mx31pdk/Kconfig"
@ -1269,7 +1264,6 @@ source "board/spear/spear320/Kconfig"
source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/birdland/bav335x/Kconfig"
source "board/timll/devkit3250/Kconfig"

View File

@ -1,6 +1,6 @@
#
# (C) Copyright 2014
# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
#
# SPDX-License-Identifier: GPL-2.0+
#

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2017
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2017
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -490,3 +490,10 @@ config SYS_MC_RSV_MEM_ALIGN
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
config HAS_FSL_XHCI_USB
bool
default y if ARCH_LS1043A || ARCH_LS1046A
help
For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
pins, select it when the pins are assigned to USB.

View File

@ -35,6 +35,7 @@ int ppa_init(void)
unsigned int el = current_el();
void *ppa_fit_addr;
u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
u32 *loadable_l, *loadable_h;
int ret;
#ifdef CONFIG_CHAIN_OF_TRUST
@ -240,9 +241,9 @@ int ppa_init(void)
PPA_KEY_HASH,
&ppa_img_addr);
if (ret != 0)
printf("PPA validation failed\n");
printf("SEC firmware(s) validation failed\n");
else
printf("PPA validation Successful\n");
printf("SEC firmware(s) validation Successful\n");
}
#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
@ -254,15 +255,24 @@ int ppa_init(void)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
boot_loc_ptr_l = &gur->bootlocptrl;
boot_loc_ptr_h = &gur->bootlocptrh;
/* Assign addresses to loadable ptrs */
loadable_l = &gur->scratchrw[4];
loadable_h = &gur->scratchrw[5];
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
boot_loc_ptr_l = &scfg->scratchrw[1];
boot_loc_ptr_h = &scfg->scratchrw[0];
/* Assign addresses to loadable ptrs */
loadable_l = &scfg->scratchrw[2];
loadable_h = &scfg->scratchrw[3];
#endif
debug("fsl-ppa: boot_loc_ptr_l = 0x%p, boot_loc_ptr_h =0x%p\n",
boot_loc_ptr_l, boot_loc_ptr_h);
ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h);
ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h,
loadable_l, loadable_h);
#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)

View File

@ -105,6 +105,74 @@ static int sec_firmware_parse_image(const void *sec_firmware_img,
return 0;
}
/*
* SEC Firmware FIT image parser to check if any loadable is
* present. If present, verify integrity of the loadable and
* copy loadable to address provided in (loadable_h, loadable_l).
*
* Returns 0 on success and a negative errno on error task fail.
*/
static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
u32 *loadable_l, u32 *loadable_h)
{
phys_addr_t sec_firmware_loadable_addr = 0;
int conf_node_off, ld_node_off;
char *conf_node_name = NULL;
const void *data;
size_t size;
ulong load;
conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
if (conf_node_off < 0) {
printf("SEC Firmware: %s: no such config\n", conf_node_name);
return -ENOENT;
}
ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
FIT_LOADABLE_PROP);
if (ld_node_off >= 0) {
printf("SEC Firmware: '%s' present in config\n",
FIT_LOADABLE_PROP);
/* Verify secure firmware image */
if (!(fit_image_verify(sec_firmware_img, ld_node_off))) {
printf("SEC Loadable: Bad loadable image (bad CRC)\n");
return -EINVAL;
}
if (fit_image_get_data(sec_firmware_img, ld_node_off,
&data, &size)) {
printf("SEC Loadable: Can't get subimage data/size");
return -ENOENT;
}
/* Get load address, treated as load offset to secure memory */
if (fit_image_get_load(sec_firmware_img, ld_node_off, &load)) {
printf("SEC Loadable: Can't get subimage load");
return -ENOENT;
}
/* Compute load address for loadable in secure memory */
sec_firmware_loadable_addr = (sec_firmware_addr -
gd->arch.tlb_size) + load;
/* Copy loadable to secure memory and flush dcache */
debug("%s copied to address 0x%p\n",
FIT_LOADABLE_PROP, (void *)sec_firmware_loadable_addr);
memcpy((void *)sec_firmware_loadable_addr, data, size);
flush_dcache_range(sec_firmware_loadable_addr,
sec_firmware_loadable_addr + size);
}
/* Populate address ptrs for loadable image with loadbale addr */
out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK));
out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT));
return 0;
}
static int sec_firmware_copy_image(const char *title,
u64 image_addr, u32 image_size, u64 sec_firmware)
{
@ -117,9 +185,11 @@ static int sec_firmware_copy_image(const char *title,
/*
* This function will parse the SEC Firmware image, and then load it
* to secure memory.
* to secure memory. Also load any loadable if present along with SEC
* Firmware image.
*/
static int sec_firmware_load_image(const void *sec_firmware_img)
static int sec_firmware_load_image(const void *sec_firmware_img,
u32 *loadable_l, u32 *loadable_h)
{
const void *raw_image_addr;
size_t raw_image_size = 0;
@ -172,6 +242,15 @@ static int sec_firmware_load_image(const void *sec_firmware_img)
if (ret)
goto out;
/*
* Check if any loadable are present along with firmware image, if
* present load them.
*/
ret = sec_firmware_check_copy_loadable(sec_firmware_img, loadable_l,
loadable_h);
if (ret)
goto out;
sec_firmware_addr |= SEC_FIRMWARE_LOADED;
debug("SEC Firmware: Entry point: 0x%llx\n",
sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK);
@ -289,17 +368,22 @@ int sec_firmware_get_random(uint8_t *rand, int bytes)
* @sec_firmware_img: the SEC Firmware image address
* @eret_hold_l: the address to hold exception return address low
* @eret_hold_h: the address to hold exception return address high
* @loadable_l: the address to hold loadable address low
* @loadable_h: the address to hold loadable address high
*/
int sec_firmware_init(const void *sec_firmware_img,
u32 *eret_hold_l,
u32 *eret_hold_h)
u32 *eret_hold_h,
u32 *loadable_l,
u32 *loadable_h)
{
int ret;
if (!sec_firmware_is_valid(sec_firmware_img))
return -EINVAL;
ret = sec_firmware_load_image(sec_firmware_img);
ret = sec_firmware_load_image(sec_firmware_img, loadable_l,
loadable_h);
if (ret) {
printf("SEC Firmware: Failed to load image\n");
return ret;

View File

@ -309,6 +309,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic-edition.dtb \
sun8i-r16-parrot.dtb
dtb-$(CONFIG_MACH_SUN8I_A83T) += \

View File

@ -124,8 +124,8 @@
ldo15_reg: LDO15 {
regulator-name = "vdd_ldo15";
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
@ -137,7 +137,7 @@
};
ldo17_reg: LDO17 {
regulator-name = "tsp_avdd";
regulator-name = "vdd_ldo17";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;

View File

@ -76,6 +76,20 @@
num-cs = <4>;
};
usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 80 0x4>; /* Level high type */
dr_mode = "host";
};
usb1: usb3@3110000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
};
pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */

View File

@ -0,0 +1,18 @@
/*
* Copyright 2017
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/dts-v1/;
#include "imx6q.dtsi"
/ {
model = "Liebherr (LWN) display5 i.MX6 Quad Board";
compatible = "lwn,display5", "fsl,imx6q";
};

View File

@ -68,7 +68,7 @@
phy-supply = <&vcc33_io>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <2 10000 50000>;
assigned-clocks = <&cru SCLK_MAC>;

View File

@ -332,10 +332,10 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
regulator-suspend-microvolt = <3000000>;
};
};

View File

@ -36,13 +36,13 @@
module_led {
label = "module_led";
gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
sd_card_led {
label = "sd_card_led";
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
};
@ -94,8 +94,7 @@
compatible = "regulator-fixed";
regulator-name = "usbhub_enable";
enable-active-low;
gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
regulator-always-on;
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -111,8 +110,8 @@
compatible = "regulator-fixed";
u-boot,dm-pre-reloc;
regulator-name = "bios_enable";
enable-active-low;
gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@ -140,7 +139,7 @@
vcc5v0_otg: vcc5v0-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc5v0_otg";
@ -150,7 +149,7 @@
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-low;
gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc5v0_host";
@ -196,7 +195,7 @@
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <2 10000 50000>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
@ -224,7 +223,7 @@
vdd_gpu: fan535555@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "fan53555-reg";
regulator-name = "vdd_gpu";
@ -348,11 +347,11 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
regulator-suspend-microvolt = <3000000>;
};
};
@ -426,7 +425,7 @@
vdd_cpu_b: fan53555@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
vsel-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "fan53555-reg";
regulator-name = "vdd_cpu_b";
@ -469,7 +468,7 @@
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
assigned-clock-rates = <100000000>;
ep-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;
@ -524,23 +523,23 @@
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&dwc3_typec0 {
status = "disabled";
};
&usb_host1_ehci {
&usb_host0_ohci {
status = "disabled";
};
&dwc3_typec0 {
status = "okay";
};
&usb_host1_ehci {
status = "disabled";
};
&usb_host1_ohci {
status = "okay";
status = "disabled";
};
&dwc3_typec1 {
@ -564,42 +563,43 @@
puma_pin_hog: puma_pin_hog {
rockchip,pins =
/* We need pull-ups on Q7 buttons */
<0 4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
<0 10 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
<0 11 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
<0 9 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
<RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
<RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
<RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
<RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 22 RK_FUNC_GPIO &pcfg_pull_up>;
<RK_GPIO1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds_pins_puma: led_pins@0 {
rockchip,pins =
<2 25 RK_FUNC_GPIO &pcfg_pull_none>,
<1 2 RK_FUNC_GPIO &pcfg_pull_none>;
<RK_GPIO2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
<RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb2 {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins =
<0 2 RK_FUNC_GPIO &pcfg_pull_none>;
<RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
host_vbus_drv: host-vbus-drv {
rockchip,pins =
<0 2 RK_FUNC_GPIO &pcfg_pull_none>;
<RK_GPIO4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
i2c8 {
i2c8_xfer_a: i2c8-xfer {
rockchip,pins = <1 21 RK_FUNC_1 &pcfg_pull_up>,
<1 20 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins =
<RK_GPIO1 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
};
};
};
@ -624,8 +624,8 @@
&i2c6_xfer {
/* Enable pull-ups, the pins would float otherwise. */
rockchip,pins =
<2 10 RK_FUNC_2 &pcfg_pull_up>,
<2 9 RK_FUNC_2 &pcfg_pull_up>;
<RK_GPIO2 RK_PB2 RK_FUNC_2 &pcfg_pull_up>,
<RK_GPIO2 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
};
&i2c7 {

View File

@ -438,7 +438,7 @@
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
power-source = <1800>;
};
sdhi2_pins_uhs: sd2_uhs {

View File

@ -0,0 +1,321 @@
/*
* Copyright (c) 2017 Free Electrons <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-a33.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "BananaPi M2 Magic";
compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
blue {
label = "bpi-m2m:blue:usr";
gpios = <&pio 2 7 GPIO_ACTIVE_LOW>;
};
green {
label = "bpi-m2m:green:usr";
gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>;
};
red {
label = "bpi-m2m:red:power";
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
reg_vcc5v0: vcc5v0 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
};
};
&codec {
status = "okay";
};
&cpu0 {
cpu-supply = <&reg_dcdc3>;
};
&cpu0_opp_table {
opp@1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <1320000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1320000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
};
&dai {
status = "okay";
};
&ehci0 {
status = "okay";
};
/* This is the i2c bus exposed on the DSI connector for the touch panel */
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "disabled";
};
/* This is the i2c bus exposed on the GPIO header */
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "disabled";
};
/* This is the i2c bus exposed on the CSI connector to control the sensor */
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "disabled";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_aldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&ohci0 {
status = "okay";
};
&r_rsb {
status = "okay";
axp22x: pmic@3a3 {
compatible = "x-powers,axp223";
reg = <0x3a3>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <&reg_dcdc1>;
x-powers,drive-vbus-en;
};
};
#include "axp223.dtsi"
&ac_power_supply {
status = "okay";
};
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-io";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vdd-dll";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_dc1sw {
regulator-name = "vcc-lcd";
};
&reg_dc5ldo {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpus";
};
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-3v0";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-sys";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpu";
};
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc-dram";
};
/*
* Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same
* time, with the two being in sync. Since this is not really
* supported right now, just use the two as always on, and we will fix
* it later.
*/
&reg_dldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi0";
};
&reg_dldo2 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi1";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&sound {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usb_power_supply {
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus-supply = <&reg_vcc5v0>;
status = "okay";
};

View File

@ -1,5 +1,14 @@
#include <config.h>
/*
* This is the maximum size the U-Boot binary can be, which is basically
* the start of the environment, minus the start of the U-Boot binary in
* the MMC. This makes the assumption that the MMC is using 512-bytes
* blocks, but devices using something other than that remains to be
* seen.
*/
#define UBOOT_MMC_MAX_SIZE (CONFIG_ENV_OFFSET - (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512))
/ {
binman {
filename = "u-boot-sunxi-with-spl.bin";
@ -8,6 +17,9 @@
filename = "spl/sunxi-spl.bin";
};
u-boot-img {
#ifdef CONFIG_MMC
size = <UBOOT_MMC_MAX_SIZE>;
#endif
pos = <CONFIG_SPL_PAD_TO>;
};
};

View File

@ -175,6 +175,19 @@
"gpio_range4",
"gpio_range5";
ngpios = <200>;
socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
<21 217 3>;
};
adamv@57920000 {
compatible = "socionext,uniphier-ld11-adamv",
"simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
adamv_rst: reset {
compatible = "socionext,uniphier-ld11-adamv-reset";
#reset-cells = <1>;
};
};
i2c0: i2c@58780000 {

View File

@ -223,6 +223,36 @@
clock-frequency = <58820000>;
};
gpio: gpio@55000000 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000000 0x200>;
interrupt-parent = <&aidet>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 96 0 0>,
<&pinctrl 160 0 0>;
gpio-ranges-group-names = "gpio_range0",
"gpio_range1",
"gpio_range2";
ngpios = <205>;
socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
<21 217 3>;
};
adamv@57920000 {
compatible = "socionext,uniphier-ld20-adamv",
"simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
adamv_rst: reset {
compatible = "socionext,uniphier-ld20-adamv-reset";
#reset-cells = <1>;
};
};
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";

View File

@ -69,11 +69,6 @@
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
&nand {
status = "okay";
};

View File

@ -50,7 +50,6 @@
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
@ -295,11 +294,9 @@
compatible = "socionext,uniphier-ld4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld4-pinctrl";
u-boot,dm-pre-reloc;
};
};

View File

@ -71,11 +71,6 @@
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
&nand {
status = "okay";
};

View File

@ -23,6 +23,21 @@
function = "emmc";
};
pinctrl_ether_mii: ether_mii_grp {
groups = "ether_mii";
function = "ether_mii";
};
pinctrl_ether_rgmii: ether_rgmii_grp {
groups = "ether_rgmii";
function = "ether_rgmii";
};
pinctrl_ether_rmii: ether_rmii_grp {
groups = "ether_rmii";
function = "ether_rmii";
};
pinctrl_i2c0: i2c0_grp {
groups = "i2c0";
function = "i2c0";

View File

@ -90,12 +90,3 @@
&usb3 {
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

View File

@ -83,12 +83,3 @@
&usb1 {
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

View File

@ -85,24 +85,3 @@
&usb3 {
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&mio_clk {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};
&pinctrl_emmc {
u-boot,dm-pre-reloc;
};

View File

@ -58,7 +58,6 @@
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
@ -224,7 +223,6 @@
compatible = "socionext,uniphier-pro4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
u-boot,dm-pre-reloc;
mio_clk: clock {
compatible = "socionext,uniphier-pro4-mio-clock";
@ -333,11 +331,9 @@
compatible = "socionext,uniphier-pro4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-pro4-pinctrl";
u-boot,dm-pre-reloc;
};
};

View File

@ -55,12 +55,3 @@
&sd {
status = "okay";
};
/* for U-Boot only */
&serial1 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};

View File

@ -132,7 +132,6 @@
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
@ -311,7 +310,6 @@
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
u-boot,dm-pre-reloc;
sd_clk: clock {
compatible = "socionext,uniphier-pro5-sd-clock";
@ -344,11 +342,9 @@
compatible = "socionext,uniphier-pro5-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-pro5-pinctrl";
u-boot,dm-pre-reloc;
};
};

View File

@ -66,24 +66,3 @@
&usb1 {
status = "okay";
};
/* for U-Boot only */
&serial2 {
u-boot,dm-pre-reloc;
};
&sd_clk {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&pinctrl_uart2 {
u-boot,dm-pre-reloc;
};
&pinctrl_emmc {
u-boot,dm-pre-reloc;
};

View File

@ -49,24 +49,3 @@
&usb0 {
status = "okay";
};
/* for U-Boot only */
&serial2 {
u-boot,dm-pre-reloc;
};
&sd_clk {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&pinctrl_uart2 {
u-boot,dm-pre-reloc;
};
&pinctrl_emmc {
u-boot,dm-pre-reloc;
};

View File

@ -120,7 +120,6 @@
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
@ -297,7 +296,6 @@
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
u-boot,dm-pre-reloc;
sd_clk: clock {
compatible = "socionext,uniphier-pxs2-sd-clock";
@ -365,11 +363,9 @@
compatible = "socionext,uniphier-pxs2-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-pxs2-pinctrl";
u-boot,dm-pre-reloc;
};
};

View File

@ -68,3 +68,7 @@
&usb1 {
status = "okay";
};
&nand {
status = "okay";
};

View File

@ -73,11 +73,6 @@
status = "okay";
};
/* for U-Boot only */
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
&nand {
status = "okay";
};

View File

@ -50,7 +50,6 @@
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
@ -299,11 +298,9 @@
compatible = "socionext,uniphier-sld8-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-sld8-pinctrl";
u-boot,dm-pre-reloc;
};
};

View File

@ -0,0 +1,61 @@
/ {
soc {
u-boot,dm-pre-reloc;
serial@54006800 {
u-boot,dm-pre-reloc;
};
serial@54006900 {
u-boot,dm-pre-reloc;
};
serial@54006a00 {
u-boot,dm-pre-reloc;
};
mioctrl@59810000 {
u-boot,dm-pre-reloc;
clock {
u-boot,dm-pre-reloc;
};
};
sdctrl@59810000 {
u-boot,dm-pre-reloc;
clock {
u-boot,dm-pre-reloc;
};
};
soc-glue@5f800000 {
u-boot,dm-pre-reloc;
pinctrl {
u-boot,dm-pre-reloc;
emmc_grp {
u-boot,dm-pre-reloc;
};
uart0_grp {
u-boot,dm-pre-reloc;
};
uart1_grp {
u-boot,dm-pre-reloc;
};
uart2_grp {
u-boot,dm-pre-reloc;
};
};
};
};
};
&emmc {
u-boot,dm-pre-reloc;
};

View File

@ -16,7 +16,7 @@
* Reserve secure memory
* To be aligned with MMU block size
*/
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A

View File

@ -4,5 +4,9 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SYS_PROTO_IMX5_
#define __SYS_PROTO_IMX5_
#include <asm/mach-imx/sys_proto.h>
#endif /* __SYS_PROTO_IMX5_ */

View File

@ -346,6 +346,9 @@
#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
#endif
#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000)
/* Only for i.MX6SX */
#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)

View File

@ -178,4 +178,17 @@
|IOMUXC_GPR13_SATA_PHY_3_MASK \
|IOMUXC_GPR13_SATA_PHY_2_MASK \
|IOMUXC_GPR13_SATA_PHY_1_MASK)
/*
* Setup RGMII voltage levels on iMX6 SoC - the
*
* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - register
*
* 1P2V_IO - USB_HSIC, MIPI_HSI
* 1P5V_IO - ENET pins
*/
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x020e0790
#define DDR_SEL_1P2V_IO (0x2 << 18)
#define DDR_SEL_1P5V_IO (0x3 << 18)
#endif /* __ASM_ARCH_IOMUX_H__ */

View File

@ -5,7 +5,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SYS_PROTO_IMX6_
#define __SYS_PROTO_IMX6_
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch/iomux.h>
#define USBPHY_PWD 0x00000000
@ -16,3 +20,15 @@
int imx6_pcie_toggle_power(void);
int imx6_pcie_toggle_reset(void);
/**
* iomuxc_set_rgmii_io_voltage - set voltage level of RGMII/USB pins
*
* @param io_vol - the voltage IO level of pins
*/
static inline void iomuxc_set_rgmii_io_voltage(int io_vol)
{
__raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII);
}
#endif /* __SYS_PROTO_IMX6_ */

View File

@ -3,8 +3,12 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SYS_PROTO_IMX7_
#define __SYS_PROTO_IMX7_
#include <asm/mach-imx/sys_proto.h>
void set_wdog_reset(struct wdog_regs *wdog);
enum boot_device get_boot_device(void);
#endif /* __SYS_PROTO_IMX7_ */

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2010
* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
* Copyright (C) 2010, STMicroelectronics - All Rights Reserved
* Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2009
* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
* Copyright (C) 2009, STMicroelectronics - All Rights Reserved
* Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,5 +1,6 @@
/*
* (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com>
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2017
* Patrice Chotard <patrice.chotard@st.com>
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2016
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2016
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2016
* Vikas Manocha, <vikas.manocha@st.com>
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2016
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2016
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2016
* Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2016
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2016
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* Copyright (C) STMicroelectronics SA 2017
* Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* Copyright (C) STMicroelectronics SA 2017
* Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2014
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -158,7 +158,7 @@ struct sunxi_ccm_reg {
#define CPU_CLK_SRC_OSC24M 0
#define CPU_CLK_SRC_PLL1 1
#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0xff) << 8)
#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8)
#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
#define CMM_PLL1_CLOCK_TIME_2 (0x2 << 24)

View File

@ -124,5 +124,8 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
const struct display_timing *mode,
bool ext_hvsync, bool is_composite);
void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon,
int dotclock, int *clk_div, int *clk_double,
bool is_composite);
#endif /* _LCDC_H */

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2017
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -9,8 +9,10 @@
#define PSCI_INVALID_VER 0xffffffff
#define SEC_JR3_OFFSET 0x40000
#define WORD_MASK 0xffffffff
#define WORD_SHIFT 32
int sec_firmware_init(const void *, u32 *, u32 *);
int sec_firmware_init(const void *, u32 *, u32 *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
bool sec_firmware_support_hwrng(void);

View File

@ -0,0 +1,30 @@
if ARCH_MX25
config MX25
bool
default y
select SYS_FSL_ERRATUM_ESDHC_A001
choice
prompt "MX25 board select"
optional
config TARGET_MX25PDK
bool "Support mx25pdk"
select BOARD_LATE_INIT
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
config TARGET_ZMX25
bool "Support zmx25"
select BOARD_LATE_INIT
select CPU_ARM926EJS1
endchoice
config SYS_SOC
default "mx25"
source "board/freescale/mx25pdk/Kconfig"
source "board/syteco/zmx25/Kconfig"
endif

View File

@ -6,6 +6,7 @@ config MX5
config MX51
bool
select SYS_FSL_ERRATUM_ESDHC_A001
config MX53
bool
@ -52,7 +53,6 @@ config TARGET_MX53SMD
config TARGET_TS4800
bool "Support TS4800"
select MX51
select SYS_FSL_ERRATUM_ESDHC_A001
config TARGET_USBARMORY
bool "Support USB armory"

View File

@ -138,6 +138,12 @@ config TARGET_DHCOMIMX6
select DM_THERMAL
imply CMD_SPL
config TARGET_DISPLAY5
bool "LWN DISPLAY5 board"
select SUPPORT_SPL
select DM
select DM_SERIAL
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
select BOARD_LATE_INIT
@ -459,6 +465,7 @@ source "board/phytec/pfla02/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/samtec/vining_2000/Kconfig"
source "board/liebherr/display5/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"

View File

@ -11,6 +11,7 @@ config OMAP34XX
select ARM_ERRATA_621766
select ARM_ERRATA_725233
select USE_TINY_PRINTF
imply NAND_OMAP_GPMC
imply SPL_EXT_SUPPORT
imply SPL_FAT_SUPPORT
imply SPL_GPIO_SUPPORT
@ -30,6 +31,8 @@ config OMAP34XX
config OMAP44XX
bool "OMAP44XX SoC"
select USE_TINY_PRINTF
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_DISPLAY_PRINT
imply SPL_EXT_SUPPORT
imply SPL_FAT_SUPPORT
@ -39,6 +42,7 @@ config OMAP44XX
imply SPL_LIBDISK_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_MMC_SUPPORT
imply SPL_NAND_SIMPLE
imply SPL_NAND_SUPPORT
imply SPL_POWER_SUPPORT
imply SPL_SERIAL_SUPPORT
@ -49,6 +53,8 @@ config OMAP54XX
bool "OMAP54XX SoC"
select ARM_ERRATA_798870
select SYS_THUMB_BUILD
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_DISPLAY_PRINT
imply SPL_ENV_SUPPORT
imply SPL_EXT_SUPPORT
@ -59,6 +65,8 @@ config OMAP54XX
imply SPL_LIBDISK_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_MMC_SUPPORT
imply SPL_NAND_AM33XX_BCH
imply SPL_NAND_AM33XX_BCH
imply SPL_NAND_SUPPORT
imply SPL_POWER_SUPPORT
imply SPL_SERIAL_SUPPORT
@ -73,6 +81,8 @@ config TI814X
config TI816X
bool "TI816X SoC"
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
help
Support for AM335x SOC from Texas Instruments.
The AM335x high performance SOC features a Cortex-A8
@ -80,8 +90,12 @@ config TI816X
config AM43XX
bool "AM43XX SoC"
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_DM
imply SPL_DM_SEQ_ALIAS
imply SPL_NAND_AM33XX_BCH
imply SPL_NAND_SUPPORT
imply SPL_OF_CONTROL
imply SPL_OF_TRANSLATE
imply SPL_SEPARATE_BSS
@ -97,6 +111,10 @@ config AM43XX
config AM33XX
bool "AM33XX SoC"
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_NAND_AM33XX_BCH
imply SPL_NAND_SUPPORT
imply SYS_I2C_OMAP24XX
imply SYS_THUMB_BUILD
imply USE_TINY_PRINTF

View File

@ -1,7 +1,7 @@
if RCAR_32
choice
prompt "Renesus ARM SoCs board select"
prompt "Renesas ARM SoCs board select"
optional
config TARGET_ARMADILLO_800EVA

View File

@ -25,7 +25,7 @@ void *rockchip_get_cru(void)
if (ret)
return ERR_PTR(ret);
priv = devfdt_get_addr_ptr(dev);
priv = dev_get_priv(dev);
return priv->cru;
}

View File

@ -1,6 +1,6 @@
#
# (C) Copyright 2016
# Vikas Manocha, <vikas.manocha@gmail.com>
# Copyright (C) 2016, STMicroelectronics - All Rights Reserved
# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
#
# SPDX-License-Identifier: GPL-2.0+
#

View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2016
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

View File

@ -1,6 +1,6 @@
#
# Copyright (c) 2017
# Patrice Chotard <patrice.chotard@st.com>
# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
#
# SPDX-License-Identifier: GPL-2.0+
#

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@ -1,6 +1,6 @@
/*
* Copyright (C) STMicroelectronics SA 2017
* Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/

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@ -606,7 +606,7 @@ config AXP_GPIO
---help---
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
config VIDEO
config VIDEO_SUNXI
bool "Enable graphical uboot console on HDMI, LCD or VGA"
depends on !MACH_SUN8I_A83T
depends on !MACH_SUNXI_H3_H5
@ -614,6 +614,8 @@ config VIDEO
depends on !MACH_SUN8I_V3S
depends on !MACH_SUN9I
depends on !MACH_SUN50I
select VIDEO
imply VIDEO_DT_SIMPLEFB
default y
---help---
Say Y here to add support for using a cfb console on the HDMI, LCD
@ -622,21 +624,21 @@ config VIDEO
config VIDEO_HDMI
bool "HDMI output support"
depends on VIDEO && !MACH_SUN8I
depends on VIDEO_SUNXI && !MACH_SUN8I
default y
---help---
Say Y here to add support for outputting video over HDMI.
config VIDEO_VGA
bool "VGA output support"
depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
default n
---help---
Say Y here to add support for outputting video over VGA.
config VIDEO_VGA_VIA_LCD
bool "VGA via LCD controller support"
depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
default n
---help---
Say Y here to add support for external DACs connected to the parallel
@ -663,14 +665,14 @@ config VIDEO_VGA_EXTERNAL_DAC_EN
config VIDEO_COMPOSITE
bool "Composite video output support"
depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
default n
---help---
Say Y here to add support for outputting composite video.
config VIDEO_LCD_MODE
string "LCD panel timing details"
depends on VIDEO
depends on VIDEO_SUNXI
default ""
---help---
LCD panel timing details string, leave empty if there is no LCD panel.
@ -680,14 +682,14 @@ config VIDEO_LCD_MODE
config VIDEO_LCD_DCLK_PHASE
int "LCD panel display clock phase"
depends on VIDEO
depends on VIDEO_SUNXI || DM_VIDEO
default 1
---help---
Select LCD panel display clock phase shift, range 0-3.
config VIDEO_LCD_POWER
string "LCD panel power enable pin"
depends on VIDEO
depends on VIDEO_SUNXI
default ""
---help---
Set the power enable pin for the LCD panel. This takes a string in the
@ -695,7 +697,7 @@ config VIDEO_LCD_POWER
config VIDEO_LCD_RESET
string "LCD panel reset pin"
depends on VIDEO
depends on VIDEO_SUNXI
default ""
---help---
Set the reset pin for the LCD panel. This takes a string in the format
@ -703,7 +705,7 @@ config VIDEO_LCD_RESET
config VIDEO_LCD_BL_EN
string "LCD panel backlight enable pin"
depends on VIDEO
depends on VIDEO_SUNXI
default ""
---help---
Set the backlight enable pin for the LCD panel. This takes a string in the
@ -712,7 +714,7 @@ config VIDEO_LCD_BL_EN
config VIDEO_LCD_BL_PWM
string "LCD panel backlight pwm pin"
depends on VIDEO
depends on VIDEO_SUNXI
default ""
---help---
Set the backlight pwm pin for the LCD panel. This takes a string in the
@ -720,14 +722,14 @@ config VIDEO_LCD_BL_PWM
config VIDEO_LCD_BL_PWM_ACTIVE_LOW
bool "LCD panel backlight pwm is inverted"
depends on VIDEO
depends on VIDEO_SUNXI
default y
---help---
Set this if the backlight pwm output is active low.
config VIDEO_LCD_PANEL_I2C
bool "LCD panel needs to be configured via i2c"
depends on VIDEO
depends on VIDEO_SUNXI
default n
select CMD_I2C
---help---
@ -768,6 +770,7 @@ config VIDEO_DE2
depends on SUNXI_DE2
select DM_VIDEO
select DISPLAY
imply VIDEO_DT_SIMPLEFB
default y
---help---
Say y here if you want to build DE2 video driver which is present on
@ -776,7 +779,7 @@ config VIDEO_DE2
choice
prompt "LCD panel support"
depends on VIDEO
depends on VIDEO_SUNXI
---help---
Select which type of LCD panel to support.

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@ -117,4 +117,6 @@ config CMD_DDRMPHY_DUMP
The command "ddrmphy" shows the resulting parameters of DDR Multi PHY
training; it is useful for the evaluation of DDR Multi PHY training.
config SYS_SOC
default "uniphier-v7" if ARCH_UNIPHIER_LD4_SLD8 || ARCH_UNIPHIER_V7_MULTI
endif

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@ -17,9 +17,6 @@ void uniphier_ld4_clk_init(void)
/* deassert reset */
tmp = readl(SC_RSTCTRL);
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
@ -28,9 +25,6 @@ void uniphier_ld4_clk_init(void)
/* provide clocks */
tmp = readl(SC_CLKCTRL);
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_CLKCTRL_CEN_ETHER;
#endif
#ifdef CONFIG_USB_EHCI_HCD
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
#endif

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@ -21,9 +21,6 @@ void uniphier_pro4_clk_init(void)
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
@ -43,9 +40,6 @@ void uniphier_pro4_clk_init(void)
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
#endif
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_CLKCTRL_CEN_ETHER;
#endif
#ifdef CONFIG_USB_EHCI_HCD
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
#endif

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@ -19,9 +19,6 @@ void uniphier_pxs2_clk_init(void)
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
@ -45,9 +42,6 @@ void uniphier_pxs2_clk_init(void)
tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
#endif
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_CLKCTRL_CEN_ETHER;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif

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@ -5,9 +5,13 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/printk.h>
#include <time.h>
#include "ddrphy-init.h"
#include "ddrphy-regs.h"
@ -108,7 +112,7 @@ int ddrphy_training(void __iomem *phy_base)
u32 init_flag = PHY_PIR_INIT;
u32 done_flag = PHY_PGSR0_IDONE;
int timeout = 50000; /* 50 msec is long enough */
#ifdef DISPLAY_ELAPSED_TIME
#ifdef DEBUG
ulong start = get_timer(0);
#endif
@ -121,8 +125,7 @@ int ddrphy_training(void __iomem *phy_base)
do {
if (--timeout < 0) {
printf("%s: error: timeout during DDR training\n",
__func__);
pr_err("timeout during DDR training\n");
return -ETIMEDOUT;
}
udelay(1);
@ -131,14 +134,13 @@ int ddrphy_training(void __iomem *phy_base)
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
if (pgsr0 & init_sequence[i].err_flag) {
printf("%s: error: %s failed\n", __func__,
init_sequence[i].description);
pr_err("%s failed\n", init_sequence[i].description);
return -EIO;
}
}
#ifdef DISPLAY_ELAPSED_TIME
printf("%s: info: elapsed time %ld msec\n", get_timer(start));
#ifdef DEBUG
pr_debug("DDR training: elapsed time %ld msec\n", get_timer(start));
#endif
return 0;

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@ -184,12 +184,18 @@ __secondary_start_page:
mtspr SPRN_PIR,r4 /* write to PIR register */
#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
mfspr r8, L1CSR2
clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */
mtspr L1CSR2, r8
#else
#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
slwi r8,r4,1
addi r8,r8,32
mtspr L1CSR2,r8
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)

View File

@ -402,15 +402,6 @@ config FSP_BROKEN_HOB
do not overwrite the important boot service data which is used by
FSP, otherwise the subsequent call to fsp_notify() will fail.
config FSP_LOCKDOWN_SPI
bool
depends on HAVE_FSP
help
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). This option should be turned on
for such FSP and U-Boot will configure the SPI opcode registers
before the lock-down.
config ENABLE_MRC_CACHE
bool "Enable MRC cache"
depends on !EFI && !SYS_COREBOOT
@ -664,6 +655,7 @@ endmenu
config HAVE_ACPI_RESUME
bool "Enable ACPI S3 resume"
select ENABLE_MRC_CACHE
help
Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
state where all system context is lost except system memory. U-Boot
@ -677,7 +669,6 @@ config HAVE_ACPI_RESUME
config S3_VGA_ROM_RUN
bool "Re-run VGA option ROMs on S3 resume"
depends on HAVE_ACPI_RESUME
default y if HAVE_ACPI_RESUME
help
Execute VGA option ROMs in U-Boot when resuming from S3. Normally
this is needed when graphics console is being used in the kernel.

View File

@ -8,117 +8,20 @@
#include <common.h>
#include <fdtdec.h>
#include <asm/arch/fsp/azalia.h>
#include <asm/fsp/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
/* ALC262 Verb Table - 10EC0262 */
static const uint32_t verb_table_data13[] = {
/* Pin Complex (NID 0x11) */
0x01171cf0,
0x01171d11,
0x01171e11,
0x01171f41,
/* Pin Complex (NID 0x12) */
0x01271cf0,
0x01271d11,
0x01271e11,
0x01271f41,
/* Pin Complex (NID 0x14) */
0x01471c10,
0x01471d40,
0x01471e01,
0x01471f01,
/* Pin Complex (NID 0x15) */
0x01571cf0,
0x01571d11,
0x01571e11,
0x01571f41,
/* Pin Complex (NID 0x16) */
0x01671cf0,
0x01671d11,
0x01671e11,
0x01671f41,
/* Pin Complex (NID 0x18) */
0x01871c20,
0x01871d98,
0x01871ea1,
0x01871f01,
/* Pin Complex (NID 0x19) */
0x01971c21,
0x01971d98,
0x01971ea1,
0x01971f02,
/* Pin Complex (NID 0x1A) */
0x01a71c2f,
0x01a71d30,
0x01a71e81,
0x01a71f01,
/* Pin Complex */
0x01b71c1f,
0x01b71d40,
0x01b71e21,
0x01b71f02,
/* Pin Complex */
0x01c71cf0,
0x01c71d11,
0x01c71e11,
0x01c71f41,
/* Pin Complex */
0x01d71c01,
0x01d71dc6,
0x01d71e14,
0x01d71f40,
/* Pin Complex */
0x01e71cf0,
0x01e71d11,
0x01e71e11,
0x01e71f41,
/* Pin Complex */
0x01f71cf0,
0x01f71d11,
0x01f71e11,
0x01f71f41,
};
/*
* This needs to be in ROM since if we put it in CAR, FSP init loses it when
* it drops CAR.
/**
* Override the FSP's Azalia configuration data
*
* TODO(sjg@chromium.org): Move to device tree when FSP allows it
*
* VerbTable: (RealTek ALC262)
* Revision ID = 0xFF, support all steps
* Codec Verb Table For AZALIA
* Codec Address: CAd value (0/1/2)
* Codec Vendor: 0x10EC0262
* @azalia: pointer to be updated to point to a ROM address where Azalia
* configuration data is stored
*/
static const struct pch_azalia_verb_table azalia_verb_table[] = {
{
{
0x10ec0262,
0x0000,
0xff,
0x01,
0x000b,
0x0002,
},
verb_table_data13
}
};
const struct pch_azalia_config azalia_config = {
.pme_enable = 1,
.docking_supported = 1,
.docking_attached = 0,
.hdmi_codec_enable = 1,
.azalia_v_ci_enable = 1,
.rsvdbits = 0,
.azalia_verb_table_num = 1,
.azalia_verb_table = azalia_verb_table,
.reset_wait_timer_us = 300
};
__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
{
*azalia = NULL;
}
/**
* Override the FSP's configuration data.
@ -138,8 +41,6 @@ void update_fsp_configs(struct fsp_config_data *config,
rt_buf->common.boot_mode = config->common.boot_mode;
rt_buf->common.upd_data = &config->fsp_upd;
fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
if (node < 0) {
debug("%s: Cannot find FSP node\n", __func__);
@ -174,6 +75,8 @@ void update_fsp_configs(struct fsp_config_data *config,
SATA_MODE_AHCI);
fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
"fsp,enable-azalia");
if (fsp_upd->enable_azalia)
update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr);
fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode",
LPE_MODE_PCI);

View File

@ -10,6 +10,13 @@
#include <asm/irq.h>
#include <asm/mrccache.h>
#include <asm/post.h>
#include <asm/arch/iomap.h>
/* GPIO SUS */
#define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
#define GPIO_SUS_DFX5_CONF0 0x150
#define BYT_TRIG_LVL BIT(24)
#define BYT_TRIG_POS BIT(25)
#ifndef CONFIG_EFI_APP
int arch_cpu_init(void)
@ -33,6 +40,21 @@ int arch_misc_init(void)
mrccache_save();
#endif
/*
* For some unknown reason, FSP (gold4) for BayTrail configures
* the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25).
* This does not cause any issue when Linux kernel runs w/ or w/o
* the pinctrl driver for BayTrail. However this causes unstable
* S3 resume if the pinctrl driver is included in the kernel build.
* As this pin keeps generating interrupts during an S3 resume,
* and there is no IRQ requester in the kernel to handle it, the
* kernel seems to hang and does not continue resuming.
*
* Clear the mysterious interrupt bits for this pin.
*/
clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0,
BYT_TRIG_LVL | BYT_TRIG_POS);
return 0;
}

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@ -12,7 +12,6 @@ config INTEL_BRASWELL
imply HAVE_INTEL_ME
imply HAVE_VBT
imply ENABLE_MRC_CACHE
imply ENV_IS_IN_SPI_FLASH
imply AHCI_PCI
imply ICH_SPI
imply MMC
@ -32,8 +31,4 @@ config FSP_ADDR
hex
default 0xfff20000
config FSP_LOCKDOWN_SPI
bool
default y
endif

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@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += braswell.o cpu.o early_uart.o fsp_configs.o
obj-y += braswell.o early_uart.o fsp_configs.o

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@ -1,170 +0,0 @@
/*
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Derived from arch/x86/cpu/baytrail/cpu.c
*/
#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <asm/cpu.h>
#include <asm/cpu_x86.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/msr.h>
#include <asm/turbo.h>
static const unsigned int braswell_bus_freq_table[] = {
83333333,
100000000,
133333333,
116666666,
80000000,
93333333,
90000000,
88900000,
87500000
};
static unsigned int braswell_bus_freq(void)
{
msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))
return braswell_bus_freq_table[clk_info.lo & 0xf];
return 0;
}
static unsigned long braswell_tsc_freq(void)
{
msr_t platform_info;
ulong bclk = braswell_bus_freq();
if (!bclk)
return 0;
platform_info = msr_read(MSR_PLATFORM_INFO);
return bclk * ((platform_info.lo >> 8) & 0xff);
}
static int braswell_get_info(struct udevice *dev, struct cpu_info *info)
{
info->cpu_freq = braswell_tsc_freq();
info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);
return 0;
}
static int braswell_get_count(struct udevice *dev)
{
int ecx = 0;
/*
* Use the algorithm described in Intel 64 and IA-32 Architectures
* Software Developer's Manual Volume 3 (3A, 3B & 3C): System
* Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
* of CPUID Extended Topology Leaf.
*/
while (1) {
struct cpuid_result leaf_b;
leaf_b = cpuid_ext(0xb, ecx);
/*
* Braswell doesn't have hyperthreading so just determine the
* number of cores by from level type (ecx[15:8] == * 2)
*/
if ((leaf_b.ecx & 0xff00) == 0x0200)
return leaf_b.ebx & 0xffff;
ecx++;
}
return 0;
}
static void braswell_set_max_freq(void)
{
msr_t perf_ctl;
msr_t msr;
/* Enable speed step */
msr = msr_read(MSR_IA32_MISC_ENABLES);
msr.lo |= (1 << 16);
msr_write(MSR_IA32_MISC_ENABLES, msr);
/* Enable Burst Mode */
msr = msr_read(MSR_IA32_MISC_ENABLES);
msr.hi = 0;
msr_write(MSR_IA32_MISC_ENABLES, msr);
/*
* Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to
* bits [15:8] of the PERF_CTL
*/
msr = msr_read(MSR_IACORE_TURBO_RATIOS);
perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
/*
* Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to
* bits [7:0] of the PERF_CTL
*/
msr = msr_read(MSR_IACORE_TURBO_VIDS);
perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
perf_ctl.hi = 0;
msr_write(MSR_IA32_PERF_CTL, perf_ctl);
}
static int braswell_probe(struct udevice *dev)
{
debug("Init Braswell core\n");
/*
* On Braswell the turbo disable bit is actually scoped at the
* building-block level, not package. For non-BSP cores that are
* within a building block, enable turbo. The cores within the BSP's
* building block will just see it already enabled and move on.
*/
if (lapicid())
turbo_enable();
/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),
msr_clrsetbits_64(MSR_POWER_MISC,
ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);
/* Disable C1E */
msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
msr_setbits_64(MSR_POWER_MISC, 0x44);
/* Set this core to max frequency ratio */
braswell_set_max_freq();
return 0;
}
static const struct udevice_id braswell_ids[] = {
{ .compatible = "intel,braswell-cpu" },
{ }
};
static const struct cpu_ops braswell_ops = {
.get_desc = cpu_x86_get_desc,
.get_info = braswell_get_info,
.get_count = braswell_get_count,
.get_vendor = cpu_x86_get_vendor,
};
U_BOOT_DRIVER(cpu_x86_braswell_drv) = {
.name = "cpu_x86_braswell",
.id = UCLASS_CPU,
.of_match = braswell_ids,
.bind = cpu_x86_bind,
.probe = braswell_probe,
.ops = &braswell_ops,
};

View File

@ -37,28 +37,28 @@
cpu@0 {
device_type = "cpu";
compatible = "intel,braswell-cpu";
compatible = "cpu-x86";
reg = <0>;
intel,apic-id = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "intel,braswell-cpu";
compatible = "cpu-x86";
reg = <1>;
intel,apic-id = <2>;
};
cpu@2 {
device_type = "cpu";
compatible = "intel,braswell-cpu";
compatible = "cpu-x86";
reg = <2>;
intel,apic-id = <4>;
};
cpu@3 {
device_type = "cpu";
compatible = "intel,braswell-cpu";
compatible = "cpu-x86";
reg = <3>;
intel,apic-id = <6>;
};
@ -143,6 +143,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
intel,spi-lock-down;
spi-flash@0 {
#address-cells = <1>;
@ -194,7 +195,6 @@
fsp,pmic-i2c-bus = <0>;
fsp,enable-isp;
fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
fsp,turbo-mode;
fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
fsp,sd-detect-chk;
};

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