Prepare v2017.11

Signed-off-by: Tom Rini <trini@konsulko.com>
Revert "console: simplify puts()"
2017-11-13 20:08:06 -05:00 · 2017-11-12 16:18:16 -05:00 · 2017-11-12 16:18:16 -05:00 · 2017-11-12 16:17:31 -05:00 · 2017-11-10 10:04:21 -05:00 · 2017-11-10 19:21:24 +05:30
63 changed files with 1616 additions and 145 deletions
--- a/2
+++ b/2
@ -5,7 +5,7 @@
 VERSION = 2017
 PATCHLEVEL = 11
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
 NAME =

 # *DOCUMENTATION*
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@ -341,17 +341,6 @@ config TARGET_WORK_92105
 	select CPU_ARM926EJS
 	select SUPPORT_SPL

-config TARGET_MX25PDK
-	bool "Support mx25pdk"
-	select BOARD_LATE_INIT
-	select CPU_ARM926EJS
-	select BOARD_EARLY_INIT_F
-
-config TARGET_ZMX25
-	bool "Support zmx25"
-	select BOARD_LATE_INIT
-	select CPU_ARM926EJS
-
 config TARGET_APF27
 	bool "Support apf27"
 	select CPU_ARM926EJS
@ -599,6 +588,10 @@ config ARCH_MESON
 	  targeted at media players and tablet computers. We currently
 	  support the S905 (GXBaby) 64-bit SoC.

+config ARCH_MX25
+	bool "NXP MX25"
+	select CPU_ARM926EJS
+
 config ARCH_MX7ULP
        bool "NXP MX7ULP"
        select CPU_V7
@ -1162,6 +1155,8 @@ source "arch/arm/mach-mvebu/Kconfig"

 source "arch/arm/cpu/armv7/ls102xa/Kconfig"

+source "arch/arm/mach-imx/mx2/Kconfig"
+
 source "arch/arm/mach-imx/mx7ulp/Kconfig"

 source "arch/arm/mach-imx/mx7/Kconfig"
@ -1244,7 +1239,6 @@ source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
-source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
 source "board/freescale/mx31ads/Kconfig"
 source "board/freescale/mx31pdk/Kconfig"
@ -1270,7 +1264,6 @@ source "board/spear/spear320/Kconfig"
 source "board/spear/spear600/Kconfig"
 source "board/spear/x600/Kconfig"
 source "board/st/stv0991/Kconfig"
-source "board/syteco/zmx25/Kconfig"
 source "board/tcl/sl50/Kconfig"
 source "board/birdland/bav335x/Kconfig"
 source "board/timll/devkit3250/Kconfig"
--- a/arch/arm/dts/imx6q-display5.dts
+++ b/arch/arm/dts/imx6q-display5.dts
@ -0,0 +1,18 @@
+/*
+ * Copyright 2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+
+/ {
+	model = "Liebherr (LWN) display5 i.MX6 Quad Board";
+	compatible = "lwn,display5", "fsl,imx6q";
+};
--- a/arch/arm/dts/rk3368-lion.dts
+++ b/arch/arm/dts/rk3368-lion.dts
@ -68,7 +68,7 @@
 	phy-supply = <&vcc33_io>;
 	phy-mode = "rgmii";
 	clock_in_out = "input";
-	snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
+	snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
 	snps,reset-active-low;
 	snps,reset-delays-us = <2 10000 50000>;
 	assigned-clocks = <&cru SCLK_MAC>;
--- a/arch/arm/dts/rk3399-firefly.dts
+++ b/arch/arm/dts/rk3399-firefly.dts
@ -332,10 +332,10 @@
 				regulator-always-on;
 				regulator-boot-on;
 				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
+				regulator-max-microvolt = <3000000>;
 				regulator-state-mem {
 					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
+					regulator-suspend-microvolt = <3000000>;
 				};
 			};

--- a/arch/arm/dts/rk3399-puma.dtsi
+++ b/arch/arm/dts/rk3399-puma.dtsi
@ -36,13 +36,13 @@

 		module_led {
 			label = "module_led";
-			gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};

 		sd_card_led {
 			label = "sd_card_led";
-			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 		};
 	};
@ -94,8 +94,7 @@
 		compatible = "regulator-fixed";
 		regulator-name = "usbhub_enable";
 		enable-active-low;
-		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
-		regulator-always-on;
+		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
 		regulator-boot-on;
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@ -111,8 +110,8 @@
 		compatible = "regulator-fixed";
 		u-boot,dm-pre-reloc;
 		regulator-name = "bios_enable";
-		enable-active-low;
-		gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
 		regulator-always-on;
 		regulator-boot-on;
 		regulator-min-microvolt = <1800000>;
@ -140,7 +139,7 @@
 	vcc5v0_otg: vcc5v0-otg-regulator {
 		compatible = "regulator-fixed";
 		enable-active-high;
-		gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&otg_vbus_drv>;
 		regulator-name = "vcc5v0_otg";
@ -150,7 +149,7 @@
 	vcc5v0_host: vcc5v0-host-regulator {
 		compatible = "regulator-fixed";
 		enable-active-low;
-		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&host_vbus_drv>;
 		regulator-name = "vcc5v0_host";
@ -196,7 +195,7 @@
 	phy-supply = <&vcc_phy>;
 	phy-mode = "rgmii";
 	clock_in_out = "input";
-	snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>;
+	snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
 	snps,reset-active-low;
 	snps,reset-delays-us = <2 10000 50000>;
 	assigned-clocks = <&cru SCLK_RMII_SRC>;
@ -224,7 +223,7 @@
 	vdd_gpu: fan535555@60 {
 		compatible = "fcs,fan53555";
 		reg = <0x60>;
-		vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
 		vin-supply = <&vcc5v0_sys>;
 		regulator-compatible = "fan53555-reg";
 		regulator-name = "vdd_gpu";
@ -348,11 +347,11 @@
 				regulator-always-on;
 				regulator-boot-on;
 				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
+				regulator-max-microvolt = <3000000>;
 				regulator-name = "vcc_sd";
 				regulator-state-mem {
 					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
+					regulator-suspend-microvolt = <3000000>;
 				};
 			};

@ -426,7 +425,7 @@
 	vdd_cpu_b: fan53555@60 {
 		compatible = "fcs,fan53555";
 		reg = <0x60>;
-		vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+		vsel-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
 		vin-supply = <&vcc5v0_sys>;
 		regulator-compatible = "fan53555-reg";
 		regulator-name = "vdd_cpu_b";
@ -469,7 +468,7 @@
 	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
 	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
 	assigned-clock-rates = <100000000>;
-	ep-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+	ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
 	num-lanes = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_clkreqn>;
@ -524,23 +523,23 @@
 };

 &usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&dwc3_typec0 {
 	status = "disabled";
 };

-&usb_host1_ehci {
+&usb_host0_ohci {
+	status = "disabled";
+};
+
+&dwc3_typec0 {
 	status = "okay";
 };

+&usb_host1_ehci {
+	status = "disabled";
+};
+
 &usb_host1_ohci {
-	status = "okay";
+	status = "disabled";
 };

 &dwc3_typec1 {
@ -564,42 +563,43 @@
 		puma_pin_hog: puma_pin_hog {
 			rockchip,pins =
 				/* We need pull-ups on Q7 buttons */
-				<0  4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
-				<0 10 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
-				<0 11 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
-				<0  9 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
+				<RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
+				<RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
+				<RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
+				<RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
 		};
 	};

 	pmic {
 		pmic_int_l: pmic-int-l {
 			rockchip,pins =
-				<1 22 RK_FUNC_GPIO &pcfg_pull_up>;
+				<RK_GPIO1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 	};

 	leds_pins_puma: led_pins@0 {
 			rockchip,pins =
-				<2 25 RK_FUNC_GPIO &pcfg_pull_none>,
-				<1 2 RK_FUNC_GPIO &pcfg_pull_none>;
+				<RK_GPIO2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
+				<RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 	};

 	usb2 {
 		otg_vbus_drv: otg-vbus-drv {
 			rockchip,pins =
-				<0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+				<RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};

 		host_vbus_drv: host-vbus-drv {
 			rockchip,pins =
-				<0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+				<RK_GPIO4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};

 	i2c8 {
 		i2c8_xfer_a: i2c8-xfer {
-			rockchip,pins = <1 21 RK_FUNC_1 &pcfg_pull_up>,
-					<1 20 RK_FUNC_1 &pcfg_pull_up>;
+			rockchip,pins =
+				<RK_GPIO1 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
+				<RK_GPIO1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
 		};
 	};
 };
@ -624,8 +624,8 @@
 &i2c6_xfer {
 	/* Enable pull-ups, the pins would float otherwise. */
 	rockchip,pins =
-		<2 10 RK_FUNC_2 &pcfg_pull_up>,
-		<2 9 RK_FUNC_2 &pcfg_pull_up>;
+		<RK_GPIO2 RK_PB2 RK_FUNC_2 &pcfg_pull_up>,
+		<RK_GPIO2 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
 };

 &i2c7 {
--- a/arch/arm/dts/salvator-common.dtsi
+++ b/arch/arm/dts/salvator-common.dtsi
@ -438,7 +438,7 @@
 	sdhi2_pins: sd2 {
 		groups = "sdhi2_data8", "sdhi2_ctrl";
 		function = "sdhi2";
-		power-source = <3300>;
+		power-source = <1800>;
 	};

 	sdhi2_pins_uhs: sd2_uhs {
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@ -4,5 +4,9 @@
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
+#ifndef __SYS_PROTO_IMX5_
+#define __SYS_PROTO_IMX5_

 #include <asm/mach-imx/sys_proto.h>
+
+#endif /* __SYS_PROTO_IMX5_ */
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@ -178,4 +178,17 @@
 				|IOMUXC_GPR13_SATA_PHY_3_MASK \
 				|IOMUXC_GPR13_SATA_PHY_2_MASK \
 				|IOMUXC_GPR13_SATA_PHY_1_MASK)
+
+/*
+ * Setup RGMII voltage levels on iMX6 SoC - the
+ *
+ * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - register
+ *
+ * 1P2V_IO - USB_HSIC, MIPI_HSI
+ * 1P5V_IO - ENET pins
+ */
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII	0x020e0790
+#define DDR_SEL_1P2V_IO (0x2 << 18)
+#define DDR_SEL_1P5V_IO (0x3 << 18)
+
 #endif	/* __ASM_ARCH_IOMUX_H__ */
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@ -5,7 +5,11 @@
 * SPDX-License-Identifier:	GPL-2.0+
 */

+#ifndef __SYS_PROTO_IMX6_
+#define __SYS_PROTO_IMX6_
+
 #include <asm/mach-imx/sys_proto.h>
+#include <asm/arch/iomux.h>

 #define USBPHY_PWD		0x00000000

@ -16,3 +20,15 @@

 int imx6_pcie_toggle_power(void);
 int imx6_pcie_toggle_reset(void);
+
+/**
+ * iomuxc_set_rgmii_io_voltage - set voltage level of RGMII/USB pins
+ *
+ * @param io_vol - the voltage IO level of pins
+ */
+static inline void iomuxc_set_rgmii_io_voltage(int io_vol)
+{
+	__raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII);
+}
+
+#endif /* __SYS_PROTO_IMX6_ */
--- a/arch/arm/include/asm/arch-mx7/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx7/sys_proto.h
@ -3,8 +3,12 @@
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
+#ifndef __SYS_PROTO_IMX7_
+#define __SYS_PROTO_IMX7_

 #include <asm/mach-imx/sys_proto.h>

 void set_wdog_reset(struct wdog_regs *wdog);
 enum boot_device get_boot_device(void);
+
+#endif /* __SYS_PROTO_IMX7_ */
--- a/arch/arm/mach-imx/mx2/Kconfig
+++ b/arch/arm/mach-imx/mx2/Kconfig
@ -0,0 +1,30 @@
+if ARCH_MX25
+
+config MX25
+	bool
+	default y
+	select SYS_FSL_ERRATUM_ESDHC_A001
+choice
+	prompt "MX25 board select"
+	optional
+
+config TARGET_MX25PDK
+	bool "Support mx25pdk"
+	select BOARD_LATE_INIT
+	select CPU_ARM926EJS
+	select BOARD_EARLY_INIT_F
+
+config TARGET_ZMX25
+	bool "Support zmx25"
+	select BOARD_LATE_INIT
+	select CPU_ARM926EJS1
+
+endchoice
+
+config SYS_SOC
+	default "mx25"
+
+source "board/freescale/mx25pdk/Kconfig"
+source "board/syteco/zmx25/Kconfig"
+
+endif
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@ -6,6 +6,7 @@ config MX5

 config MX51
 	bool
+	select SYS_FSL_ERRATUM_ESDHC_A001

 config MX53
 	bool
@ -52,7 +53,6 @@ config TARGET_MX53SMD
 config TARGET_TS4800
 	bool "Support TS4800"
 	select MX51
-	select SYS_FSL_ERRATUM_ESDHC_A001

 config TARGET_USBARMORY
 	bool "Support USB armory"
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@ -138,6 +138,12 @@ config TARGET_DHCOMIMX6
 	select DM_THERMAL
 	imply CMD_SPL

+config TARGET_DISPLAY5
+	bool "LWN DISPLAY5 board"
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+
 config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 	select BOARD_LATE_INIT
@ -459,6 +465,7 @@ source "board/phytec/pfla02/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/samtec/vining_2000/Kconfig"
+source "board/liebherr/display5/Kconfig"
 source "board/liebherr/mccmon6/Kconfig"
 source "board/logicpd/imx6/Kconfig"
 source "board/seco/Kconfig"
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@ -36,7 +36,7 @@
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
 #include <asm/io.h>
-#include <asm/arch/sys_proto.h>
+
 DECLARE_GLOBAL_DATA_PTR;

 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
--- a/board/engicam/geam6ul/MAINTAINERS
+++ b/board/engicam/geam6ul/MAINTAINERS
@ -2,7 +2,7 @@ GEAM6UL BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/geam6ul
-F:	include/configs/imx6ul_geam.h
+F:	include/configs/imx6-engicam.h
 F:	configs/imx6ul_geam_mmc_defconfig
 F:	configs/imx6ul_geam_nand_defconfig
 F:	arch/arm/dts/imx6ul-geam-kit.dts
--- a/board/engicam/icorem6/MAINTAINERS
+++ b/board/engicam/icorem6/MAINTAINERS
@ -2,7 +2,7 @@ ICOREM6QDL BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/icorem6
-F:	include/configs/imx6qdl_icore.h
+F:	include/configs/imx6-engicam.h
 F:	configs/imx6qdl_icore_mmc_defconfig
 F:	configs/imx6qdl_icore_nand_defconfig
 F:	arch/arm/dts/imx6qdl-icore.dtsi
--- a/board/engicam/icorem6/README
+++ b/board/engicam/icorem6/README
@ -3,11 +3,8 @@ How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and Quad/Dual Starter Kit:

 $ make mrproper

- Configure U-Boot for Engicam i.CoreM6 Quad/Dual:
-$ make imx6q_icore_mmc_defconfig
-
- Configure U-Boot for Engicam i.CoreM6 Solo/DualLite:
-$ make imx6dl_icore_mmc_defconfig
+- Configure U-Boot for Engicam i.CoreM6 Quad/Dual/Solo/DualLite:
+$ make imx6qdl_icore_mmc_defconfig

 - Build U-Boot
 $ make
--- a/board/engicam/icorem6_rqs/MAINTAINERS
+++ b/board/engicam/icorem6_rqs/MAINTAINERS
@ -2,7 +2,7 @@ ICOREM6QDL_RQS BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/icorem6_rqs
-F:	include/configs/imx6qdl_icore_rqs.h
+F:	include/configs/imx6-engicam.h
 F:	configs/imx6qdl_icore_rqs_defconfig
 F:	arch/arm/dts/imx6qdl-icore-rqs.dtsi
 F:	arch/arm/dts/imx6q-icore-rqs.dts
--- a/board/engicam/icorem6_rqs/README
+++ b/board/engicam/icorem6_rqs/README
@ -3,11 +3,8 @@ How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and Quad/Dual Starter Ki

 $ make mrproper

- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual:
-$ make imx6q_icore_rqs_mmc_defconfig
-
- Configure U-Boot for Engicam i.CoreM6 RQS Solo/DualLite:
-$ make imx6dl_icore_rqs_mmc_defconfig
+- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual/Solo/DualLite:
+$ make imx6qdl_icore_rqs_defconfig

 - Build U-Boot
 $ make
--- a/board/engicam/isiotmx6ul/MAINTAINERS
+++ b/board/engicam/isiotmx6ul/MAINTAINERS
@ -2,7 +2,7 @@ ISIOTMX6UL BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/isiotmx6ul
-F:	include/configs/imx6ul_isiot.h
+F:	include/configs/imx6-engicam.h
 F:	configs/imx6ul_isiot_mmc_defconfig
 F:	configs/imx6ul_isiot_emmc_defconfig
 F:	configs/imx6ul_isiot_nand_defconfig
--- a/board/liebherr/display5/Kconfig
+++ b/board/liebherr/display5/Kconfig
@ -0,0 +1,18 @@
+if TARGET_DISPLAY5
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "display5"
+
+config SYS_VENDOR
+	default "liebherr"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "display5"
+
+endif
--- a/board/liebherr/display5/MAINTAINERS
+++ b/board/liebherr/display5/MAINTAINERS
@ -0,0 +1,7 @@
+DISPLAY5 BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/liebherr/display5/
+F:	include/configs/display5.h
+F:	configs/display5_defconfig
+F:	configs/display5_factory_defconfig
--- a/board/liebherr/display5/Makefile
+++ b/board/liebherr/display5/Makefile
@ -0,0 +1,11 @@
+#
+# Copyright (C) 2017, DENX Software Engineering
+# Lukasz Majewski <lukma@denx.de>
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+obj-y = common.o spl.o
+else
+obj-y := common.o display5.o
+endif
--- a/board/liebherr/display5/common.c
+++ b/board/liebherr/display5/common.c
@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/mx6-pins.h>
+#include "common.h"
+
+iomux_v3_cfg_t const uart_pads[] = {
+	/* UART4 */
+	MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart_console_pads[] = {
+	/* UART5 */
+	MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void displ5_set_iomux_uart_spl(void)
+{
+	SETUP_IOMUX_PADS(uart_console_pads);
+}
+
+void displ5_set_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart_pads);
+}
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi_pads[] = {
+	/* SPI3 */
+	MX6_PAD_DISP0_DAT2__ECSPI3_MISO	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT3__ECSPI3_SS0	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT4__ECSPI3_SS1	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT5__ECSPI3_SS2	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT6__ECSPI3_SS3	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT7__ECSPI3_RDY	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const ecspi2_pads[] = {
+	/* SPI2, NOR Flash nWP, CS0 */
+	MX6_PAD_CSI0_DAT10__ECSPI2_MISO	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI0_DAT9__ECSPI2_MOSI	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI0_DAT8__ECSPI2_SCLK	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__GPIO5_IO29	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__GPIO7_IO00	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+	if (bus != 1 || cs != (IMX_GPIO_NR(5, 29) << 8))
+		return -EINVAL;
+
+	return IMX_GPIO_NR(5, 29);
+}
+
+void displ5_set_iomux_ecspi_spl(void)
+{
+	SETUP_IOMUX_PADS(ecspi2_pads);
+}
+
+void displ5_set_iomux_ecspi(void)
+{
+	SETUP_IOMUX_PADS(ecspi_pads);
+}
+
+#else
+void displ5_set_iomux_ecspi_spl(void) {}
+void displ5_set_iomux_ecspi(void) {}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__SD4_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__SD4_RESET	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+void displ5_set_iomux_usdhc_spl(void)
+{
+	SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+void displ5_set_iomux_usdhc(void)
+{
+	SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+#else
+void displ5_set_iomux_usdhc_spl(void) {}
+void displ5_set_iomux_usdhc(void) {}
+#endif
--- a/board/liebherr/display5/common.h
+++ b/board/liebherr/display5/common.h
@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DISPL5_COMMON_H_
+#define __DISPL5_COMMON_H_
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED	  |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+void displ5_set_iomux_uart_spl(void);
+void displ5_set_iomux_uart(void);
+void displ5_set_iomux_ecspi_spl(void);
+void displ5_set_iomux_ecspi(void);
+void displ5_set_iomux_usdhc_spl(void);
+void displ5_set_iomux_usdhc(void);
+
+#endif /* __DISPL5_COMMON_H_ */
--- a/board/liebherr/display5/display5.c
+++ b/board/liebherr/display5/display5.c
@ -0,0 +1,384 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <malloc.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+
+#include <dm.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/platdata.h>
+
+#ifndef CONFIG_MXC_SPI
+#error "CONFIG_SPI must be set for this board"
+#error "Please check your config file"
+#endif
+
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool hw_ids_valid;
+static bool sw_ids_valid;
+static u32 cpu_id;
+static u32 unit_id;
+
+#define SW0	IMX_GPIO_NR(2, 4)
+#define SW1	IMX_GPIO_NR(2, 5)
+#define SW2	IMX_GPIO_NR(2, 6)
+#define SW3	IMX_GPIO_NR(2, 7)
+#define HW0	IMX_GPIO_NR(6, 7)
+#define HW1	IMX_GPIO_NR(6, 9)
+#define HW2	IMX_GPIO_NR(6, 10)
+#define HW3	IMX_GPIO_NR(6, 11)
+#define HW4	IMX_GPIO_NR(4, 7)
+#define HW5	IMX_GPIO_NR(4, 11)
+#define HW6	IMX_GPIO_NR(4, 13)
+#define HW7	IMX_GPIO_NR(4, 15)
+
+int gpio_table_sw_ids[] = {
+	SW0, SW1, SW2, SW3
+};
+
+const char *gpio_table_sw_ids_names[] = {
+	"sw0", "sw1", "sw2", "sw3"
+};
+
+int gpio_table_hw_ids[] = {
+	HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7
+};
+
+const char *gpio_table_hw_ids_names[] = {
+	"hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
+};
+
+static int get_board_id(int *ids, const char **c, int size,
+			bool *valid, u32 *id)
+{
+	int i, ret, val;
+
+	*valid = false;
+
+	for (i = 0; i < size; i++) {
+		ret = gpio_request(ids[i], c[i]);
+		if (ret) {
+			printf("Can't request SWx gpios\n");
+			return ret;
+		}
+	}
+
+	for (i = 0; i < size; i++) {
+		ret = gpio_direction_input(ids[i]);
+		if (ret) {
+			printf("Can't set SWx gpios direction\n");
+			return ret;
+		}
+	}
+
+	for (i = 0; i < size; i++) {
+		val = gpio_get_value(ids[i]);
+		if (val < 0) {
+			printf("Can't get SW%d ID\n", i);
+			*id = 0;
+			return val;
+		}
+		*id |= val << i;
+	}
+	*valid = true;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+#define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1: TFA9879 */
+struct i2c_pads_info i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+		.gp = IMX_GPIO_NR(3, 21)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+		.gp = IMX_GPIO_NR(3, 28)
+	}
+};
+
+/* I2C2: TIVO TM4C123 */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+		.gp = IMX_GPIO_NR(3, 16)
+	}
+};
+
+/* I2C3: PMIC PF0100, EEPROM AT24C256C */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+		.gp = IMX_GPIO_NR(3, 17)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+
+iomux_v3_cfg_t const misc_pads[] = {
+	/* Prod ID GPIO pins */
+	MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* HW revision GPIO pins */
+	MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* XTALOSC */
+	MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{ USDHC4_BASE_ADDR, 0, 8, },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	displ5_set_iomux_usdhc();
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+static void displ5_setup_ecspi(void)
+{
+	int ret;
+
+	displ5_set_iomux_ecspi();
+
+	ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0");
+	if (!ret)
+		gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
+
+	ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp");
+	if (!ret)
+		gpio_direction_output(IMX_GPIO_NR(7, 0), 1);
+}
+
+#ifdef CONFIG_FEC_MXC
+iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	/* for old evalboard with R159 present and R160 not populated */
+	MX6_PAD_GPIO_16__ENET_REF_CLK		| MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/*INT#_GBE*/
+	MX6_PAD_ENET_TX_EN__GPIO1_IO28		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+	gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/
+}
+
+int board_eth_init(bd_t *bd)
+{
+	struct phy_device *phydev;
+	struct mii_dev *bus;
+	int ret;
+
+	setup_iomux_enet();
+
+	iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
+
+	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	bus = fec_get_miibus(IMX_FEC_BASE, -1);
+	if (!bus)
+		return -ENODEV;
+
+	/*
+	 * We use here the "rgmii-id" mode of operation and allow M88E1512
+	 * PHY to use its internally callibrated RX/TX delays
+	 */
+	phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */,
+				  PHY_INTERFACE_MODE_RGMII_ID);
+	if (!phydev) {
+		ret = -ENODEV;
+		goto err_phy;
+	}
+
+	/* display5 due to PCB routing can only work with 100 Mbps */
+	phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
+				 ADVERTISED_1000baseX_Full |
+				 SUPPORTED_1000baseT_Half |
+				 SUPPORTED_1000baseT_Full);
+
+	ret  = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev);
+	if (ret)
+		goto err_sw;
+
+	return 0;
+
+err_sw:
+	free(phydev);
+err_phy:
+	mdio_unregister(bus);
+	free(bus);
+	return ret;
+}
+#endif /* CONFIG_FEC_MXC */
+
+/*
+ * Do not overwrite the console
+ * Always use serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	fdt_fixup_ethernet(blob);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	debug("board init\n");
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Setup iomux for non console UARTS */
+	displ5_set_iomux_uart();
+
+	displ5_setup_ecspi();
+
+	SETUP_IOMUX_PADS(misc_pads);
+
+	get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0],
+		     ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id);
+	debug("SWx unit_id 0x%x\n", unit_id);
+
+	get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0],
+		     ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id);
+	debug("HWx cpu_id 0x%x\n", cpu_id);
+
+	if (hw_ids_valid && sw_ids_valid)
+		printf("ID:    unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
+
+	udelay(25);
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* eMMC, USDHC-4, 8-bit bus width */
+	/* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
+	{"emmc",    MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{"spinor",  MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
+	{NULL,	0},
+};
+
+static void setup_boot_modes(void)
+{
+	add_board_boot_modes(board_boot_modes);
+}
+#else
+static inline void setup_boot_modes(void) {}
+#endif
+
+int misc_init_r(void)
+{
+	setup_boot_modes();
+	return 0;
+}
+
+static struct mxc_serial_platdata mxc_serial_plat = {
+	.reg = (struct mxc_uart *)UART5_BASE,
+};
+
+U_BOOT_DEVICE(mxc_serial) = {
+	.name = "serial_mxc",
+	.platdata = &mxc_serial_plat,
+};
--- a/board/liebherr/display5/spl.c
+++ b/board/liebherr/display5/spl.c
@ -0,0 +1,247 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <libfdt.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include "asm/arch/crm_regs.h"
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+#include "asm/arch/iomux.h"
+#include <asm/mach-imx/iomux-v3.h>
+#include <environment.h>
+#include <fsl_esdhc.h>
+#include <netdev.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdclk_1 = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_reset = 0x00000030,
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = 0x00000030,
+	.dram_sdodt1 = 0x00000030,
+
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_sdqs2 = 0x00000030,
+	.dram_sdqs3 = 0x00000030,
+	.dram_sdqs4 = 0x00000030,
+	.dram_sdqs5 = 0x00000030,
+	.dram_sdqs6 = 0x00000030,
+	.dram_sdqs7 = 0x00000030,
+
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_dqm2 = 0x00000030,
+	.dram_dqm3 = 0x00000030,
+	.dram_dqm4 = 0x00000030,
+	.dram_dqm5 = 0x00000030,
+	.dram_dqm6 = 0x00000030,
+	.dram_dqm7 = 0x00000030,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_b2ds = 0x00000030,
+	.grp_b3ds = 0x00000030,
+	.grp_b4ds = 0x00000030,
+	.grp_b5ds = 0x00000030,
+	.grp_b6ds = 0x00000030,
+	.grp_b7ds = 0x00000030,
+};
+
+/* 4x128Mx16.cfg */
+static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x002D0028,
+	.p0_mpwldectrl1 = 0x0032002D,
+	.p1_mpwldectrl0 = 0x00210036,
+	.p1_mpwldectrl1 = 0x0019002E,
+	.p0_mpdgctrl0 = 0x4349035C,
+	.p0_mpdgctrl1 = 0x0348033D,
+	.p1_mpdgctrl0 = 0x43550362,
+	.p1_mpdgctrl1 = 0x03520316,
+	.p0_mprddlctl = 0x41393940,
+	.p1_mprddlctl = 0x3F3A3C47,
+	.p0_mpwrdlctl = 0x413A423A,
+	.p1_mpwrdlctl = 0x4042483E,
+};
+
+/* MT41K128M16JT-125 (2Gb density) */
+static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC3F, &ccm->CCGR1);
+	writel(0x0FFFCFC0, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = 2,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 32Gb per CS */
+		/* single chip select */
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
+		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
+	};
+
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+static void displ5_init_ecspi(void)
+{
+	displ5_set_iomux_ecspi_spl();
+	enable_spi_clk(1, 1);
+}
+#else
+static inline void displ5_init_ecspi(void) { }
+#endif
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	.esdhc_base = USDHC4_BASE_ADDR,
+	.max_bus_width = 8,
+};
+
+int board_mmc_init(bd_t *bd)
+{
+	displ5_set_iomux_usdhc_spl();
+
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+	gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
+
+	return fsl_esdhc_initialize(bd, &usdhc_cfg);
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	displ5_set_iomux_uart_spl();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	displ5_init_ecspi();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	/* Default boot sequence SPI -> MMC */
+	spl_boot_list[0] = spl_boot_device();
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+	spl_boot_list[2] = BOOT_DEVICE_UART;
+	spl_boot_list[3] = BOOT_DEVICE_NONE;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	/* 'fastboot' */
+	const char *s;
+
+	env_init();
+	env_load();
+
+	s = env_get("BOOT_FROM");
+	if (s && strcmp(s, "ACTIVE") == 0) {
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		spl_boot_list[1] = spl_boot_device();
+	}
+#endif
+}
+
+void reset_cpu(ulong addr) {}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	if (env_get_yesno("boot_os") != 1)
+		return 1;
+#endif
+	return 0;
+}
+#endif
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@ -217,6 +217,8 @@ int board_init(void)
 	satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
 	gpio_request(satapwr_pin, "satapwr");
 	gpio_direction_output(satapwr_pin, 1);
+	/* Give attached sata device time to power-up to avoid link timeouts */
+	mdelay(500);
 #endif
 #ifdef CONFIG_MACPWR
 	macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
--- a/common/console.c
+++ b/common/console.c
@ -450,6 +450,12 @@ static void pre_console_putc(const char c)
 	unmap_sysmem(buffer);
 }

+static void pre_console_puts(const char *s)
+{
+	while (*s)
+		pre_console_putc(*s++);
+}
+
 static void print_pre_console_buffer(int flushpoint)
 {
 	unsigned long in = 0, out = 0;
@ -477,6 +483,7 @@ static void print_pre_console_buffer(int flushpoint)
 }
 #else
 static inline void pre_console_putc(const char c) {}
+static inline void pre_console_puts(const char *s) {}
 static inline void print_pre_console_buffer(int flushpoint) {}
 #endif

@ -518,8 +525,41 @@ void putc(const char c)

 void puts(const char *s)
 {
-	while (*s)
-		putc(*s++);
+#ifdef CONFIG_DEBUG_UART
+	if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
+		while (*s) {
+			int ch = *s++;
+
+			printch(ch);
+		}
+		return;
+	}
+#endif
+#ifdef CONFIG_CONSOLE_RECORD
+	if (gd && (gd->flags & GD_FLG_RECORD) && gd->console_out.start)
+		membuff_put(&gd->console_out, s, strlen(s));
+#endif
+#ifdef CONFIG_SILENT_CONSOLE
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+#endif
+
+#ifdef CONFIG_DISABLE_CONSOLE
+	if (gd->flags & GD_FLG_DISABLE_CONSOLE)
+		return;
+#endif
+
+	if (!gd->have_console)
+		return pre_console_puts(s);
+
+	if (gd->flags & GD_FLG_DEVINIT) {
+		/* Send to the standard output */
+		fputs(stdout, s);
+	} else {
+		/* Send directly to the handler */
+		pre_console_puts(s);
+		serial_puts(s);
+	}
 }

 #ifdef CONFIG_CONSOLE_RECORD
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@ -142,11 +142,12 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 	default 0x50 if ARCH_SUNXI
 	default 0x75 if ARCH_DAVINCI
 	default 0x8a if ARCH_MX6
-	default 0x100 if ARCH_ROCKCHIP || ARCH_UNIPHIER
+	default 0x100 if ARCH_UNIPHIER
 	default 0x140 if ARCH_MVEBU
 	default 0x200 if ARCH_SOCFPGA || ARCH_AT91
 	default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \
 		         OMAP54XX || AM33XX || AM43XX
+	default 0x4000 if ARCH_ROCKCHIP
 	help
 	  Address on the MMC to load U-Boot from, when the MMC is being used
 	  in raw mode. Units: MMC sectors (1 sector = 512 bytes).
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_DISPLAY5=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_SPL=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SAVEENV=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="display5 > "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),8m(lin-recovery),4m(swu-kernel),8m(swu-initramfs),-(reserved)"
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MARVELL=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@ -0,0 +1,76 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_DISPLAY5=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="display5 factory > "
+CONFIG_BOOTCMD_OVERRIDE=y
+CONFIG_BOOTCOMMAND="run factory"
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),8m(lin-recovery),4m(swu-kernel),8m(swu-initramfs),-(reserved)"
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SF=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Liebherr"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT=y
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@ -12,7 +12,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@ -12,7 +12,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_SPL_ATF_SUPPORT=y
 CONFIG_SPL_ATF_TEXT_BASE=0x00010000
 CONFIG_CMD_BOOTZ=y
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_ARCH_MX25=y
 CONFIG_TARGET_MX25PDK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
 CONFIG_BOOTDELAY=1
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@ -21,6 +21,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi-flash.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs)"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_REGEX=y
--- a/configs/zmx25_defconfig
+++ b/configs/zmx25_defconfig
@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_ARCH_MX25=y
 CONFIG_TARGET_ZMX25=y
 CONFIG_BOOTDELAY=5
 # CONFIG_DISPLAY_CPUINFO is not set
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@ -99,13 +99,13 @@ To write an image that boots from an SD card (assumed to be /dev/sdc):
   ./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
 	firefly-rk3288/spl/u-boot-spl-dtb.bin out && \
   sudo dd if=out of=/dev/sdc seek=64 && \
-   sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=256
+   sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=16384

 This puts the Rockchip header and SPL image first and then places the U-Boot
-image at block 256 (i.e. 128KB from the start of the SD card). This
+image at block 16384 (i.e. 8MB from the start of the SD card). This
 corresponds with this setting in U-Boot:

-   #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	256
+   #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x4000

 Put this SD (or micro-SD) card into your board and reset it. You should see
 something like:
@ -166,7 +166,7 @@ To write an image that boots from an SD card (assumed to be /dev/mmcblk0):
   ./tools/mkimage -n rk3288 -T rksd -d ./tpl/u-boot-tpl.bin out &&
    cat ./spl/u-boot-spl-dtb.bin >> out &&
    sudo dd if=out of=/dev/mmcblk0 seek=64 &&
-    sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 seek=256
+    sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 seek=16384

 Booting from an SD card on RK3188
 =================================
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@ -171,20 +171,20 @@ static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
 	uint databuf;
 	uint size;
 	uint irqstat;
-	uint timeout;
+	ulong start;

 	if (data->flags & MMC_DATA_READ) {
 		blocks = data->blocks;
 		buffer = data->dest;
 		while (blocks) {
-			timeout = PIO_TIMEOUT;
+			start = get_timer(0);
 			size = data->blocksize;
 			irqstat = esdhc_read32(&regs->irqstat);
-			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
-				&& --timeout);
-			if (timeout <= 0) {
-				printf("\nData Read Failed in PIO Mode.");
-				return;
+			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
+				if (get_timer(start) > PIO_TIMEOUT) {
+					printf("\nData Read Failed in PIO Mode.");
+					return;
+				}
 			}
 			while (size && (!(irqstat & IRQSTAT_TC))) {
 				udelay(100); /* Wait before last byte transfer complete */
@ -200,14 +200,14 @@ static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
 		blocks = data->blocks;
 		buffer = (char *)data->src;
 		while (blocks) {
-			timeout = PIO_TIMEOUT;
+			start = get_timer(0);
 			size = data->blocksize;
 			irqstat = esdhc_read32(&regs->irqstat);
-			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
-				&& --timeout);
-			if (timeout <= 0) {
-				printf("\nData Write Failed in PIO Mode.");
-				return;
+			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
+				if (get_timer(start) > PIO_TIMEOUT) {
+					printf("\nData Write Failed in PIO Mode.");
+					return;
+				}
 			}
 			while (size && (!(irqstat & IRQSTAT_TC))) {
 				udelay(100); /* Wait before last byte transfer complete */
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@ -247,6 +247,7 @@ config SUN7I_GMAC
 config SUN4I_EMAC
 	bool "Allwinner Sun4i Ethernet MAC support"
 	depends on DM_ETH
+	select PHYLIB
 	help
 	  This driver supports the Allwinner based SUN4I Ethernet MAC.

--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@ -21,7 +21,7 @@ obj-$(CONFIG_DNET) += dnet.o
 obj-$(CONFIG_E1000) += e1000.o
 obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
-obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
+obj-$(CONFIG_SUN4I_EMAC) += sunxi_emac.o
 obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
 obj-$(CONFIG_ENC28J60) += enc28j60.o
 obj-$(CONFIG_EP93XX) += ep93xx_eth.o
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@ -604,6 +604,8 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 {
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

+#ifdef CONFIG_MACH_SUNXI_H3_H5
+	/* Only H3/H5 have clock controls for internal EPHY */
 	if (priv->use_internal_phy) {
 		/* Set clock gating for ephy */
 		setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
@ -611,6 +613,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 		/* Deassert EPHY */
 		setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
 	}
+#endif

 	/* Set clock gating for emac */
 	setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
--- a/drivers/video/sunxi/sunxi_de2.c
+++ b/drivers/video/sunxi/sunxi_de2.c
@ -346,13 +346,19 @@ int sunxi_simplefb_setup(void *blob)
 					 "sunxi_dw_hdmi", &hdmi);
 	if (ret) {
 		debug("HDMI not present\n");
-		return 0;
+	} else if (device_active(hdmi)) {
+		if (mux == 0)
+			pipeline = "mixer0-lcd0-hdmi";
+		else
+			pipeline = "mixer1-lcd1-hdmi";
+	} else {
+		debug("HDMI present but not probed\n");
 	}

-	if (mux == 0)
-		pipeline = "mixer0-lcd0-hdmi";
-	else
-		pipeline = "mixer1-lcd1-hdmi";
+	if (!pipeline) {
+		debug("No active display present\n");
+		return 0;
+	}

 	de2_priv = dev_get_uclass_priv(de2);
 	de2_plat = dev_get_uclass_platdata(de2);
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@ -0,0 +1,408 @@
+/*
+ * Copyright (C) 2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+/* Falcon Mode */
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x18000000
+#define CONFIG_CMD_SPL_WRITE_SIZE	(44 * SZ_1K)
+
+/* Falcon Mode - MMC support */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x3F00
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	\
+	(CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x100	/* 128KiB */
+
+/*
+ * display5 SPI-NOR memory layout
+ *
+ * The definition can be found in Kconfig's
+ * CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT
+ *
+ * 0x000000 - 0x020000 : SPI.SPL (128KiB)
+ * 0x020000 - 0x120000 : SPI.u-boot (1MiB)
+ * 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB)
+ * 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB)
+ * 0x140000 - 0x940000 : SPI.fitImage-recovery (8MiB)
+ * 0x940000 - 0xD40000 : SPI.swupdate-kernel-FIT (4MiB)
+ * 0xD40000 - 0x1540000 : SPI.swupdate-initramfs  (8MiB)
+ */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_MTD_DEVICE
+#define CONFIG_SPI_FLASH_MTD
+#define CONFIG_MTD_PARTITIONS
+#endif
+
+/* Below values are "dummy" - only to avoid build break */
+#define CONFIG_SYS_SPI_KERNEL_OFFS      0x150000
+#define CONFIG_SYS_SPI_ARGS_OFFS        0x140000
+#define CONFIG_SYS_SPI_ARGS_SIZE        0x10000
+
+#include "imx6_spl.h"
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+#define CONFIG_SPL_SPI_LOAD
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * 1024 * 1024)
+#define CONFIG_MISC_INIT_R
+
+/*#define CONFIG_MXC_UART*/
+#define CONFIG_MXC_UART_BASE		UART5_BASE
+
+/* SPI NOR Flash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS		1
+#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(5, 29) << 8))
+#define CONFIG_SF_DEFAULT_SPEED		50000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#endif
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_MXC_I2C3
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_I2C_EDID
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
+
+/* Ethernet */
+#ifdef CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_MII
+#endif
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+#ifndef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND "run boot_mmc"
+#endif
+
+#define PARTS_DEFAULT \
+	/* Linux partitions */ \
+	"partitions=" \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=kernel_raw1,start=128K,size=8M,uuid=${uuid_gpt_kernel_raw1};" \
+	"name=rootfs1,size=1528M,uuid=${uuid_gpt_rootfs1};" \
+	"name=kernel_raw2,size=8M,uuid=${uuid_gpt_kernel_raw2};" \
+	"name=rootfs2,size=1528M,uuid=${uuid_gpt_rootfs2};" \
+	"name=data,size=-,uuid=${uuid_gpt_data}\0"
+
+#define FACTORY_PROCEDURE \
+	"echo '#######################';" \
+	"echo '# Factory Boot        #';" \
+	"echo '#######################';" \
+	"env default -a;" \
+	"saveenv;" \
+	"gpt write mmc ${mmcdev} ${partitions};" \
+	"run tftp_sf_SPL;" \
+	"run tftp_sf_uboot;" \
+	TFTP_UPDATE_KERNEL \
+	"run tftp_sf_fitImg_recovery;" \
+	"run tftp_sf_fitImg_SWU;" \
+	"run tftp_sf_initramfs_SWU;" \
+	TFTP_UPDATE_ROOTFS \
+	"echo '#######################';" \
+	"echo '# END - OK            #';" \
+	"echo '#######################';" \
+	"setenv bootcmd 'env default -a; saveenv; run falcon_setup; reset';" \
+	"setenv boot_os 'n';" \
+	"saveenv;" \
+	"reset;"
+
+#define SWUPDATE_RECOVERY_PROCEDURE \
+	"echo '#######################';" \
+	"echo '# RECOVERY SWUupdate  #';" \
+	"echo '#######################';" \
+	"setenv loadaddr_swu_initramfs 0x14000000;" \
+	"setenv bootargs console=${console} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+		":${hostname}::off root=/dev/ram rw;" \
+	"sf probe;" \
+	"sf read ${loadaddr} swu-kernel;" \
+	"sf read ${loadaddr_swu_initramfs} swu-initramfs;" \
+	"bootm ${loadaddr} ${loadaddr_swu_initramfs};"
+
+#define KERNEL_RECOVERY_PROCEDURE \
+	"echo '#######################';" \
+	"echo '# RECOVERY KERNEL IMG #';" \
+	"echo '#######################';" \
+	"sf probe;" \
+	"sf read ${loadaddr} lin-recovery;" \
+	"bootm;"
+
+#define SETUP_BOOTARGS \
+	"run set_rootfs_part;" \
+	"setenv bootargs ${bootargs} console=${console} "	  \
+		      "root=/dev/mmcblk${mmcdev}p${rootfs_part} " \
+		      "rootwait rootfstype=ext4 rw; " \
+	"run set_kernel_part;" \
+	"part start mmc ${mmcdev} ${kernel_part} lba_start; " \
+	"mmc read ${loadaddr} ${lba_start} 0x2000; " \
+	"setenv fdt_conf imx6q-${board}-${display}.dtb; "
+
+/* All the numbers are in LBAs */
+#define __TFTP_UPDATE_KERNEL \
+	"tftp_mmc_fitImg=" \
+	   "if test ! -n ${kernel_part}; then " \
+	       "setenv kernel_part ${kernel_part_active};" \
+	   "fi;" \
+	   "if tftp ${loadaddr} ${kernel_file}; then " \
+	       "setexpr fw_sz ${filesize} / 0x200; " \
+	       "setexpr fw_sz ${fw_sz} + 1; "  \
+	       "part start mmc ${mmcdev} ${kernel_part} lba_start; " \
+	       "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \
+	   "; fi\0" \
+
+#define TFTP_UPDATE_KERNEL \
+	"setenv kernel_part ${kernel_part_active};" \
+	"run tftp_mmc_fitImg;" \
+	"setenv kernel_part ${kernel_part_backup};" \
+	"run tftp_mmc_fitImg;" \
+
+#define __TFTP_UPDATE_ROOTFS \
+	"tftp_mmc_rootfs=" \
+	   "if test ! -n ${rootfs_part}; then " \
+	       "setenv rootfs_part ${rootfs_part_active};" \
+	   "fi;" \
+	   "if tftp ${loadaddr} ${rootfs_file}; then " \
+	       "setexpr fw_sz ${filesize} / 0x200; " \
+	       "setexpr fw_sz ${fw_sz} + 1; "  \
+	       "part start mmc ${mmcdev} ${rootfs_part} lba_start; " \
+	       "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \
+	   "; fi\0" \
+
+/* To save some considerable time, we only once download the rootfs image */
+/* and store it on 'active' and 'backup' rootfs partitions */
+#define TFTP_UPDATE_ROOTFS \
+	"setenv rootfs_part ${rootfs_part_active};" \
+	"run tftp_mmc_rootfs;" \
+	"part start mmc ${mmcdev} ${rootfs_part_backup} lba_start;" \
+	"mmc write ${loadaddr} ${lba_start} ${fw_sz};" \
+
+#define TFTP_UPDATE_RECOVERY_SWU_KERNEL \
+	"tftp_sf_fitImg_SWU=" \
+	    "if tftp ${loadaddr} ${kernel_file}; then " \
+		"sf probe;" \
+		"sf erase swu-kernel +${filesize};" \
+		"sf write ${loadaddr} swu-kernel ${filesize};" \
+	"; fi\0"	  \
+
+#define TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \
+	"swu_initramfs_file=swupdate-image-display5.ext3.gz.u-boot\0" \
+	"tftp_sf_initramfs_SWU=" \
+	    "if tftp ${loadaddr} ${swu_initramfs_file}; then " \
+		"sf probe;" \
+		"sf erase swu-initramfs +${filesize};" \
+		"sf write ${loadaddr} swu-initramfs ${filesize};" \
+	"; fi\0"	  \
+
+#define TFTP_UPDATE_RECOVERY_KERNEL_INITRAMFS \
+	"kernel_recovery_file=fitImage-initramfs\0" \
+	"tftp_sf_fitImg_recovery=" \
+	    "if tftp ${loadaddr} ${kernel_recovery_file}; then " \
+		"sf probe;" \
+		"sf erase lin-recovery +${filesize};" \
+		"sf write ${loadaddr} lin-recovery ${filesize};" \
+	"; fi\0"	  \
+
+#define TFTP_UPDATE_BOOTLOADER \
+	"ubootfile=u-boot.img\0" \
+	"ubootfileSPL=SPL\0" \
+	"tftp_sf_uboot=" \
+	    "if tftp ${loadaddr} ${ubootfile}; then " \
+		"sf probe;" \
+		"sf erase u-boot +${filesize};" \
+		"sf write ${loadaddr} u-boot ${filesize}" \
+	"; fi\0"	  \
+	"tftp_sf_SPL="	  \
+	    "if tftp ${loadaddr} ${ubootfileSPL}; then " \
+		"sf probe;" \
+		"setexpr uboot_SPL_size ${filesize} + 0x400;" \
+		"sf erase 0x0 +${uboot_SPL_size};" \
+		"sf write ${loadaddr} 0x400 ${filesize};" \
+	"fi\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS	  \
+	PARTS_DEFAULT \
+	"display=tianma-tm070-800x480\0" \
+	"board=display5\0" \
+	"mmcdev=0\0" \
+	"altbootcmd=run recovery\0" \
+	"bootdelay=1\0" \
+	"baudrate=115200\0" \
+	"bootcmd=" CONFIG_BOOTCOMMAND "\0" \
+	"factory=" FACTORY_PROCEDURE "\0" \
+	"bootlimit=3\0" \
+	"ethact=FEC\0" \
+	"netdev=eth0\0" \
+	"boot_os=y\0" \
+	"hostname=display5\0" \
+	"loadaddr=0x12000000\0" \
+	"fdtaddr=0x12800000\0" \
+	"console=ttymxc4,115200 quiet\0" \
+	"fdtfile=imx6q-display5.dtb\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_file=fitImage\0" \
+	"up=run tftp_sf_SPL; run tftp_sf_uboot\0" \
+	"download_kernel=" \
+		"tftpboot ${loadaddr} ${kernel_file};\0" \
+	"boot_kernel_recovery=" KERNEL_RECOVERY_PROCEDURE "\0" \
+	"boot_swu_recovery=" SWUPDATE_RECOVERY_PROCEDURE "\0" \
+	"recovery=" \
+	"if test ${BOOT_FROM_RECOVERY} = SWU; then " \
+	     "echo BOOT: RECOVERY: SWU;" \
+	     "run boot_swu_recovery;" \
+	"else " \
+	     "echo BOOT: RECOVERY: Linux;" \
+	     "run boot_kernel_recovery;" \
+	"fi\0" \
+	"boot_tftp=" \
+	"if run download_kernel; then "	  \
+	     "setenv bootargs console=${console} " \
+	     "root=/dev/mmcblk0p2 rootwait;" \
+	     "bootm ${loadaddr} - ${fdtaddr};" \
+	"fi\0" \
+	"addip=setenv bootargs ${bootargs} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
+	    "${hostname}:eth0:on"	  \
+	"\0"	  \
+	"nfsargs=setenv bootargs " \
+	"root=/dev/nfs rw "	  \
+	"nfsroot=${serverip}:${rootpath},nolock,nfsvers=3" \
+	"\0" \
+	"rootpath=/srv/tftp/DISP5/rootfs\0" \
+	"boot_nfs=" \
+	"if run download_kernel; then "	  \
+	     "run nfsargs;"	  \
+	     "run addip;"	  \
+	     "setenv bootargs ${bootargs} console=${console};"	  \
+	     "setenv fdt_conf imx6q-${board}-${display}.dtb; " \
+	     "bootm ${loadaddr}#conf@${fdt_conf};" \
+	"fi\0" \
+	"falcon_setup=" \
+	"if mmc dev ${mmcdev}; then "	  \
+	     SETUP_BOOTARGS \
+	     "spl export fdt ${loadaddr}#conf@${fdt_conf};" \
+	     "setexpr fw_sz ${fdtargslen} / 0x200; " \
+	     "setexpr fw_sz ${fw_sz} + 1; "  \
+	     "mmc write ${fdtargsaddr} " \
+	     __stringify(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)" ${fw_sz}; " \
+	"fi\0" \
+	"boot_mmc=" \
+	"if mmc dev ${mmcdev}; then "	  \
+	     SETUP_BOOTARGS \
+	     "bootm ${loadaddr}#conf@${fdt_conf};" \
+	"fi\0" \
+	"set_kernel_part=" \
+	"if test ${BOOT_FROM} = ACTIVE; then " \
+	     "setenv kernel_part ${kernel_part_active};" \
+	     "echo BOOT: ACTIVE;" \
+	"else if test ${BOOT_FROM} = BACKUP; then " \
+	     "setenv kernel_part ${kernel_part_backup};" \
+	     "echo BOOT: BACKUP;" \
+	"else " \
+	     "run recovery;" \
+	"fi;fi\0" \
+	"set_rootfs_part=" \
+	"if test ${BOOT_FROM} = ACTIVE; then " \
+	     "setenv rootfs_part ${rootfs_part_active};" \
+	"else if test ${BOOT_FROM} = BACKUP; then " \
+	     "setenv rootfs_part ${rootfs_part_backup};" \
+	"else " \
+	     "run recovery;" \
+	"fi;fi\0" \
+	"BOOT_FROM=ACTIVE\0" \
+	"BOOT_FROM_RECOVERY=Linux\0" \
+	TFTP_UPDATE_BOOTLOADER \
+	"kernel_part_active=1\0" \
+	"kernel_part_backup=3\0" \
+	__TFTP_UPDATE_KERNEL \
+	"rootfs_part_active=2\0" \
+	"rootfs_part_backup=4\0" \
+	"rootfs_file=core-image-lwn-display5.ext4\0" \
+	__TFTP_UPDATE_ROOTFS \
+	TFTP_UPDATE_RECOVERY_KERNEL_INITRAMFS \
+	TFTP_UPDATE_RECOVERY_SWU_KERNEL \
+	TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \
+	"\0" \
+
+/* Miscellaneous configurable options */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE		2048
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_STANDALONE_LOAD_ADDR	0x10001000
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+
+/* ENV config */
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE		(SZ_64K)
+/* The 0x120000 value corresponds to above SPI-NOR memory MAP */
+#define CONFIG_ENV_OFFSET		(0x120000)
+#define CONFIG_ENV_SECT_SIZE		(SZ_64K)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#endif
+
+#define CONFIG_MXC_USB_PORTSC           (PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif /* __CONFIG_H */
--- a/include/configs/evb_rk3229.h
+++ b/include/configs/evb_rk3229.h
@ -11,8 +11,6 @@


 /* Store env in emmc */
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_SIZE                 (32 << 10)
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_SYS_MMC_ENV_PART         0
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
--- a/include/configs/kylin_rk3036.h
+++ b/include/configs/kylin_rk3036.h
@ -13,8 +13,6 @@
 #ifndef CONFIG_SPL_BUILD

 /* Store env in emmc */
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_SIZE			SZ_32K
 #define CONFIG_SYS_MMC_ENV_DEV		0 /* emmc */
 #define CONFIG_SYS_MMC_ENV_PART		0 /* user area */

--- a/include/configs/lion_rk3368.h
+++ b/include/configs/lion_rk3368.h
@ -13,6 +13,5 @@
 #define KERNEL_LOAD_ADDR		0x280000
 #define DTB_LOAD_ADDR			0x5600000
 #define INITRD_LOAD_ADDR		0x5bf0000
-#define CONFIG_ENV_SIZE			0x2000

 #endif
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@ -11,7 +11,6 @@

 /* High Level Configuration Options */

-#define CONFIG_MX25
 #define CONFIG_SYS_TEXT_BASE		0x81200000
 #define CONFIG_MXC_GPIO
 #define CONFIG_SYS_FSL_CLK
--- a/include/configs/puma_rk3399.h
+++ b/include/configs/puma_rk3399.h
@ -17,7 +17,15 @@
 #undef CONFIG_ENV_OFFSET
 #define CONFIG_ENV_OFFSET (240 * 1024)

+#if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_SYS_MMC_ENV_DEV 1
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+#endif

 #define SDRAM_BANK_SIZE			(2UL << 30)

--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@ -10,7 +10,6 @@
 #include "rockchip-common.h"

 #define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@ -14,7 +14,6 @@

 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 #define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024

--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@ -10,7 +10,6 @@
 #include "rockchip-common.h"

 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/*  64M */
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@ -12,7 +12,6 @@

 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 #define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024

--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@ -9,7 +9,6 @@

 #include "rockchip-common.h"

-#define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@ -10,7 +10,6 @@
 #include "rockchip-common.h"

 #define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
--- a/include/configs/rock.h
+++ b/include/configs/rock.h
@ -12,18 +12,4 @@

 #define CONFIG_SYS_MMC_ENV_DEV 0

-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-/* SPL @ 32k for 34k
- * u-boot directly after @ 68k for 400k or so
- * ENV @ 992k
- */
-#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
-#else
-/* SPL @ 32k for ~36k
- * ENV @ 96k
- * u-boot @ 128K
- */
-#define CONFIG_ENV_OFFSET (96 * 1024)
-#endif
-
 #endif
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@ -61,19 +61,11 @@

 #endif

-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-/* SPL @ 32k for 34k
- * u-boot directly after @ 68k for 400k or so
- * ENV @ 992k
+/*
+ * Rockchip SoCs use fixed ENV 32KB@(4MB-32KB)
 */
-#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
-#else
-/* SPL @ 32k for ~36k
- * ENV @ 96k
- * u-boot @ 128K
- */
-#define CONFIG_ENV_OFFSET (96 * 1024)
-#endif
+#define CONFIG_ENV_OFFSET	(SZ_4M - SZ_32K)
+#define CONFIG_ENV_SIZE		SZ_32K

 #define CONFIG_DISPLAY_BOARDINFO_LATE

--- a/include/configs/sheep_rk3368.h
+++ b/include/configs/sheep_rk3368.h
@ -13,7 +13,6 @@
 #define KERNEL_LOAD_ADDR		0x280000
 #define DTB_LOAD_ADDR			0x5600000
 #define INITRD_LOAD_ADDR		0x5bf0000
-#define CONFIG_ENV_SIZE			0x2000

 #define CONFIG_CONSOLE_SCROLL_LINES	10

--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@ -286,7 +286,7 @@ extern int soft_i2c_gpio_scl;
 #endif /* CONFIG_VIDEO_SUNXI */

 /* Ethernet support */
-#ifdef CONFIG_SUNXI_EMAC
+#ifdef CONFIG_SUN4I_EMAC
 #define CONFIG_PHY_ADDR		1
 #define CONFIG_MII			/* MII PHY management		*/
 #endif
--- a/include/configs/vyasa-rk3288.h
+++ b/include/configs/vyasa-rk3288.h
@ -31,10 +31,10 @@
 #define CONFIG_SYS_SPL_ARGS_ADDR	0x0ffe5000
 #define CONFIG_CMD_SPL_WRITE_SIZE      (128 * SZ_1K)

-/* Falcon Mode - MMC support: args@1MB kernel@2MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
+/* Falcon Mode - MMC support: args@16MB kernel@17MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR		0x8000	/* 16MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS		(CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR		0x8800	/* 17MB */
 #endif

 #endif
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@ -12,7 +12,6 @@

 #include <asm/arch/imx-regs.h>

-#define CONFIG_MX25
 #define CONFIG_SYS_TEXT_BASE		0xA0000000

 #define CONFIG_SYS_TIMER_RATE		32768
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@ -130,7 +130,7 @@
 #define XFERTYP_DMAEN		0x00000001

 #define CINS_TIMEOUT		1000
-#define PIO_TIMEOUT		100000
+#define PIO_TIMEOUT		500

 #define DSADDR		0x2e004
Author	SHA1	Message	Date
Tom Rini	c253573f3e	Prepare v2017.11 Signed-off-by: Tom Rini <trini@konsulko.com>	2017-11-13 20:08:06 -05:00
Soeren Moch	be135cc5eb	Revert "console: simplify puts()" This reverts commit `c61d0009fe`. A tbs2910 board user reported a very slow console frambuffer as regression in current u-boot. I could bisect this down to the above mentioned commit. This revert brings back the fast framebuffer console (one cache flush per string in puts(), not after each char). Reported-by: Uwe Scheffler <scheffler.u@web.de> Signed-off-by: Soeren Moch <smoch@web.de> Tested-by: Uwe Scheffler <scheffler.u@web.de> Reviewed-by: Simon Glass <sjg@chromium.org>	2017-11-12 16:18:16 -05:00
Angelo Dureghello	ae147ab4a8	board: sysam: stmark2: add missing environment location Signed-off-by: Angelo Dureghello <angelo@sysam.it>	2017-11-12 16:18:16 -05:00
Marek Vasut	2bfd43e550	ARM: rmobile: Fix eMMC signal voltage on Salvator-X/XS The eMMC is 1V8 device only and the signaling is always 1V8, fix the DT for Salvator-X/XS to describe the hardware correctly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>	2017-11-12 16:17:31 -05:00
Tom Rini	66bd5a3ebb	Merge git://git.denx.de/u-boot-sunxi	2017-11-10 10:04:21 -05:00
Werner Böllmann	8e2c2d413c	sunxi: SATA link timeout fix After updating u-boot from v2016.01 to 2017.09, issue with "SATA link 0 timeout." on my Cubietruck board. mdelay milled after moving satapwr code to board. "sunxi: Turn satapwr on from board_init" (sha1: `9fbb0c3aa4`) After adding the "mdelay(500);" line that was lost in the path the error is gone. Signed-off-by: Werner Böllmann <Werner.Boellmann@fh-dortmund.de> [Rebased and updated change and commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>	2017-11-10 19:21:24 +05:30
Chen-Yu Tsai	13ae2a40e7	net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com>	2017-11-10 19:10:33 +05:30
Tom Rini	60567a320f	Merge git://git.denx.de/u-boot-rockchip	2017-11-10 08:19:01 -05:00
Jagan Teki	36b6e0cc3c	rockchip: configs: vyasa: Update falcon offsets Update the falcon offsets for args to 16MB and kernel to 17MB Since the below commit updated U-Boot proper location along with rockchip boot image offsets "spl: set SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x4000 for rockchip" (sha1: `8f4d62b403`) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-10 14:08:22 +01:00
Jagan Teki	d80599e894	rockchip: doc: Fix U-Boot proper location for falcon This patch fixed U-Boot proper location has been missed to update in bewlo commit "rockchip: doc: update U-Boot location info" (sha1: `73e6dbe855`) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-10 14:08:21 +01:00
Goldschmidt Simon	341e44ed66	rockchip: doc: update U-Boot location info The U-Boot location has been moved to block 16384. This is 8MB, not 4MB. Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-10 14:08:20 +01:00
Tom Rini	1c4043e532	Merge branch 'master' of git://git.denx.de/u-boot-sunxi	2017-11-09 08:11:40 -05:00
Tom Rini	3c674b7e87	Merge branch 'master' of git://www.denx.de/git/u-boot-imx	2017-11-09 08:11:30 -05:00
Lukasz Majewski	9c8979cdb7	imx7: Add include guards for include/asm/arch-mx7/sys_proto.h file Signed-off-by: Lukasz Majewski <lukma@denx.de>	2017-11-09 11:32:49 +01:00
Lukasz Majewski	e895e996ab	imx5: Add include guards for include/asm/arch-mx5/sys_proto.h file Signed-off-by: Lukasz Majewski <lukma@denx.de>	2017-11-09 11:32:49 +01:00
Lukasz Majewski	90d0e38c1e	imx6: Add include guards for include/asm/arch-mx6/sys_proto.h file Signed-off-by: Lukasz Majewski <lukma@denx.de>	2017-11-09 11:32:49 +01:00
Lukasz Majewski	a3eec24ad3	imx:display5: Add support for LWN's DISPLAY5 board This commit provides support for LWN's IMX6Q based DISPLAY5 board. Signed-off-by: Lukasz Majewski <lukma@denx.de>	2017-11-09 11:32:49 +01:00
Lukasz Majewski	ec1b26973c	imx6: iomux: Add generic function to set RGMII IO voltage on IMX6 SoCs This commit provides generic function to set the RGMII/HSIC IO voltage level on iMX6 devices. Signed-off-by: Lukasz Majewski <lukma@denx.de>	2017-11-09 11:32:49 +01:00
Lukasz Majewski	8ea754da60	board: imx6: marsboard: Remove doubled #include <asm/arch/sys_proto.h> The sys_proto.h file has been included earlier in this file. Signed-off-by: Lukasz Majewski <lukma@denx.de>	2017-11-09 11:32:49 +01:00
Artturi Alm	6270a3f035	sunxi: restore PHYLIB for CONFIG_SUN4I_EMAC users due misnaming of CONFIG_SUN4I_EMAC in include/configs/sunxi-common.h, likely missed in: commit `3146f0c017` ("Move PHYLIB to Kconfig") Signed-off-by: Artturi Alm <artturi.alm@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>	2017-11-09 14:39:30 +05:30
Artturi Alm	e286fada9d	sunxi: fix CONFIG_SUNXI_EMAC references fixes CONFIG_SUNXI_EMAC references from drivers/net/Makefile and include/configs/sunxi-common.h likely forgotten in: commit `abc3e4df59` ("sunxi: Convert SUNXI_EMAC to Kconfig") Signed-off-by: Artturi Alm <artturi.alm@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>	2017-11-09 14:39:09 +05:30
Benoît Thébaudeau	bcfb365375	mmc: fsl_esdhc: Fix PIO timeout The following error has been observed on i.MX25 with a high-speed SDSC card: Data Write Failed in PIO Mode. It was caused by the timeout set on PRSSTAT.BWEN, which was triggered because this bit takes 15 ms to be set after writing the first block to DATPORT with this card. Without this timeout, all the blocks are properly written. This timeout was implemented by decrementing a variable, so it was depending on the CPU frequency. Fix this issue by setting this timeout to a long enough absolute duration (500 ms). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>	2017-11-07 10:26:27 +01:00
Jagan Teki	cc65e354fe	i.MX6: engicam: Fix MAINTAINERS/README - Update newly added include/configs file in MAINTAINERS - Update newly added defconfig file in README Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>	2017-11-07 10:13:39 +01:00
Fabio Estevam	b2e6ad451b	mx51: Select the ESDHC_A001 erratum When a high speed card is connected to mx51evk the following error is seen: U-Boot 2017.11-rc2 (Oct 18 2017 - 13:49:26 -0200) CPU: Freescale i.MX51 rev3.0 at 800 MHz Reset cause: POR Board: MX51EVK DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - read failed, using default environment In: serial Out: serial Err: serial Net: FEC Hit any key to stop autoboot: 0 => saveenv Saving Environment to MMC... Writing to MMC(0)... failed The root cause for the failure is the eSDHC-A001 erratum: "eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 0x4,0x8, and 0xC" that is listed on some PowerArchitecture chips: https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf Even though eSDHC-A001 is not documented on the i.MX51 errata document, I have confirmed with the NXP design team that this erratum does affect i.MX51, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001 at SoC level. The i.MX51 ts4800 board already selects this option, but it is better to move this selection to the i.MX51 SoC level instead. Successfully tested with a high speed SD card on a mx51evk board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>	2017-11-07 10:13:11 +01:00
Fabio Estevam	5d09c27138	mx25: Select the ESDHC_A001 erratum When a high speed card is connected to mx25 the following error is seen: U-Boot 2017.11-rc2-00104-gb79372a (Oct 31 2017 - 11:02:22 -0200) CPU: Freescale i.MX25 rev1.2 at 399 MHz Reset cause: POR Board: MX25PDK I2C: ready DRAM: 64 MiB No arch specific invalidate_icache_all available! MMC: FSL_SDHC: 0 *** Warning - read failed, using default environment In: serial Out: serial Err: serial Net: FEC Hit any key to stop autoboot: 0 => saveenv Saving Environment to MMC... Writing to MMC(0)... failed , which prevents any usage of the SD card. The root cause for the failure is the eSDHC-A001 erratum: "eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 0x4,0x8, and 0xC" that is listed on some PowerArchitecture chips: https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf Even though eSDHC-A001 is not documented on the i.MX25 errata document, I have confirmed with the NXP design team that this erratum does affect i.MX25, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001 at SoC level. Successfully tested with a high speed SD card on a mx25pdk board. Suggested-by: Benoît Thébaudeau <benoit@wsystem.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Otavio Salvador <otavio@ossystems.com.br> # mx25pdk	2017-11-07 10:13:00 +01:00
Fabio Estevam	07df697e14	mx25: Move MX25 selection to Kconfig The motivation for moving MX25 selection to Kconfig is to be able to better handle MX25 specific errata, so that an errata option can be selected at SoC level instead of board level. This selection method also aligns with the way other i.MX SoCs are selected in U-Boot. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>	2017-11-07 10:12:50 +01:00
Kever Yang	021a8ae00a	rockchip: remove SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR from defconfig Use default value 0x4000 for SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR instead of define a new one. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-07 09:16:58 +01:00
Kever Yang	73e6dbe855	rockchip: doc: update U-Boot location info Update rockchip U-Boot location to 0x4000/16384. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-07 09:16:57 +01:00
Kever Yang	8f4d62b403	spl: set SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x4000 for rockchip Rockchip use a 'loader2' partition for U-Boot, so u-boot.bin or u-boot.itb load by SPL need to locate at0x4000. Detail here: http://opensource.rock-chips.com/wiki_Boot_option Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-07 09:16:57 +01:00
Klaus Goger	b5557ffc0f	rockchip: board: puma_rk3399: make env location selectable via Kconfig The environment storage location is selectable via Kconfig. We support eMMC, SD and SPI-NOR as location for U-Boot. This adds support to store the environment in the SPI-NOR additional to the default eMMC location. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-07 09:16:57 +01:00
Klaus Goger	4f70039b36	rockchip: dts: rk3399: change sd-card io voltage to 3.0V The VCC_SD and VCC_SDIO rail should only be powered up to 3.0V on RK3399 platforms. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-07 09:16:57 +01:00
Klaus Goger	366812fa26	rockchip: dts: Use defines for pin names in rk3399-puma.dtsi and rk3368-lion.dts pinctrl/rockchip.h provides defines that map pin numbers to pin names. Use them to make the dts more human readable. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-07 09:16:57 +01:00
Philipp Tomsich	b1e1ce2cd4	rockchip: dts: rk3399-puma: update USB configuration This change updates the USB configuration for the RK3399-Q7 in the DTS: * fixes the OTG board configuration by enabling it ('okay') * improves the speed of 'usb start' by disabling the unused EHCI/OHCI controllers Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>	2017-11-07 09:16:57 +01:00
Philipp Tomsich	f2a9513168	rockchip: dts: rk3399-puma: update usbhub_enable regulator To correctly model the usbhub_enable regulator for U-Boot, we need to change the settings to: * the GPIO polarity is GPIO_ACTIVE_LOW * should be set to inactive (enable-active-low) when boot-on settings are applied * it can be changed at runtime (i.e. remove the always-on) Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>	2017-11-07 09:16:57 +01:00
Philipp Tomsich	df1e6212f9	rockchip: dts: rk3399-puma: fix the modelling of BIOS_DISABLE The fixed regulator for overriding BIOS_DISABLE had been modelling backwards (i.e. the GPIO polarity and the enable-active-low/high property had both been inverted), causing the 'regulator' command to always print/expect 'disabled'/'enabled' backwards. This fixes the mix-up and models it correctly: * the GPIO is low-active * the regulator should be enabled (enable-active-high) during boot-on initialisation Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>	2017-11-07 09:16:56 +01:00
Kever Yang	be942f2e0d	rockchip: config: use common CONFIG_ENV_SIZE for all SoCs All Rockchip SoCs use 32KB as CONFIG_ENV_SIZE. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-07 09:16:56 +01:00
Kever Yang	c742043f74	rockchip: config: sync the ENV offset from rockchip legacy U-Boot Using the ENV offset from rockchip legacy U-Boot for all SoCs, the offset is 4MB-32KB Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-07 09:16:56 +01:00
Kever Yang	5d2f1d8271	rockchip: rock: remove CONFIG_ENV_OFFSET We use the same default ENV setting in rockchip_common.h for all SoC. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	2017-11-07 09:16:56 +01:00
Icenowy Zheng	460b15adc9	video: sunxi: de2: fix SimpleFB node creation when HDMI not initialized When HDMI is not initialized (e.g. no monitor is plugged), the current SimpleFB code will still create a broken SimpleFB node. Detect whether HDMI is initialized when creating SimpleFB node. Fixes: `be5b96f0e4` ("sunxi: setup simplefb for Allwinner DE2") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>	2017-11-06 13:43:28 +05:30