Fix: move watchdog feed more early

Update version in Makefile to prepare the label v2021.10-stm32mp-r2
for OpenSTLinux V4.1

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I235b2792161ab02f0eee2af19506eed828a8dc6e

.azure-pipelines.yml

@@ -1,17 +1,15 @@
 variables:
-  windows_vm: windows-2019
+  windows_vm: vs2017-win2016
   ubuntu_vm: ubuntu-18.04
   macos_vm: macOS-10.15
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20220113-03Feb2022
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
   container_option: -u 0
   work_dir: /u
 
-stages:
-- stage: testsuites
-  jobs:
+jobs:
   - job: tools_only_windows
     displayName: 'Ensure host tools build for Windows'
     pool:
@@ -23,10 +21,9 @@ stages:
       - script: |
           sfx.exe -y -o%CD:~0,2%\
           %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syyuu"
-          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Su"
         displayName: 'Update MSYS2'
       - script: |
-          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel"
+          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel"
         displayName: 'Install Toolchain'
       - script: |
           echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh
@@ -43,7 +40,7 @@ stages:
     pool:
       vmImage: $(macos_vm)
     steps:
-      - script: brew install make ossp-uuid
+      - script: brew install make
         displayName: Brew install dependencies
       - script: |
           gmake tools-only_config tools-only NO_SDL=1 \
@@ -52,33 +49,6 @@ stages:
             -j$(sysctl -n hw.logicalcpu)
         displayName: 'Perform tools-only build'
 
-  - job: check_for_migrated_symbols_in_board_header
-    displayName: 'Check for migrated symbols in board header'
-    pool:
-      vmImage: $(ubuntu_vm)
-    container:
-      image: $(ci_runner_image)
-      options: $(container_option)
-    steps:
-      - script: |
-          KSYMLST=`mktemp`
-          KUSEDLST=`mktemp`
-          cat `find . -name "Kconfig*"` | \
-             sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-             -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-             | sort -u > $KSYMLST
-          for CFG in `find include/configs -name "*.h"`; do
-             grep '#define[[:blank:]]CONFIG_' $CFG | \
-                sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' | \
-                sort -u > ${KUSEDLST} || true
-             NUM=`comm -12 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
-                cut -d , -f 3`
-             if [[ $NUM -ne 0 ]]; then
-                echo "Unmigrated symbols found in $CFG"
-                exit 1
-             fi
-          done
-
   - job: cppcheck
     displayName: 'Static code analysis with cppcheck'
     pool:
@@ -199,11 +169,10 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
+          ./tools/buildman/buildman --fetch-arch arm
+          export PATH=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/:$PATH
           test/nokia_rx51_test.sh
 
-- stage: test_py
-  jobs:
   - job: test_py
     displayName: 'test.py'
     pool:
@@ -214,7 +183,7 @@ stages:
           TEST_PY_BD: "sandbox"
         sandbox_clang:
           TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-13"
+          OVERRIDE: "-O clang-12"
         sandbox_spl:
           TEST_PY_BD: "sandbox_spl"
           TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
@@ -223,16 +192,9 @@ stages:
           TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
         sandbox_flattree:
           TEST_PY_BD: "sandbox_flattree"
-        coreboot:
-          TEST_PY_BD: "coreboot"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
         evb_ast2500:
           TEST_PY_BD: "evb-ast2500"
           TEST_PY_ID: "--id qemu"
-        vexpress_ca9x4:
-          TEST_PY_BD: "vexpress_ca9x4"
-          TEST_PY_ID: "--id qemu"
         integratorcp_cm926ejs:
           TEST_PY_BD: "integratorcp_cm926ejs"
           TEST_PY_ID: "--id qemu"
@@ -292,12 +254,6 @@ stages:
         r2dplus_tulip:
           TEST_PY_BD: "r2dplus"
           TEST_PY_ID: "--id tulip_qemu"
-        sifive_unleashed_sdcard:
-          TEST_PY_BD: "sifive_unleashed"
-          TEST_PY_ID: "--id sdcard_qemu"
-        sifive_unleashed_spi-nor:
-          TEST_PY_BD: "sifive_unleashed"
-          TEST_PY_ID: "--id spi-nor_qemu"
         xilinx_zynq_virt:
           TEST_PY_BD: "xilinx_zynq_virt"
           TEST_PY_ID: "--id qemu"
@@ -333,7 +289,7 @@ stages:
               wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
               export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
           fi
-          if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
+          if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
               wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
               export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
           fi
@@ -346,24 +302,6 @@ stages:
           cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
           cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
           cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
-          # create sdcard / spi-nor images for sifive unleashed using genimage
-          if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
-              mkdir -p root;
-              cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
-              cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
-              rm -rf tmp;
-              genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
-              cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
-              rm -rf tmp;
-              genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
-              cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
-          fi
-          if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-              wget -O - "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
-              wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
-              chmod a+x cbfstool;
-              ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
-          fi
           virtualenv -p /usr/bin/python3 /tmp/venv
           . /tmp/venv/bin/activate
           pip install -r test/py/requirements.txt
@@ -396,8 +334,6 @@ stages:
           # Some tests using libguestfs-tools need the fuse device to run
           docker run "$@" --device /dev/fuse:/dev/fuse -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh
 
-- stage: world_build
-  jobs:
   - job: build_the_world
     displayName: 'Build the World'
     pool:

.get_maintainer.conf

@@ -1 +0,0 @@
---find-maintainer-files --maintainer-path=.

.gitattributes

@@ -3,4 +3,3 @@
 # Denote all files that are truly binary and should not be modified
 *.bmp binary
 *.ttf binary
-*.gz binary

.gitignore

@@ -95,10 +95,3 @@ GTAGS
 
 # Python cache
 __pycache__
-
-# Python code coverage output (python3-coverage html)
-/htmlcov/
-
-# pylint files
-/pylint.cur
-/pylint.out/

.gitlab-ci.yml

@@ -2,7 +2,7 @@
 
 # Grab our configured image.  The source for this is found at:
 # https://source.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:focal-20220113-03Feb2022
+image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -23,7 +23,7 @@ stages:
         wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
         export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
       fi
-    - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
+    - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
         wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
         export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
       fi
@@ -40,28 +40,6 @@ stages:
     - cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
     - cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
     - cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
-    # create sdcard / spi-nor images for sifive unleashed using genimage
-    - if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
-        mkdir -p root;
-        cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
-        cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
-        rm -rf tmp;
-        genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
-        cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
-        rm -rf tmp;
-        genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
-        cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
-      fi
-    - if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-        wget -O -
-          "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |
-          xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
-        wget -O -
-          "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >
-          cbfstool;
-        chmod a+x cbfstool;
-        ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
-      fi
     - virtualenv -p /usr/bin/python3 /tmp/venv
     - . /tmp/venv/bin/activate
     - pip install -r test/py/requirements.txt
@@ -71,10 +49,6 @@ stages:
       ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
         ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
         --build-dir "$UBOOT_TRAVIS_BUILD_DIR"
-    # It seems that the files in /tmp go away, so copy out what we need
-    - if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-        cp -v /tmp/coreboot/*.{html,css} .;
-      fi
 
 build all 32bit ARM platforms:
   stage: world build
@@ -119,27 +93,6 @@ build all other platforms:
         exit $ret;
       fi;
 
-check for migrated symbols in board header:
-  stage: testsuites
-  script:
-    - KSYMLST=`mktemp`;
-      KUSEDLST=`mktemp`;
-      cat `find . -name "Kconfig*"` |
-         sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-         -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-         | sort -u > $KSYMLST;
-      for CFG in `find include/configs -name "*.h"`; do
-         grep '#define[[:blank:]]CONFIG_' $CFG |
-            sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' |
-            sort -u > ${KUSEDLST} || true;
-         NUM=`comm -12 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
-            cut -d , -f 3`;
-         if [[ $NUM -ne 0 ]]; then
-            echo "Unmigrated symbols found in $CFG";
-            exit 1;
-         fi;
-      done
-
 # QA jobs for code analytics
 # static code analysis with cppcheck (we can add --enable=all later)
 cppcheck:
@@ -212,7 +165,8 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
 Run tests for Nokia RX-51 (aka N900):
   stage: testsuites
   script:
-    - export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH;
+    - ./tools/buildman/buildman --fetch-arch arm;
+      export PATH=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/:$PATH;
       test/nokia_rx51_test.sh
 
 # Test sandbox with test.py
@@ -224,7 +178,7 @@ sandbox test.py:
 sandbox with clang test.py:
   variables:
     TEST_PY_BD: "sandbox"
-    OVERRIDE: "-O clang-13"
+    OVERRIDE: "-O clang-12"
   <<: *buildman_and_testpy_dfn
 
 sandbox_spl test.py:
@@ -250,12 +204,6 @@ sandbox_flattree test.py:
     TEST_PY_BD: "sandbox_flattree"
   <<: *buildman_and_testpy_dfn
 
-vexpress_ca9x4 test.py:
-  variables:
-    TEST_PY_BD: "vexpress_ca9x4"
-    TEST_PY_ID: "--id qemu"
-  <<: *buildman_and_testpy_dfn
-
 integratorcp_cm926ejs test.py:
   variables:
     TEST_PY_BD: "integratorcp_cm926ejs"
@@ -369,18 +317,6 @@ r2dplus_tulip test.py:
     TEST_PY_ID: "--id tulip_qemu"
   <<: *buildman_and_testpy_dfn
 
-sifive_unleashed_sdcard test.py:
-  variables:
-    TEST_PY_BD: "sifive_unleashed"
-    TEST_PY_ID: "--id sdcard_qemu"
-  <<: *buildman_and_testpy_dfn
-
-sifive_unleashed_spi-nor test.py:
-  variables:
-    TEST_PY_BD: "sifive_unleashed"
-    TEST_PY_ID: "--id spi-nor_qemu"
-  <<: *buildman_and_testpy_dfn
-
 xilinx_zynq_virt test.py:
   variables:
     TEST_PY_BD: "xilinx_zynq_virt"
@@ -401,15 +337,3 @@ xtfpga test.py:
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
-
-coreboot test.py:
-  variables:
-    TEST_PY_BD: "coreboot"
-    TEST_PY_TEST_SPEC: "not sleep"
-    TEST_PY_ID: "--id qemu"
-  artifacts:
-    paths:
-      - "*.html"
-      - "*.css"
-    expire_in: 1 week
-  <<: *buildman_and_testpy_dfn

.mailmap

@@ -20,19 +20,15 @@ Allen Martin <amartin@nvidia.com>
 Andreas Bießmann <andreas.devel@googlemail.com>
 Andreas Bießmann <andreas@biessmann.org>
 Aneesh V <aneesh@ti.com>
-Anup Patel <anup@brainfault.org> <anup.patel@wdc.com>
-Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
 Dirk Behme <dirk.behme@googlemail.com>
 Fabio Estevam <fabio.estevam@nxp.com>
-Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
 Jagan Teki <402jagan@gmail.com>
 Jagan Teki <jaganna@gmail.com>
 Jagan Teki <jaganna@xilinx.com>
 Jagan Teki <jagannadh.teki@gmail.com>
 Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
-Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
 Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
 Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
 Markus Klotzbuecher <mk@denx.de>

.readthedocs.yml

@@ -5,13 +5,6 @@
 # Required
 version: 2
 
-build:
-  os: "ubuntu-20.04"
-  apt_packages:
-    - python3-six
-  tools:
-    python: "3.9"
-
 # Build documentation in the docs/ directory with Sphinx
 sphinx:
   configuration: doc/conf.py
@@ -19,6 +12,8 @@ sphinx:
 # Optionally build your docs in additional formats such as PDF and ePub
 formats: []
 
-python:
-  install:
-    - requirements: doc/sphinx/requirements.txt
+# Optionally set the version of Python and requirements required to build your docs
+# python:
+#   version: 3.7
+#   install:
+#     - requirements: docs/requirements.txt

CONTRIBUTING.md

@@ -0,0 +1,30 @@
+# Contributing guide
+
+This document serves as a checklist before contributing to this repository. It includes links to read up on if topics are unclear to you.
+
+This guide mainly focuses on the proper use of Git.
+
+## 1. Issues
+
+STM32MPU projects do not activate "Github issues" feature for the time being. If you need to report an issue or question about this project deliverables, you can report them using [ ST Support Center ](https://my.st.com/ols#/ols/newrequest)  or  [ ST Community MPU Forum ](https://community.st.com/s/topic/0TO0X0000003u2AWAQ/stm32-mpus).
+
+## 2. Pull Requests
+
+STMicrolectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure.
+
+* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual CLA (https://cla.st.com).
+* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate CLA (https://cla.st.com) mentioning your GitHub account name.
+* If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account you can check here (https://cla.st.com).
+
+Please note that:
+* The Corporate CLA will always take precedence over the Individual CLA.
+* One CLA submission is sufficient, for any project proposed by STMicroelectronics.
+
+__How to proceed__
+
+* We recommend to fork the project in your GitHub account to further develop your contribution. Please use the latest commit version.
+* Please, submit one Pull Request for one new feature or proposal. This will ease the analysis and final merge if accepted.
+
+__Note__
+
+Merge will not be done directly in GitHub but it will need first to follow internal integration process before public deliver in a standard release. The Pull request will stay open until it is merged and delivered.

Kconfig

@@ -83,6 +83,7 @@ config CC_OPTIMIZE_FOR_SIZE
 
 config OPTIMIZE_INLINING
 	bool "Allow compiler to uninline functions marked 'inline' in full U-Boot"
+	default n
 	help
 	  This option determines if U-Boot forces gcc to inline the functions
 	  developers have marked 'inline'. Doing so takes away freedom from gcc to
@@ -92,6 +93,7 @@ config OPTIMIZE_INLINING
 config SPL_OPTIMIZE_INLINING
 	bool "Allow compiler to uninline functions marked 'inline' in SPL"
 	depends on SPL
+	default n
 	help
 	  This option determines if U-Boot forces gcc to inline the functions
 	  developers have marked 'inline'. Doing so takes away freedom from gcc to
@@ -104,6 +106,7 @@ config ARCH_SUPPORTS_LTO
 config LTO
 	bool "Enable Link Time Optimizations"
 	depends on ARCH_SUPPORTS_LTO
+	default n
 	help
 	  This option enables Link Time Optimization (LTO), a mechanism which
 	  allows the compiler to optimize between different compilation units.
@@ -124,6 +127,7 @@ config LTO
 config TPL_OPTIMIZE_INLINING
 	bool "Allow compiler to uninline functions marked 'inline' in TPL"
 	depends on TPL
+	default n
 	help
 	  This option determines if U-Boot forces gcc to inline the functions
 	  developers have marked 'inline'. Doing so takes away freedom from gcc to
@@ -245,12 +249,8 @@ config SYS_MALLOC_F_LEN
 
 config SYS_MALLOC_LEN
 	hex "Define memory for Dynamic allocation"
-	default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
-	default 0x200000 if ARCH_BMIPS || X86
-	default 0x120000 if MACH_SUNIV
-	default 0x220000 if MACH_SUN8I_V3S
-	default 0x4020000 if ARCH_SUNXI
-	default 0x400000
+	depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP
+	default 0x2000000 if ARCH_ROCKCHIP
 	help
 	  This defines memory to be allocated for Dynamic allocation
 	  TODO: Use for other architectures
@@ -307,6 +307,7 @@ if EXPERT
 
 config SYS_MALLOC_DEFAULT_TO_INIT
 	bool "Default malloc to init while reserving the memory for it"
+	default n
 	help
 	  It may happen that one needs to move the dynamic allocation
 	  from one to another memory range, eg. when moving the malloc
@@ -353,13 +354,6 @@ config SPL_IMAGE
 	  used to generate a combined image with SPL and main U-Boot
 	  proper as one single image.
 
-config REMAKE_ELF
-	bool "Recreate an ELF image from raw U-Boot binary"
-	help
-	  Enable this to recreate an ELF image (u-boot.elf) from the raw
-	  U-Boot binary (u-boot.bin), which may already have been statically
-	  relocated and may already have a device-tree appended to it.
-
 config BUILD_TARGET
 	string "Build target special images"
 	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
@@ -395,21 +389,6 @@ config SYS_LDSCRIPT
 	  Path within the source tree to the linker script to use for the
 	  main U-Boot binary.
 
-config SYS_LOAD_ADDR
-	hex "Address in memory to use by default"
-	default 0x01000000 if ARCH_SOCFPGA
-	default 0x02000000 if PPC || X86
-	default 0x81000000 if MACH_SUNIV
-	default 0x22000000 if MACH_SUN9I
-	default 0x42000000 if ARCH_SUNXI
-	default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
-	default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
-	default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
-	default 0x80800000 if ARCH_MX7
-	default 0x90000000 if FSL_LSCH2 || FSL_LSCH3
-	help
-	  Address in memory to use as the default safe load address.
-
 config ERR_PTR_OFFSET
 	hex
 	default 0x0
@@ -444,6 +423,7 @@ config SYS_HAS_SRAM
 	default y if TARGET_PIC32MZDASK
 	default y if TARGET_DEVKIT8000
 	default y if TARGET_TRICORDER
+	default n
 	help
 	  Enable this to allow support for the on board SRAM.
 	  SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
@@ -463,12 +443,6 @@ config SYS_SRAM_SIZE
 	default 0x10000 if TARGET_TRICORDER
 	default 0x0
 
-config MP
-	bool "Support for multiprocessor"
-	help
-	  This provides an option to bringup different processors
-	  in multiprocessor cases.
-
 config EXAMPLES
 	bool "Compile API examples"
 	depends on !SANDBOX
@@ -481,8 +455,6 @@ endmenu		# General setup
 
 source "api/Kconfig"
 
-source "boot/Kconfig"
-
 source "common/Kconfig"
 
 source "cmd/Kconfig"

Licenses/lgpl-2.0.txt

@@ -133,7 +133,7 @@ such a program is covered only if its contents constitute a work based
 on the Library (independent of the use of the Library in a tool for
 writing it).  Whether that is true depends on what the Library does
 and what the program that uses the Library does.
-
+  
   1. You may copy and distribute verbatim copies of the Library's
 complete source code as you receive it, in any medium, provided that
 you conspicuously and appropriately publish on each copy an

MAINTAINERS

@@ -50,12 +50,6 @@ so much easier [Ed]
 Maintainers List (try to look for most precise areas first)
 
 		-----------------------------------
-ACPI:
-M:	Simon Glass <sjg@chromium.org>
-S:	Maintained
-F:	cmd/acpi.c
-F:	lib/acpi/
-
 ANDROID AB
 M:	Igor Opaniuk <igor.opaniuk@gmail.com>
 R:	Sam Protsenko <joe.skb7@gmail.com>
@@ -114,17 +108,6 @@ L:	uboot-snps-arc@synopsys.com
 F:	doc/device-tree-bindings/mmc/snps,dw-mmc.txt
 F:	drivers/mmc/snps_dw_mmc.c
 
-APPLE M1 SOC SUPPORT
-M:	Mark Kettenis <kettenis@openbsd.org>
-S:	Maintained
-F:	arch/arm/include/asm/arch-m1/
-F:	arch/arm/mach-apple/
-F:	configs/apple_m1_defconfig
-F:	drivers/iommu/apple_dart.c
-F:	drivers/pinctrl/pinctrl-apple.c
-F:	drivers/watchdog/apple_wdt.c
-F:	include/configs/apple.h
-
 ARM
 M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
@@ -278,35 +261,12 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
 F:	arch/arm/mach-kirkwood/
 F:	arch/arm/mach-mvebu/
 F:	drivers/ata/ahci_mvebu.c
-F:	drivers/clk/mvebu/
 F:	drivers/ddr/marvell/
 F:	drivers/gpio/mvebu_gpio.c
-F:	drivers/i2c/mvtwsi.c
-F:	drivers/mmc/xenon_sdhci.c
-F:	drivers/phy/marvell/
-F:	drivers/pinctrl/mvebu/
-F:	drivers/rtc/armada38x.c
 F:	drivers/spi/kirkwood_spi.c
-F:	drivers/spi/mvebu_a3700_spi.c
-F:	drivers/pci/pcie_dw_mvebu.c
-F:	drivers/watchdog/armada-37xx-wdt.c
-F:	drivers/watchdog/orion_wdt.c
-F:	include/configs/mv-common.h
-
-ARM MARVELL PCIE CONTROLLER DRIVERS
-M:	Pali Rohár <pali@kernel.org>
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
-F:	drivers/pci/pci-aardvark.c
 F:	drivers/pci/pci_mvebu.c
-
-ARM MARVELL SERIAL DRIVERS
-M:	Pali Rohár <pali@kernel.org>
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
-F:	drivers/serial/serial_mvebu_a3700.c
+F:	drivers/pci/pcie_dw_mvebu.c
+F:	drivers/watchdog/orion_wdt.c
 
 ARM MARVELL PXA
 M:	Marek Vasut <marex@denx.de>
@@ -352,7 +312,6 @@ F:	arch/arm/mach-at91/
 F:	board/atmel/
 F:	drivers/cpu/at91_cpu.c
 F:	drivers/misc/microchip_flexcom.c
-F:	include/dt-bindings/mfd/atmel-flexcom.h
 F:	drivers/timer/mchp-pit64b-timer.c
 
 ARM NEXELL S5P4418
@@ -431,9 +390,7 @@ F:	drivers/gpio/msm_gpio.c
 F:	drivers/mmc/msm_sdhci.c
 F:	drivers/phy/msm8916-usbh-phy.c
 F:	drivers/serial/serial_msm.c
-F:	drivers/serial/serial_msm_geni.c
 F:	drivers/smem/msm_smem.c
-F:	drivers/spmi/spmi-msm.c
 F:	drivers/usb/host/ehci-msm.c
 
 ARM STI
@@ -481,6 +438,7 @@ F:	drivers/power/regulator/stpmic1.c
 F:	drivers/ram/stm32mp1/
 F:	drivers/remoteproc/stm32_copro.c
 F:	drivers/reset/stm32-reset.c
+F:	drivers/rng/optee_rng.c
 F:	drivers/rng/stm32mp1_rng.c
 F:	drivers/rtc/stm32_rtc.c
 F:	drivers/serial/serial_stm32.*
@@ -529,8 +487,6 @@ ARM TI
 M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-ti.git
-F:	arch/arm/dts/am57xx*
-F:	arch/arm/dts/dra7*
 F:	arch/arm/mach-davinci/
 F:	arch/arm/mach-k3/
 F:	arch/arm/mach-keystone/
@@ -550,11 +506,9 @@ F:	drivers/phy/omap-usb2-phy.c
 F:	drivers/phy/phy-ti-am654.c
 F:	drivers/phy/ti-pipe3-phy.c
 F:	drivers/ram/k3*
-F:	drivers/remoteproc/ipu_rproc.c
 F:	drivers/remoteproc/k3_system_controller.c
 F:	drivers/remoteproc/pruc_rpoc.c
 F:	drivers/remoteproc/ti*
-F:	drivers/reset/reset-dra7.c
 F:	drivers/reset/reset-ti-sci.c
 F:	drivers/rtc/davinci.c
 F:	drivers/serial/serial_omap.c
@@ -572,12 +526,7 @@ R:	Linus Walleij <linus.walleij@linaro.org>
 S:	Maintained
 F:	arch/arm/dts/ste-*
 F:	arch/arm/mach-u8500/
-F:	drivers/gpio/nmk_gpio.c
-F:	drivers/phy/phy-ab8500-usb.c
-F:	drivers/power/pmic/ab8500.c
 F:	drivers/timer/nomadik-mtu-timer.c
-F:	drivers/usb/musb-new/ux500.c
-F:	drivers/video/mcde_simple.c
 
 ARM UNIPHIER
 S:	Orphan (Since 2020-09)
@@ -637,7 +586,6 @@ F:	drivers/clk/clk_zynqmp.c
 F:	driver/firmware/firmware-zynqmp.c
 F:	drivers/fpga/zynqpl.c
 F:	drivers/gpio/zynq_gpio.c
-F:	drivers/gpio/zynqmp_gpio_modepin.c
 F:	drivers/i2c/i2c-cdns.c
 F:	drivers/i2c/muxes/pca954x.c
 F:	drivers/i2c/zynq_i2c.c
@@ -646,7 +594,6 @@ F:	drivers/mmc/zynq_sdhci.c
 F:	drivers/mtd/nand/raw/zynq_nand.c
 F:	drivers/net/phy/xilinx_phy.c
 F:	drivers/net/zynq_gem.c
-F:	drivers/phy/phy-zynqmp.c
 F:	drivers/serial/serial_zynq.c
 F:	drivers/reset/reset-zynqmp.c
 F:	drivers/rtc/zynqmp_rtc.c
@@ -704,7 +651,6 @@ F:	drivers/mtd/jedec_flash.c
 
 CLOCK
 M:	Lukasz Majewski <lukma@denx.de>
-M:	Sean Anderson <seanga2@gmail.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-clk.git
 F:	drivers/clk/
@@ -742,27 +688,13 @@ F:	drivers/core/
 F:	include/dm/
 F:	test/dm/
 
-EFI APP
-M:	Simon Glass <sjg@chromium.org>
-M:	Heinrich Schuchardt <xypron.glpk@gmx.de>
-S:	Maintained
-W:	https://u-boot.readthedocs.io/en/latest/develop/uefi/u-boot_on_efi.html
-F:	board/efi/efi-x86_app
-F:	configs/efi-x86_app*
-F:	doc/develop/uefi/u-boot_on_efi.rst
-F:	drivers/block/efi-media-uclass.c
-F:	drivers/block/sb_efi_media.c
-F:	lib/efi/efi_app.c
-F:	scripts/build-efi.sh
-F:	test/dm/efi_media.c
-
 EFI PAYLOAD
 M:	Heinrich Schuchardt <xypron.glpk@gmx.de>
+R:	Alexander Graf <agraf@csgraf.de>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-efi.git
 F:	doc/api/efi.rst
 F:	doc/develop/uefi/*
-F:	doc/mkeficapsule.1
 F:	doc/usage/bootefi.rst
 F:	drivers/rtc/emul_rtc.c
 F:	include/capitalization.h
@@ -801,25 +733,6 @@ F:	test/env/
 F:	tools/env*
 F:	tools/mkenvimage.c
 
-ENVIRONMENT AS TEXT
-M:	Simon Glass <sjg@chromium.org>
-R:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	doc/usage/environment.rst
-F:	scripts/env2string.awk
-
-FASTBOOT
-S:	Orphaned
-F:	cmd/fastboot.c
-F:	doc/android/fastboot*.rst
-F:	include/fastboot.h
-F:	include/fastboot-internal.h
-F:	include/net/fastboot.h
-F:	drivers/fastboot/
-F:	drivers/usb/gadget/f_fastboot.c
-F:	net/fastboot.c
-F:	test/dm/fastboot.c
-
 FPGA
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
@@ -838,7 +751,6 @@ F:	include/fdt*
 F:	include/linux/libfdt*
 F:	cmd/fdt.c
 F:	common/fdt_support.c
-F:	scripts/dtc-version.sh
 
 FREEBSD
 M:	Rafal Jaworowski <raj@semihalf.com>
@@ -858,16 +770,6 @@ S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-i2c.git
 F:	drivers/i2c/
 
-KWBIMAGE / KWBOOT TOOLS
-M:	Pali Rohár <pali@kernel.org>
-M:	Marek Behún <marek.behun@nic.cz>
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
-F:	doc/README.kwbimage
-F:	doc/kwboot.1
-F:	tools/kwb*
-
 LOGGING
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -1109,7 +1011,6 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-riscv.git
 F:	arch/riscv/
 F:	cmd/riscv/
 F:	doc/usage/sbi.rst
-F:	drivers/sysreset/sysreset_sbi.c
 F:	drivers/timer/andes_plmt_timer.c
 F:	drivers/timer/sifive_clint_timer.c
 F:	tools/prelink-riscv.c
@@ -1247,11 +1148,6 @@ F:	configs/am65x_hs_evm_a53_defconfig
 F:	configs/j721e_hs_evm_r5_defconfig
 F:	configs/j721e_hs_evm_a72_defconfig
 
-TPM DRIVERS
-M:	Ilias Apalodimas <ilias.apalodimas@linaro.org>
-S:	Maintained
-F:	drivers/tpm/
-
 TQ GROUP
 #M:	Martin Krause <martin.krause@tq-systems.de>
 S:	Orphaned (Since 2016-02)
@@ -1327,7 +1223,7 @@ F:	arch/x86/
 F:	cmd/x86/
 
 XEN
-M:	Anastasiia Lukianenko <vicooodin@gmail.com>
+M:	Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
 M:	Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
 S:	Maintained
 F:	arch/arm/cpu/armv8/xen/

Makefile

@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-VERSION = 2022
-PATCHLEVEL = 04
+VERSION = 2021
+PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -stm32mp-r2
 NAME =
 
 # *DOCUMENTATION*
@@ -299,7 +299,9 @@ KBUILD_HOSTLDLIBS   := $(HOST_LFS_LIBS) $(HOSTLDLIBS)
 # have older compilers as their default, so we make it explicit for
 # these that our host tools are GNU11 (i.e. C11 w/ GNU extensions).
 CSTD_FLAG := -std=gnu11
+ifeq ($(HOSTOS),linux)
 KBUILD_HOSTCFLAGS += $(CSTD_FLAG)
+endif
 
 ifeq ($(HOSTOS),cygwin)
 KBUILD_HOSTCFLAGS	+= -ansi
@@ -325,14 +327,14 @@ os_x_before	= $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \
 	$(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
 
 os_x_after = $(shell if [ $(DARWIN_MAJOR_VERSION) -ge $(1) -a \
-	$(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
+	$(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)	
 
 # Snow Leopards build environment has no longer restrictions as described above
 HOSTCC       = $(call os_x_before, 10, 5, "cc", "gcc")
 KBUILD_HOSTCFLAGS  += $(call os_x_before, 10, 4, "-traditional-cpp")
 KBUILD_HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")
 
-# macOS Mojave (10.14.X)
+# macOS Mojave (10.14.X) 
 # Undefined symbols for architecture x86_64: "_PyArg_ParseTuple"
 KBUILD_HOSTLDFLAGS += $(call os_x_after, 10, 14, "-lpython -dynamclib", "")
 endif
@@ -413,13 +415,7 @@ PERL		= perl
 PYTHON		?= python
 PYTHON2		= python2
 PYTHON3		?= python3
-
-# The devicetree compiler and pylibfdt are automatically built unless DTC is
-# provided. If DTC is provided, it is assumed the pylibfdt is available too.
-DTC_INTREE	:= $(objtree)/scripts/dtc/dtc
-DTC		?= $(DTC_INTREE)
-DTC_MIN_VERSION	:= 010406
-
+DTC		?= $(objtree)/scripts/dtc/dtc
 CHECK		= sparse
 
 CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@@ -517,11 +513,10 @@ version_h := include/generated/version_autogenerated.h
 timestamp_h := include/generated/timestamp_autogenerated.h
 defaultenv_h := include/generated/defaultenv_autogenerated.h
 dt_h := include/generated/dt.h
-env_h := include/generated/environment.h
 
 no-dot-config-targets := clean clobber mrproper distclean \
 			 help %docs check% coccicheck \
-			 ubootversion backup tests check qcheck tcheck pylint
+			 ubootversion backup tests check qcheck tcheck
 
 config-targets := 0
 mixed-targets  := 0
@@ -809,7 +804,6 @@ HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makef
 
 libs-$(CONFIG_API) += api/
 libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
-libs-y += boot/
 libs-y += cmd/
 libs-y += common/
 libs-$(CONFIG_OF_EMBED) += dts/
@@ -819,9 +813,23 @@ libs-y += fs/
 libs-y += net/
 libs-y += disk/
 libs-y += drivers/
+libs-y += drivers/dma/
+libs-y += drivers/gpio/
+libs-y += drivers/net/
+libs-y += drivers/net/phy/
+libs-y += drivers/power/ \
+	drivers/power/domain/ \
+	drivers/power/fuel_gauge/ \
+	drivers/power/mfd/ \
+	drivers/power/pmic/ \
+	drivers/power/battery/ \
+	drivers/power/regulator/
+libs-y += drivers/spi/
+libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
 libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
 libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
 libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/
+libs-y += drivers/serial/
 libs-y += drivers/usb/cdns3/
 libs-y += drivers/usb/dwc3/
 libs-y += drivers/usb/common/
@@ -835,6 +843,7 @@ libs-y += drivers/usb/mtu3/
 libs-y += drivers/usb/musb/
 libs-y += drivers/usb/musb-new/
 libs-y += drivers/usb/phy/
+libs-y += drivers/usb/typec/
 libs-y += drivers/usb/ulpi/
 ifdef CONFIG_POST
 libs-y += post/
@@ -944,13 +953,12 @@ INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
 endif
 endif
 INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
-
-# Allow omitting the .dtb output if it is not normally used
-INPUTS-$(CONFIG_OF_SEPARATE) += $(if $(CONFIG_OF_OMIT_DTB),dts/dt.dtb,u-boot.dtb)
+INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb
+INPUTS-$(CONFIG_BINMAN_STANDALONE_FDT) += u-boot.dtb
 ifeq ($(CONFIG_SPL_FRAMEWORK),y)
 INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
 endif
-INPUTS-$(CONFIG_SANDBOX) += u-boot.dtb
+INPUTS-$(CONFIG_OF_HOSTFILE) += u-boot.dtb
 ifneq ($(CONFIG_SPL_TARGET),)
 INPUTS-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
 endif
@@ -1000,9 +1008,6 @@ LDFLAGS_u-boot += $(LDFLAGS_FINAL)
 # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
 LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)
 
-# ld.lld support
-LDFLAGS_u-boot += -z notext
-
 LDFLAGS_u-boot += --build-id=none
 
 ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),)
@@ -1055,10 +1060,6 @@ quiet_cmd_cfgcheck = CFGCHK  $2
 cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
 		$(srctree)/scripts/config_whitelist.txt $(srctree)
 
-quiet_cmd_ofcheck = OFCHK   $2
-cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \
-		$(srctree)/scripts/of_allowlist.txt
-
 # Concat the value of all the CONFIGs (result is 'y' or 'yy', etc. )
 got = $(foreach cfg,$(1),$($(cfg)))
 
@@ -1101,7 +1102,7 @@ endif
 ifeq ($(CONFIG_DEPRECATED),y)
 	$(warning "You have deprecated configuration options enabled in your .config! Please check your configuration.")
 endif
-ifeq ($(CONFIG_OF_EMBED)$(CONFIG_EFI_APP),y)
+ifeq ($(CONFIG_OF_EMBED),y)
 	@echo >&2 "===================== WARNING ======================"
 	@echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
 	@echo >&2 "be used for debugging purposes. Please use"
@@ -1123,25 +1124,22 @@ ifneq ($(CONFIG_DM),y)
 	@echo >&2 "Failure to update may result in board removal."
 	@echo >&2 "See doc/driver-model/migration.rst for more info."
 	@echo >&2 "===================================================="
+endif
+ifeq ($(CONFIG_STM32MP15x_STM32IMAGE),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board uses CONFIG_STM32MP15x_STM32IMAGE for STM32 image"
+	@echo >&2 "support in TF-A and these configuration is deprecated."
+	@echo >&2 "Please migrate to FIP support in TF-A instead."
+	@echo >&2 "===================================================="
 endif
 	$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
 		$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
 	$(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET))
 	$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
-	$(call deprecated,CONFIG_DM_KEYBOARD,Keyboard drivers,v2022.10,$(CONFIG_KEYBOARD))
-	@# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which
-	@# confuses this rule. Use if() to send just a single character which
-	@# is enable to tell 'deprecated' that one of these symbols exists
-	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x))
-	$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
-	$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
 	@# Check that this build does not use CONFIG options that we do not
 	@# know about unless they are in Kconfig. All the existing CONFIG
 	@# options are whitelisted, so new ones should not be added.
 	$(call cmd,cfgcheck,u-boot.cfg)
-	@# Check that this build does not override OF_HAS_PRIOR_STAGE by
-	@# disabling OF_BOARD.
-	$(call cmd,ofcheck,$(KCONFIG_CONFIG))
 
 PHONY += dtbs
 dtbs: dts/dt.dtb
@@ -1195,7 +1193,7 @@ u-boot.bin: u-boot-fit-dtb.bin FORCE
 u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
 	$(call if_changed,cat)
 
-else ifeq ($(CONFIG_OF_SEPARATE).$(CONFIG_OF_OMIT_DTB),y.)
+else ifeq ($(CONFIG_OF_SEPARATE),y)
 u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
 	$(call if_changed,cat)
 
@@ -1262,7 +1260,7 @@ binary_size_check: u-boot-nodtb.bin FORCE
 			echo "u-boot.map shows a binary size of $$map_size" >&2 ; \
 			echo "  but u-boot-nodtb.bin shows $$file_size" >&2 ; \
 			exit 1; \
-		fi; \
+		fi \
 	fi
 
 ifeq ($(CONFIG_INIT_SP_RELATIVE)$(CONFIG_OF_SEPARATE),yy)
@@ -1316,24 +1314,24 @@ u-boot.ldr:	u-boot
 # Use 'make BINMAN_VERBOSE=3' to set vebosity level
 default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
 
+# Tell binman whether we have a devicetree for SPL and TPL
+have_spl_dt := $(if $(CONFIG_SPL_OF_PLATDATA),,$(CONFIG_SPL_OF_CONTROL))
+have_tpl_dt := $(if $(CONFIG_TPL_OF_PLATDATA),,$(CONFIG_TPL_OF_CONTROL))
+
 quiet_cmd_binman = BINMAN  $@
 cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
-		$(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \
                 --toolpath $(objtree)/tools \
 		$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
 		build -u -d u-boot.dtb -O . -m --allow-missing \
-		--fake-ext-blobs \
 		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
 		-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
-		$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
 		-a atf-bl31-path=${BL31} \
 		-a opensbi-path=${OPENSBI} \
 		-a default-dt=$(default_dt) \
 		-a scp-path=$(SCP) \
 		-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
 		-a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \
-		-a spl-dtb=$(CONFIG_SPL_OF_REAL) \
-		-a tpl-dtb=$(CONFIG_TPL_OF_REAL) \
+		-a spl-dtb=$(have_spl_dt) -a tpl-dtb=$(have_tpl_dt) \
 		$(BINMAN_$(@F))
 
 OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
@@ -1362,6 +1360,9 @@ $(U_BOOT_ITS): $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
 else
 ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),)
 U_BOOT_ITS := u-boot.its
+ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
+U_BOOT_ITS_DEPS += u-boot-nodtb.bin
+endif
 ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
 U_BOOT_ITS_DEPS += u-boot
 endif
@@ -1430,7 +1431,7 @@ u-boot-lzma.img: u-boot.bin.lzma FORCE
 
 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
 		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
-			$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \
+			$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \
 		,$(UBOOT_BIN)) FORCE
 	$(call if_changed,mkimage)
 	$(BOARD_SIZE_CHECK)
@@ -1444,7 +1445,7 @@ MKIMAGEFLAGS_u-boot.itb += -B 0x8
 
 ifdef U_BOOT_ITS
 u-boot.itb: u-boot-nodtb.bin \
-		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \
+		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
 		$(U_BOOT_ITS) FORCE
 	$(call if_changed,mkfitimage)
 	$(BOARD_SIZE_CHECK)
@@ -1536,6 +1537,7 @@ else
 ifeq ($(CONFIG_BINMAN),y)
 flash.bin: spl/u-boot-spl.bin $(INPUTS-y) FORCE
 	$(call if_changed,binman)
+	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 else
 flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
@@ -1762,7 +1764,7 @@ endif
 # May be overridden by arch/$(ARCH)/config.mk
 ifdef CONFIG_LTO
 quiet_cmd_u-boot__ ?= LTO     $@
-      cmd_u-boot__ ?=								\
+      cmd_u-boot__ ?= 								\
 		$(CC) -nostdlib -nostartfiles					\
 		$(LTO_FINAL_LDFLAGS) $(c_flags)					\
 		$(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@	\
@@ -1775,10 +1777,6 @@ quiet_cmd_u-boot__ ?= LTO     $@
 		-Wl,-Map,u-boot.map;						\
 		$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
 else
-# Note: Linking efi-x86_app64 causes a segfault in the linker at present
-# when using x86_64-linux-gnu-ld.bfd
-# For now, disable --whole-archive which makes things link, although not
-# correctly
 quiet_cmd_u-boot__ ?= LD      $@
       cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@		\
 		-T u-boot.lds $(u-boot-init)					\
@@ -1812,69 +1810,6 @@ quiet_cmd_sym ?= SYM     $@
 u-boot.sym: u-boot FORCE
 	$(call if_changed,sym)
 
-# Environment processing
-# ---------------------------------------------------------------------------
-
-# Directory where we expect the .env file, if it exists
-ENV_DIR := $(srctree)/board/$(BOARDDIR)
-
-# Basename of .env file, stripping quotes
-ENV_SOURCE_FILE := $(CONFIG_ENV_SOURCE_FILE:"%"=%)
-
-# Filename of .env file
-ENV_FILE_CFG := $(ENV_DIR)/$(ENV_SOURCE_FILE).env
-
-# Default filename, if CONFIG_ENV_SOURCE_FILE is empty
-ENV_FILE_BOARD := $(ENV_DIR)/$(CONFIG_SYS_BOARD:"%"=%).env
-
-# Select between the CONFIG_ENV_SOURCE_FILE and the default one
-ENV_FILE := $(if $(ENV_SOURCE_FILE),$(ENV_FILE_CFG),$(wildcard $(ENV_FILE_BOARD)))
-
-# Run the environment text file through the preprocessor, but only if it is
-# non-empty, to save time and possible build errors if something is wonky with
-# the board
-quiet_cmd_gen_envp = ENVP    $@
-      cmd_gen_envp = \
-	if [ -s "$(ENV_FILE)" ]; then \
-		$(CPP) -P $(CFLAGS) -x assembler-with-cpp -D__ASSEMBLY__ \
-			-D__UBOOT_CONFIG__ \
-			-I . -I include -I $(srctree)/include \
-			-include linux/kconfig.h -include include/config.h \
-			-I$(srctree)/arch/$(ARCH)/include \
-			$< -o $@; \
-	else \
-		touch $@ ; \
-	fi
-include/generated/env.in: include/generated/env.txt FORCE
-	$(call cmd,gen_envp)
-
-# Regenerate the environment if it changes
-# We use 'wildcard' since the file is not required to exist (at present), in
-# which case we don't want this dependency, but instead should create an empty
-# file
-# This rule is useful since it shows the source file for the environment
-quiet_cmd_envc = ENVC    $@
-      cmd_envc = \
-	if [ -f "$<" ]; then \
-		cat $< > $@; \
-	elif [ -n "$(ENV_SOURCE_FILE)" ]; then \
-		echo "Missing file $(ENV_FILE_CFG)"; \
-	else \
-		touch $@ ; \
-	fi
-
-include/generated/env.txt: $(wildcard $(ENV_FILE)) FORCE
-	$(call cmd,envc)
-
-# Write out the resulting environment, converted to a C string
-quiet_cmd_gen_envt = ENVT    $@
-      cmd_gen_envt = \
-	awk -f $(srctree)/scripts/env2string.awk $< >$@
-$(env_h): include/generated/env.in
-	$(call cmd,gen_envt)
-
-# ---------------------------------------------------------------------------
-
 # The actual objects are generated when descending,
 # make sure no implicit rule kicks in
 $(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
@@ -1930,7 +1865,7 @@ endif
 # prepare2 creates a makefile if using a separate output directory
 prepare2: prepare3 outputmakefile cfg
 
-prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) $(env_h) \
+prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) \
                    include/config/auto.conf
 ifeq ($(wildcard $(LDSCRIPT)),)
 	@echo >&2 "  Could not find linker script."
@@ -1980,6 +1915,7 @@ define filechk_timestamp.h
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"'; \
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
+			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_EPOCH %s'; \
 		else \
 			return 42; \
@@ -1988,6 +1924,7 @@ define filechk_timestamp.h
 		LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
 		LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
 		LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
+		LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
 		LC_ALL=C date +'#define U_BOOT_EPOCH %s'; \
 	fi)
 endef
@@ -2044,29 +1981,9 @@ endif
 
 endif
 
-# Check dtc and pylibfdt, if DTC is provided, else build them
 PHONY += scripts_dtc
 scripts_dtc: scripts_basic
-	$(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
-		$(MAKE) $(build)=scripts/dtc; \
-	else \
-		if ! $(DTC) -v >/dev/null; then \
-			echo '*** Failed to check dtc version: $(DTC)'; \
-			false; \
-		else \
-			if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
-				echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
-				false; \
-			else \
-				if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
-					if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
-						echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
-						false; \
-					fi; \
-				fi; \
-			fi; \
-		fi; \
-	fi
+	$(Q)$(MAKE) $(build)=scripts/dtc
 
 # ---------------------------------------------------------------------------
 quiet_cmd_cpp_lds = LDS     $@
@@ -2186,12 +2103,10 @@ CLEAN_DIRS  += $(MODVERDIR) \
 			$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
 
 CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \
-	       u-boot* MLO* SPL System.map fit-dtb.blob* \
+	       boot* u-boot* MLO* SPL System.map fit-dtb.blob* \
 	       u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
 	       lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
-	       idbloader.img flash.bin flash.log defconfig keep-syms-lto.c \
-	       mkimage-out.spl.mkimage mkimage.spl.mkimage imx-boot.map \
-	       itb.fit.fit itb.fit.itb itb.map spl.map
+	       idbloader.img flash.bin flash.log defconfig keep-syms-lto.c
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated spl tpl \
@@ -2258,49 +2173,6 @@ distclean: mrproper
 		-type f -print | xargs rm -f
 	@rm -f boards.cfg CHANGELOG
 
-# See doc/develop/python_cq.rst
-PHONY += pylint
-PYLINT_BASE := scripts/pylint.base
-PYLINT_CUR := pylint.cur
-PYLINT_DIFF := pylint.diff
-pylint:
-	$(Q)echo "Running pylint on all files (summary in $(PYLINT_CUR); output in pylint.out/)"
-	$(Q)mkdir -p pylint.out
-	$(Q)rm -f pylint.out/out*
-	$(Q)find tools test -name "*.py" \
-		| xargs -n1 -P$(shell nproc 2>/dev/null || echo 1) \
-			sh -c 'pylint --reports=y --exit-zero -f parseable --ignore-imports=yes $$@ > pylint.out/$$(echo $$@ | tr / _ | sed s/.py//)' _
-	$(Q)rm -f $(PYLINT_CUR)
-	$(Q)( cd pylint.out; for f in *; do \
-		sed -ne "s/Your code has been rated at \([-0-9.]*\).*/$$f \1/p" $$f; \
-	done ) | sort > $(PYLINT_CUR)
-	$(Q)base=$$(mktemp) cur=$$(mktemp); cut -d' ' -f1 $(PYLINT_BASE) >$$base; \
-		cut -d' ' -f1 $(PYLINT_CUR) >$$cur; \
-		comm -3 $$base $$cur > $(PYLINT_DIFF); \
-		if [ -s $(PYLINT_DIFF) ]; then \
-			echo "Files have been added/removed. Try:\n\tcp $(PYLINT_CUR) $(PYLINT_BASE)"; \
-			echo; \
-			echo "Added files:"; \
-			comm -13 $$base $$cur; \
-			echo; \
-			echo "Removed files:"; \
-			comm -23 $$base $$cur; \
-			false; \
-		else \
-			rm $$base $$cur $(PYLINT_DIFF); \
-		fi
-	$(Q)bad=false; while read base_file base_val <&3 && read cur_file cur_val <&4; do \
-		if awk "BEGIN {exit !($$cur_val < $$base_val)}"; then \
-			echo "$$base_file: Score was $$base_val, now $$cur_val"; \
-			bad=true; fi; \
-		done 3<$(PYLINT_BASE) 4<$(PYLINT_CUR); \
-		if $$bad; then \
-			echo "Some files have regressed, please fix"; \
-			false; \
-		else \
-			echo "No pylint regressions"; \
-		fi
-
 backup:
 	F=`basename $(srctree)` ; cd .. ; \
 	gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
@@ -2319,7 +2191,6 @@ help:
 	@echo  '  check           - Run all automated tests that use sandbox'
 	@echo  '  qcheck          - Run quick automated tests that use sandbox'
 	@echo  '  tcheck          - Run quick automated tests on tools'
-	@echo  '  pylint          - Run pylint on all Python files'
 	@echo  ''
 	@echo  'Other generic targets:'
 	@echo  '  all		  - Build all necessary images depending on configuration'

README

@@ -144,7 +144,6 @@ Directory Hierarchy:
   /xtensa		Files generic to Xtensa architecture
 /api			Machine/arch-independent API for external apps
 /board			Board-dependent files
-/boot			Support for images and booting
 /cmd			U-Boot commands functions
 /common			Misc architecture-independent functions
 /configs		Board default configuration files
@@ -301,6 +300,7 @@ board_init_r():
 	- loads U-Boot or (in falcon mode) Linux
 
 
+
 Configuration Options:
 ----------------------
 
@@ -465,6 +465,10 @@ The following options need to be configured:
 		Board config to use DDR3L. It can be enabled for SoCs with
 		DDR3L controllers.
 
+		CONFIG_SYS_FSL_DDR4
+		Board config to use DDR4. It can be enabled for SoCs with
+		DDR4 controllers.
+
 		CONFIG_SYS_FSL_IFC_BE
 		Defines the IFC controller register space as Big Endian
 
@@ -477,6 +481,15 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_LBC_CLK_DIV
 		Defines divider of platform clock(clock input to eLBC controller).
 
+		CONFIG_SYS_FSL_PBL_PBI
+		It enables addition of RCW (Power on reset configuration) in built image.
+		Please refer doc/README.pblimage for more details
+
+		CONFIG_SYS_FSL_PBL_RCW
+		It adds PBI(pre-boot instructions) commands in u-boot build image.
+		PBI commands can be used to configure SoC before it starts the execution.
+		Please refer doc/README.pblimage for more details
+
 		CONFIG_SYS_FSL_DDR_BE
 		Defines the DDR controller register space as Big Endian
 
@@ -565,6 +578,11 @@ The following options need to be configured:
 		boards with QUICC Engines require OF_QE to set UCC MAC
 		addresses
 
+		CONFIG_OF_BOARD_SETUP
+
+		Board code has addition modification that it wants to make
+		to the flat device tree before handing it off to the kernel
+
 		CONFIG_OF_SYSTEM_SETUP
 
 		Other code has addition modification that it wants to make
@@ -581,6 +599,16 @@ The following options need to be configured:
 		crash. This is needed for buggy hardware (uc101) where
 		no pull down resistor is connected to the signal IDE5V_DD7.
 
+		CONFIG_MACH_TYPE	[relevant for ARM only][mandatory]
+
+		This setting is mandatory for all boards that have only one
+		machine type and must be used to specify the machine type
+		number as it appears in the ARM machine registry
+		(see https://www.arm.linux.org.uk/developer/machines/).
+		Only boards that have multiple machine types supported
+		in a single configuration file and the machine type is
+		runtime discoverable, do not have to use this setting.
+
 - vxWorks boot parameters:
 
 		bootvx constructs a valid bootline using the following
@@ -591,6 +619,9 @@ The following options need to be configured:
 		Note: If a "bootargs" environment is defined, it will override
 		the defaults discussed just above.
 
+- Cache Configuration:
+		CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
+
 - Cache Configuration for ARM:
 		CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
 				      controller
@@ -598,6 +629,10 @@ The following options need to be configured:
 					controller register space
 
 - Serial Ports:
+		CONFIG_PL011_SERIAL
+
+		Define this if you want support for Amba PrimeCell PL011 UARTs.
+
 		CONFIG_PL011_CLOCK
 
 		If you have Amba PrimeCell PL011 UARTs, set this variable to
@@ -614,6 +649,19 @@ The following options need to be configured:
 		Define this variable to enable hw flow control in serial driver.
 		Current user of this option is drivers/serial/nsl16550.c driver
 
+- Autoboot Command:
+		CONFIG_BOOTCOMMAND
+		Only needed when CONFIG_BOOTDELAY is enabled;
+		define a command string that is automatically executed
+		when no character is read on the console interface
+		within "Boot Delay" after reset.
+
+		CONFIG_RAMBOOT and CONFIG_NFSBOOT
+		The value of these goes into the environment as
+		"ramboot" and "nfsboot" respectively, and can be used
+		as a convenience, when switching between booting from
+		RAM and NFS.
+
 - Serial Download Echo Mode:
 		CONFIG_LOADS_ECHO
 		If defined to 1, all characters received during a
@@ -623,6 +671,11 @@ The following options need to be configured:
 		time on others. This setting #define's the initial
 		value of the "loads_echo" environment variable.
 
+- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
+		CONFIG_KGDB_BAUDRATE
+		Select one of the baudrates listed in
+		CONFIG_SYS_BAUDRATE_TABLE, see below.
+
 - Removal of commands
 		If no commands are needed to boot, you can disable
 		CONFIG_CMDLINE to remove them. In this case, the command line
@@ -638,7 +691,57 @@ The following options need to be configured:
 		which adds regex support to some commands, as for
 		example "env grep" and "setexpr".
 
+- Device tree:
+		CONFIG_OF_CONTROL
+		If this variable is defined, U-Boot will use a device tree
+		to configure its devices, instead of relying on statically
+		compiled #defines in the board file. This option is
+		experimental and only available on a few boards. The device
+		tree is available in the global data as gd->fdt_blob.
+
+		U-Boot needs to get its device tree from somewhere. This can
+		be done using one of the three options below:
+
+		CONFIG_OF_EMBED
+		If this variable is defined, U-Boot will embed a device tree
+		binary in its image. This device tree file should be in the
+		board directory and called <soc>-<board>.dts. The binary file
+		is then picked up in board_init_f() and made available through
+		the global data structure as gd->fdt_blob.
+
+		CONFIG_OF_SEPARATE
+		If this variable is defined, U-Boot will build a device tree
+		binary. It will be called u-boot.dtb. Architecture-specific
+		code will locate it at run-time. Generally this works by:
+
+			cat u-boot.bin u-boot.dtb >image.bin
+
+		and in fact, U-Boot does this for you, creating a file called
+		u-boot-dtb.bin which is useful in the common case. You can
+		still use the individual files if you need something more
+		exotic.
+
+		CONFIG_OF_BOARD
+		If this variable is defined, U-Boot will use the device tree
+		provided by the board at runtime instead of embedding one with
+		the image. Only boards defining board_fdt_blob_setup() support
+		this option (see include/fdtdec.h file).
+
 - Watchdog:
+		CONFIG_WATCHDOG
+		If this variable is defined, it enables watchdog
+		support for the SoC. There must be support in the SoC
+		specific code for a watchdog. For the 8xx
+		CPUs, the SIU Watchdog feature is enabled in the SYPCR
+		register.  When supported for a specific SoC is
+		available, then no further board specific code should
+		be needed to use it.
+
+		CONFIG_HW_WATCHDOG
+		When using a watchdog circuitry external to the used
+		SoC, then define this variable and provide board
+		specific code for the "hw_watchdog_reset" function.
+
 		CONFIG_SYS_WATCHDOG_FREQ
 		Some platforms automatically call WATCHDOG_RESET()
 		from the timer interrupt handler every
@@ -720,6 +823,20 @@ The following options need to be configured:
 		CONFIG_SCSI) you must configure support for at
 		least one non-MTD partition type as well.
 
+- IDE Reset method:
+		CONFIG_IDE_RESET_ROUTINE - this is defined in several
+		board configurations files but used nowhere!
+
+		CONFIG_IDE_RESET - is this is defined, IDE Reset will
+		be performed by calling the function
+			ide_set_reset(int reset)
+		which has to be defined in a board specific file
+
+- ATAPI Support:
+		CONFIG_ATAPI
+
+		Set this to enable ATAPI support.
+
 - LBA48 Support
 		CONFIG_LBA48
 
@@ -732,12 +849,29 @@ The following options need to be configured:
 			When enabled, makes the IDE subsystem use 64bit sector addresses.
 			Default is 32bit.
 
+- SCSI Support:
+		CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
+		CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
+		CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
+		maximum numbers of LUNs, SCSI ID's and target
+		devices.
+
+		The environment variable 'scsidevs' is set to the number of
+		SCSI devices found during the last scan.
+
 - NETWORK Support (PCI):
+		CONFIG_E1000
+		Support for Intel 8254x/8257x gigabit chips.
+
 		CONFIG_E1000_SPI
 		Utility code for direct access to the SPI bus on Intel 8257x.
 		This does not do anything useful unless you set at least one
 		of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC.
 
+		CONFIG_E1000_SPI_GENERIC
+		Allow generic access to the SPI bus on the Intel 8257x, for
+		example with the "sspi" command.
+
 		CONFIG_NATSEMI
 		Support for National dp83815 chips.
 
@@ -745,6 +879,17 @@ The following options need to be configured:
 		Support for National dp8382[01] gigabit chips.
 
 - NETWORK Support (other):
+
+		CONFIG_DRIVER_AT91EMAC
+		Support for AT91RM9200 EMAC.
+
+			CONFIG_RMII
+			Define this to use reduced MII inteface
+
+			CONFIG_DRIVER_AT91EMAC_QUIET
+			If this defined, the driver is quiet.
+			The driver doen't show link status messages.
+
 		CONFIG_CALXEDA_XGMAC
 		Support for the Calxeda XGMAC device
 
@@ -886,6 +1031,10 @@ The following options need to be configured:
 			whether the enumeration has succeded at high speed or full
 			speed.
 
+			CONFIG_SYS_CONSOLE_IS_IN_ENV
+			Define this if you want stdin, stdout &/or stderr to
+			be set to usbtty.
+
 		If you have a USB-IF assigned VendorID then you may wish to
 		define your own vendor specific values either in BoardName.h
 		or directly in usbd_vendor_info.h. If you don't define
@@ -978,6 +1127,9 @@ The following options need to be configured:
 		sending again an USB request to the device.
 
 - Journaling Flash filesystem support:
+		CONFIG_JFFS2_NAND
+		Define these for a default partition on a NAND device
+
 		CONFIG_SYS_JFFS2_FIRST_SECTOR,
 		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
 		Define these for a default partition on a NOR device
@@ -985,6 +1137,14 @@ The following options need to be configured:
 - Keyboard Support:
 		See Kconfig help for available keyboard drivers.
 
+		CONFIG_KEYBOARD
+
+		Define this to enable a custom keyboard support.
+		This simply calls drv_keyboard_init() which must be
+		defined in your board-specific files. This option is deprecated
+		and is only used by novena. For new boards, use driver model
+		instead.
+
 - Video support:
 		CONFIG_FSL_DIU_FB
 		Enable the Freescale DIU video driver.	Reference boards for
@@ -996,6 +1156,7 @@ The following options need to be configured:
 			CONFIG_CFB_CONSOLE
 			CONFIG_VIDEO_SW_CURSOR
 			CONFIG_VGA_AS_SINGLE_DEVICE
+			CONFIG_VIDEO_LOGO
 			CONFIG_VIDEO_BMP_LOGO
 
 		The DIU driver will look for the 'video-mode' environment
@@ -1085,6 +1246,11 @@ The following options need to be configured:
 
 		Support drawing of RLE8-compressed bitmaps on the LCD.
 
+		CONFIG_I2C_EDID
+
+		Enables an 'i2c edid' command which can read EDID
+		information over I2C from an attached LCD display.
+
 - MII/PHY support:
 		CONFIG_PHY_CLOCK_FREQ (ppc4xx)
 
@@ -1117,6 +1283,11 @@ The following options need to be configured:
 		server to contact when using the "tftboot" command.
 		(Environment variable "serverip")
 
+		CONFIG_KEEP_SERVERADDR
+
+		Keeps the server's MAC address, in the env 'serveraddr'
+		for passing to bootargs (like Linux's netconsole option)
+
 - Gateway IP address:
 		CONFIG_GATEWAYIP
 
@@ -1182,6 +1353,9 @@ The following options need to be configured:
 		CONFIG_BOOTP_VENDOREX
 		CONFIG_BOOTP_MAY_FAIL
 
+		CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
+		environment variable, not the BOOTP server.
+
 		CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
 		after the configured retry count, the call will fail
 		instead of starting over.  This can be used to fail over
@@ -1287,7 +1461,129 @@ The following options need to be configured:
 		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
 		with a list of GPIO LEDs that have inverted polarity.
 
-- I2C Support:
+- I2C Support:	CONFIG_SYS_I2C_LEGACY
+
+		Note: This is deprecated in favour of driver model. Use
+		CONFIG_DM_I2C instead.
+
+		This enable the legacy i2c subsystem, and will allow you to use
+		i2c commands at the u-boot command line (as long as you set
+		    CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
+		    for defining speed and slave address
+		  - activate second bus with I2C_SOFT_DECLARATIONS2 define
+		    CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
+		    for defining speed and slave address
+		  - activate third bus with I2C_SOFT_DECLARATIONS3 define
+		    CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
+		    for defining speed and slave address
+		  - activate fourth bus with I2C_SOFT_DECLARATIONS4 define
+		    CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
+		    for defining speed and slave address
+
+		- drivers/i2c/fsl_i2c.c:
+		  - activate i2c driver with CONFIG_SYS_I2C_FSL
+		    define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
+		    offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
+		    CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
+		    bus.
+		  - If your board supports a second fsl i2c bus, define
+		    CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
+		    CONFIG_SYS_FSL_I2C2_SPEED for the speed and
+		    CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
+		    second bus.
+
+		- drivers/i2c/tegra_i2c.c:
+		  - activate this driver with CONFIG_SYS_I2C_TEGRA
+		  - This driver adds 4 i2c buses with a fix speed from
+		    100000 and the slave addr 0!
+
+		- drivers/i2c/ppc4xx_i2c.c
+		  - activate this driver with CONFIG_SYS_I2C_PPC4XX
+		  - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
+		  - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
+
+		- drivers/i2c/i2c_mxc.c
+		  - activate this driver with CONFIG_SYS_I2C_MXC
+		  - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
+		  - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
+		  - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
+		  - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
+		  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
+		  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
+		  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
+		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
+		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
+		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
+		  - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
+		  - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
+		If those defines are not set, default value is 100000
+		for speed, and 0 for slave.
+
+		- drivers/i2c/rcar_i2c.c:
+		  - activate this driver with CONFIG_SYS_I2C_RCAR
+		  - This driver adds 4 i2c buses
+
+		- drivers/i2c/sh_i2c.c:
+		  - activate this driver with CONFIG_SYS_I2C_SH
+		  - This driver adds from 2 to 5 i2c buses
+
+		  - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
+		  - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
+		  - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
+		  - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
+		  - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
+		  - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
+		  - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
+		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
+		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
+		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+		  - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
+
+		- drivers/i2c/omap24xx_i2c.c
+		  - activate this driver with CONFIG_SYS_I2C_OMAP24XX
+		  - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
+		  - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
+		  - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
+		  - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
+		  - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
+
+		- drivers/i2c/s3c24x0_i2c.c:
+		  - activate this driver with CONFIG_SYS_I2C_S3C24X0
+		  - This driver adds i2c buses (11 for Exynos5250, Exynos5420
+		    9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
+		    with a fix speed from 100000 and the slave addr 0!
+
+		- drivers/i2c/ihs_i2c.c
+		  - activate this driver with CONFIG_SYS_I2C_IHS
+		  - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
+		  - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
+		  - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
+		  - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
+		  - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
+		  - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
+		  - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
+		  - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
+		  - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
+		  - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
+		  - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
+		  - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
+		  - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL
+		  - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1
+		  - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1
+		  - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1
+		  - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1
+		  - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1
+		  - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1
+		  - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1
+		  - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1
+
+		additional defines:
+
 		CONFIG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c buses you want to use.
 
@@ -1465,6 +1761,16 @@ The following options need to be configured:
 		SPI EEPROM, also an instance works with Crystal A/D and
 		D/As on the SACSng board)
 
+		CONFIG_SOFT_SPI
+
+		Enables a software (bit-bang) SPI driver rather than
+		using hardware support. This is a general purpose
+		driver that only requires three general I/O port pins
+		(two outputs, one input) to function. If this is
+		defined, the board configuration must define several
+		SPI configuration items (port pins to use, etc). For
+		an example, see include/configs/sacsng.h.
+
 		CONFIG_SYS_SPI_MXC_WAIT
 		Timeout for waiting until spi transfer completed.
 		default: (CONFIG_SYS_HZ/100)     /* 10 ms */
@@ -1530,6 +1836,13 @@ The following options need to be configured:
 		Time to wait after FPGA configuration. The default is
 		200 ms.
 
+- Configuration Management:
+
+		CONFIG_IDENT_STRING
+
+		If defined, this string will be added to the U-Boot
+		version information (U_BOOT_VERSION)
+
 - Vendor Parameter Protection:
 
 		U-Boot considers the values of the environment
@@ -1591,6 +1904,14 @@ The following options need to be configured:
 			HERMES, IP860, RPXlite, LWMON,
 			FLAGADM
 
+- Access to physical memory region (> 4GB)
+		Some basic support is provided for operations on memory not
+		normally accessible to U-Boot - e.g. some architectures
+		support access to more than 4GB of memory on 32-bit
+		machines using physical address extension or similar.
+		Define CONFIG_PHYSMEM to access this basic support, which
+		currently only supports clearing the memory.
+
 - Error Recovery:
 		CONFIG_NET_RETRY_COUNT
 
@@ -1789,6 +2110,9 @@ The following options need to be configured:
 		CONFIG_SPL
 		Enable building of SPL globally.
 
+		CONFIG_SPL_LDSCRIPT
+		LDSCRIPT for linking the SPL binary.
+
 		CONFIG_SPL_MAX_FOOTPRINT
 		Maximum size in memory allocated to the SPL, BSS included.
 		When defined, the linker checks that the actual memory
@@ -1843,6 +2167,10 @@ The following options need to be configured:
 		CONFIG_SYS_SPL_MALLOC_SIZE
 		The size of the malloc pool used in SPL.
 
+		CONFIG_SPL_OS_BOOT
+		Enable booting directly to an OS from SPL.
+		See also: doc/README.falcon
+
 		CONFIG_SPL_DISPLAY_PRINT
 		For ARM, enable an optional function to print more information
 		about the running system.
@@ -1850,6 +2178,14 @@ The following options need to be configured:
 		CONFIG_SPL_INIT_MINIMAL
 		Arch init code should be built for a very small image
 
+		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+		Partition on the MMC to load U-Boot from when the MMC is being
+		used in raw mode
+
+		CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
+		Sector to load kernel uImage from when MMC is being
+		used in raw mode (for Falcon mode)
+
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
 		Sector and number of sectors to load kernel argument
@@ -1900,6 +2236,9 @@ The following options need to be configured:
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
 
+		CONFIG_SYS_NAND_U_BOOT_OFFS
+		Location in NAND to read U-Boot from
+
 		CONFIG_SYS_NAND_U_BOOT_DST
 		Location in memory to load U-Boot to
 
@@ -2124,6 +2463,9 @@ Configuration Settings:
 		Enables allocating and saving a kernel copy of the bd_info in
 		space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
 
+- CONFIG_SYS_MAX_FLASH_BANKS:
+		Max number of Flash memory banks
+
 - CONFIG_SYS_MAX_FLASH_SECT:
 		Max number of sectors on a Flash chip
 
@@ -2372,6 +2714,14 @@ Low Level (hardware related) configuration options:
 		If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
 		forced to a value that ensures that CCSR is not relocated.
 
+- CONFIG_IDE_AHB:
+		Most IDE controllers were designed to be connected with PCI
+		interface. Only few of them were designed for AHB interface.
+		When software is doing ATA command and data transfer to
+		IDE devices through IDE-AHB controller, some additional
+		registers accessing to these kind of IDE-AHB controller
+		is required.
+
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx systems only]
@@ -2415,6 +2765,17 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_MAMR_PTA:
 		periodic timer for refresh
 
+- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
+  CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
+  CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
+  CONFIG_SYS_BR1_PRELIM:
+		Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
+
+- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
+  CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
+  CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
+		Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
+
 - CONFIG_SYS_SRIO:
 		Chip has SRIO or not
 
@@ -2512,6 +2873,22 @@ Low Level (hardware related) configuration options:
 		This only takes effect if the memory commands are activated
 		globally (CONFIG_CMD_MEMORY).
 
+- CONFIG_SKIP_LOWLEVEL_INIT
+		[ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain
+		low level initializations (like setting up the memory
+		controller) are omitted and/or U-Boot does not
+		relocate itself into RAM.
+
+		Normally this variable MUST NOT be defined. The only
+		exception is when U-Boot is loaded (to RAM) by some
+		other boot loader or by a debugger which performs
+		these initializations itself.
+
+- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+		[ARM926EJ-S only] This allows just the call to lowlevel_init()
+		to be skipped. The normal CP15 init (such as enabling the
+		instruction cache) is still performed.
+
 - CONFIG_SPL_BUILD
 		Set when the currently-running compilation is for an artifact
 		that will end up in the SPL (as opposed to the TPL or U-Boot
@@ -2803,6 +3180,334 @@ TODO.
 For now: just type "help <command>".
 
 
+Environment Variables:
+======================
+
+U-Boot supports user configuration using Environment Variables which
+can be made persistent by saving to Flash memory.
+
+Environment Variables are set using "setenv", printed using
+"printenv", and saved to Flash using "saveenv". Using "setenv"
+without a value can be used to delete a variable from the
+environment. As long as you don't save the environment you are
+working with an in-memory copy. In case the Flash area containing the
+environment is erased by accident, a default environment is provided.
+
+Some configuration options can be set using Environment Variables.
+
+List of environment variables (most likely not complete):
+
+  baudrate	- see CONFIG_BAUDRATE
+
+  bootdelay	- see CONFIG_BOOTDELAY
+
+  bootcmd	- see CONFIG_BOOTCOMMAND
+
+  bootargs	- Boot arguments when booting an RTOS image
+
+  bootfile	- Name of the image to load with TFTP
+
+  bootm_low	- Memory range available for image processing in the bootm
+		  command can be restricted. This variable is given as
+		  a hexadecimal number and defines lowest address allowed
+		  for use by the bootm command. See also "bootm_size"
+		  environment variable. Address defined by "bootm_low" is
+		  also the base of the initial memory mapping for the Linux
+		  kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
+		  bootm_mapsize.
+
+  bootm_mapsize - Size of the initial memory mapping for the Linux kernel.
+		  This variable is given as a hexadecimal number and it
+		  defines the size of the memory region starting at base
+		  address bootm_low that is accessible by the Linux kernel
+		  during early boot.  If unset, CONFIG_SYS_BOOTMAPSZ is used
+		  as the default value if it is defined, and bootm_size is
+		  used otherwise.
+
+  bootm_size	- Memory range available for image processing in the bootm
+		  command can be restricted. This variable is given as
+		  a hexadecimal number and defines the size of the region
+		  allowed for use by the bootm command. See also "bootm_low"
+		  environment variable.
+
+  bootstopkeysha256, bootdelaykey, bootstopkey	- See README.autoboot
+
+  updatefile	- Location of the software update file on a TFTP server, used
+		  by the automatic software update feature. Please refer to
+		  documentation in doc/README.update for more details.
+
+  autoload	- if set to "no" (any string beginning with 'n'),
+		  "bootp" will just load perform a lookup of the
+		  configuration from the BOOTP server, but not try to
+		  load any image using TFTP
+
+  autostart	- if set to "yes", an image loaded using the "bootp",
+		  "rarpboot", "tftpboot" or "diskboot" commands will
+		  be automatically started (by internally calling
+		  "bootm")
+
+		  If set to "no", a standalone image passed to the
+		  "bootm" command will be copied to the load address
+		  (and eventually uncompressed), but NOT be started.
+		  This can be used to load and uncompress arbitrary
+		  data.
+
+  fdt_high	- if set this restricts the maximum address that the
+		  flattened device tree will be copied into upon boot.
+		  For example, if you have a system with 1 GB memory
+		  at physical address 0x10000000, while Linux kernel
+		  only recognizes the first 704 MB as low memory, you
+		  may need to set fdt_high as 0x3C000000 to have the
+		  device tree blob be copied to the maximum address
+		  of the 704 MB low memory, so that Linux kernel can
+		  access it during the boot procedure.
+
+		  If this is set to the special value 0xFFFFFFFF then
+		  the fdt will not be copied at all on boot.  For this
+		  to work it must reside in writable memory, have
+		  sufficient padding on the end of it for u-boot to
+		  add the information it needs into it, and the memory
+		  must be accessible by the kernel.
+
+  fdtcontroladdr- if set this is the address of the control flattened
+		  device tree used by U-Boot when CONFIG_OF_CONTROL is
+		  defined.
+
+  i2cfast	- (PPC405GP|PPC405EP only)
+		  if set to 'y' configures Linux I2C driver for fast
+		  mode (400kHZ). This environment variable is used in
+		  initialization code. So, for changes to be effective
+		  it must be saved and board must be reset.
+
+  initrd_high	- restrict positioning of initrd images:
+		  If this variable is not set, initrd images will be
+		  copied to the highest possible address in RAM; this
+		  is usually what you want since it allows for
+		  maximum initrd size. If for some reason you want to
+		  make sure that the initrd image is loaded below the
+		  CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
+		  variable to a value of "no" or "off" or "0".
+		  Alternatively, you can set it to a maximum upper
+		  address to use (U-Boot will still check that it
+		  does not overwrite the U-Boot stack and data).
+
+		  For instance, when you have a system with 16 MB
+		  RAM, and want to reserve 4 MB from use by Linux,
+		  you can do this by adding "mem=12M" to the value of
+		  the "bootargs" variable. However, now you must make
+		  sure that the initrd image is placed in the first
+		  12 MB as well - this can be done with
+
+		  setenv initrd_high 00c00000
+
+		  If you set initrd_high to 0xFFFFFFFF, this is an
+		  indication to U-Boot that all addresses are legal
+		  for the Linux kernel, including addresses in flash
+		  memory. In this case U-Boot will NOT COPY the
+		  ramdisk at all. This may be useful to reduce the
+		  boot time on your system, but requires that this
+		  feature is supported by your Linux kernel.
+
+  ipaddr	- IP address; needed for tftpboot command
+
+  loadaddr	- Default load address for commands like "bootp",
+		  "rarpboot", "tftpboot", "loadb" or "diskboot"
+
+  loads_echo	- see CONFIG_LOADS_ECHO
+
+  serverip	- TFTP server IP address; needed for tftpboot command
+
+  bootretry	- see CONFIG_BOOT_RETRY_TIME
+
+  bootdelaykey	- see CONFIG_AUTOBOOT_DELAY_STR
+
+  bootstopkey	- see CONFIG_AUTOBOOT_STOP_STR
+
+  ethprime	- controls which interface is used first.
+
+  ethact	- controls which interface is currently active.
+		  For example you can do the following
+
+		  => setenv ethact FEC
+		  => ping 192.168.0.1 # traffic sent on FEC
+		  => setenv ethact SCC
+		  => ping 10.0.0.1 # traffic sent on SCC
+
+  ethrotate	- When set to "no" U-Boot does not go through all
+		  available network interfaces.
+		  It just stays at the currently selected interface.
+
+  netretry	- When set to "no" each network operation will
+		  either succeed or fail without retrying.
+		  When set to "once" the network operation will
+		  fail when all the available network interfaces
+		  are tried once without success.
+		  Useful on scripts which control the retry operation
+		  themselves.
+
+  npe_ucode	- set load address for the NPE microcode
+
+  silent_linux  - If set then Linux will be told to boot silently, by
+		  changing the console to be empty. If "yes" it will be
+		  made silent. If "no" it will not be made silent. If
+		  unset, then it will be made silent if the U-Boot console
+		  is silent.
+
+  tftpsrcp	- If this is set, the value is used for TFTP's
+		  UDP source port.
+
+  tftpdstp	- If this is set, the value is used for TFTP's UDP
+		  destination port instead of the Well Know Port 69.
+
+  tftpblocksize - Block size to use for TFTP transfers; if not set,
+		  we use the TFTP server's default block size
+
+  tftptimeout	- Retransmission timeout for TFTP packets (in milli-
+		  seconds, minimum value is 1000 = 1 second). Defines
+		  when a packet is considered to be lost so it has to
+		  be retransmitted. The default is 5000 = 5 seconds.
+		  Lowering this value may make downloads succeed
+		  faster in networks with high packet loss rates or
+		  with unreliable TFTP servers.
+
+  tftptimeoutcountmax	- maximum count of TFTP timeouts (no
+		  unit, minimum value = 0). Defines how many timeouts
+		  can happen during a single file transfer before that
+		  transfer is aborted. The default is 10, and 0 means
+		  'no timeouts allowed'. Increasing this value may help
+		  downloads succeed with high packet loss rates, or with
+		  unreliable TFTP servers or client hardware.
+
+  tftpwindowsize	- if this is set, the value is used for TFTP's
+		  window size as described by RFC 7440.
+		  This means the count of blocks we can receive before
+		  sending ack to server.
+
+  vlan		- When set to a value < 4095 the traffic over
+		  Ethernet is encapsulated/received over 802.1q
+		  VLAN tagged frames.
+
+  bootpretryperiod	- Period during which BOOTP/DHCP sends retries.
+		  Unsigned value, in milliseconds. If not set, the period will
+		  be either the default (28000), or a value based on
+		  CONFIG_NET_RETRY_COUNT, if defined. This value has
+		  precedence over the valu based on CONFIG_NET_RETRY_COUNT.
+
+  memmatches	- Number of matches found by the last 'ms' command, in hex
+
+  memaddr	- Address of the last match found by the 'ms' command, in hex,
+		  or 0 if none
+
+  mempos	- Index position of the last match found by the 'ms' command,
+		  in units of the size (.b, .w, .l) of the search
+
+  zbootbase	- (x86 only) Base address of the bzImage 'setup' block
+
+  zbootaddr	- (x86 only) Address of the loaded bzImage, typically
+		  BZIMAGE_LOAD_ADDR which is 0x100000
+
+The following image location variables contain the location of images
+used in booting. The "Image" column gives the role of the image and is
+not an environment variable name. The other columns are environment
+variable names. "File Name" gives the name of the file on a TFTP
+server, "RAM Address" gives the location in RAM the image will be
+loaded to, and "Flash Location" gives the image's address in NOR
+flash or offset in NAND flash.
+
+*Note* - these variables don't have to be defined for all boards, some
+boards currently use other variables for these purposes, and some
+boards use these variables for other purposes.
+
+Image		    File Name	     RAM Address       Flash Location
+-----		    ---------	     -----------       --------------
+u-boot		    u-boot	     u-boot_addr_r     u-boot_addr
+Linux kernel	    bootfile	     kernel_addr_r     kernel_addr
+device tree blob    fdtfile	     fdt_addr_r	       fdt_addr
+ramdisk		    ramdiskfile	     ramdisk_addr_r    ramdisk_addr
+
+The following environment variables may be used and automatically
+updated by the network boot commands ("bootp" and "rarpboot"),
+depending the information provided by your boot server:
+
+  bootfile	- see above
+  dnsip		- IP address of your Domain Name Server
+  dnsip2	- IP address of your secondary Domain Name Server
+  gatewayip	- IP address of the Gateway (Router) to use
+  hostname	- Target hostname
+  ipaddr	- see above
+  netmask	- Subnet Mask
+  rootpath	- Pathname of the root filesystem on the NFS server
+  serverip	- see above
+
+
+There are two special Environment Variables:
+
+  serial#	- contains hardware identification information such
+		  as type string and/or serial number
+  ethaddr	- Ethernet address
+
+These variables can be set only once (usually during manufacturing of
+the board). U-Boot refuses to delete or overwrite these variables
+once they have been set once.
+
+
+Further special Environment Variables:
+
+  ver		- Contains the U-Boot version string as printed
+		  with the "version" command. This variable is
+		  readonly (see CONFIG_VERSION_VARIABLE).
+
+
+Please note that changes to some configuration parameters may take
+only effect after the next boot (yes, that's just like Windoze :-).
+
+
+Callback functions for environment variables:
+---------------------------------------------
+
+For some environment variables, the behavior of u-boot needs to change
+when their values are changed.  This functionality allows functions to
+be associated with arbitrary variables.  On creation, overwrite, or
+deletion, the callback will provide the opportunity for some side
+effect to happen or for the change to be rejected.
+
+The callbacks are named and associated with a function using the
+U_BOOT_ENV_CALLBACK macro in your board or driver code.
+
+These callbacks are associated with variables in one of two ways.  The
+static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
+in the board configuration to a string that defines a list of
+associations.  The list must be in the following format:
+
+	entry = variable_name[:callback_name]
+	list = entry[,list]
+
+If the callback name is not specified, then the callback is deleted.
+Spaces are also allowed anywhere in the list.
+
+Callbacks can also be associated by defining the ".callbacks" variable
+with the same list format above.  Any association in ".callbacks" will
+override any association in the static list. You can define
+CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
+".callbacks" environment variable in the default or embedded environment.
+
+If CONFIG_REGEX is defined, the variable_name above is evaluated as a
+regular expression. This allows multiple variables to be connected to
+the same callback without explicitly listing them all out.
+
+The signature of the callback functions is:
+
+    int callback(const char *name, const char *value, enum env_op op, int flags)
+
+* name - changed environment variable
+* value - new value of the environment variable
+* op - operation (create, overwrite, or delete)
+* flags - attributes of the environment variable change, see flags H_* in
+  include/search.h
+
+The return value is 0 if the variable change is accepted and 1 otherwise.
+
+
 Note for Redundant Ethernet Interfaces:
 =======================================
 
@@ -2868,7 +3573,8 @@ details; basically, the header defines the following image properties:
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
   LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
-  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, INTEGRITY).
+  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
+  INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
   IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: ARM, Intel x86, MIPS, NDS32, Nios II, PowerPC).

SECURITY.md

@@ -0,0 +1,8 @@
+# Report potential product security vulnerabilities
+ST places a high priority on security, and our Product Security Incident Response Team (PSIRT) is committed to rapidly addressing potential security vulnerabilities affecting our products. PSIRT's long history and vast experience in security allows ST to perform clear analyses and provide appropriate guidance on mitigations  and solutions when applicable.
+If you wish to report potential security vulnerabilities regarding our products, **please do not report them through public GitHub issues.** Instead, we encourage you to report them to our ST PSIRT following the process described at: **https://www.st.com/content/st_com/en/security/report-vulnerabilities.html**
+
+### IMPORTANT - READ CAREFULLY:
+STMicroelectronics International N.V., on behalf of itself, its affiliates and  subsidiaries, (collectively “ST”) takes all potential security vulnerability reports or other related communications (“Report(s)”)  seriously. In order to review Your Report (the terms “You” and “Yours”  include your employer, and all affiliates, subsidiaries and related  persons or entities) and take actions as deemed appropriate, ST requires that we have the rights and Your permission to do so.
+As such, by submitting Your Report to ST, You agree that You have the right to do so, and You grant to ST the rights to use the Report for purposes related to security vulnerability analysis, testing, correction, patching, reporting and any other related purpose or function.
+By submitting Your Report, You agree that ST’s [Privacy Policy](https://www.st.com/content/st_com/en/common/privacy-portal.html) applies to all related communications.

api/Kconfig

@@ -2,6 +2,7 @@ menu "API"
 
 config API
 	bool "Enable U-Boot API"
+	default n
 	help
 	  This option enables the U-Boot API. See api/README for more information.
 

api/api_storage.c

@@ -9,7 +9,6 @@
 #include <common.h>
 #include <api_public.h>
 #include <part.h>
-#include <scsi.h>
 
 #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
 #include <usb.h>
@@ -72,7 +71,7 @@ void dev_stor_init(void)
 	specs[ENUM_SATA].name = "sata";
 #endif
 #if defined(CONFIG_SCSI)
-	specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE;
+	specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
 	specs[ENUM_SCSI].enum_started = 0;
 	specs[ENUM_SCSI].enum_ended = 0;
 	specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;

arch/Kconfig

@@ -1,7 +1,3 @@
-config ARCH_MAP_SYSMEM
-	depends on SANDBOX || NDS32
-	def_bool y
-
 config CREATE_ARCH_SYMLINK
 	bool
 
@@ -11,27 +7,6 @@ config HAVE_ARCH_IOREMAP
 config NEEDS_MANUAL_RELOC
 	bool
 
-config SYS_CACHE_SHIFT_4
-	bool
-
-config SYS_CACHE_SHIFT_5
-	bool
-
-config SYS_CACHE_SHIFT_6
-	bool
-
-config SYS_CACHE_SHIFT_7
-	bool
-
-config SYS_CACHELINE_SIZE
-	int
-	default 128 if SYS_CACHE_SHIFT_7
-	default 64 if SYS_CACHE_SHIFT_6
-	default 32 if SYS_CACHE_SHIFT_5
-	default 16 if SYS_CACHE_SHIFT_4
-	# Fall-back for MIPS
-	default 32 if MIPS
-
 config LINKER_LIST_ALIGN
 	int
 	default 32 if SANDBOX
@@ -54,7 +29,6 @@ config ARC
 	select DM
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
-	select SYS_CACHE_SHIFT_7
 	select TIMER
 
 config ARM
@@ -62,7 +36,6 @@ config ARM
 	select ARCH_SUPPORTS_LTO
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC if !ARM64
-	select SUPPORT_ACPI
 	select SUPPORT_OF_CONTROL
 
 config M68K
@@ -71,7 +44,6 @@ config M68K
 	select NEEDS_MANUAL_RELOC
 	select SYS_BOOT_GET_CMDLINE
 	select SYS_BOOT_GET_KBD
-	select SYS_CACHE_SHIFT_4
 	select SUPPORT_OF_CONTROL
 
 config MICROBLAZE
@@ -125,7 +97,7 @@ config RISCV
 	imply SPL_OF_CONTROL
 	imply SPL_LIBCOMMON_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
-	imply SPL_SERIAL
+	imply SPL_SERIAL_SUPPORT
 	imply SPL_TIMER
 
 config SANDBOX
@@ -150,10 +122,8 @@ config SANDBOX
 	select SPI
 	select SUPPORT_OF_CONTROL
 	select SYSRESET_CMD_POWEROFF
-	select SYS_CACHE_SHIFT_4
 	select IRQ
 	select SUPPORT_EXTENSION_SCAN
-	select SUPPORT_ACPI
 	imply BITREVERSE
 	select BLOBLIST
 	imply LTO
@@ -172,11 +142,11 @@ config SANDBOX
 	imply FIRMWARE
 	imply HASH_VERIFY
 	imply LZMA
+	imply SCSI
 	imply TEE
 	imply AVB_VERIFY
 	imply LIBAVB
 	imply CMD_AVB
-	imply PARTITION_TYPE_GUID
 	imply SCP03
 	imply CMD_SCP03
 	imply UDP_FUNCTION_FASTBOOT
@@ -200,9 +170,6 @@ config SANDBOX
 	imply PHY_FIXED
 	imply DM_DSA
 	imply CMD_EXTENSION
-	imply KEYBOARD
-	imply PHYSMEM
-	imply GENERATE_ACPI_TABLE
 
 config SH
 	bool "SuperH architecture"
@@ -219,9 +186,7 @@ config X86
 	select HAVE_PRIVATE_LIBGCC
 	select OF_CONTROL
 	select PCI
-	select SUPPORT_ACPI
 	select SUPPORT_OF_CONTROL
-	select SYS_CACHE_SHIFT_6
 	select TIMER
 	select USE_PRIVATE_LIBGCC
 	select X86_TSC_TIMER
@@ -255,12 +220,10 @@ config X86
 	imply USB_ETHER_SMSC95XX
 	imply USB_HOST_ETHER
 	imply PCH
-	imply PHYSMEM
 	imply RTC_MC146818
-	imply ACPIGEN if !QEMU && !EFI_APP
+	imply ACPIGEN if !QEMU
 	imply SYSINFO if GENERATE_SMBIOS_TABLE
 	imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
-	imply TIMESTAMP
 
 	# Thing to enable for when SPL/TPL are enabled: SPL
 	imply SPL_DM
@@ -270,9 +233,9 @@ config X86
 	imply SPL_PINCTRL
 	imply SPL_LIBCOMMON_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
-	imply SPL_SERIAL
+	imply SPL_SERIAL_SUPPORT
 	imply SPL_SPI_FLASH_SUPPORT
-	imply SPL_SPI
+	imply SPL_SPI_SUPPORT
 	imply SPL_OF_CONTROL
 	imply SPL_TIMER
 	imply SPL_REGMAP
@@ -284,7 +247,7 @@ config X86
 	imply TPL_PINCTRL
 	imply TPL_LIBCOMMON_SUPPORT
 	imply TPL_LIBGENERIC_SUPPORT
-	imply TPL_SERIAL
+	imply TPL_SERIAL_SUPPORT
 	imply TPL_OF_CONTROL
 	imply TPL_TIMER
 	imply TPL_REGMAP
@@ -362,75 +325,6 @@ config SYS_DISABLE_DCACHE_OPS
 	 Note that, its up to the individual architectures to implement
 	 this functionality.
 
-config SYS_IMMR
-	hex
-	depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
-	default 0xFF000000 if MPC8xx
-	default 0xF0000000 if ARCH_MPC8313
-	default 0xE0000000 if MPC83xx && !ARCH_MPC8313
-	default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
-	default SYS_CCSRBAR_DEFAULT
-	help
-	  Address for the Internal Memory-Mapped Registers (IMMR) window used
-	  to configure the features of many Freescale / NXP SoCs.
-
-config SKIP_LOWLEVEL_INIT
-	bool "Skip the calls to certain low level initialization functions"
-	depends on ARM || NDS32 || MIPS || RISCV
-	help
-	  If enabled, then certain low level initializations (like setting up
-	  the memory controller) are omitted and/or U-Boot does not relocate
-	  itself into RAM.
-	  Normally this variable MUST NOT be defined. The only exception is
-	  when U-Boot is loaded (to RAM) by some other boot loader or by a
-	  debugger which performs these initializations itself.
-
-config SPL_SKIP_LOWLEVEL_INIT
-	bool "Skip the calls to certain low level initialization functions"
-	depends on SPL && (ARM || NDS32 || MIPS || RISCV)
-	help
-	  If enabled, then certain low level initializations (like setting up
-	  the memory controller) are omitted and/or U-Boot does not relocate
-	  itself into RAM.
-	  Normally this variable MUST NOT be defined. The only exception is
-	  when U-Boot is loaded (to RAM) by some other boot loader or by a
-	  debugger which performs these initializations itself.
-
-config TPL_SKIP_LOWLEVEL_INIT
-	bool "Skip the calls to certain low level initialization functions"
-	depends on SPL && ARM
-	help
-	  If enabled, then certain low level initializations (like setting up
-	  the memory controller) are omitted and/or U-Boot does not relocate
-	  itself into RAM.
-	  Normally this variable MUST NOT be defined. The only exception is
-	  when U-Boot is loaded (to RAM) by some other boot loader or by a
-	  debugger which performs these initializations itself.
-
-config SKIP_LOWLEVEL_INIT_ONLY
-	bool "Skip the call to lowlevel_init during early boot ONLY"
-	depends on ARM
-	help
-	  This allows just the call to lowlevel_init() to be skipped. The
-	  normal CP15 init (such as enabling the instruction cache) is still
-	  performed.
-
-config SPL_SKIP_LOWLEVEL_INIT_ONLY
-	bool "Skip the call to lowlevel_init during early boot ONLY"
-	depends on SPL && ARM
-	help
-	  This allows just the call to lowlevel_init() to be skipped. The
-	  normal CP15 init (such as enabling the instruction cache) is still
-	  performed.
-
-config TPL_SKIP_LOWLEVEL_INIT_ONLY
-	bool "Skip the call to lowlevel_init during early boot ONLY"
-	depends on TPL && ARM
-	help
-	  This allows just the call to lowlevel_init() to be skipped. The
-	  normal CP15 init (such as enabling the instruction cache) is still
-	  performed.
-
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
 source "arch/m68k/Kconfig"

arch/arc/Kconfig

@@ -104,11 +104,13 @@ endchoice
 
 config CPU_BIG_ENDIAN
 	bool "Enable Big Endian Mode"
+	default n
 	help
 	  Build kernel for Big Endian Mode of ARC CPU
 
 config SYS_ICACHE_OFF
 	bool "Do not enable icache"
+	default n
 	help
 	  Do not enable instruction cache in U-Boot.
 
@@ -121,6 +123,7 @@ config SPL_SYS_ICACHE_OFF
 
 config SYS_DCACHE_OFF
 	bool "Do not enable dcache"
+	default n
 	help
 	  Do not enable data cache in U-Boot.
 
@@ -133,12 +136,14 @@ config SPL_SYS_DCACHE_OFF
 
 menuconfig ARC_DBG
 	bool "ARC debugging"
+	default n
 
 if ARC_DBG
 
 config ARC_DBG_IOC_ENABLE
 	bool "Enable IO coherency unit"
 	depends on CPU_ARCHS38
+	default n
 	help
 	  Enable IO coherency unit to debug problems with caches and
 	  DMA peripherals.

arch/arc/dts/Makefile

@@ -8,8 +8,6 @@ dtb-$(CONFIG_TARGET_EMSDP) +=  emsdp.dtb
 dtb-$(CONFIG_TARGET_HSDK) +=  hsdk.dtb hsdk-4xd.dtb
 dtb-$(CONFIG_TARGET_IOT_DEVKIT) +=  iot_devkit.dtb
 
-include $(srctree)/scripts/Makefile.dts
-
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000

arch/arc/include/asm/cache.h

@@ -16,6 +16,9 @@
  */
 #define ARCH_DMA_MINALIGN	128
 
+/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
+#define CONFIG_SYS_CACHELINE_SIZE	ARCH_DMA_MINALIGN
+
 #if defined(ARC_MMU_ABSENT)
 #define CONFIG_ARC_MMU_VER 0
 #elif defined(CONFIG_ARC_MMU_V2)

arch/arc/lib/bootm.c

@@ -8,12 +8,42 @@
 #include <env.h>
 #include <image.h>
 #include <irq_func.h>
+#include <lmb.h>
 #include <log.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static ulong get_sp(void)
+{
+	ulong ret;
+
+	asm("mov %0, sp" : "=r"(ret) : );
+	return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+	ulong sp;
+
+	/*
+	 * Booting a (Linux) kernel image
+	 *
+	 * Allocate space for command line and board info - the
+	 * address should be as high as possible within the reach of
+	 * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+	 * memory, which means far enough below the current stack
+	 * pointer.
+	 */
+	sp = get_sp();
+	debug("## Current stack ends at 0x%08lx ", sp);
+
+	/* adjust sp by 4K to be safe */
+	sp -= 4096;
+	lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
+}
+
 static int cleanup_before_linux(void)
 {
 	disable_interrupts();
@@ -63,7 +93,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 	       "(fake run for tracing)" : "");
 	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
 
-	if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
+	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
 		r0 = 2;
 		r2 = (unsigned int)images->ft_addr;
 	} else {

arch/arc/lib/cache.c

@@ -11,7 +11,6 @@
 #include <linux/compiler.h>
 #include <linux/kernel.h>
 #include <linux/log2.h>
-#include <lmb.h>
 #include <asm/arcregs.h>
 #include <asm/arc-bcr.h>
 #include <asm/cache.h>
@@ -821,16 +820,3 @@ void sync_n_cleanup_cache_all(void)
 
 	__ic_entire_invalidate();
 }
-
-static ulong get_sp(void)
-{
-	ulong ret;
-
-	asm("mov %0, sp" : "=r"(ret) : );
-	return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
-	arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-}

arch/arc/lib/cpu.c

@@ -4,7 +4,6 @@
  */
 
 #include <common.h>
-#include <clock_legacy.h>
 #include <init.h>
 #include <malloc.h>
 #include <vsprintf.h>
@@ -19,7 +18,7 @@ int arch_cpu_init(void)
 {
 	timer_init();
 
-	gd->cpu_clk = get_board_sys_clk();
+	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
 	cache_init();

arch/arc/lib/libgcc2.h

@@ -35,7 +35,7 @@ typedef		 int HItype	__attribute__ ((mode (HI)));
 typedef unsigned int UHItype	__attribute__ ((mode (HI)));
 #if MIN_UNITS_PER_WORD > 1
 /* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1.  */
-typedef		 int SItype	__attribute__ ((mode (SI)));
+typedef 	 int SItype	__attribute__ ((mode (SI)));
 typedef unsigned int USItype	__attribute__ ((mode (SI)));
 #if __SIZEOF_LONG_LONG__ > 4
 /* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2.  */

arch/arm/Kconfig

@@ -9,19 +9,9 @@ config ARM64
 	select PHYS_64BIT
 	select SYS_CACHE_SHIFT_6
 
-config ARM64_CRC32
-	bool "Enable support for CRC32 instruction"
-	depends on ARM64
-	default y
-	help
-	  ARMv8 implements dedicated crc32 instruction for crc32 calculation.
-	  This is faster than software crc32 calculation. This instruction may
-	  not be present on all ARMv8.0, but is always present on ARMv8.1 and
-	  newer.
-
+if ARM64
 config POSITION_INDEPENDENT
 	bool "Generate position-independent pre-relocation code"
-	depends on ARM64 || CPU_V7A
 	help
 	  U-Boot expects to be linked to a specific hard-coded address, and to
 	  be loaded to and run from that address. This option lifts that
@@ -32,7 +22,6 @@ config POSITION_INDEPENDENT
 
 config INIT_SP_RELATIVE
 	bool "Specify the early stack pointer relative to the .bss section"
-	depends on ARM64
 	default n if ARCH_QEMU
 	default y if POSITION_INDEPENDENT
 	help
@@ -48,7 +37,6 @@ config INIT_SP_RELATIVE
 
 config SYS_INIT_SP_BSS_OFFSET
 	int "Early stack offset from the .bss base address"
-	depends on ARM64
 	depends on INIT_SP_RELATIVE
 	default 524288
 	help
@@ -58,7 +46,6 @@ config SYS_INIT_SP_BSS_OFFSET
 	  do not overlap any appended DTB.
 
 config LINUX_KERNEL_IMAGE_HEADER
-	depends on ARM64
 	bool
 	help
 	  Place a Linux kernel image header at the start of the U-Boot binary.
@@ -67,21 +54,19 @@ config LINUX_KERNEL_IMAGE_HEADER
 	  image header reports the amount of memory (BSS and similar) that
 	  U-Boot needs to use, but which isn't part of the binary.
 
+if LINUX_KERNEL_IMAGE_HEADER
 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
-	depends on LINUX_KERNEL_IMAGE_HEADER
 	hex
 	help
 	  The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
 	  TEXT_OFFSET value written to the Linux kernel image header.
-
-config GICV2
-	bool
-
-config GICV3
-	bool
+endif
+endif
 
 config GIC_V3_ITS
 	bool "ARM GICV3 ITS"
+	select REGMAP
+	select SYSCON
 	select IRQ
 	help
 	  ARM GICV3 Interrupt translation service (ITS).
@@ -119,6 +104,7 @@ config THUMB2_KERNEL
 
 config SYS_ICACHE_OFF
 	bool "Do not enable icache"
+	default n
 	help
 	  Do not enable instruction cache in U-Boot.
 
@@ -131,6 +117,7 @@ config SPL_SYS_ICACHE_OFF
 
 config SYS_DCACHE_OFF
 	bool "Do not enable dcache"
+	default n
 	help
 	  Do not enable data cache in U-Boot.
 
@@ -311,10 +298,6 @@ config CPU_PXA
 	select SYS_CACHE_SHIFT_5
 	imply SYS_ARM_MMU
 
-config CPU_PXA27X
-	bool
-	select CPU_PXA
-
 config CPU_SA1100
 	bool
 	select SYS_CACHE_SHIFT_5
@@ -349,6 +332,21 @@ config SYS_ARM_ARCH
 	default 4 if CPU_SA1100
 	default 8 if ARM64
 
+config SYS_CACHE_SHIFT_5
+	bool
+
+config SYS_CACHE_SHIFT_6
+	bool
+
+config SYS_CACHE_SHIFT_7
+	bool
+
+config SYS_CACHELINE_SIZE
+	int
+	default 128 if SYS_CACHE_SHIFT_7
+	default 64 if SYS_CACHE_SHIFT_6
+	default 32 if SYS_CACHE_SHIFT_5
+
 choice
 	prompt "Select the ARM data write cache policy"
 	default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
@@ -452,10 +450,14 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
 	  values, then choose this option, and create a file included as
 	  <asm/arch/boot0.h> which contains the required assembler code.
 
+config ARM_CORTEX_CPU_IS_UP
+	bool
+	default n
+
 config USE_ARCH_MEMCPY
 	bool "Use an assembly optimized implementation of memcpy"
-	default y if !ARM64
-	depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
+	default y
+	depends on !ARM64
 	help
 	  Enable the generation of an optimized version of memcpy.
 	  Such an implementation may be faster under some conditions
@@ -464,7 +466,7 @@ config USE_ARCH_MEMCPY
 config SPL_USE_ARCH_MEMCPY
 	bool "Use an assembly optimized implementation of memcpy for SPL"
 	default y if USE_ARCH_MEMCPY
-	depends on SPL
+	depends on !ARM64 && SPL
 	help
 	  Enable the generation of an optimized version of memcpy.
 	  Such an implementation may be faster under some conditions
@@ -473,43 +475,16 @@ config SPL_USE_ARCH_MEMCPY
 config TPL_USE_ARCH_MEMCPY
 	bool "Use an assembly optimized implementation of memcpy for TPL"
 	default y if USE_ARCH_MEMCPY
-	depends on TPL
+	depends on !ARM64 && TPL
 	help
 	  Enable the generation of an optimized version of memcpy.
 	  Such an implementation may be faster under some conditions
 	  but may increase the binary size.
 
-config USE_ARCH_MEMMOVE
-	bool "Use an assembly optimized implementation of memmove" if !ARM64
-	default USE_ARCH_MEMCPY if ARM64
-	depends on ARM64
-	help
-	  Enable the generation of an optimized version of memmove.
-	  Such an implementation may be faster under some conditions
-	  but may increase the binary size.
-
-config SPL_USE_ARCH_MEMMOVE
-	bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
-	default SPL_USE_ARCH_MEMCPY if ARM64
-	depends on SPL && ARM64
-	help
-	  Enable the generation of an optimized version of memmove.
-	  Such an implementation may be faster under some conditions
-	  but may increase the binary size.
-
-config TPL_USE_ARCH_MEMMOVE
-	bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
-	default TPL_USE_ARCH_MEMCPY if ARM64
-	depends on TPL && ARM64
-	help
-	  Enable the generation of an optimized version of memmove.
-	  Such an implementation may be faster under some conditions
-	  but may increase the binary size.
-
 config USE_ARCH_MEMSET
 	bool "Use an assembly optimized implementation of memset"
-	default y if !ARM64
-	depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
+	default y
+	depends on !ARM64
 	help
 	  Enable the generation of an optimized version of memset.
 	  Such an implementation may be faster under some conditions
@@ -518,7 +493,7 @@ config USE_ARCH_MEMSET
 config SPL_USE_ARCH_MEMSET
 	bool "Use an assembly optimized implementation of memset for SPL"
 	default y if USE_ARCH_MEMSET
-	depends on SPL
+	depends on !ARM64 && SPL
 	help
 	  Enable the generation of an optimized version of memset.
 	  Such an implementation may be faster under some conditions
@@ -527,7 +502,7 @@ config SPL_USE_ARCH_MEMSET
 config TPL_USE_ARCH_MEMSET
 	bool "Use an assembly optimized implementation of memset for TPL"
 	default y if USE_ARCH_MEMSET
-	depends on TPL
+	depends on !ARM64 && TPL
 	help
 	  Enable the generation of an optimized version of memset.
 	  Such an implementation may be faster under some conditions
@@ -550,6 +525,11 @@ config ARCH_AT91
 	select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
 	select SPL_SEPARATE_BSS if SPL
 
+config TARGET_ASPENITE
+	bool "Support aspenite"
+	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
+
 config ARCH_DAVINCI
 	bool "TI DaVinci"
 	select CPU_ARM926EJS
@@ -599,6 +579,11 @@ config TARGET_STV0991
 	select SPI_FLASH
 	imply CMD_DM
 
+config TARGET_FLEA3
+	bool "Support flea3"
+	select CPU_ARM1136
+	select GPIO_EXTRA_HEADER
+
 config ARCH_BCM283X
 	bool "Broadcom BCM283X family"
 	select DM
@@ -635,17 +620,12 @@ config ARCH_BCMSTB
 	select DM
 	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
+	select OF_PRIOR_STAGE
 	imply CMD_DM
-	imply OF_HAS_PRIOR_STAGE
 	help
 	  This enables support for Broadcom ARM-based set-top box
 	  chipsets, including the 7445 family of chips.
 
-config TARGET_VEXPRESS_CA9X4
-	bool "Support vexpress_ca9x4"
-	select CPU_V7A
-	select PL011_SERIAL
-
 config TARGET_BCMCYGNUS
 	bool "Support bcmcygnus"
 	select CPU_V7A
@@ -709,12 +689,12 @@ config ARCH_HIGHBANK
 	select DM
 	select DM_SERIAL
 	select OF_CONTROL
+	select OF_BOARD
 	select CLK
 	select CLK_CCF
 	select AHCI
 	select DM_ETH
 	select PHYS_64BIT
-	imply OF_HAS_PRIOR_STAGE
 
 config ARCH_INTEGRATOR
 	bool "ARM Ltd. Integrator family"
@@ -743,7 +723,6 @@ config ARCH_KEYSTONE
 	bool "TI Keystone"
 	select CMD_POWEROFF
 	select CPU_V7A
-	select DDR_SPD
 	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	select SYS_ARCH_TIMER
@@ -808,7 +787,6 @@ config ARCH_IMX8
 	select ARM64
 	select DM
 	select GPIO_EXTRA_HEADER
-	select MACH_IMX
 	select OF_CONTROL
 	select ENABLE_ARM_SOC_BOOT0_HOOK
 
@@ -816,11 +794,9 @@ config ARCH_IMX8M
 	bool "NXP i.MX8M platform"
 	select ARM64
 	select GPIO_EXTRA_HEADER
-	select MACH_IMX
 	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
-	select SYS_I2C_MXC
 	select DM
 	select SUPPORT_SPL
 	imply CMD_DM
@@ -829,7 +805,6 @@ config ARCH_IMX8ULP
 	bool "NXP i.MX8ULP platform"
 	select ARM64
 	select DM
-	select MACH_IMX
 	select OF_CONTROL
 	select SUPPORT_SPL
 	select GPIO_EXTRA_HEADER
@@ -841,7 +816,6 @@ config ARCH_IMXRT
 	select DM
 	select DM_SERIAL
 	select GPIO_EXTRA_HEADER
-	select MACH_IMX
 	select SUPPORT_SPL
 	imply CMD_DM
 
@@ -849,29 +823,31 @@ config ARCH_MX23
 	bool "NXP i.MX23 family"
 	select CPU_ARM926EJS
 	select GPIO_EXTRA_HEADER
-	select MACH_IMX
 	select PL011_SERIAL
 	select SUPPORT_SPL
 
+config ARCH_MX25
+	bool "NXP MX25"
+	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
+	imply MXC_GPIO
+
 config ARCH_MX28
 	bool "NXP i.MX28 family"
 	select CPU_ARM926EJS
 	select GPIO_EXTRA_HEADER
 	select PL011_SERIAL
-	select MACH_IMX
 	select SUPPORT_SPL
 
 config ARCH_MX31
 	bool "NXP i.MX31 family"
 	select CPU_ARM1136
 	select GPIO_EXTRA_HEADER
-	select MACH_IMX
 
 config ARCH_MX7ULP
 	bool "NXP MX7ULP"
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
-	select MACH_IMX
 	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -884,7 +860,6 @@ config ARCH_MX7
 	select ARCH_MISC_INIT
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
-	select MACH_IMX
 	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -896,7 +871,6 @@ config ARCH_MX6
 	bool "Freescale MX6"
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
-	select MACH_IMX
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -913,7 +887,6 @@ config ARCH_MX5
 	select BOARD_EARLY_INIT_F
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
-	select MACH_IMX
 	imply MXC_GPIO
 
 config ARCH_NEXELL
@@ -922,39 +895,6 @@ config ARCH_NEXELL
 	select DM
 	select GPIO_EXTRA_HEADER
 
-config ARCH_APPLE
-	bool "Apple SoCs"
-	select ARM64
-	select BLK
-	select CLK
-	select CMD_USB
-	select DM
-	select DM_GPIO
-	select DM_KEYBOARD
-	select DM_MAILBOX
-	select DM_RESET
-	select DM_SERIAL
-	select DM_SPI
-	select DM_USB
-	select DM_VIDEO
-	select IOMMU
-	select LINUX_KERNEL_IMAGE_HEADER
-	select OF_CONTROL
-	select PINCTRL
-	select POSITION_INDEPENDENT
-	select POWER_DOMAIN
-	select REGMAP
-	select SPI
-	select SYSCON
-	select SYSRESET
-	select SYSRESET_WATCHDOG
-	select SYSRESET_WATCHDOG_AUTO
-	select USB
-	imply CMD_DM
-	imply CMD_GPT
-	imply DISTRO_DEFAULTS
-	imply OF_HAS_PRIOR_STAGE
-
 config ARCH_OWL
 	bool "Actions Semi OWL SoCs"
 	select DM
@@ -978,7 +918,6 @@ config ARCH_QEMU
 	imply DM_RNG
 	imply DM_RTC
 	imply RTC_PL031
-	imply OF_HAS_PRIOR_STAGE
 
 config ARCH_RMOBILE
 	bool "Renesas ARM SoCs"
@@ -1013,7 +952,6 @@ config ARCH_SOCFPGA
 	select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select DM
 	select DM_SERIAL
-	select GICV2
 	select GPIO_EXTRA_HEADER
 	select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select OF_CONTROL
@@ -1024,7 +962,7 @@ config ARCH_SOCFPGA
 	select SPL_NAND_SUPPORT if SPL_NAND_DENALI
 	select SPL_OF_CONTROL
 	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
-	select SPL_SERIAL
+	select SPL_SERIAL_SUPPORT
 	select SPL_SYSRESET
 	select SPL_WATCHDOG
 	select SUPPORT_SPL
@@ -1044,11 +982,11 @@ config ARCH_SOCFPGA
 	imply SPL_DM_SPI
 	imply SPL_DM_SPI_FLASH
 	imply SPL_LIBDISK_SUPPORT
-	imply SPL_MMC
+	imply SPL_MMC_SUPPORT
 	imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
 	imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
 	imply SPL_SPI_FLASH_SUPPORT
-	imply SPL_SPI
+	imply SPL_SPI_SUPPORT
 	imply L2X0_CACHE
 
 config ARCH_SUNXI
@@ -1061,7 +999,6 @@ config ARCH_SUNXI
 	select DM
 	select DM_ETH
 	select DM_GPIO
-	select DM_I2C if I2C
 	select DM_KEYBOARD
 	select DM_MMC if MMC
 	select DM_SCSI if SCSI
@@ -1071,7 +1008,6 @@ config ARCH_SUNXI
 	select OF_CONTROL
 	select OF_SEPARATE
 	select SPECIFY_CONSOLE_INDEX
-	select SPL_SEPARATE_BSS if SPL
 	select SPL_STACK_R if SPL
 	select SPL_SYS_MALLOC_SIMPLE if SPL
 	select SPL_SYS_THUMB_BUILD if !ARM64
@@ -1096,14 +1032,10 @@ config ARCH_SUNXI
 	imply SPL_GPIO
 	imply SPL_LIBCOMMON_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
-	imply SPL_MMC if MMC
+	imply SPL_MMC_SUPPORT if MMC
 	imply SPL_POWER
-	imply SPL_SERIAL
-	imply SYSRESET
-	imply SYSRESET_WATCHDOG
-	imply SYSRESET_WATCHDOG_AUTO
+	imply SPL_SERIAL_SUPPORT
 	imply USB_GADGET
-	imply WDT
 
 config ARCH_U8500
 	bool "ST-Ericsson U8500 Series"
@@ -1112,22 +1044,14 @@ config ARCH_U8500
 	select DM_GPIO
 	select DM_MMC if MMC
 	select DM_SERIAL
-	select DM_USB_GADGET if DM_USB
 	select OF_CONTROL
 	select SYSRESET
 	select TIMER
-	imply AB8500_USB_PHY
 	imply ARM_PL180_MMCI
-	imply CLK
-	imply DM_PMIC
 	imply DM_RTC
-	imply NOMADIK_GPIO
 	imply NOMADIK_MTU_TIMER
-	imply PHY
 	imply PL01X_SERIAL
-	imply PMIC_AB8500
 	imply RTC_PL031
-	imply SYS_THUMB_BUILD
 	imply SYSRESET_SYSCON
 
 config ARCH_VERSAL
@@ -1138,7 +1062,6 @@ config ARCH_VERSAL
 	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
-	select GICV3
 	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SOC_DEVICE
@@ -1149,7 +1072,6 @@ config ARCH_VF610
 	bool "Freescale Vybrid"
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
-	select MACH_IMX
 	select SYS_FSL_ERRATUM_ESDHC111
 	imply CMD_MTDPARTS
 	imply MTD_RAW_NAND
@@ -1208,8 +1130,7 @@ config ARCH_ZYNQMP
 	select DM_SERIAL
 	select DM_SPI if SPI
 	select DM_SPI_FLASH if DM_SPI
-	imply FIRMWARE
-	select GICV2
+	select FIRMWARE
 	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
@@ -1218,7 +1139,7 @@ config ARCH_ZYNQMP
 	select SPL_DM_SPI if SPI && SPL_DM
 	select SPL_DM_SPI_FLASH if SPL_DM_SPI
 	select SPL_DM_MAILBOX if SPL
-	imply SPL_FIRMWARE if SPL
+	select SPL_FIRMWARE if SPL
 	select SPL_SEPARATE_BSS if SPL
 	select SUPPORT_SPL
 	select ZYNQMP_IPI
@@ -1229,7 +1150,6 @@ config ARCH_ZYNQMP
 	imply FAT_WRITE
 	imply MP
 	imply DM_USB_GADGET
-	imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
 
 config ARCH_TEGRA
 	bool "NVIDIA Tegra"
@@ -1257,6 +1177,7 @@ config TARGET_VEXPRESS64_JUNO
 	select PL01X_SERIAL
 	select DM
 	select OF_CONTROL
+	select OF_BOARD
 	select CLK
 	select DM_SERIAL
 	select ARM_PSCI_FW
@@ -1264,7 +1185,6 @@ config TARGET_VEXPRESS64_JUNO
 	select DM_ETH
 	select BLK
 	select USB
-	imply OF_HAS_PRIOR_STAGE
 
 config TARGET_TOTAL_COMPUTE
 	bool "Support Total Compute Platform"
@@ -1777,24 +1697,9 @@ config TARGET_SL28
 	help
 	  Support for Kontron SMARC-sAL28 board.
 
-config TARGET_TEN64
-	bool "Support ten64"
-	select ARCH_LS1088A
-	select ARCH_MISC_INIT
-	select ARM64
-	select ARMV8_MULTIENTRY
-	select ARCH_SUPPORT_TFABOOT
-	select BOARD_LATE_INIT
-	select SUPPORT_SPL
-	select FSL_DDR_INTERACTIVE if !SD_BOOT
-	select GPIO_EXTRA_HEADER
-	help
-	  Support for Traverse Technologies Ten64 board, based
-	  on NXP LS1088A.
-
 config TARGET_COLIBRI_PXA270
 	bool "Support colibri_pxa270"
-	select CPU_PXA27X
+	select CPU_PXA
 	select GPIO_EXTRA_HEADER
 
 config ARCH_UNIPHIER
@@ -1875,7 +1780,6 @@ config ARCH_STM32MP
 	select OF_SYSTEM_SETUP
 	select PINCTRL
 	select REGMAP
-	select SUPPORT_SPL
 	select SYSCON
 	select SYSRESET
 	select SYS_THUMB_BUILD
@@ -1885,7 +1789,6 @@ config ARCH_STM32MP
 	imply OF_LIBFDT_OVERLAY
 	imply ENV_VARS_UBOOT_RUNTIME_CONFIG
 	imply USE_PREBOOT
-	imply TIMESTAMP
 	help
 	  Support for STM32MP SoC family developed by STMicroelectronics,
 	  MPUs based on ARM cortex A core
@@ -1937,8 +1840,6 @@ config ARCH_OCTEONTX
 	select OF_LIVE
 	select BOARD_LATE_INIT
 	select SYS_CACHE_SHIFT_7
-	select SYS_PCI_64BIT if PCI
-	imply OF_HAS_PRIOR_STAGE
 
 config ARCH_OCTEONTX2
 	bool "Support OcteonTX2 SoCs"
@@ -1950,8 +1851,6 @@ config ARCH_OCTEONTX2
 	select OF_LIVE
 	select BOARD_LATE_INIT
 	select SYS_CACHE_SHIFT_7
-	select SYS_PCI_64BIT if PCI
-	imply OF_HAS_PRIOR_STAGE
 
 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
@@ -1978,7 +1877,6 @@ config TARGET_DURIAN
 config TARGET_PRESIDIO_ASIC
 	bool "Support Cortina Presidio ASIC Platform"
 	select ARM64
-	select GICV2
 
 config TARGET_XENGUEST_ARM64
 	bool "Xen guest ARM64"
@@ -1988,60 +1886,15 @@ config TARGET_XENGUEST_ARM64
 	select LINUX_KERNEL_IMAGE_HEADER
 	select XEN_SERIAL
 	select SSCANF
-	imply OF_HAS_PRIOR_STAGE
-
 endchoice
 
-config SUPPORT_PASSING_ATAGS
-	bool "Support pre-devicetree ATAG-based booting"
-	depends on !ARM64
-	imply SETUP_MEMORY_TAGS
-	help
-	  Support for booting older Linux kernels, using ATAGs rather than
-	  passing a devicetree.  This is option is rarely used, and the
-	  semantics are defined at
-	  https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
-
-config SETUP_MEMORY_TAGS
-	bool "Pass memory size information via ATAG"
-	depends on SUPPORT_PASSING_ATAGS
-
-config CMDLINE_TAG
-	bool "Pass Linux kernel cmdline via ATAG"
-	depends on SUPPORT_PASSING_ATAGS
-
-config INITRD_TAG
-	bool "Pass initrd starting point and size via ATAG"
-	depends on SUPPORT_PASSING_ATAGS
-
-config REVISION_TAG
-	bool "Pass system revision via ATAG"
-	depends on SUPPORT_PASSING_ATAGS
-
-config SERIAL_TAG
-	bool "Pass system serial number via ATAG"
-	depends on SUPPORT_PASSING_ATAGS
-
-config STATIC_MACH_TYPE
-	bool "Statically define the Machine ID number"
-	help
-	  When booting via ATAGs, enable this option if we know the correct
-	  machine ID number to use at compile time.  Some systems will be
-	  passed the number dynamically by whatever loads U-Boot.
-
-config MACH_TYPE
-	int "Machine ID number"
-	depends on STATIC_MACH_TYPE
-	help
-	  When booting via ATAGs, the machine type must be passed as a number.
-	  For the full list see https://www.arm.linux.org.uk/developer/machines
-
 config ARCH_SUPPORT_TFABOOT
 	bool
 
 config TFABOOT
 	bool "Support for booting from TF-A"
 	depends on ARCH_SUPPORT_TFABOOT
+	default n
 	help
 	  Some platforms support the setup of secure registers (for instance
 	  for CPU errata handling) or provide secure services like PSCI.
@@ -2076,16 +1929,6 @@ config ISW_ENTRY_ADDR
 	  image headers.
 endif
 
-config SYS_KWD_CONFIG
-	string "kwbimage config file path"
-	depends on ARCH_KIRKWOOD || ARCH_MVEBU
-	default "arch/arm/mach-mvebu/kwbimage.cfg"
-	help
-	  Path within the source directory to the kwbimage.cfg file to use
-	  when packaging the U-Boot image for use.
-
-source "arch/arm/mach-apple/Kconfig"
-
 source "arch/arm/mach-aspeed/Kconfig"
 
 source "arch/arm/mach-at91/Kconfig"
@@ -2120,6 +1963,8 @@ source "arch/arm/mach-octeontx2/Kconfig"
 
 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
 
+source "arch/arm/mach-imx/mx2/Kconfig"
+
 source "arch/arm/mach-imx/mx3/Kconfig"
 
 source "arch/arm/mach-imx/mx5/Kconfig"
@@ -2200,9 +2045,10 @@ source "board/armltd/total_compute/Kconfig"
 
 source "board/bosch/shc/Kconfig"
 source "board/bosch/guardian/Kconfig"
+source "board/CarMediaLab/flea3/Kconfig"
+source "board/Marvell/aspenite/Kconfig"
 source "board/Marvell/octeontx/Kconfig"
 source "board/Marvell/octeontx2/Kconfig"
-source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/cortina/presidio-asic/Kconfig"
 source "board/broadcom/bcm963158/Kconfig"
@@ -2241,7 +2087,6 @@ source "board/socionext/developerbox/Kconfig"
 source "board/st/stv0991/Kconfig"
 source "board/tcl/sl50/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
-source "board/traverse/ten64/Kconfig"
 source "board/variscite/dart_6ul/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/phytium/durian/Kconfig"

arch/arm/Makefile

@@ -18,11 +18,7 @@ arch-$(CONFIG_CPU_V7A)		=$(call cc-option, -march=armv7-a, \
 				 $(call cc-option, -march=armv7))
 arch-$(CONFIG_CPU_V7M)		=-march=armv7-m
 arch-$(CONFIG_CPU_V7R)		=-march=armv7-r
-ifeq ($(CONFIG_ARM64_CRC32),y)
-arch-$(CONFIG_ARM64)		=-march=armv8-a+crc
-else
 arch-$(CONFIG_ARM64)		=-march=armv8-a
-endif
 
 # On Tegra systems we must build SPL for the armv4 core on the device
 # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
@@ -55,7 +51,6 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-machine-$(CONFIG_ARCH_APPLE)		+= apple
 machine-$(CONFIG_ARCH_ASPEED)		+= aspeed
 machine-$(CONFIG_ARCH_AT91)		+= at91
 machine-$(CONFIG_ARCH_BCM283X)		+= bcm283x
@@ -112,7 +107,7 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
 libs-y += arch/arm/mach-imx/
 endif
 else

arch/arm/config.mk

@@ -25,7 +25,6 @@ endif
 
 PLATFORM_RELFLAGS += -fno-common -ffixed-r9
 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
-		     $(call cc-option,-mgeneral-regs-only) \
       $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 
 # LLVM support
@@ -159,8 +158,7 @@ ifdef CONFIG_EFI_LOADER
 OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
 endif
 
-ifdef CONFIG_MACH_IMX
-ifneq ($(CONFIG_IMX_CONFIG),"")
+ifneq ($(CONFIG_IMX_CONFIG),)
 ifdef CONFIG_SPL
 ifndef CONFIG_SPL_BUILD
 INPUTS-y += SPL
@@ -176,7 +174,6 @@ ifneq ($(CONFIG_VF610),)
 INPUTS-y += u-boot.vyb
 endif
 endif
-endif
 
 EFI_LDS := elf_arm_efi.lds
 EFI_CRT0 := crt0_arm_efi.o

arch/arm/cpu/arm1136/Makefile

@@ -7,3 +7,4 @@ extra-y	= start.o
 
 obj-y += ../arm11/
 obj-$(CONFIG_MX31) += mx31/
+obj-$(CONFIG_MX35) += mx35/

arch/arm/cpu/arm1136/mx35/Makefile

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+
+obj-y	+= generic.o
+obj-y	+= timer.o
+obj-y	+= mx35_sdram.o
+obj-y	+= relocate.o

arch/arm/cpu/arm1136/mx35/generic.c

@@ -0,0 +1,530 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <command.h>
+#include <div64.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
+#endif
+#include <netdev.h>
+#include <spl.h>
+
+#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
+#define CLK_CODE_ARM(c)		(((c) >> 16) & 0xFF)
+#define CLK_CODE_AHB(c)		(((c) >>  8) & 0xFF)
+#define CLK_CODE_PATH(c)	((c) & 0xFF)
+
+#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+static int g_clk_mux_auto[8] = {
+	CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
+	CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
+};
+
+static int g_clk_mux_consumer[16] = {
+	CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
+	-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
+	CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
+	-1, -1, CLK_CODE(4, 2, 0), -1,
+};
+
+static int hsp_div_table[3][16] = {
+	{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
+	{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
+	{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
+};
+
+u32 get_cpu_rev(void)
+{
+	int reg;
+	struct iim_regs *iim =
+		(struct iim_regs *)IIM_BASE_ADDR;
+	reg = readl(&iim->iim_srev);
+	if (!reg) {
+		reg = readw(ROMPATCH_REV);
+		reg <<= 4;
+	} else {
+		reg += CHIP_REV_1_0;
+	}
+
+	return 0x35000 + (reg & 0xFF);
+}
+
+static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
+{
+	int *pclk_mux;
+	if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
+		pclk_mux = g_clk_mux_consumer +
+			((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
+			MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
+	} else {
+		pclk_mux = g_clk_mux_auto +
+			((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
+			MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
+	}
+
+	if ((*pclk_mux) == -1)
+		return -1;
+
+	if (fi && fd) {
+		if (!CLK_CODE_PATH(*pclk_mux)) {
+			*fi = *fd = 1;
+			return CLK_CODE_ARM(*pclk_mux);
+		}
+		if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
+			*fi = 3;
+			*fd = 4;
+		} else {
+			*fi = 2;
+			*fd = 3;
+		}
+	}
+	return CLK_CODE_ARM(*pclk_mux);
+}
+
+static int get_ahb_div(u32 pdr0)
+{
+	int *pclk_mux;
+
+	pclk_mux = g_clk_mux_consumer +
+		((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
+		MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
+
+	if ((*pclk_mux) == -1)
+		return -1;
+
+	return CLK_CODE_AHB(*pclk_mux);
+}
+
+static u32 decode_pll(u32 reg, u32 infreq)
+{
+	u32 mfi = (reg >> 10) & 0xf;
+	s32 mfn = reg & 0x3ff;
+	u32 mfd = (reg >> 16) & 0x3ff;
+	u32 pd = (reg >> 26) & 0xf;
+
+	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
+	mfd += 1;
+	pd += 1;
+
+	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+		mfd * pd);
+}
+
+static u32 get_mcu_main_clk(void)
+{
+	u32 arm_div = 0, fi = 0, fd = 0;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
+	fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
+	return fi / (arm_div * fd);
+}
+
+static u32 get_ipg_clk(void)
+{
+	u32 freq = get_mcu_main_clk();
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 pdr0 = readl(&ccm->pdr0);
+
+	return freq / (get_ahb_div(pdr0) * 2);
+}
+
+static u32 get_ipg_per_clk(void)
+{
+	u32 freq = get_mcu_main_clk();
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 pdr0 = readl(&ccm->pdr0);
+	u32 pdr4 = readl(&ccm->pdr4);
+	u32 div;
+	if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
+		div = CCM_GET_DIVIDER(pdr4,
+			MXC_CCM_PDR4_PER0_PODF_MASK,
+			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
+	} else {
+		div = CCM_GET_DIVIDER(pdr0,
+			MXC_CCM_PDR0_PER_PODF_MASK,
+			MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
+		div *= get_ahb_div(pdr0);
+	}
+	return freq / div;
+}
+
+u32 imx_get_uartclk(void)
+{
+	u32 freq;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 pdr4 = readl(&ccm->pdr4);
+
+	if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
+		freq = get_mcu_main_clk();
+	else
+		freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
+	freq /= CCM_GET_DIVIDER(pdr4,
+			MXC_CCM_PDR4_UART_PODF_MASK,
+			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
+	return freq;
+}
+
+unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
+{
+	u32 nfc_pdf, hsp_podf;
+	u32 pll, ret_val = 0, usb_podf;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 reg = readl(&ccm->pdr0);
+	u32 reg4 = readl(&ccm->pdr4);
+
+	reg |= 0x1;
+
+	switch (clk) {
+	case CPU_CLK:
+		ret_val = get_mcu_main_clk();
+		break;
+	case AHB_CLK:
+		ret_val = get_mcu_main_clk();
+		break;
+	case HSP_CLK:
+		if (reg & CLKMODE_CONSUMER) {
+			hsp_podf = (reg >> 20) & 0x3;
+			pll = get_mcu_main_clk();
+			hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
+			if (hsp_podf > 0) {
+				ret_val = pll / hsp_podf;
+			} else {
+				puts("mismatch HSP with ARM clock setting\n");
+				ret_val = 0;
+			}
+		} else {
+			ret_val = get_mcu_main_clk();
+		}
+		break;
+	case IPG_CLK:
+		ret_val = get_ipg_clk();
+		break;
+	case IPG_PER_CLK:
+		ret_val = get_ipg_per_clk();
+		break;
+	case NFC_CLK:
+		nfc_pdf = (reg4 >> 28) & 0xF;
+		pll = get_mcu_main_clk();
+		/* AHB/nfc_pdf */
+		ret_val = pll / (nfc_pdf + 1);
+		break;
+	case USB_CLK:
+		usb_podf = (reg4 >> 22) & 0x3F;
+		if (reg4 & 0x200)
+			pll = get_mcu_main_clk();
+		else
+			pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
+
+		ret_val = pll / (usb_podf + 1);
+		break;
+	default:
+		printf("Unknown clock: %d\n", clk);
+		break;
+	}
+
+	return ret_val;
+}
+unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
+{
+	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 mpdr2 = readl(&ccm->pdr2);
+	u32 mpdr3 = readl(&ccm->pdr3);
+	u32 mpdr4 = readl(&ccm->pdr4);
+
+	switch (clk) {
+	case UART1_BAUD:
+	case UART2_BAUD:
+	case UART3_BAUD:
+		clk_sel = mpdr3 & (1 << 14);
+		pdf = (mpdr4 >> 10) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case SSI1_BAUD:
+		pre_pdf = (mpdr2 >> 24) & 0x7;
+		pdf = mpdr2 & 0x3F;
+		clk_sel = mpdr2 & (1 << 6);
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	case SSI2_BAUD:
+		pre_pdf = (mpdr2 >> 27) & 0x7;
+		pdf = (mpdr2 >> 8) & 0x3F;
+		clk_sel = mpdr2 & (1 << 6);
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	case CSI_BAUD:
+		clk_sel = mpdr2 & (1 << 7);
+		pdf = (mpdr2 >> 16) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case MSHC_CLK:
+		pre_pdf = readl(&ccm->pdr1);
+		clk_sel = (pre_pdf & 0x80);
+		pdf = (pre_pdf >> 22) & 0x3F;
+		pre_pdf = (pre_pdf >> 28) & 0x7;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	case ESDHC1_CLK:
+		clk_sel = mpdr3 & 0x40;
+		pdf = mpdr3 & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case ESDHC2_CLK:
+		clk_sel = mpdr3 & 0x40;
+		pdf = (mpdr3 >> 8) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case ESDHC3_CLK:
+		clk_sel = mpdr3 & 0x40;
+		pdf = (mpdr3 >> 16) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case SPDIF_CLK:
+		clk_sel = mpdr3 & 0x400000;
+		pre_pdf = (mpdr3 >> 29) & 0x7;
+		pdf = (mpdr3 >> 23) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	default:
+		printf("%s(): This clock: %d not supported yet\n",
+				__func__, clk);
+		break;
+	}
+
+	return ret_val;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return get_mcu_main_clk();
+	case MXC_AHB_CLK:
+		break;
+	case MXC_IPG_CLK:
+		return get_ipg_clk();
+	case MXC_IPG_PERCLK:
+	case MXC_I2C_CLK:
+		return get_ipg_per_clk();
+	case MXC_UART_CLK:
+		return imx_get_uartclk();
+	case MXC_ESDHC1_CLK:
+		return mxc_get_peri_clock(ESDHC1_CLK);
+	case MXC_ESDHC2_CLK:
+		return mxc_get_peri_clock(ESDHC2_CLK);
+	case MXC_ESDHC3_CLK:
+		return mxc_get_peri_clock(ESDHC3_CLK);
+	case MXC_USB_CLK:
+		return mxc_get_main_clock(USB_CLK);
+	case MXC_FEC_CLK:
+		return get_ipg_clk();
+	case MXC_CSPI_CLK:
+		return get_ipg_clk();
+	}
+	return -1;
+}
+
+#ifdef CONFIG_FEC_MXC
+/*
+ * The MX35 has no fuse for MAC, return a NULL MAC
+ */
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	memset(mac, 0, 6);
+}
+
+u32 imx_get_fecclk(void)
+{
+	return mxc_get_clock(MXC_IPG_CLK);
+}
+#endif
+
+int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	u32 cpufreq = get_mcu_main_clk();
+	printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
+	printf("ipg clock     : %dHz\n", get_ipg_clk());
+	printf("ipg per clock : %dHz\n", get_ipg_per_clk());
+	printf("uart clock    : %dHz\n", mxc_get_clock(MXC_UART_CLK));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
+	"display clocks",
+	""
+);
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x0F;
+
+	switch (cause) {
+	case 0x0000:
+		return "POR";
+	case 0x0002:
+		return "JTAG";
+	case 0x0004:
+		return "RST";
+	case 0x0008:
+		return "WDOG";
+	default:
+		return "unknown reset";
+	}
+}
+
+int print_cpuinfo(void)
+{
+	u32 srev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX35 rev %d.%d at %d MHz.\n",
+		(srev & 0xF0) >> 4, (srev & 0x0F),
+		get_mcu_main_clk() / 1000000);
+
+	printf("Reset cause: %s\n", get_reset_cause());
+
+	return 0;
+}
+#endif
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(struct bd_info *bis)
+{
+	int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+	rc = fecmxc_initialize(bis);
+#endif
+
+	return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(struct bd_info *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
+#endif
+	return 0;
+}
+
+#define RCSR_MEM_CTL_WEIM	0
+#define RCSR_MEM_CTL_NAND	1
+#define RCSR_MEM_CTL_ATA	2
+#define RCSR_MEM_CTL_EXPANSION	3
+#define RCSR_MEM_TYPE_NOR	0
+#define RCSR_MEM_TYPE_ONENAND	2
+#define RCSR_MEM_TYPE_SD	0
+#define RCSR_MEM_TYPE_I2C	2
+#define RCSR_MEM_TYPE_SPI	3
+
+u32 spl_boot_device(void)
+{
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 rcsr = readl(&ccm->rcsr);
+	u32 mem_type, mem_ctl;
+
+	/* In external mode, no boot device is returned */
+	if ((rcsr >> 10) & 0x03)
+		return BOOT_DEVICE_NONE;
+
+	mem_ctl = (rcsr >> 25) & 0x03;
+	mem_type = (rcsr >> 23) & 0x03;
+
+	switch (mem_ctl) {
+	case RCSR_MEM_CTL_WEIM:
+		switch (mem_type) {
+		case RCSR_MEM_TYPE_NOR:
+			return BOOT_DEVICE_NOR;
+		case RCSR_MEM_TYPE_ONENAND:
+			return BOOT_DEVICE_ONENAND;
+		default:
+			return BOOT_DEVICE_NONE;
+		}
+	case RCSR_MEM_CTL_NAND:
+		return BOOT_DEVICE_NAND;
+	case RCSR_MEM_CTL_EXPANSION:
+		switch (mem_type) {
+		case RCSR_MEM_TYPE_SD:
+			return BOOT_DEVICE_MMC1;
+		case RCSR_MEM_TYPE_I2C:
+			return BOOT_DEVICE_I2C;
+		case RCSR_MEM_TYPE_SPI:
+			return BOOT_DEVICE_SPI;
+		default:
+			return BOOT_DEVICE_NONE;
+		}
+	}
+
+	return BOOT_DEVICE_NONE;
+}

arch/arm/cpu/arm1136/mx35/mx35_sdram.c

@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ */
+
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+
+#define ESDCTL_DDR2_EMR2	0x04000000
+#define ESDCTL_DDR2_EMR3	0x06000000
+#define ESDCTL_PRECHARGE	0x00000400
+#define ESDCTL_DDR2_EN_DLL	0x02000400
+#define ESDCTL_DDR2_RESET_DLL	0x00000333
+#define ESDCTL_DDR2_MR		0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+enum {
+	SMODE_NORMAL =	0,
+	SMODE_PRECHARGE,
+	SMODE_AUTO_REFRESH,
+	SMODE_LOAD_REG,
+	SMODE_MANUAL_REFRESH
+};
+
+#define set_mode(x, en, m)	(x | (en << 31) | (m << 28))
+
+static inline void dram_wait(unsigned int count)
+{
+	volatile unsigned int wait = count;
+
+	while (wait--)
+		;
+
+}
+
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+	u32 row, u32 col, u32 dsize, u32 refresh)
+{
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+	u32 *cfg_reg, *ctl_reg;
+	u32 val;
+	u32 ctlval;
+
+	switch (start_address) {
+	case CSD0_BASE_ADDR:
+		cfg_reg = &esdc->esdcfg0;
+		ctl_reg = &esdc->esdctl0;
+		break;
+	case CSD1_BASE_ADDR:
+		cfg_reg = &esdc->esdcfg1;
+		ctl_reg = &esdc->esdctl1;
+		break;
+	default:
+		return;
+	}
+
+	/* The MX35 supports 11 up to 14 rows */
+	if (row < 11 || row > 14 || col < 8 || col > 10)
+		return;
+	ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
+
+	/* Initialize MISC register for DDR2 */
+	val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+		ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+	writel(val, &esdc->esdmisc);
+	val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+	writel(val, &esdc->esdmisc);
+
+	/*
+	 * according to DDR2 specs, wait a while before
+	 * the PRECHARGE_ALL command
+	 */
+	dram_wait(0x20000);
+
+	/* Load DDR2 config and timing */
+	writel(ddr2_config, cfg_reg);
+
+	/* Precharge ALL */
+	writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+		ctl_reg);
+	writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+	/* Load mode */
+	writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+		ctl_reg);
+	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+	/* Precharge ALL */
+	writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+		ctl_reg);
+	writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+	/* Set mode auto refresh : at least two refresh are required */
+	writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
+		ctl_reg);
+	writel(0xda, start_address);
+	writel(0xda, start_address);
+
+	writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+		ctl_reg);
+	writeb(0xda, start_address + ESDCTL_DDR2_MR);
+	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+	/* OCD mode exit */
+	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+	/* Set normal mode */
+	writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
+		ctl_reg);
+
+	dram_wait(0x20000);
+
+	/* Do not set delay lines, only for MDDR */
+}

arch/arm/cpu/arm1136/mx35/relocate.S

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  relocate - i.MX35-specific vector relocation
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX35 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+	.section	.text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+	bx	lr
+
+ENDPROC(relocate_vectors)

arch/arm/cpu/arm1136/mx35/timer.c

@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/ptrace.h>
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR       (1<<15)	/* Software reset */
+#define GPTCR_FRR       (1<<9)	/* Freerun / restart */
+#define GPTCR_CLKSOURCE_32   (4<<6)	/* Clock source */
+#define GPTCR_TEN       (1)	/* Timer enable */
+
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ * The 32KHz 32-bit timer overruns in 134217 seconds
+ */
+int timer_init(void)
+{
+	int i;
+	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+	struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
+
+	/* setup GP Timer 1 */
+	writel(GPTCR_SWR, &gpt->ctrl);
+
+	writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
+
+	for (i = 0; i < 100; i++)
+		writel(0, &gpt->ctrl); /* We have no udelay by now */
+	writel(0, &gpt->pre); /* prescaler = 1 */
+	/* Freerun Mode, 32KHz input */
+	writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+			&gpt->ctrl);
+	writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
+
+	return 0;
+}

arch/arm/cpu/arm1136/start.S

@@ -39,7 +39,7 @@ reset:
 	msr	cpsr,r0
 
 	/* the mask ROM code should have PLL and others stable */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl  cpu_init_crit
 #endif
 
@@ -62,7 +62,7 @@ c_runtime_cpu_setup:
  *
  *************************************************************************
  */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -81,7 +81,7 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * Jump to board specific initialization... The Mask ROM will have already initialized
 	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
@@ -91,4 +91,4 @@ cpu_init_crit:
 	mov	lr, ip		/* restore link */
 #endif
 	mov	pc, lr		/* back to my caller */
-#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

arch/arm/cpu/arm720t/start.S

@@ -37,8 +37,8 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
-		!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+		!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 	bl	cpu_init_crit
 #endif
 
@@ -62,8 +62,8 @@ c_runtime_cpu_setup:
  *************************************************************************
  */
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
-		!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+		!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 cpu_init_crit:
 
 	mov	ip, lr
@@ -76,4 +76,4 @@ cpu_init_crit:
 	mov	lr, ip
 
 	mov	pc, lr
-#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

arch/arm/cpu/arm920t/ep93xx/speed.c

@@ -6,13 +6,12 @@
  */
 
 #include <common.h>
-#include <clock_legacy.h>
 #include <asm/arch/ep93xx.h>
 #include <asm/io.h>
 #include <div64.h>
 
 /*
- * get_board_sys_clk() should be defined as the input frequency of the PLL.
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  *
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -21,14 +20,14 @@
 /*
  * return the PLL output frequency
  *
- * PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
+ * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
  * / (X2IPD + 1) / 2^PS
  */
 static ulong get_PLLCLK(uint32_t *pllreg)
 {
 	uint8_t i;
 	const uint32_t clkset = readl(pllreg);
-	uint64_t rate = get_board_sys_clk();
+	uint64_t rate = CONFIG_SYS_CLK_FREQ;
 	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
 	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
 	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
@@ -88,9 +87,9 @@ ulong get_UCLK(void)
 
 	const uint32_t value = readl(&syscon->pwrcnt);
 	if (value & SYSCON_PWRCNT_UART_BAUD)
-		uclk_rate = get_board_sys_clk();
+		uclk_rate = CONFIG_SYS_CLK_FREQ;
 	else
-		uclk_rate = get_board_sys_clk() / 2;
+		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
 
 	return uclk_rate;
 }

arch/arm/cpu/arm920t/imx/speed.c

@@ -7,14 +7,13 @@
 
 #include <common.h>
 #if defined (CONFIG_IMX)
-#include <clock_legacy.h>
 
 #include <asm/arch/imx-regs.h>
 
 /* ------------------------------------------------------------------------- */
 /* NOTE: This describes the proper use of this file.
  *
- * get_board_sys_clk() should be defined as the input frequency of the PLL.
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  * SH FIXME: 16780000 in our case
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -46,7 +45,7 @@ ulong get_mcuPLLCLK(void)
 
 	mfi = mfi<=5 ? 5 : mfi;
 
-	return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+	return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
 }
 
 ulong get_FCLK(void)

arch/arm/cpu/arm920t/start.S

@@ -35,11 +35,25 @@ reset:
 	orr	r0, r0, #0xd3
 	msr	cpsr, r0
 
+#if	defined(CONFIG_AT91RM9200DK)
+	/*
+	 * relocate exception table
+	 */
+	ldr	r0, =_start
+	ldr	r1, =0x0
+	mov	r2, #16
+copyex:
+	subs	r2, r2, #1
+	ldr	r3, [r0], #4
+	str	r3, [r1], #4
+	bne	copyex
+#endif
+
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 
@@ -64,7 +78,7 @@ c_runtime_cpu_setup:
  */
 
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -83,7 +97,7 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * before relocating, we have to setup RAM timing
 	 * because memory timing is board-dependend, you will
@@ -95,4 +109,4 @@ cpu_init_crit:
 	mov	lr, ip
 #endif
 	mov	pc, lr
-#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

arch/arm/cpu/arm926ejs/Makefile

@@ -12,10 +12,11 @@ extra-y	:=
 endif
 endif
 
+obj-$(CONFIG_ARMADA100) += armada100/
+obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 
 # some files can only build in ARM or THUMB2, not THUMB1
 

arch/arm/cpu/arm926ejs/armada100/Makefile

@@ -1,10 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
-# (C) Copyright 2014-2021 Tony Dinh <mibodhi@gmail.com>
-#
-# Based on
+# (C) Copyright 2010
 # Marvell Semiconductor <www.marvell.com>
 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
 
-obj-y	:= pogo_v4.o
+obj-y	= cpu.o timer.o dram.o

arch/arm/cpu/arm926ejs/armada100/cpu.c

@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada100.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID	(1<<8)
+#define L2C_RAM_SEL	(1<<4)
+
+int arch_cpu_init(void)
+{
+	u32 val;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+
+	/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
+	val = readl(&cpuregs->cpu_conf);
+	val = val | SET_MRVL_ID;
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable Clocks for all hardware units */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on AIB and AIB-APB Functional clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
+
+	/* ensure L2 cache is not mapped as SRAM */
+	val = readl(&cpuregs->cpu_conf);
+	val = val & ~(L2C_RAM_SEL);
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK, &apb1clkres->gpio);
+
+#ifdef CONFIG_I2C_MV
+	/* Enable general I2C clock */
+	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+
+	/* Enable power I2C clock */
+	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+#endif
+
+	/*
+	 * Enable Functional and APB clock at 14.7456MHz
+	 * for configured UART console
+	 */
+#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart3);
+#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart2);
+#else
+	writel(UARTCLK14745KHZ, &apb1clkres->uart1);
+#endif
+	icache_enable();
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 id;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif

arch/arm/cpu/arm926ejs/armada100/dram.c

@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * ARMADA100 DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet Appendix A.17
+ */
+struct armd1ddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+	u32	pad[3];
+};
+
+struct armd1ddr_registers {
+	u8	pad[0x100 - 0x000];
+	struct armd1ddr_map_registers mmap[2];
+};
+
+/*
+ * armd1_sdram_base - reads SDRAM Base Address Register
+ */
+u32 armd1_sdram_base(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * armd1_sdram_size - reads SDRAM size
+ */
+u32 armd1_sdram_size(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return ((0x8 << (result - 0x7)) * 1024 * 1024);
+	}
+}
+
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = armd1_sdram_base(i);
+		gd->bd->bi_dram[i].size = armd1_sdram_size(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+int dram_init_banksize(void)
+{
+	dram_init();
+
+	return 0;
+}

arch/arm/cpu/arm926ejs/armada100/timer.c

@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <time.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada100.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+/*
+ * Timer registers
+ * Refer Section A.6 in Datasheet
+ */
+struct armd1tmr_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr;
+};
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
+
+/* For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	volatile int loop=100;
+
+	writel(COUNT_RD_REQ, &armd1timers->cvwr);
+	while (loop--);
+	return(readl(&armd1timers->cvwr));
+}
+
+static ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->arch.tbl) {
+		/* normal mode */
+		gd->arch.tbu += now - gd->arch.tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
+	}
+	gd->arch.tbl = now;
+
+	return gd->arch.tbu;
+}
+
+ulong get_timer(ulong base)
+{
+	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+		base);
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime);
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+
+	/* Enable Timer clock at 3.25 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &armd1timers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &armd1timers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x1, &armd1timers->preload_ctrl[TIMER]);
+
+	/* Enable timer 0 */
+	writel(0x1, &armd1timers->cer);
+	/* init the gd->arch.tbu and gd->arch.tbl value */
+	gd->arch.tbl = read_timer();
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+#define MPMU_APRR_WDTR	(1<<4)
+#define TMR_WFAR	0xbaba	/* WDT Register First key */
+#define TMP_WSAR	0xeb10	/* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu(void)
+{
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	u32 val;
+
+	/* negate hardware reset to the WDT after system reset */
+	val = readl(&mpmu->aprr);
+	val = val | MPMU_APRR_WDTR;
+	writel(val, &mpmu->aprr);
+
+	/* reset/enable WDT clock */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+
+	/* clear previous WDT status */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0, &armd1timers->wdt_sts);
+
+	/* set match counter */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0xf, &armd1timers->wdt_match_r);
+
+	/* enable WDT reset */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0x3, &armd1timers->wdt_match_en);
+
+	while(1);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm926ejs/cache.c

@@ -89,3 +89,4 @@ void enable_caches(void)
 	dcache_enable();
 #endif
 }
+

arch/arm/cpu/arm926ejs/cpu.c

@@ -21,19 +21,6 @@
 
 static void cache_flush(void);
 
-/************************************************************
- * sdelay() - simple spin loop.  Will be constant time as
- *  its generally used in bypass conditions only.  This
- *  is necessary until timers are accessible.
- *
- *  not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay(unsigned long loops)
-{
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0"(loops));
-}
-
 int cleanup_before_linux (void)
 {
 	/*

arch/arm/cpu/arm926ejs/mx25/Makefile

@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
 
-obj-y	:= vexpress_common.o
+obj-y	+= generic.o timer.o reset.o relocate.o

arch/arm/cpu/arm926ejs/mx25/generic.c

@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on mx27/generic.c:
+ *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <div64.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+/*
+ *  get the system pll clock in Hz
+ *
+ *                  mfi + mfn / (mfd +1)
+ *  f = 2 * f_ref * --------------------
+ *                        pd + 1
+ */
+static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+{
+	unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
+	    & CCM_PLL_MFI_MASK;
+	int mfn = (pll >> CCM_PLL_MFN_SHIFT)
+	    & CCM_PLL_MFN_MASK;
+	unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
+	    & CCM_PLL_MFD_MASK;
+	unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
+	    & CCM_PLL_PD_MASK;
+
+	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
+	mfd += 1;
+	pd += 1;
+
+	return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
+		     mfd * pd);
+}
+
+static ulong imx_get_mpllclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = MXC_HCLK;
+
+	return imx_decode_pll(readl(&ccm->mpctl), fref);
+}
+
+static ulong imx_get_upllclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = MXC_HCLK;
+
+	return imx_decode_pll(readl(&ccm->upctl), fref);
+}
+
+static ulong imx_get_armclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong cctl = readl(&ccm->cctl);
+	ulong fref = imx_get_mpllclk();
+	ulong div;
+
+	if (cctl & CCM_CCTL_ARM_SRC)
+		fref = lldiv((u64) fref * 3, 4);
+
+	div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
+	       & CCM_CCTL_ARM_DIV_MASK) + 1;
+
+	return fref / div;
+}
+
+static ulong imx_get_ahbclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong cctl = readl(&ccm->cctl);
+	ulong fref = imx_get_armclk();
+	ulong div;
+
+	div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
+	       & CCM_CCTL_AHB_DIV_MASK) + 1;
+
+	return fref / div;
+}
+
+static ulong imx_get_ipgclk(void)
+{
+	return imx_get_ahbclk() / 2;
+}
+
+static ulong imx_get_perclk(int clk)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
+						     imx_get_ahbclk();
+	ulong div;
+
+	div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
+	div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
+
+	return fref / div;
+}
+
+int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
+	ulong div = (fref + freq - 1) / freq;
+
+	if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
+		return -EINVAL;
+
+	clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
+			CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
+			div << CCM_PERCLK_SHIFT(clk));
+	if (from_upll)
+		setbits_le32(&ccm->mcr, 1 << clk);
+	else
+		clrbits_le32(&ccm->mcr, 1 << clk);
+	return 0;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	if (clk >= MXC_CLK_NUM)
+		return -1;
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return imx_get_armclk();
+	case MXC_AHB_CLK:
+		return imx_get_ahbclk();
+	case MXC_IPG_CLK:
+	case MXC_CSPI_CLK:
+	case MXC_FEC_CLK:
+		return imx_get_ipgclk();
+	default:
+		return imx_get_perclk(clk);
+	}
+}
+
+u32 get_cpu_rev(void)
+{
+	u32 srev;
+	u32 system_rev = 0x25000;
+
+	/* read SREV register from IIM module */
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	srev = readl(&iim->iim_srev);
+
+	switch (srev) {
+	case 0x00:
+		system_rev |= CHIP_REV_1_0;
+		break;
+	case 0x01:
+		system_rev |= CHIP_REV_1_1;
+		break;
+	case 0x02:
+		system_rev |= CHIP_REV_1_2;
+		break;
+	default:
+		system_rev |= 0x8000;
+		break;
+	}
+
+	return system_rev;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x0f;
+
+	if (cause == 0)
+		return "POR";
+	else if (cause == 1)
+		return "RST";
+	else if ((cause & 2) == 2)
+		return "WDOG";
+	else if ((cause & 4) == 4)
+		return "SW RESET";
+	else if ((cause & 8) == 8)
+		return "JTAG";
+	else
+		return "unknown reset";
+
+}
+
+int print_cpuinfo(void)
+{
+	char buf[32];
+	u32 cpurev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX25 rev%d.%d%s at %s MHz\n",
+		(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
+		((cpurev & 0x8000) ? " unknown" : ""),
+		strmhz(buf, imx_get_armclk()));
+	printf("Reset cause: %s\n", get_reset_cause());
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_FEC_MXC)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(struct bd_info *bis)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong val;
+
+	val = readl(&ccm->cgr0);
+	val |= (1 << 23);
+	writel(val, &ccm->cgr0);
+	return fecmxc_initialize(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#else
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(struct bd_info *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	int i;
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+			(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	for (i = 0; i < 6; i++)
+		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
+#endif /* CONFIG_FEC_MXC */

arch/arm/cpu/arm926ejs/mx25/relocate.S

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  relocate - i.MX25-specific vector relocation
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX25 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+	.section	.text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+	bx	lr
+
+ENDPROC(relocate_vectors)

arch/arm/cpu/arm926ejs/mx25/reset.c

@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let it time out
+ */
+void reset_cpu(void)
+{
+	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
+	/* Disable watchdog and set Time-Out field to 0 */
+	writew(0, &regs->wcr);
+
+	/* Write Service Sequence */
+	writew(WSR_UNLOCK1, &regs->wsr);
+	writew(WSR_UNLOCK2, &regs->wsr);
+
+	/* Enable watchdog */
+	writew(WCR_WDE, &regs->wcr);
+
+	while (1) ;
+}

arch/arm/cpu/arm926ejs/mx25/timer.c

@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *	Add support for MX25
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/ptrace.h>
+
+/* nothing really to do with interrupts, just starts up a counter. */
+/* The 32KHz 32-bit timer overruns in 134217 seconds */
+int timer_init(void)
+{
+	int i;
+	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+
+	/* setup GP Timer 1 */
+	writel(GPT_CTRL_SWR, &gpt->ctrl);
+
+	writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
+
+	for (i = 0; i < 100; i++)
+		writel(0, &gpt->ctrl); /* We have no udelay by now */
+	writel(0, &gpt->pre); /* prescaler = 1 */
+	/* Freerun Mode, 32KHz input */
+	writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
+			&gpt->ctrl);
+	writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
+
+	return 0;
+}

arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg

@@ -2,5 +2,5 @@ DISPLAYPROGRESS
 SECTION 0x0 BOOTABLE
  TAG LAST
  LOAD     0x1000     spl/u-boot-spl.bin
- LOAD IVT 0xE000     0x1000
- CALL HAB 0xE000     0x0
+ LOAD IVT 0x8000     0x1000
+ CALL HAB 0x8000     0x0

arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

@@ -2,8 +2,8 @@ DISPLAYPROGRESS
 SECTION 0x0 BOOTABLE
  TAG LAST
  LOAD     0x1000     spl/u-boot-spl.bin
- LOAD IVT 0xE000     0x1000
- CALL HAB 0xE000     0x0
+ LOAD IVT 0x8000     0x1000
+ CALL HAB 0x8000     0x0
  LOAD     0x40002000 u-boot.bin
- LOAD IVT 0xE000     0x40002000
- CALL HAB 0xE000     0x0
+ LOAD IVT 0x8000     0x40002000
+ CALL HAB 0x8000     0x0

arch/arm/cpu/arm926ejs/mxs/spl_boot.c

@@ -23,7 +23,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 static gd_t gdata __section(".data");
-#ifdef CONFIG_SPL_SERIAL
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
 static struct bd_info bdata __section(".data");
 #endif
 
@@ -108,7 +108,7 @@ static void mxs_spl_fixup_vectors(void)
 
 static void mxs_spl_console_init(void)
 {
-#ifdef CONFIG_SPL_SERIAL
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
 	gd->bd = &bdata;
 	gd->baudrate = CONFIG_BAUDRATE;
 	serial_init();

arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

@@ -627,11 +627,11 @@ static void mxs_power_enable_4p2(void)
 
 	mxs_power_init_dcdc_4p2_source();
 
-	writel(vddioctrl, &power_regs->hw_power_vddioctrl);
+	writel(vdddctrl, &power_regs->hw_power_vdddctrl);
 	early_delay(20);
 	writel(vddactrl, &power_regs->hw_power_vddactrl);
 	early_delay(20);
-	writel(vdddctrl, &power_regs->hw_power_vdddctrl);
+	writel(vddioctrl, &power_regs->hw_power_vddioctrl);
 
 	/*
 	 * Check if FET is enabled on either powerout and if so,

arch/arm/cpu/arm926ejs/start.S

@@ -17,7 +17,6 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <common.h>
-#include <linux/linkage.h>
 
 /*
  *************************************************************************
@@ -33,13 +32,8 @@
  */
 
 	.globl	reset
-	.globl	save_boot_params_ret
-	.type   save_boot_params_ret,%function
 
 reset:
-	/* Allow the board to save important registers */
-	b	save_boot_params
-save_boot_params_ret:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
@@ -52,7 +46,7 @@ save_boot_params_ret:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 
@@ -75,7 +69,7 @@ c_runtime_cpu_setup:
  *
  *************************************************************************
  */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush D cache before disabling it
@@ -106,7 +100,7 @@ flush_dcache:
 #endif
 	mcr	p15, 0, r0, c1, c0, 0
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */
@@ -115,17 +109,4 @@ flush_dcache:
 	mov	lr, r4		/* restore link */
 #endif
 	mov	pc, lr		/* back to my caller */
-#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
-
-/*************************************************************************
- *
- * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
- *	__attribute__((weak));
- *
- * Stack pointer is not yet initialized at this moment
- * Don't save anything to stack even if compiled with -O0
- *
- *************************************************************************/
-WEAK(save_boot_params)
-	b	save_boot_params_ret	/* back to my caller */
-ENDPROC(save_boot_params)
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

arch/arm/cpu/arm926ejs/sunxi/Makefile

@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
-
-obj-y	+= fel_utils.o
-CFLAGS_fel_utils.o := -marm

arch/arm/cpu/arm926ejs/sunxi/config.mk

@@ -1,6 +0,0 @@
-# Build a combined spl + u-boot image
-ifdef CONFIG_SPL
-ifndef CONFIG_SPL_BUILD
-ALL-y += u-boot-sunxi-with-spl.bin
-endif
-endif

arch/arm/cpu/arm926ejs/sunxi/fel_utils.S

@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Utility functions for FEL mode.
- *
- * Copyright (c) 2015 Google, Inc
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/system.h>
-#include <linux/linkage.h>
-
-ENTRY(save_boot_params)
-	ldr	r0, =fel_stash
-	str	sp, [r0, #0]
-	str	lr, [r0, #4]
-	mrs	lr, cpsr		@ Read CPSR
-	str	lr, [r0, #8]
-	mrc	p15, 0, lr, c1, c0, 0	@ Read CP15 SCTLR Register
-	str	lr, [r0, #12]
-	b	save_boot_params_ret
-ENDPROC(save_boot_params)
-
-ENTRY(return_to_fel)
-	mov	sp, r0
-	mov	lr, r1
-	ldr	r0, =fel_stash
-	ldr	r1, [r0, #16]
-	mcr	p15, 0, r1, c1, c0, 0	@ Write CP15 Control Register
-	ldr	r1, [r0, #12]
-	msr	cpsr, r1		@ Write CPSR
-	bx	lr
-ENDPROC(return_to_fel)

arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds

@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2018
- * Icenowy Zheng <icenowy@aosc.io>
- *
- * Based on arch/arm/cpu/armv7/sunxi/u-boot-spl.lds:
- */
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
-		LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
-		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	.text      :
-	{
-		__start = .;
-		*(.vectors)
-		*(.text*)
-	} > .sram
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
-	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	} > .sram
-
-	. = ALIGN(4);
-	__image_copy_end = .;
-	_end = .;
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start = .;
-		*(.bss*)
-		. = ALIGN(4);
-		__bss_end = .;
-	} > .sdram
-}

arch/arm/cpu/arm946es/start.S

@@ -45,7 +45,7 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 
@@ -70,7 +70,7 @@ c_runtime_cpu_setup:
  */
 
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -89,7 +89,7 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
 	mcr	p15, 0, r0, c1, c0, 0
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */

arch/arm/cpu/armv7/Kconfig

@@ -76,9 +76,4 @@ config ARMV7_LPAE
 	Say Y here to use the long descriptor page table format. This is
 	required if U-Boot runs in HYP mode.
 
-config SPL_ARMV7_SET_CORTEX_SMPEN
-	bool
-	help
-	  Enable the ARM Cortex ACTLR.SMP enable bit on SPL startup.
-
 endif

arch/arm/cpu/armv7/Makefile

@@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o
 obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
 endif
 
-ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y)
+ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif
 

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -1,6 +1,5 @@
 config ARCH_LS1021A
 	bool
-	select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
 	select SYS_FSL_DDR_BE if SYS_FSL_DDR
 	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
 	select SYS_FSL_ERRATUM_A008378
@@ -21,7 +20,6 @@ config ARCH_LS1021A
 	select SYS_FSL_SEC_LE
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
-	select SYS_I2C_MXC
 	imply CMD_PCI
 	imply SCSI
 	imply SCSI_AHCI

arch/arm/cpu/armv7/ls102xa/clock.c

@@ -39,11 +39,11 @@ void get_sys_info(struct sys_info *sys_info)
 	uint i;
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = get_board_sys_clk();
+	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 
 	sys_info->freq_systembus = sysclk;
-#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
-	sys_info->freq_ddrbus = get_board_ddr_clk();
+#ifdef CONFIG_DDR_CLK_FREQ
+	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
 	sys_info->freq_ddrbus = sysclk;
 #endif

arch/arm/cpu/armv7/ls102xa/fdt.c

@@ -131,9 +131,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	sysclk_path = fdt_get_alias(blob, "sysclk");
 	if (sysclk_path)
 		do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
-				     get_board_sys_clk(), 1);
+				     CONFIG_SYS_CLK_FREQ, 1);
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
-			       "clock-frequency", get_board_sys_clk(), 1);
+			       "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 
 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
 #define UBOOT_HEAD_LEN	0x1000
@@ -184,13 +184,13 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 	off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
 					    CONFIG_SYS_IFC_ADDR);
-	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
+	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 #else
 	off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
 					    QSPI0_BASE_ADDR);
-	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
+	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 	off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
 					    DSPI1_BASE_ADDR);
-	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
+	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 #endif
 }

arch/arm/cpu/armv7/ls102xa/spl.c

@@ -8,7 +8,7 @@
 
 u32 spl_boot_device(void)
 {
-#ifdef CONFIG_SPL_MMC
+#ifdef CONFIG_SPL_MMC_SUPPORT
 	return BOOT_DEVICE_MMC1;
 #endif
 	return BOOT_DEVICE_NAND;

arch/arm/cpu/armv7/psci-common.c

@@ -43,3 +43,4 @@ u32 __secure psci_get_context_id(int cpu)
 {
 	return psci_context_id[cpu];
 }
+

arch/arm/cpu/armv7/s5p-common/timer.c

@@ -37,7 +37,7 @@ static inline struct s5p_timer *s5p_get_base_timer(void)
  * This operates at 1MHz and counts downwards. It will wrap about every
  * hour (2^32 microseconds).
  *
- * Return: current value of timer
+ * @return current value of timer
  */
 static unsigned long timer_get_us_down(void)
 {

arch/arm/cpu/armv7/start.S

@@ -39,42 +39,6 @@ reset:
 	/* Allow the board to save important registers */
 	b	save_boot_params
 save_boot_params_ret:
-#ifdef CONFIG_POSITION_INDEPENDENT
-	/*
-	 * Fix .rela.dyn relocations. This allows U-Boot to loaded to and
-	 * executed at a different address than it was linked at.
-	 */
-pie_fixup:
-	adr	r0, reset	/* r0 <- Runtime value of reset label */
-	ldr	r1, =reset	/* r1 <- Linked value of reset label */
-	subs	r4, r0, r1	/* r4 <- Runtime-vs-link offset */
-	beq	pie_fixup_done
-
-	adr	r0, pie_fixup
-	ldr	r1, _rel_dyn_start_ofs
-	add	r2, r0, r1	/* r2 <- Runtime &__rel_dyn_start */
-	ldr	r1, _rel_dyn_end_ofs
-	add	r3, r0, r1	/* r3 <- Runtime &__rel_dyn_end */
-
-pie_fix_loop:
-	ldr	r0, [r2]	/* r0 <- Link location */
-	ldr	r1, [r2, #4]	/* r1 <- fixup */
-	cmp	r1, #23		/* relative fixup? */
-	bne	pie_skip_reloc
-
-	/* relative fix: increase location by offset */
-	add	r0, r4
-	ldr	r1, [r0]
-	add	r1, r4
-	str	r1, [r0]
-	str	r0, [r2]
-	add	r2, #8
-pie_skip_reloc:
-	cmp	r2, r3
-	blo	pie_fix_loop
-pie_fixup_done:
-#endif
-
 #ifdef CONFIG_ARMV7_LPAE
 /*
  * check for Hypervisor support
@@ -116,11 +80,11 @@ switch_to_hypervisor_ret:
 #endif
 
 	/* the mask ROM code should have PLL and others stable */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #ifdef CONFIG_CPU_V7A
 	bl	cpu_init_cp15
 #endif
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	bl	cpu_init_crit
 #endif
 #endif
@@ -173,17 +137,6 @@ ENDPROC(switch_to_hypervisor)
  *
  *************************************************************************/
 ENTRY(cpu_init_cp15)
-
-#if CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN)
-	/*
-	 * The Arm Cortex-A7 TRM says this bit must be enabled before
-	 * "any cache or TLB maintenance operations are performed".
-	 */
-	mrc	p15, 0, r0, c1, c0, 1	@ read auxilary control register
-	orr	r0, r0, #1 << 6		@ set SMP bit to enable coherency
-	mcr	p15, 0, r0, c1, c0, 1	@ write auxilary control register
-#endif
-
 	/*
 	 * Invalidate L1 I/D
 	 */
@@ -367,8 +320,8 @@ skip_errata_801819:
 	mov	pc, r5			@ back to my caller
 ENDPROC(cpu_init_cp15)
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
-	!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+	!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 /*************************************************************************
  *
  * CPU_init_critical registers
@@ -387,10 +340,3 @@ ENTRY(cpu_init_crit)
 	b	lowlevel_init		@ go setup pll,mux,memory
 ENDPROC(cpu_init_crit)
 #endif
-
-#if CONFIG_POSITION_INDEPENDENT
-_rel_dyn_start_ofs:
-	.word	__rel_dyn_start - pie_fixup
-_rel_dyn_end_ofs:
-	.word	__rel_dyn_end - pie_fixup
-#endif

arch/arm/cpu/armv7/sunxi/Makefile

@@ -5,13 +5,11 @@
 # Based on some other Makefile
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+obj-y	+= timer.o
 
 obj-$(CONFIG_MACH_SUN6I)	+= tzpc.o
 obj-$(CONFIG_MACH_SUN8I_H3)	+= tzpc.o
 
-obj-$(CONFIG_MACH_SUN6I)	+= sram.o
-obj-$(CONFIG_MACH_SUN8I)	+= sram.o
-
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
 endif

arch/arm/cpu/armv7/sunxi/sram.c

@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
- *
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * SRAM init for older sunxi SoCs.
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-
-void sunxi_sram_init(void)
-{
-	/*
-	 * Undocumented magic taken from boot0, without this DRAM
-	 * access gets messed up (seems cache related).
-	 * The boot0 sources describe this as: "config ema for cache sram"
-	 * Newer SoCs (A83T, H3 and anything beyond) don't need this anymore.
-	 */
-	if (IS_ENABLED(CONFIG_MACH_SUN6I))
-		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
-
-	if (IS_ENABLED(CONFIG_MACH_SUN8I)) {
-		uint version = sunxi_get_sram_id();
-
-		if (IS_ENABLED(CONFIG_MACH_SUN8I_A23)) {
-			if (version == 0x1650)
-				setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
-			else /* 0x1661 ? */
-				setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
-		} else if (IS_ENABLED(CONFIG_MACH_SUN8I_A33)) {
-			if (version != 0x1667)
-				setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
-		}
-	}
-}

arch/arm/cpu/armv7/sunxi/timer.c

@@ -51,7 +51,6 @@ int timer_init(void)
 	struct sunxi_timer_reg *timers =
 		(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
 	struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
-
 	writel(TIMER_LOAD_VAL, &timer->inter);
 	writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
 	       &timer->ctl);
@@ -59,14 +58,15 @@ int timer_init(void)
 	return 0;
 }
 
+/* timer without interrupts */
 static ulong get_timer_masked(void)
 {
 	/* current tick value */
 	ulong now = TICKS_TO_HZ(read_timer());
 
-	if (now >= gd->arch.lastinc) {	/* normal (non rollover) */
+	if (now >= gd->arch.lastinc)	/* normal (non rollover) */
 		gd->arch.tbl += (now - gd->arch.lastinc);
-	} else {
+	else {
 		/* rollover */
 		gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
 				- gd->arch.lastinc) + now;
@@ -76,7 +76,6 @@ static ulong get_timer_masked(void)
 	return gd->arch.tbl;
 }
 
-/* timer without interrupts */
 ulong get_timer(ulong base)
 {
 	return get_timer_masked() - base;

arch/arm/cpu/armv7m/cpu.c

@@ -12,7 +12,6 @@
 #include <irq_func.h>
 #include <asm/io.h>
 #include <asm/armv7m.h>
-#include <spl.h>
 
 /*
  * This is called right before passing control to
@@ -57,8 +56,3 @@ void reset_cpu(void)
 		| (V7M_SCB->aircr & V7M_AIRCR_PRIGROUP_MSK)
 		| V7M_AIRCR_SYSRESET, &V7M_SCB->aircr);
 }
-
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
-	spl_image->entry_point |= 0x1;
-}

arch/arm/cpu/armv8/Kconfig

@@ -3,6 +3,7 @@ if ARM64
 config ARMV8_SPL_EXCEPTION_VECTORS
 	bool "Install crash dump exception vectors"
 	depends on SPL
+	default n
 	help
 	  The default exception vector table is only used for the crash
 	  dump, but still takes quite a lot of space in the image size.
@@ -102,7 +103,7 @@ config PSCI_RESET
 	bool "Use PSCI for reset and shutdown"
 	default y
 	select ARM_SMCCC if OF_CONTROL
-	depends on !ARCH_APPLE && !ARCH_BCM283X && !ARCH_EXYNOS7 && \
+	depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
 		   !TARGET_LS2080AQDS && \
 		   !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
 		   !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
@@ -127,6 +128,7 @@ config PSCI_RESET
 
 config ARMV8_PSCI
 	bool "Enable PSCI support" if EXPERT
+	default n
 	help
 	  PSCI is Power State Coordination Interface defined by ARM.
 	  The PSCI in U-boot provides a general framework and each platform
@@ -154,6 +156,7 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
 
 config ARMV8_EA_EL3_FIRST
 	bool "External aborts and SError interrupt exception are taken in EL3"
+	default n
 	help
 	  Exception handling at all exception levels for External Abort and
 	  SError interrupt exception are taken in EL3.

arch/arm/cpu/armv8/Makefile

@@ -42,5 +42,6 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
 obj-$(CONFIG_ARMV8_PSCI) += psci.o
+obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
 obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
 obj-$(CONFIG_XEN) += xen/

arch/arm/cpu/armv8/cache.S

@@ -27,11 +27,13 @@ ENTRY(__asm_dcache_level)
 	msr	csselr_el1, x12		/* select cache level */
 	isb				/* sync change of cssidr_el1 */
 	mrs	x6, ccsidr_el1		/* read the new cssidr_el1 */
-	ubfx	x2, x6,  #0,  #3	/* x2 <- log2(cache line size)-4 */
-	ubfx	x3, x6,  #3, #10	/* x3 <- number of cache ways - 1 */
-	ubfx	x4, x6, #13, #15	/* x4 <- number of cache sets - 1 */
+	and	x2, x6, #7		/* x2 <- log2(cache line size)-4 */
 	add	x2, x2, #4		/* x2 <- log2(cache line size) */
+	mov	x3, #0x3ff
+	and	x3, x3, x6, lsr #3	/* x3 <- max number of #ways */
 	clz	w5, w3			/* bit position of #ways */
+	mov	x4, #0x7fff
+	and	x4, x4, x6, lsr #13	/* x4 <- max number of #sets */
 	/* x12 <- cache level << 1 */
 	/* x2 <- line length offset */
 	/* x3 <- number of cache ways - 1 */
@@ -70,7 +72,8 @@ ENTRY(__asm_dcache_all)
 	mov	x1, x0
 	dsb	sy
 	mrs	x10, clidr_el1		/* read clidr_el1 */
-	ubfx	x11, x10, #24, #3	/* x11 <- loc */
+	lsr	x11, x10, #24
+	and	x11, x11, #0x7		/* x11 <- loc */
 	cbz	x11, finished		/* if loc is 0, exit */
 	mov	x15, lr
 	mov	x0, #0			/* start flush at cache level 0 */
@@ -80,7 +83,8 @@ ENTRY(__asm_dcache_all)
 	/* x15 <- return address */
 
 loop_level:
-	add	x12, x0, x0, lsl #1	/* x12 <- tripled cache level */
+	lsl	x12, x0, #1
+	add	x12, x12, x0		/* x0 <- tripled cache level */
 	lsr	x12, x10, x12
 	and	x12, x12, #7		/* x12 <- cache type */
 	cmp	x12, #2
@@ -127,7 +131,8 @@ ENDPROC(__asm_invalidate_dcache_all)
 .pushsection .text.__asm_flush_dcache_range, "ax"
 ENTRY(__asm_flush_dcache_range)
 	mrs	x3, ctr_el0
-	ubfx	x3, x3, #16, #4
+	lsr	x3, x3, #16
+	and	x3, x3, #0xf
 	mov	x2, #4
 	lsl	x2, x2, x3		/* cache line size */
 
@@ -153,7 +158,7 @@ ENDPROC(__asm_flush_dcache_range)
 .pushsection .text.__asm_invalidate_dcache_range, "ax"
 ENTRY(__asm_invalidate_dcache_range)
 	mrs	x3, ctr_el0
-	ubfx	x3, x3, #16, #4
+	ubfm	x3, x3, #16, #19
 	mov	x2, #4
 	lsl	x2, x2, x3		/* cache line size */
 

arch/arm/cpu/armv8/fel_utils.S

@@ -64,18 +64,18 @@ ENTRY(return_to_fel)
 
 /* AArch32 code to restore the state from fel_stash and return back to FEL. */
 back_in_32:
-	.word	0xe59f0028	// ldr	r0, [pc, #40]	; load fel_stash address
-	.word	0xe5901008	// ldr	r1, [r0, #8]
-	.word	0xe129f001	// msr	CPSR_fc, r1
+	.word	0xe59f0028 	// ldr	r0, [pc, #40]	; load fel_stash address
+	.word	0xe5901008 	// ldr	r1, [r0, #8]
+	.word	0xe129f001 	// msr	CPSR_fc, r1
 	.word	0xf57ff06f	// isb
-	.word	0xe590d000	// ldr	sp, [r0]
-	.word	0xe590e004	// ldr	lr, [r0, #4]
-	.word	0xe5901010	// ldr	r1, [r0, #16]
-	.word	0xee0c1f10	// mcr	15, 0, r1, cr12, cr0, {0} ; VBAR
-	.word	0xe590100c	// ldr	r1, [r0, #12]
-	.word	0xee011f10	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
+	.word	0xe590d000 	// ldr	sp, [r0]
+	.word	0xe590e004 	// ldr	lr, [r0, #4]
+	.word	0xe5901010 	// ldr	r1, [r0, #16]
+	.word	0xee0c1f10 	// mcr	15, 0, r1, cr12, cr0, {0} ; VBAR
+	.word	0xe590100c 	// ldr	r1, [r0, #12]
+	.word	0xee011f10 	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
 	.word	0xf57ff06f	// isb
-	.word	0xe12fff1e	// bx	lr		; return to FEL
+	.word	0xe12fff1e 	// bx	lr		; return to FEL
 fel_stash_addr:
 	.word   0x00000000	// receives fel_stash addr, by AA64 code above
 ENDPROC(return_to_fel)

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -4,13 +4,11 @@ config ARCH_LS1012A
 	select ARM_ERRATA_855873 if !TFABOOT
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
-	select GICV2
-	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_MMDC
-	select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
+	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009007
@@ -21,14 +19,12 @@ config ARCH_LS1012A
 	select SYS_I2C_MXC_I2C1 if !DM_I2C
 	select SYS_I2C_MXC_I2C2 if !DM_I2C
 	imply PANIC_HANG
-	imply TIMESTAMP
 
 config ARCH_LS1028A
 	bool
 	select ARMV8_SET_SMPEN
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
-	select GICV3
 	select NXP_LSCH3_2
 	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_SRDS_1
@@ -42,7 +38,6 @@ config ARCH_LS1028A
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
 	select FSL_TZASC_1
-	select FSL_TZPC_BP147
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
@@ -61,12 +56,9 @@ config ARCH_LS1043A
 	bool
 	select ARMV8_SET_SMPEN
 	select ARM_ERRATA_855873 if !TFABOOT
-	select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
-	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
-	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -80,7 +72,7 @@ config ARCH_LS1043A
 	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
-	select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
+	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_ERRATUM_A010539
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_DDR4
@@ -92,17 +84,13 @@ config ARCH_LS1043A
 	select SYS_I2C_MXC_I2C3 if !DM_I2C
 	select SYS_I2C_MXC_I2C4 if !DM_I2C
 	imply CMD_PCI
-	imply ID_EEPROM
 
 config ARCH_LS1046A
 	bool
 	select ARMV8_SET_SMPEN
-	select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
-	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
-	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -129,20 +117,15 @@ config ARCH_LS1046A
 	select SYS_I2C_MXC_I2C2 if !DM_I2C
 	select SYS_I2C_MXC_I2C3 if !DM_I2C
 	select SYS_I2C_MXC_I2C4 if !DM_I2C
-	imply ID_EEPROM
 	imply SCSI
 	imply SCSI_AHCI
-	imply SPL_SYS_I2C_LEGACY
 
 config ARCH_LS1088A
 	bool
 	select ARMV8_SET_SMPEN
 	select ARM_ERRATA_855873 if !TFABOOT
-	select FSL_IFC
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
-	select GICV3
-	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -175,9 +158,7 @@ config ARCH_LS1088A
 	select SYS_I2C_MXC_I2C3 if !TFABOOT
 	select SYS_I2C_MXC_I2C4 if !TFABOOT
 	select RESV_RAM if GIC_V3_ITS
-	imply ID_EEPROM
 	imply SCSI
-	imply SPL_SYS_I2C_LEGACY
 	imply PANIC_HANG
 
 config ARCH_LS2080A
@@ -187,11 +168,8 @@ config ARCH_LS2080A
 	select ARM_ERRATA_828024
 	select ARM_ERRATA_829520
 	select ARM_ERRATA_833471
-	select FSL_IFC
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
-	select GICV3
-	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -232,19 +210,12 @@ config ARCH_LS2080A
 	select SYS_I2C_MXC_I2C4 if !TFABOOT
 	select RESV_RAM if GIC_V3_ITS
 	imply DISTRO_DEFAULTS
-	imply ID_EEPROM
 	imply PANIC_HANG
-	imply SPL_SYS_I2C_LEGACY
 
 config ARCH_LX2162A
 	bool
 	select ARMV8_SET_SMPEN
-	select FSL_DDR_BIST
-	select FSL_DDR_INTERACTIVE
-	select FSL_LAYERSCAPE
 	select FSL_LSCH3
-	select FSL_TZPC_BP147
-	select GICV3
 	select NXP_LSCH3_2
 	select SYS_HAS_SERDES
 	select SYS_FSL_SRDS_1
@@ -263,7 +234,6 @@ config ARCH_LX2162A
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
-	select SYS_PCI_64BIT if PCI
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
@@ -272,17 +242,11 @@ config ARCH_LX2162A
 	imply PANIC_HANG
 	imply SCSI
 	imply SCSI_AHCI
-	imply SPL_SYS_I2C_LEGACY
 
 config ARCH_LX2160A
 	bool
 	select ARMV8_SET_SMPEN
-	select FSL_DDR_BIST
-	select FSL_DDR_INTERACTIVE
-	select FSL_LAYERSCAPE
 	select FSL_LSCH3
-	select FSL_TZPC_BP147
-	select GICV3
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select NXP_LSCH3_2
 	select SYS_HAS_SERDES
@@ -303,21 +267,17 @@ config ARCH_LX2160A
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
-	select SYS_PCI_64BIT if PCI
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
 	select RESV_RAM if GIC_V3_ITS
 	imply DISTRO_DEFAULTS
-	imply ID_EEPROM
 	imply PANIC_HANG
 	imply SCSI
 	imply SCSI_AHCI
-	imply SPL_SYS_I2C_LEGACY
 
 config FSL_LSCH2
 	bool
-	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_5
@@ -469,6 +429,7 @@ config QSPI_AHB_INIT
 
 config FSPI_AHB_EN_4BYTE
 	bool "Enable 4-byte Fast Read command for AHB mode"
+	default n
 	help
 	  The default setting for FlexSPI AHB bus just supports 3-byte addressing.
 	  But some FlexSPI flash sizes are up to 64MBytes.
@@ -531,6 +492,10 @@ endmenu
 menu "Layerscape clock tree configuration"
 	depends on FSL_LSCH2 || FSL_LSCH3
 
+config SYS_FSL_CLK
+	bool "Enable clock tree initialization"
+	default y
+
 config CLUSTER_CLK_FREQ
 	int "Reference clock of core cluster"
 	depends on ARCH_LS1012A

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -5,7 +5,6 @@
  */
 
 #include <common.h>
-#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <env.h>
 #include <fsl_ddr_sdram.h>
@@ -1148,7 +1147,7 @@ int arch_early_init_r(void)
 #endif
 #ifdef CONFIG_SYS_FSL_HAS_RGMII
 	/* some dpmacs in armv8a based freescale layerscape SOCs can be
-	 * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
+	 * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
 	 * EC*_PMUX(rgmii) bits in RCW.
 	 * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
 	 * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits

arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3

@@ -42,22 +42,22 @@ Flash Layout
    pre-silicon platforms (simulator and emulator):
 
 	-------------------------
-	|	FIT Image	|
+	| 	FIT Image	|
 	| (linux + DTB + RFS)	|
 	------------------------- ----> 0x0120_0000
-	|	Debug Server FW |
+	| 	Debug Server FW |
 	------------------------- ----> 0x00C0_0000
-	|	AIOP FW		|
+	|	AIOP FW 	|
 	------------------------- ----> 0x0070_0000
-	|	MC FW		|
+	|	MC FW 		|
 	------------------------- ----> 0x006C_0000
-	|	MC DPL Blob	|
+	| 	MC DPL Blob 	|
 	------------------------- ----> 0x0020_0000
-	|	BootLoader + Env|
+	| 	BootLoader + Env|
 	------------------------- ----> 0x0000_1000
-	|	PBI		|
+	|	PBI 		|
 	------------------------- ----> 0x0000_0080
-	|	RCW		|
+	|	RCW 		|
 	------------------------- ----> 0x0000_0000
 
 	32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
@@ -70,45 +70,45 @@ Flash Layout
 	----------------------------------------- ----> 0x5_8790_0000	|
 	| FIT Image (linux + DTB + RFS)	(40M)	|			|
 	----------------------------------------- ----> 0x5_8510_0000	|
-	|	PHY firmware (2M)		|			|
+	|	PHY firmware (2M)	 	|			|
 	----------------------------------------- ----> 0x5_84F0_0000	| 64K
 	|	Debug Server FW (2M)		|			| Alt
 	----------------------------------------- ----> 0x5_84D0_0000	| Bank
 	|	AIOP FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8490_0000 (vbank4)
-	|	MC DPC Blob (1M)		|			|
+	|	MC DPC Blob (1M) 		|			|
 	----------------------------------------- ----> 0x5_8480_0000	|
 	|	MC DPL Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8470_0000	|
-	|	MC FW (4M)			|			|
+	| 	MC FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8430_0000	|
-	|	BootLoader Environment (1M)	|			|
+	|	BootLoader Environment (1M) 	|			|
 	----------------------------------------- ----> 0x5_8420_0000	|
 	|	BootLoader (1M)			|			|
 	----------------------------------------- ----> 0x5_8410_0000	|
-	|	RCW and PBI (1M)		|			|
+	|	RCW and PBI (1M) 		|			|
 	----------------------------------------- ----> 0x5_8400_0000 ---
 	|	.. Unused .. (7M)		|			|
 	----------------------------------------- ----> 0x5_8390_0000	|
 	| FIT Image (linux + DTB + RFS)	(40M)	|			|
 	----------------------------------------- ----> 0x5_8110_0000	|
-	|	PHY firmware (2M)		|			|
+	|	PHY firmware (2M)	 	|			|
 	----------------------------------------- ----> 0x5_80F0_0000	| 64K
 	|	Debug Server FW (2M)		|			| Bank
 	----------------------------------------- ----> 0x5_80D0_0000	|
 	|	AIOP FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8090_0000 (vbank0)
-	|	MC DPC Blob (1M)		|			|
+	|	MC DPC Blob (1M) 		|			|
 	----------------------------------------- ----> 0x5_8080_0000	|
 	|	MC DPL Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8070_0000	|
-	|	MC FW (4M)			|			|
+	| 	MC FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8030_0000	|
-	|	BootLoader Environment (1M)	|			|
+	|	BootLoader Environment (1M) 	|			|
 	----------------------------------------- ----> 0x5_8020_0000	|
 	|	BootLoader (1M)			|			|
 	----------------------------------------- ----> 0x5_8010_0000	|
-	|	RCW and PBI (1M)		|			|
+	|	RCW and PBI (1M) 		|			|
 	----------------------------------------- ----> 0x5_8000_0000 ---
 
 	128-MB NOR flash layout for QDS and RDB boards

arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

@@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features:
    - Hardware buffer management for buffer allocation and de-allocation (BMan)
    - Cryptography acceleration (SEC)
  - Ethernet interfaces by FMan
-   - Up to 1 x 10GBase-R supporting 10G interface
+   - Up to 1 x XFI supporting 10G interface
    - Up to 1 x QSGMII
    - Up to 4 x SGMII supporting 1000Mbps
    - Up to 2 x SGMII supporting 2500Mbps
@@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features:
    - Two PLLs per four-lane SerDes
    - Support for 10G operation
  - Ethernet interfaces by FMan
-   - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10)
+   - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
    - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
    - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
    - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
@@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features:
   Single WRIOP tile supporting 130Gbps using 18 MACs
   Support for 10G-SXGMII (aka USXGMII).
   Support for SGMII (and 1000Base-KX)
-  Support for 10GBase-R (and 10GBase-KR)
+  Support for XFI (and 10GBase-KR)
   Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
   Support for XLAUI (and 40GBase-KR4) for 40G.
   Support for two RGMII parallel interfaces.
@@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features:
   Ethernet interfaces
   Support for 10G-SXGMII (aka USXGMII).
   Support for SGMII (and 1000Base-KX)
-  Support for 10GBase-R (and 10GBase-KR)
+  Support for XFI (and 10GBase-KR)
   Support for CAUI2 (50G) and 25G-AUI(25G).
   Support for XLAUI (and 40GBase-KR4) for 40G.
   Support for two RGMII parallel interfaces.

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -161,9 +161,14 @@ void fsl_fdt_disable_usb(void *blob)
 	 * controller is used, SYSCLK must meet the additional requirement
 	 * of 100 MHz.
 	 */
-	if (get_board_sys_clk() != 100000000)
-		fdt_for_each_node_by_compatible(off, blob, -1, "snps,dwc3")
+	if (CONFIG_SYS_CLK_FREQ != 100000000) {
+		off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
+		while (off != -FDT_ERR_NOTFOUND) {
 			fdt_status_disabled(blob, off);
+			off = fdt_node_offset_by_compatible(blob, off,
+							    "snps,dwc3");
+		}
+	}
 }
 
 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
@@ -422,7 +427,7 @@ static void fdt_disable_multimedia(void *blob, unsigned int svr)
 		fdt_status_disabled(blob, off);
 
 	/* Disable GPU node */
-	off = fdt_node_offset_by_compatible(blob, -1, "vivante,gc");
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
 	if (off != -FDT_ERR_NOTFOUND)
 		fdt_status_disabled(blob, off);
 }
@@ -650,7 +655,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 #endif
 
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
-			     get_board_sys_clk(), 1);
+			     CONFIG_SYS_CLK_FREQ, 1);
 
 #ifdef CONFIG_GIC_V3_ITS
 	ls_gic_rd_tables_init(blob);

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c

@@ -249,7 +249,7 @@ int setup_serdes_volt(u32 svdd)
 
 	/*
 	 * If SVDD set failed, will not return directly, so that the
-	 * serdes lanes can complete resetting.
+	 * serdes lanes can complete reseting.
 	 */
 	ret = set_serdes_volt(svdd_tar);
 	if (ret)

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -52,17 +52,17 @@ void get_sys_info(struct sys_info *sys_info)
 	uint i, cluster;
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = get_board_sys_clk();
+	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	unsigned long cluster_clk;
 
 	sys_info->freq_systembus = sysclk;
 #ifndef CONFIG_CLUSTER_CLK_FREQ
-#define CONFIG_CLUSTER_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_CLUSTER_CLK_FREQ	CONFIG_SYS_CLK_FREQ
 #endif
 	cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
 
-#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
-	sys_info->freq_ddrbus = get_board_ddr_clk();
+#ifdef CONFIG_DDR_CLK_FREQ
+	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
 	sys_info->freq_ddrbus = sysclk;
 #endif

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

@@ -72,16 +72,16 @@ void get_sys_info(struct sys_info *sys_info)
 #endif
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = get_board_sys_clk();
+	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
 	u32 c_pll_sel, cplx_pll;
 	void *offset;
 
 	sys_info->freq_systembus = sysclk;
-#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
-	sys_info->freq_ddrbus = get_board_ddr_clk();
+#ifdef CONFIG_DDR_CLK_FREQ
+	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-	sys_info->freq_ddrbus2 = get_board_ddr_clk();
+	sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
 #endif
 #else
 	sys_info->freq_ddrbus = sysclk;

arch/arm/cpu/armv8/fsl-layerscape/icid.c

@@ -116,7 +116,8 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
 	int noff, len, icid;
 	const u32 *prop;
 
-	fdt_for_each_node_by_compatible(noff, blob, -1, compat) {
+	noff = fdt_node_offset_by_compatible(blob, -1, compat);
+	while (noff > 0) {
 		prop = fdt_getprop(blob, noff, "cell-index", &len);
 		if (!prop) {
 			printf("WARNING missing cell-index for fman port\n");
@@ -136,6 +137,8 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
 		}
 
 		fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1);
+
+		noff = fdt_node_offset_by_compatible(blob, noff, compat);
 	}
 }
 

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -250,7 +250,7 @@ ENTRY(lowlevel_init)
 	 * b. We use only Region0 whose NSAID write/read is EN
 	 *
 	 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
-	 *	 placeholders.
+	 * 	 placeholders.
 	 */
 
 .macro tzasc_prog, xreg
@@ -259,7 +259,7 @@ ENTRY(lowlevel_init)
 	mov     x16, #0x10000
 	mul     x14, \xreg, x16
 	add     x14, x14,x12
-	mov	x1, #0x8
+	mov 	x1, #0x8
 	add     x1, x1, x14
 
 	ldr     w0, [x1]		/* Filter 0 Gate Keeper Register */

arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c

@@ -18,7 +18,7 @@ struct icid_id_table icid_tbl[] = {
 	SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
 	SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
 	SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
-	SET_GPU_ICID("vivante,gc", FSL_GPU_STREAM_ID),
+	SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
 	SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
 #ifdef CONFIG_FSL_CAAM
 	SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),

arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c

@@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
 	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
 	/*
-	 * LS1044A/1048A  support only one 10GBase-R port
+	 * LS1044A/1048A  support only one XFI port
 	 * Disable MAC1 for LS1044A/1048A
 	 */
 	if (serdes == FSL_SRDS_1 && lane == 2) {

arch/arm/cpu/armv8/fsl-layerscape/mp.c

@@ -4,7 +4,6 @@
  */
 
 #include <common.h>
-#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <image.h>
 #include <log.h>
@@ -15,12 +14,11 @@
 #include <asm/system.h>
 #include <asm/arch/mp.h>
 #include <asm/arch/soc.h>
-#include <linux/compat.h>
 #include <linux/delay.h>
 #include <linux/psci.h>
-#include <malloc.h>
 #include "cpu.h"
 #include <asm/arch-fsl-layerscape/soc.h>
+#include <efi_loader.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -85,7 +83,8 @@ int fsl_layerscape_wake_seconday_cores(void)
 	int i, timeout = 10;
 	u64 *table;
 #ifdef CONFIG_EFI_LOADER
-	void *reloc_addr;
+	u64 reloc_addr = U32_MAX;
+	efi_status_t ret;
 #endif
 
 #ifdef COUNTER_FREQUENCY_REAL
@@ -103,26 +102,27 @@ int fsl_layerscape_wake_seconday_cores(void)
 	 * Keep this after the __real_cntfrq update, so we have it when we
 	 * copy the complete section here.
 	 */
-	reloc_addr = memalign(PAGE_SIZE,
-			      round_up(secondary_boot_code_size, PAGE_SIZE));
-	if (reloc_addr) {
-		debug("Relocating spin table from %p to %p (size %lx)\n",
-		      secondary_boot_code_start, reloc_addr,
+	ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
+				 EFI_RESERVED_MEMORY_TYPE,
+				 efi_size_in_pages(secondary_boot_code_size),
+				 &reloc_addr);
+	if (ret == EFI_SUCCESS) {
+		debug("Relocating spin table from %llx to %llx (size %lx)\n",
+		      (u64)secondary_boot_code_start, reloc_addr,
 		      secondary_boot_code_size);
-		memcpy(reloc_addr, secondary_boot_code_start,
+		memcpy((void *)reloc_addr, secondary_boot_code_start,
 		       secondary_boot_code_size);
-		flush_dcache_range((unsigned long)reloc_addr,
-				   (unsigned long)reloc_addr +
-						  secondary_boot_code_size);
+		flush_dcache_range(reloc_addr,
+				   reloc_addr + secondary_boot_code_size);
 
 		/* set new entry point for secondary cores */
-		secondary_boot_addr += reloc_addr -
+		secondary_boot_addr += (void *)reloc_addr -
 				       secondary_boot_code_start;
 		flush_dcache_range((unsigned long)&secondary_boot_addr,
 				   (unsigned long)&secondary_boot_addr + 8);
 
 		/* this will be used to reserve the memory */
-		secondary_boot_code_start = reloc_addr;
+		secondary_boot_code_start = (void *)reloc_addr;
 	}
 #endif
 

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -41,36 +41,26 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 #ifdef CONFIG_GIC_V3_ITS
-#define PENDTABLE_MAX_SZ	ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
-#define PROPTABLE_MAX_SZ	ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
-#define GIC_LPI_SIZE		ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
-				PROPTABLE_MAX_SZ, SZ_1M)
-static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
-{
-	int err;
-	struct fdt_memory gic_rd_tables;
-
-	gic_rd_tables.start = base;
-	gic_rd_tables.end = base + size - 1;
-	err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
-					 NULL, 0, NULL, 0);
-	if (err < 0)
-		debug("%s: failed to add reserved memory: %d\n", __func__, err);
-
-	return err;
-}
-
 int ls_gic_rd_tables_init(void *blob)
 {
-	u64 gic_lpi_base;
-	int ret;
+	struct fdt_memory lpi_base;
+	fdt_addr_t addr;
+	fdt_size_t size;
+	int offset, ret;
 
-	gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
-	ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
-	if (ret)
+	offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000");
+	addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg",
+						  0, &size, false);
+
+	lpi_base.start = addr;
+	lpi_base.end = addr + size - 1;
+	ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false);
+	if (ret) {
+		debug("%s: failed to add reserved memory\n", __func__);
 		return ret;
+	}
 
-	ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+	ret = gic_lpi_tables_init();
 	if (ret)
 		debug("%s: failed to init gic-lpi-tables\n", __func__);
 
@@ -339,7 +329,7 @@ static void erratum_rcw_src(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 static void erratum_a009203(void)
 {
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
+#ifdef CONFIG_SYS_I2C_LEGACY
 	u8 __iomem *ptr;
 #ifdef I2C1_BASE_ADDR
 	ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
@@ -929,23 +919,25 @@ __weak int fsl_board_late_init(void)
 #define DWC3_GSBUSCFG0_CACHETYPE(n)        (((n) & 0xffff)            \
 	<< DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
 
-static void enable_dwc3_snooping(void)
+void enable_dwc3_snooping(void)
 {
-	static const char * const compatibles[] = {
-	    "fsl,layerscape-dwc3",
-	    "fsl,ls1028a-dwc3",
-	};
-	fdt_addr_t dwc3_base;
-	ofnode node;
+	int ret;
 	u32 val;
-	int i;
+	struct udevice *bus;
+	struct uclass *uc;
+	fdt_addr_t dwc3_base;
 
-	for (i = 0; i < ARRAY_SIZE(compatibles); i++) {
-		ofnode_for_each_compatible_node(node, compatibles[i]) {
-			dwc3_base = ofnode_get_addr(node);
-			if (dwc3_base == FDT_ADDR_T_NONE)
+	ret = uclass_get(UCLASS_USB, &uc);
+	if (ret)
+		return;
+
+	uclass_foreach_dev(bus, uc) {
+		if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) {
+			dwc3_base = devfdt_get_addr(bus);
+			if (dwc3_base == FDT_ADDR_T_NONE) {
+				dev_err(bus, "dwc3 regs missing\n");
 				continue;
-
+			}
 			val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
 			val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
 			val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);

arch/arm/cpu/armv8/fsl-layerscape/spintable.S

@@ -93,7 +93,7 @@ __secondary_boot_func:
 4:
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
 	switch_el x7, _dead_loop, 0f, _dead_loop
-0:	armv8_switch_to_el1_m x4, x6, x7, x9
+0:	armv8_switch_to_el1_m x4, x6, x7
 #else
 	switch_el x7, 0f, _dead_loop, _dead_loop
 0:	armv8_switch_to_el2_m x4, x6, x7

arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 u32 spl_boot_device(void)
 {
-#ifdef CONFIG_SPL_MMC
+#ifdef CONFIG_SPL_MMC_SUPPORT
 	return BOOT_DEVICE_MMC1;
 #endif
 #ifdef CONFIG_SPL_NAND_SUPPORT
@@ -88,14 +88,12 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 	spl_set_bd();
 
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
+#ifdef CONFIG_SYS_I2C_LEGACY
 #ifdef CONFIG_SPL_I2C
 	i2c_init_all();
 #endif
 #endif
-#if defined(CONFIG_VID) && (defined(CONFIG_ARCH_LS1088A) || \
-			    defined(CONFIG_ARCH_LX2160A) || \
-			    defined(CONFIG_ARCH_LX2162A))
+#ifdef CONFIG_VID
 	init_func_vid();
 #endif
 	dram_init();

arch/arm/cpu/armv8/hisilicon/pinmux.c

@@ -181,3 +181,5 @@ int hi6220_pinmux_config(int peripheral)
 
 	return 0;
 }
+
+

arch/arm/cpu/armv8/lowlevel_init.S

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * A lowlevel_init function that sets up the stack to call a C function to
+ * perform further init.
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	/*
+	 * Setup a temporary stack. Global data is not available yet.
+	 */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+	ldr	w0, =CONFIG_SPL_STACK
+#else
+	ldr	w0, =CONFIG_SYS_INIT_SP_ADDR
+#endif
+	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
+
+	/*
+	 * Save the old LR(passed in x29) and the current LR to stack
+	 */
+	stp	x29, x30, [sp, #-16]!
+
+	/*
+	 * Call the very early init function. This should do only the
+	 * absolute bare minimum to get started. It should not:
+	 *
+	 * - set up DRAM
+	 * - use global_data
+	 * - clear BSS
+	 * - try to start a console
+	 *
+	 * For boards with SPL this should be empty since SPL can do all of
+	 * this init in the SPL board_init_f() function which is called
+	 * immediately after this.
+	 */
+	bl	s_init
+	ldp	x29, x30, [sp]
+	ret
+ENDPROC(lowlevel_init)

arch/arm/cpu/armv8/start.S

@@ -104,6 +104,10 @@ pie_skip_reloc:
 pie_fixup_done:
 #endif
 
+#ifdef CONFIG_SYS_RESET_SCTRL
+	bl reset_sctrl
+#endif
+
 #if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
 .macro	set_vbar, regname, reg
 	msr	\regname, \reg
@@ -191,6 +195,39 @@ slave_cpu:
 master_cpu:
 	bl	_main
 
+#ifdef CONFIG_SYS_RESET_SCTRL
+reset_sctrl:
+	switch_el x1, 3f, 2f, 1f
+3:
+	mrs	x0, sctlr_el3
+	b	0f
+2:
+	mrs	x0, sctlr_el2
+	b	0f
+1:
+	mrs	x0, sctlr_el1
+
+0:
+	ldr	x1, =0xfdfffffa
+	and	x0, x0, x1
+
+	switch_el x1, 6f, 5f, 4f
+6:
+	msr	sctlr_el3, x0
+	b	7f
+5:
+	msr	sctlr_el2, x0
+	b	7f
+4:
+	msr	sctlr_el1, x0
+
+7:
+	dsb	sy
+	isb
+	b	__asm_invalidate_tlb_all
+	ret
+#endif
+
 /*-----------------------------------------------------------------------*/
 
 WEAK(apply_core_errata)

arch/arm/cpu/armv8/transition.S

@@ -40,7 +40,7 @@ ENTRY(armv8_switch_to_el1)
 	 * now, jump to the address saved in x4.
 	 */
 	br x4
-1:	armv8_switch_to_el1_m x4, x5, x6, x7
+1:	armv8_switch_to_el1_m x4, x5, x6
 ENDPROC(armv8_switch_to_el1)
 .popsection
 

arch/arm/cpu/armv8/u-boot-spl.lds

@@ -84,8 +84,4 @@ SECTIONS
 	/DISCARD/ : { *(.plt*) }
 	/DISCARD/ : { *(.interp*) }
 	/DISCARD/ : { *(.gnu*) }
-
-#ifdef CONFIG_LINUX_KERNEL_IMAGE_HEADER
-#include "linux-kernel-image-header-vars.h"
-#endif
 }

arch/arm/cpu/armv8/xen/hypercall.S

@@ -76,3 +76,4 @@ HYPERCALL2(sched_op);
 HYPERCALL2(event_channel_op);
 HYPERCALL2(hvm_op);
 HYPERCALL2(memory_op);
+

arch/arm/cpu/pxa/start.S

@@ -45,7 +45,7 @@ reset:
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl  cpu_init_crit
 #endif
 
@@ -92,7 +92,7 @@ c_runtime_cpu_setup:
  *
  *************************************************************************
  */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -111,7 +111,7 @@ cpu_init_crit:
 	mcr	p15, 0, r0, c1, c0, 0
 
 	mov	pc, lr		/* back to my caller */
-#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
 
 /*
  * Enable MMU to use DCache as DRAM.