This patch adds auto control mode debugfs CRC support based on
DPU Signature units. The evaluation window is the same to the
display region as indicated by drm_crtc_state->adjusted_mode.
The CRC data count is three when single DPU display stream is used,
while six when the pixel combiner(dual DPU display streams) is used.
Each data shows the CRC value for the 8 most significant bits of
red/green/blue channel of the entire evaluation window, which reflects
how DPU Signature unit reports CRC values.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
This patch adds helper disengcfg_sig_select() support so that
users may select different taps(FrameGen, GammaCor, Matrix or
Dither) to do signature computation. Also, select FrameGen as
the default tap in _dpu_dec_init() and call it in dpu_dec_init().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
This patch adds signature unit support in the dpu common driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The dpu common driver creates a irq chip for dpu irqs.
The parent of the irq chip on the i.MX8qm/qxp SoC is the irqsteer.
Since the irqsteer driver may support runtime PM, the dpu common
driver needs to call irq_chip_pm_get/put() where necessary to make
sure power of the irq chip is enabled/disabled properly. This
patch enables the power at the driver probe stage and disables it
at driver remove stage to achieve basic power management support
for the irq chip.
Suggested-by: Andy Duan <fugang.duan@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
After attach multiple power domains, these power domains are
power on since the state is DL_FLAG_PM_RUNTIME & DL_FLAG_RPM_ACTIVE.
The action is expected by the driver to let all power domains
always on.
Fixes: 583c9de66ebf(gpu: imx: Add dpu common driver support)
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
This patch increase the DPU single pipe maximum from 1920 to 2560 for
DPU common.
Signed-off-by: Oliver F. Brown <oliver.brown@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Increase iMX DRM CTRC maximum size 5120 width x 4096 height to support
5K wide monitors.
Signed-off-by: Oliver F. Brown <oliver.brown@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
It would be good to check of_match_device() return value in dpu_probe()
in case it returns a NULL pointer. This may avoid NULL pointer dereference
from happening.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
The crtc_states could be got concurrently if multiple atomic checks
happen simultaneously, so ERR_PTR(-EDEADLK) could be returned from
drm_atomic_get_crtc_state(). In such normal cases, we just rollback
all added drm objects and userspace could try the same atomic check
or commit again, so it's unnecessary to warn.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
The structure dpu_crtc essentially contains drm crtc. If we allocate
the instance of the structure dpu_crtc with devm_kzalloc() in ->bind(),
it would be freed in case anything in dpu_crtc_init() fails after the
call for drm_crtc_init_with_planes(). However, drm_crtc_init_with_planes()
may have already added the crtc into the crtc_list. The function
drm_mode_config_cleanup() called in imx_drm_bind() as a part of it's
bailout logic would walk through the list to try to cleanup the crtc,
which would cause the use-after-free issue. This patch changes the
dpu_crtc allocation from ->bind() to ->probe() to fix the issue. And,
with this change, ->unbind() doesn't need to cleanup the crtc anymore,
since it can be done by the imx-drm core driver.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
DPU found in i.MX8qxp SoC may drive a parallel display through
pixel link to LCDIF mux. This patch adds the device tree binding
documentation for LCDIF mux display.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
DPU found in i.MX8qxp SoC may drive parallel display via
pixel link with display stream1. The pixel link MST address
of this particular display path is 1 instead of 0. So, this
patch adds DPI encoder support so as to specify the MST
address and also to enable SYNC_CTRL and pixel link MST_VLD.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
In order to avoid garbage data left in RTRAM after disabling CRTC,
the SoC designer suggests us to disable DPRC repeat_en after FrameGen
FGEN is cleared and before ENSTS is cleared. Also, it is suggested
that FGEN clearing should be done in the frame prior to DPRC repeat_en
disablement. So, syncing to FrameGen frame counter moving is needed.
The disablement procedure should be done as soon as possible, so we
disable local irq and preemption during the procedure to ensure this.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
In the coming patch, we would wait for FrameGen counter moving in
->atomic_disable() to get synchronization before disabling DPRC
repeat_en. It appears that waiting for 50ms for video mode
1920x1080@24Hz is not enough in this case and increasing timeout
to 100ms looks ok.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The SoC designer suggests us to disable DPRC repeat_en right after
FrameGen frame counter moving so that a plane with prefetch engine
can be disabled correctly on-the-fly. This helps the plane be
enabled again later without flashing at the initial several lines
fetched by the plane. The DPRC repeat_en disablement should be done
as soon as the FrameGen frame counter moving, which requires us to
disable preemption and irq. However, based on tests, there is no
malfunction observed without the strict sequence implemented.
So, tag this as FIXME to achieve some simplicity for now.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
dprc_enable() essentially clears BYPASS bit of PRG. So, instead of
checking prefetch_start or uv_prefetch_start flags beforehand, it
doesn't hurt to call it unconditionally when prefetch is needed.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The pin-off mechanism tries to avoid disabling primary plane's
fetchunit together with CRTC and just leave it be untouched.
However, this shouldn't be something unsupported by the hardware.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Another coming patch will wait for framegen secondary channel syncup
for non-sync mode cases. It appears that waiting for 50ms for video
modes like 1920x1080p@24 and 1920x1080p@30 is not enough. So, this
patch increases the timeout value to 100ms.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The prompt string for config entry DRM_IMX_DPU is missing,
so this patch adds it.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Since of_irq_count() is not exported as a symbol, we cannot
find it's definition when imx-dpu-core is built as a module.
To address this issue, this patch calls platform_irq_count()
to get irq count instead.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Any CRTC driver should use the crtc_clock instead of clock value from
drm_display_mode structure, since the crtc_clock might differ from the
actual pixel clock needed by that mode.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
To make sure SCU misc settings are in valid status at system resume
stage, let's initialize them in dpu_resume().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The KACHUNK_CNT SCU misc setting is for DPU blit engine's prefetch engine.
It represents how many cycles are needed to trigger prefetch engine after
DPU shadow being loaded. Set it to be 32, which is recommended and tested.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The SCU misc settings of DC subsystem contain pixel link settings
and other settings, like DC sync mode and KACHUNK_CNT. So, it would
be better to rename dpu_pxlink_init() to dpu_sc_misc_init(), which
includes initialization code for all SCU misc settings of DC subsystem.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The function dpu_sc_misc_init() actually gets the SCU handle only.
So, renaming it to dpu_sc_misc_get_handle() better reflects what it does.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The LVDS encoder driver for i.MX8qxp SoC needs to enable/disable pixel link
in order to meet some sequence requirements, otherwise, display artifacts
will be seen on LVDS display. This patch avoids to enable/disable pixel
link in the FrameGen driver for this special encoder.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
i.MX8qxp LDB dual channel mode uses two LDB channels from two LDB
instances, while i.MX8qm LDB uses two LDB channels from one LDB
instance. So, this patch adds flag has_dual_ldb in struct dpu_data
so that it can be used to tell the difference.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch caches encoder_type in struct dpu_framegen when we
call framegen_cfg_videomode(). This cached type can be used
later when determining whether to enable pixel link in the
FrameGen driver or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
As DPU fetchunits support ITU601(limited range)/ITU601_FR(full range)
and ITU709(limited range) YUV to RGB color space conversions, we may
add color encoding and color range properties support for planes.
Considering software backward compatibility, the default color encoding
is set to ITU601 with full color range.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds mulitple pixel blend modes for DPU plane.
The modes are "None", "Pre-multiplied" and "Coverage".
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Now that we've already got proper default blend mode support,
we may introduce alpha in pixel feature for overlay planes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
DPU has no limitations on the plane's zpos, so we don't
have to limit the primary plane zpos to be zero and the
overlay plane zpos to be non-zero.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch improves bailout path of dpu_plane_create().
As we'll add more drm properties to the planes later,
this would simply the code.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Without the new blend modes("None", "Pre-multiplied" and "Coverage")
introduced in the below commit, the old userspace assumes alpha in
pixel is per-premultiplied by default. So, let's support the default
blend mode properly.
commit a5ec8332d4 ("drm: Add per-plane pixel blend mode property")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner support in the DPU KMS driver.
Pretty much logics are implemented to allocate/organize the
CRTC resources(extdst, framegen, tcon, pixel combiner, etc)
and plane resources(extdst, fetchunit, layerblend, etc) which
are needed to drive a high pixel rate display via pixel combiner.
Additional logics are implemented to support sync up mode fixup
found in the new version of DPU IP.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_pixengcfg_syncmode_master() helper support
so that the callers may control if a extdst is master or slave
when it works in sync mode. The bit16 of extdst's PIXENGCFG_STATIC
register controls this and it's a part of sync mode fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit7 of framegen's SECSTATCONFIG register is used to control
the sync mode fixup logic implemented in framegen. This patch
adds framegen_syncmode_fixup() helper so that the callers
may enable/disable the fixup logic for a framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Store9 unit can be shared bewteen display engine(for sync mode fixup)
and blit engine. It's proper to get the store resource in the DPU
common driver and then provide it to client platform device via
platform data.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9. So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch sets master stream id to be 1 for i.MX8QM DPU.
The master stream id is used when FrameGen works in sync mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner support in the DPU core driver.
Users may get and enable/disable/control a pixel combiner instant
via tcon functions and may tell if it is needed in a specific usecase
via the dpu_get_syncmode_min_prate() and dpu_get_singlemode_max_width()
helpers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Cache the auxiliary CRTC resources in struct dpu_crtc via the
dpu_aux_{unit}_peek() helpers so that the DPU CRTC driver may
use them later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The DPU CRTC device driver may get the CRTC group id from
the pdata of the device. Let's cache it in struct dpu_crtc
so that the driver may use it later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for tcon so that
two tcons can participate in the dual display streams
to work with pixel combiner to drive a high pixel rate
display.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for framegen so that
two framegens can work in sync mode to participate in the
dual display streams to drive a high pixel rate display
via a pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper dpu_pxlink_set_dc_sync_mode() support
so that callers may enable or disable DC sync mode.
In DC sync mode, high pixel rate video mode can be supported
by combining two display streams together.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
