This was always wrong but causes failures recently after dom0 switched
to using mu1 and claiming it's interrupt
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Correct JPEG power domain tree to make sure kernel can
boot up successfully with XRDC enforcement enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
Correct USB power domain tree to make sure kernel can
boot up successfully with XRDC enforcement enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
Remove all GPIOs LPCG clock definition to make sure they
are always ON by SCFW default setting.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
All GPIOs clock will be kept ON in SCFW by default, here
remove all GPIOs management to make sure they are always
ON.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
Avoid touch unused edma channel register in susped/resume, otherwise,
kernel crash if XRDC enabled in scfw.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Fixes: a2e6a78334 (MLK-16136-9 irqchip: imx-irqsteer: adjust irq config
via 'endian')
This patch fixes mask register offset calculation, when endian is not
default value 0 (i.e imx8mq).
Signed-off-by: Antoine Bouyer <antoine.bouyer@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
According to SPEC, when change the pll frequency and needs pll reset,
the t3 - t2 need to be greater than 1us and 1/FREF, respectively.
FREF is FIN / Prediv, the prediv is [1, 63], so choose
3us for safe.
The pll1443x does not have lock sel bit mask, so remove it.
Remove the bypass setting before changing frequency.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Removing all references to GPIO IPG clocks, this will leave all LPCG
clocks controlling GPIOs in an always ON state similar to earlier iMX
processors. By registering these clocks, unused GPIO clocks were disabled
at boot, causing issues during system suspend/resume as there is no easy
way to enable the clocks because the power domain associated with these
GPIOs are also disabled.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Controlling GPIO clocks in iMX8 is dependent on power domain,
and an unused GPIO's power domain is disabled during startup.
This makes it difficult for the GPIO driver to manage clocks for such
GPIOs. This causes failures during system suspend/resume when
GPIO registers are saved/restored.
These LPCG clocks will be always be in an enabled state, similar
to earlier iMX processors.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
scfw xrdc enforcing, and add sync for v4l2 driver and firmware
Add MU for vpu encoder and decoder power in dts for scfw xrdc enforcing,
and add sync for v4l2 driver and firmware
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
In the latest scfw design, the power domain of device should be explicit
enabled in kernel, otherwise there will be kernel dump.
For example, when using audio device to playback, the DMA channel's power
domain should be eanbled, but to avoid to call scfw API in driver, we need
to refine the tree of power domain, define the DMA channel's power domain
as audio device's parent.
And same requirement for DSP, the MU and DSP_RAM is required by DSP driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
The driver don't need to explicit enable the power domain, which
can be done by runtime power management, when the power domain tree
defined in device tree.
in this case, the MU initialization can be moved to runtime pm function.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add 1GHz, 800MHz, 700MHz, 600MHz pll clock rate setting in the pll
clock calculation table of imx8mm. These frequency point are needed
by VPU and GPU driver.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
We get pll and display clock rates twice in framegen_cfg_videomode().
This patch removes the redundant code so that the rates are got once.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
It turns out that local alpha value of the secondary input is set to
0xFF by the hardware if the secondary input is from scaler(hscaler or
vscaler). This makes the layer on this secondary input accidentally
cover the layer with higher z-order(if it exists), even though the
layer with lower z-order doesn't supply local alpha. This patch zeros
the secondary local alpha value to prevent the issue from happening.
Users are unlikely to expect local alpha to be correctly scaled, so
it looks fine to simply zero the alpha. If we find the unlikely case,
the KMS driver may later explicitly do atomic check to invalidate the case.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
HSIO MSIC/GPIO are powered by the pd_hsio_gpio domain.
Use the pd_hsio_gpio as the parent pd of the imx8 hsio to
make sure that the pd_hsio_gpio domain would be tuend on
when enable HSIO module.
BTW, PHY calibration of the PHYX2_1/PHYX1 is relied on the
results of the PHYX2_0.
So, all the HSIO PDs should be turned on when use PCIe
or SATA.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
As IC team recommended, it is better to set vsync pulse
width as 2 lines pixels, otherwise ISI will lost half
of frames.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Sandor.Yu <sandor.yu@nxp.com>
i.MX8MM shares same cpu-freq driver with i.MX8MQ, but
its EVK board has a PMIC which can scale VDD_ARM voltage
according to voltage defined in dtb, add support for it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Add i.MX8MM cpu-idle support, level #1 is wfi,
level #2 is ARM power gated.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
